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Xilinx asu ecc standalone
- #11053
#11053
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night1rider
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Xilinx asu ecc standalone
#11053
night1rider
wants to merge 14 commits into
wolfSSL:master
wolfSSL/wolfssl:master
from
night1rider:Xilinx-ASU-ECC-standalone
night1rider/wolfssl:Xilinx-ASU-ECC-standalone
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Commits
Commits on Aug 19, 2026
Xilinx Versal Gen2 ASU port: ECC, ECDH, ECIES and EdDSA offload
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benchmark: AES IV and CCM nonce sweeps, ECC curve sweep and CSV HW/SW column
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benchmark: run Ed448 and the DRBG through the device id so both can be compared
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benchmark: add AES key wrap and padded key wrap benchmarks
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Xilinx Versal Gen2 ASU ECIES: accept the default context, not just the named roles
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benchmark: keep the AES-CCM nonce sweep labels alive for the stats list
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benchmark: keep the GMAC iv16 label alive for the stats list
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benchmark: skip AES-CCM nonce and block size pairs the length field cannot encode
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Xilinx Versal Gen2 ASU: add a port README
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Xilinx Versal Gen2 ASU: require a private key before offloading ECDSA sign, ECDH and ECIES decrypt
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benchmark: build the AES key wrap benchmarks only where the _ex API exists
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Commits on Aug 20, 2026
Xilinx Versal Gen2 ASU: fix the Vitis build and correct the benchmark rows
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Xilinx Vitis SDT: make the settings template pick a random seed source
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Xilinx Versal Gen2 ASU: log why ECDH and ECIES send work to software
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