Refactor HyperBus into asynchronous, isochronous, and synchronous variants

[phsauter]

Requires #34 and #39.

This PR replaces the former monolithic HyperBus top with three clocking variants and restructures the controller into explicit frontend, midend, bridge, and backend stages. It also expands testing, hardens configuration updates, transaction segmentation, error handling, and atomic operation sequencing.

Clocking variants

• Add hyperbus_asynchronous, which uses independent system and PHY clocks, explicit CDCs, and PHY-domain reset synchronization.
• Add hyperbus_isochronous, which derives the PHY clock from the system clock using an integer divider and the 90-degree shift from the TX delay line.
• Add hyperbus_synchronous, which uses one shared clock and a TX delay line to generate the required 90-degree phase shift.
• Move the TX clock delay to the backend.

Architecture and interfaces

• Replace the monolithic dataflow with an explicit AXI frontend -> midend -> bridge -> backend pipeline.
• Introduce reusable command, TX, RX, and response structures for the interfaces between these stages.
• Use clearable common_cells CDC primitives in the asynchronous bridge and lightweight isochronous crossings where the clock relationship is known.
• Remove the obsolete phy_if layer and rename the remaining data conversion blocks to read and write adapters.
• Move PHY-specific implementation modules into src/backend/.

Configuration and transaction control

• Move configuration sequencing into the frontend.
• Stop accepting new requests, drain outstanding operations, update the backend while it is idle, and resume traffic only after the update completes.
• Add explicit flush/barrier behavior and reuse it to sequence configuration changes and atomic operations.
• Extract atomic handling into a dedicated module.
• Return invalid or unsupported accesses as protocol errors and record status information for diagnosis.
• Split transactions at chip boundaries and before exceeding the HyperBus maximum CS-low duration.
• Fix transfer control so long or slowly supplied transfers restart as additional HyperBus segments instead of stalling or violating the maximum transaction duration.

Verification

• Exercise the asynchronous, isochronous, and synchronous tops through the common AXI testbench.
• Cover single- and dual-PHY configurations.
• Add directed tests for configuration barriers, decode errors, address boundaries, cross-chip bursts, and atomic operations.
• Add maximum-size burst performance tests for read and write traffic.
• Add deliberately slow frontend traffic that requires and directly observes HyperBus transfer segmentation.
• Replace remaining hand-written RTL assertions with common_cells assertion macros.
• Pass the complete Questa regression for all three tops, the synchronous single-PHY configuration, and the configuration register testbench.