Per-chip staged configurations - #42
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Introduce asynchronous, isochronous, and synchronous top levels around a shared backend architecture. Extend the regression wrapper so each clocking arrangement is exercised.
Separate protocol-facing configuration, midend request processing, clock-domain bridges, and backend control. Add explicit drain/apply sequencing and harden segmented transaction handling.
Use reusable host and HyperBus stream structures across the midend and bridges. Isolate atomic read-modify-write sequencing and replace the legacy PHY adapters with explicit read and write adapters.
Group PHY-specific RTL under the backend, place transmit delay generation beside the PHY, and use one configurable clock-generation path for all top-level variants. Convert parameter and protocol checks to common_cells assertion macros.
Remove redundant host and isochronous buffering, adopt common_cells stream and address-decode primitives, and clarify request, atomic, configuration, and adapter control flow.
Update directed AXI tests to use the hierarchical 4 KiB register map and exercise automatic configuration drain and apply behavior.
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Requires #34, #39, #36, #40, #41.