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[RyuJIT Wasm] Handle all codegen cases for PackedSimd.Shuffle #130991

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[RyuJIT Wasm] Handle all codegen cases for PackedSimd.Shuffle #130991

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1050151
Add PackedSimd load/store mappings to table
adamperlin Jul 14, 2026
45f618e
Fix OperIsMemory{Load,Store} for PackedSimd operations
adamperlin Jul 15, 2026
7fd077a
Implement SIMD element-wise load/store codegen
adamperlin Jul 15, 2026
00c8430
Merge branch 'main' into adamperlin/wasm-simd-loads-stores
adamperlin Jul 15, 2026
f9504c5
Properly lower PackedSimd.Shuffle with non-constant operands
adamperlin Jul 17, 2026
842bb15
Merge branch 'main' into adamperlin/wasm-basic-shuffle-codegen
adamperlin Jul 17, 2026
d53c1cc
Add header comment
adamperlin Jul 17, 2026
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11 changes: 2 additions & 9 deletions src/coreclr/jit/codegenwasm.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2754,15 +2754,8 @@ void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree)
}
else // A normal store, not a WriteBarrier store
{
var_types type = tree->TypeGet();
if (type == TYP_SIMD16)
{
// Storing a SIMD16 value emits v128.store, but the data operand is not
// materialized as a v128 (it comes through as an i32), producing an invalid
// module. Bail until SIMD16 store is properly supported.
NYI_WASM_SIMD("SIMD16 store indirect");
}
instruction ins = ins_Store(type);
var_types type = tree->TypeGet();
instruction ins = ins_Store(type);

// TODO-WASM: Memory barriers

Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/gentree.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -30774,7 +30774,7 @@ bool GenTreeHWIntrinsic::OperIsMemoryLoad(GenTree** pAddr) const
{
GenTree* addr = nullptr;

#if defined(TARGET_XARCH) || defined(TARGET_ARM64)
#if defined(TARGET_XARCH) || defined(TARGET_ARM64) || defined(TARGET_WASM)
NamedIntrinsic intrinsicId = GetHWIntrinsicId();
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsicId);

Expand Down Expand Up @@ -30964,7 +30964,7 @@ bool GenTreeHWIntrinsic::OperIsMemoryLoad(GenTree** pAddr) const
}
}
#endif // TARGET_XARCH
#endif // TARGET_XARCH || TARGET_ARM64
#endif // TARGET_XARCH || TARGET_ARM64 || TARGET_WASM

if (pAddr != nullptr)
{
Expand Down Expand Up @@ -31031,7 +31031,7 @@ bool GenTreeHWIntrinsic::OperIsMemoryStore(GenTree** pAddr) const
{
GenTree* addr = nullptr;

#if defined(TARGET_XARCH) || defined(TARGET_ARM64)
#if defined(TARGET_XARCH) || defined(TARGET_ARM64) || defined(TARGET_WASM)
NamedIntrinsic intrinsicId = GetHWIntrinsicId();
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsicId);

Expand Down Expand Up @@ -31104,7 +31104,7 @@ bool GenTreeHWIntrinsic::OperIsMemoryStore(GenTree** pAddr) const
}
}
#endif // TARGET_XARCH
#endif // TARGET_XARCH || TARGET_ARM64
#endif // TARGET_XARCH || TARGET_ARM64 || TARGET_WASM

if (pAddr != nullptr)
{
Expand Down
26 changes: 23 additions & 3 deletions src/coreclr/jit/hwintrinsic.h
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Original file line number Diff line number Diff line change
Expand Up @@ -264,6 +264,8 @@ enum HWIntrinsicFlag : uint64_t
// The intrinsic supports some sort of containment analysis
HW_Flag_SupportsContainment = 0x400,
HW_Flag_ReturnsPerElementMask = 0x800,
// The intrinsic has a required immediate operand
HW_Flag_HasImmediateOperand = 0x1000,
#else
#error Unsupported platform
#endif
Expand Down Expand Up @@ -1003,10 +1005,10 @@ struct HWIntrinsicInfo

static bool HasImmediateOperand(NamedIntrinsic id)
{
#if defined(TARGET_ARM64)
#if defined(TARGET_ARM64) || defined(TARGET_WASM)
const HWIntrinsicFlag flags = lookupFlags(id);
return ((flags & HW_Flag_HasImmediateOperand) != 0);
#elif defined(TARGET_XARCH) || defined(TARGET_WASM)
#elif defined(TARGET_XARCH)
return lookupCategory(id) == HW_Category_IMM;
#else
return false;
Expand Down Expand Up @@ -1329,6 +1331,12 @@ struct HWIntrinsicInfo
*imm1Pos = 3;
break;
}
case NI_PackedSimd_Shuffle:
{
// (v128, v128, lane_imm)
*imm1Pos = 3;
Comment on lines +1336 to +1337
Comment on lines +1336 to +1337
break;
}
default:
{
unreached();
Expand Down Expand Up @@ -1472,7 +1480,12 @@ struct HWIntrinsic final

inline bool needsJumpTableFallback() const
{
return !m_node->GetImmOp()->IsCnsIntOrI();
if (HWIntrinsicInfo::HasImmediateOperand(id))
{
return !m_node->GetImmOp()->IsCnsIntOrI();
}

return false;
}

uint8_t GetImmediateLaneOperand() const
Expand All @@ -1488,6 +1501,13 @@ struct HWIntrinsic final
return static_cast<uint8_t>(lane);
}

simd16_t GetImmediateVecOperand() const
{
GenTree* immOp = m_node->GetImmOp();
assert(immOp->IsCnsVec());
return immOp->AsVecCon()->gtSimdVal;
}

NamedIntrinsic id;
HWIntrinsicCategory category;
GenTree* op1;
Expand Down
44 changes: 38 additions & 6 deletions src/coreclr/jit/hwintrinsiccodegenwasm.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -26,9 +26,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
//
void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
{
// emitIns_Lane
// emitIns_Memarg_Lane

const HWIntrinsic info(node);
genConsumeMultiOpOperands(node);

Expand All @@ -40,7 +37,12 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
{
case HW_Category_SIMD:
{
if ((info.id == NI_PackedSimd_Swizzle) && node->Op(2)->isContained())
if (info.id == NI_PackedSimd_Shuffle)
{
simd16_t shuffleMask = info.GetImmediateVecOperand();
GetEmitter()->emitIns_V128Imm(ins, shuffleMask.u8);
}
else if ((info.id == NI_PackedSimd_Swizzle) && node->Op(2)->isContained())
{
// A constant, fully in-range mask was lowered to an immediate i8x16.shuffle.
// prior codegen left the source on the value stack once (the mask
Expand All @@ -50,7 +52,7 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
GenTree* src = node->Op(1);
regNumber srcReg = GetMultiUseOperandReg(src);
GetEmitter()->emitIns_I(INS_local_get, emitActualTypeSize(src), WasmRegToIndex(srcReg));
GetEmitter()->emitIns_V128Imm(INS_i8x16_shuffle, node->Op(2)->AsVecCon()->gtSimdVal.u8);
GetEmitter()->emitIns_V128Imm(INS_i8x16_shuffle, info.GetImmediateVecOperand().u8);
}
else
{
Expand All @@ -70,6 +72,25 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
}
break;
}
case HW_Category_MemoryStore:
case HW_Category_MemoryLoad:
{
emitAttr elemSize = emitActualTypeSize(node->GetSimdBaseType());
if (info.needsJumpTableFallback())
{
genHWIntrinsicJumpTableFallback(node, info);
}
else if (HWIntrinsicInfo::HasImmediateOperand(info.id))
{
GetEmitter()->emitIns_MemargLane(ins, elemSize, 0, info.GetImmediateLaneOperand());
}
else
{
GetEmitter()->emitIns_I(ins, elemSize, 0);
}

break;
}
default:
{
NYI_WASM_SIMD("CodeGen::genHWIntrinsic: Unsupported category for table-driven intrinsic");
Expand Down Expand Up @@ -142,7 +163,11 @@ void CodeGen::genHWIntrinsicJumpTableFallback(GenTreeHWIntrinsic* node, HWIntrin
int simdSize = node->GetSimdSize();
instruction const ins = HWIntrinsicInfo::lookupIns(info.id, info.baseType, m_compiler);
int immUpperBound = HWIntrinsicInfo::lookupImmUpperBound(info.id, simdSize, info.baseType);
WasmValueType resultType = ActualTypeToWasmValueType(genActualType(node->TypeGet()));
WasmValueType resultType = WasmValueType::Invalid;
if (!node->TypeIs(TYP_VOID))
{
resultType = ActualTypeToWasmValueType(genActualType(node->TypeGet()));
}

GenTree* immOp = node->GetImmOp();
regNumber immReg = GetMultiUseOperandReg(immOp);
Expand Down Expand Up @@ -208,6 +233,13 @@ void CodeGen::genHWIntrinsicJumpTableFallback(GenTreeHWIntrinsic* node, HWIntrin
GetEmitter()->emitIns_Lane(ins, static_cast<uint8_t>(i));
break;
}
case HW_Category_MemoryLoad:
case HW_Category_MemoryStore:
{
emitAttr elemSize = emitActualTypeSize(node->GetSimdBaseType());
GetEmitter()->emitIns_MemargLane(ins, elemSize, 0, static_cast<uint8_t>(i));
break;
}
default:
{
NYI_WASM_SIMD(
Expand Down
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