[RyuJIT Wasm] Handle all codegen cases for PackedSimd.Shuffle#130991
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[RyuJIT Wasm] Handle all codegen cases for PackedSimd.Shuffle#130991adamperlin wants to merge 7 commits into
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Pull request overview
Adds/extends WebAssembly SIMD intrinsic lowering and codegen in CoreCLR RyuJIT, primarily to enable PackedSimd.Shuffle codegen and to move lane load/store intrinsics into the table-driven pipeline.
Changes:
- Add
LowerHWIntrinsicNativeShuffleto supportNI_PackedSimd_Shuffle(emit native shuffle for constant masks; rewrite non-constant masks to swizzle+swizzle+or). - Introduce
HW_Flag_HasImmediateOperandfor WASM and use it to drive lowering/codegen decisions (lane immediates, jump-table fallback, containment). - Reclassify/enable WASM lane load/store intrinsics as
HW_Category_MemoryLoad/MemoryStoreand update codegen +OperIsMemoryLoad/Storeto recognize WASM.
Reviewed changes
Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.
Show a summary per file
| File | Description |
|---|---|
| src/coreclr/jit/lowerwasm.cpp | Adds shuffle lowering; uses HasImmediateOperand to drive immediate-lane lowering and containment. |
| src/coreclr/jit/lower.h | Declares the new WASM lowering helper LowerHWIntrinsicNativeShuffle. |
| src/coreclr/jit/hwintrinsicwasm.cpp | Removes special-import handling for some lane-load intrinsics now handled table-driven; keeps immediate upper-bound logic for lane ops. |
| src/coreclr/jit/hwintrinsiclistwasm.h | Reclassifies lane load/store intrinsics to memory categories; adds immediate-operand flags for relevant intrinsics. |
| src/coreclr/jit/hwintrinsiccodegenwasm.cpp | Emits v128 immediates for shuffle; adds table-driven codegen for WASM memory load/store categories and jump-table support for lane memops. |
| src/coreclr/jit/hwintrinsic.h | Adds WASM HW_Flag_HasImmediateOperand, updates HasImmediateOperand, and adds shuffle imm-op position + immediate vector accessor. |
| src/coreclr/jit/gentree.cpp | Extends OperIsMemoryLoad/OperIsMemoryStore to include WASM. |
| src/coreclr/jit/codegenwasm.cpp | Removes NYI guard for SIMD16 store-indirect to allow emitting stores. |
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| // These intrinsics don't a required immediate operand | ||
| assert(!hasImmOp); |
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| // (v128, v128, lane_imm) | ||
| *imm1Pos = 3; |
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| GenTree* Lowering::LowerHWIntrinsicNativeShuffle(GenTreeHWIntrinsic* node) | ||
| { | ||
| assert(node->GetHWIntrinsicId() == NI_PackedSimd_Shuffle); | ||
|
|
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| GenTree* op1 = node->Op(1); |
| case NI_PackedSimd_LoadScalarVector128: | ||
| case NI_PackedSimd_LoadWideningVector128: | ||
| { | ||
| // These intrinsics don't a required immediate operand |
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| // No extra work to do if the shuffle is a constant vector, it can be contained as an immediate and emitted. | ||
| if (shuffleMask->IsCnsVec()) | ||
| { | ||
| ContainCheckHWIntrinsic(node); | ||
| return node->gtNext; | ||
| } |
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| // (v128, v128, lane_imm) | ||
| *imm1Pos = 3; |
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Stacked on #130822