Skip to content
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 8 additions & 1 deletion src/glayout/pdk/gf180_mapped/gf180_mapped.py
Original file line number Diff line number Diff line change
Expand Up @@ -131,7 +131,14 @@
models={
'nfet': 'nfet_03v3',
'pfet': 'pfet_03v3',
'mimcap': 'mimcap_1p0fF'
# El PDK llama a estos modelos cap_mim_<densidad>fF: 1f0, 1f5 o 2f0.
# 'mimcap_1p0fF' no existe -- prefijo invertido y 'p' por 'f' -- asi que
# el netlist de referencia nombraba un modelo inexistente y el LVS no
# podia emparejarlo con el cap_mim_* que extrae del layout, en ninguna
# celda con condensador. Se conserva la densidad que la intencion
# 2.0 fF/um2, que es lo que asumen las cuatro variantes del runset de LVS
# de proceso, no del generador.
'mimcap': 'cap_mim_2f0fF'
},
layers=LAYER,
pdk_files=pdk_files,
Expand Down
6 changes: 5 additions & 1 deletion src/glayout/primitives/mimcap.py
Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,12 @@ def __generate_mimcap_netlist(pdk: MappedPDK, size: tuple[float, float]) -> Netl
return Netlist(
circuit_name="MIMCap",
nodes = ['V1', 'V2'],
# C-prefix, not X: with `X` the line is a subcircuit call and the LVS
# reader never builds a capacitor device out of it, so the extracted
# MIM has nothing to pair with and shows up as a layout-only device.
# The fets go through the same rewrite in the gf180 LVS runner.
source_netlist=""".subckt {circuit_name} {nodes} l=1 w=1
X1 V1 V2 {model} l={{l}} w={{w}}
C1 V1 V2 {model} l={{l}} w={{w}}
.ends {circuit_name}""",
instance_format="X{name} {nodes} {circuit_name} l={length} w={width}",
parameters={
Expand Down