IQ1_XS, IQ1_XXS, IQ1_XXXS on an upstream base so the nightly can pin them - #91
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Three sub-IQ1_S data types: IQ1_S's algorithm with the codebook the mapping step may choose from cut to a subset of iq1s_grid, and the index stored in fewer bits. IQ1_XS id 64 46 B / 256 1024-entry grid 10-bit index 1.4375 bpw IQ1_XXS id 65 42 B / 256 512-entry grid 9-bit index 1.3125 bpw IQ1_XXXS id 66 38 B / 256 256-entry grid 8-bit index 1.1875 bpw Dequantization is IQ1_S's rule throughout, y[j] = d*(2*ls + 1)*(grid[idx][j] + delta). GGML_TYPE_COUNT is 67; 42..63 are left for upstream, which already uses 42 for Q2_0, so a stock build rejects these files rather than misreading them. CPU, CUDA dequant, MMVQ and MMQ. The MMQ path targets the current ggml_cuda_mmq_util_funcs / ggml_cuda_mmq_config API and registers the types in every per-architecture config table; Blackwell falls through to Ampere and needs none. scripts/iqxs_gen_tables.py regenerates all six codebook tables in ggml-common.h byte-identically from the three committed .npy grids, so the tables are reproducible rather than pasted. Tested on B200, CUDA 13, sm_100. test-backend-ops -o MUL_MAT passes 2/2 backends both default and with GGML_CUDA_FORCE_MMQ=1, 11 cases per type matching IQ1_S. Note the default run never enters the new MMQ kernels, since small n routes to MMVQ.
This was referenced Aug 11, 2026
danielhanchen
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Adds IQ1_XS at 1.4375 bpw, IQ1_XXS at 1.3125 and IQ1_XXXS at 1.1875 to the nightly. Pins #91 rather than #61: same commit content, but on an upstream base, so it merges onto the base tag instead of dragging two months of squash-synced master in behind it. Replayed resolve on b10356 with this set: all four pins merge, tag b10356-mix-1c79028, and the resulting tree hash matches the tree that was built and tested (cdc8f949).
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#92 merged into its stacked base branch rather than master, so the pin landed on prset-drop-merged-26841 and never reached the file the nightly reads. Same one-line addition, on top of master. #91 is merged now, into iq1-narrow-upstream-base rather than master, so the tree resolve builds still does not contain it and the pin is still what puts it in. A merged required pin keeps being mixed in, with a warning, which is the intended path here.
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The first pin for #95 was cut from fork master, whose merge base with the current base tag is from June 10, so merging it dragged in the whole fork/upstream divergence and conflicted across ~1600 files. Rebased the change onto b10359 and repinned to e2e842a. #95 now sits on penalties-upstream-base, matching how #70 and #91 are carried. Verified: all five pins merge onto b10359 in pr-set.json order, #70 via the additive resolver as before, everything else clean.
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Same change as #61, on an upstream base so the nightly can pin it. #61 stays open for review of the design; this is the branch the prebuilds would actually merge.
Why #61 cannot be pinned as it is
resolvemerges every pin onto the upstream base tag, not onto our master. Our master only shares history with upstream up toe95dae18d(2026-06-10), because upstream syncs land as squashes, most recently53fd974b4(Sync master with upstream, #80). #61 branches off that squash, so merging it ontob10356drags two months of upstream work in as fresh additions:The result is hundreds of conflicts in files the change never touches,
tools/ui/,vendor/cpp-httplib/,vendor/sheredom/, all of the "both sides add the same line(s)" shape, andadditive_merge.pyrefuses them, correctly:That is a branch-base problem, not a code problem. #70 avoids it by sitting on an upstream commit and targeting
kimi-k3-text-upstream, and this branch follows the same pattern:iq1-narrow-upstreamisb10356plus the single commit, targetingiq1-narrow-upstream-base, which isb10356untouched.The content is unchanged from #61: 41 files, 2334 insertions, 25 deletions, identical to what #61 reports. Cherry-picking
36fe8e1contob10356applies with zero conflicts, and ontob10356 + 24423 + 25731 + 70also with zero conflicts.Checks on the merged nightly tree
Built the full mix (
b10356+ 24423 + 25731 + 70 + this), CUDAsm_100, on a B200:resolvemerge of all four pinsb10356-mix-e84bfedtest-backend-opshitting the 1500s ctest timeout, run separately belowtest-backend-ops -o MUL_MAT -b CUDA0test-backend-ops -o MUL_MAT_ID -b CUDA0test-quant-type-selectiontest-llama-archsThe three types register in
llama-quantizeat the fork-local ids and quantize and generate end to end on Llama-3.2-1B with an imatrix:Sizes fall in the order the bpw table predicts.
libggml-cpu.soexportsggml_vec_dot_iq1_xs_q8_K,ggml_vec_dot_iq1_xxs_q8_K,ggml_vec_dot_iq1_xxxs_q8_Kand the three grids, and the three CUDA MMQ instances compile.Existing quant types are untouched
Built the identical tree without this commit and requantized the same model from the same imatrix with both binaries. The GGUFs are byte-identical:
DiffusionGemma, Inkling, Kimi-K3 and Muse Glimmer all survive the merge alongside it: every arch registers in
llama-arch.cpp,test-llama-archspasses, and the built libraries export their symbols (libllama.so: diffusion_gemma 17, inkling 24, kimi_k3 23, muse_glimmer 17;libmtmd.so: kimivl 7, muse_glimmer 14), with all fourllama-diffusion-*binaries linking.Pinning
Depends on #90, which drops the merged
26841pin that currently blocks the merge before anything else is reached. Once both are in, the pin url is: