Digital Communication IC Design (2020 Spring)
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Updated
Oct 30, 2020 - Verilog
Digital Communication IC Design (2020 Spring)
UC3M "Técnicas Avanzadas de Tratamiento de Señal y Comunicaciones" Lab Project
Research software and verification results for temporal zero forcing on graphs
A 13-vertex disproof of the Annor–Howerton graph conjecture, with a structural proof, machine-readable witnesses, and exact verification
UC3M "Técnicas Avanzadas de Tratamiento de Señal y Comunicaciones" Lab Project
Add a description, image, and links to the zero-forcing topic page so that developers can more easily learn about it.
To associate your repository with the zero-forcing topic, visit your repo's landing page and select "manage topics."