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Revert "ipc4: handler: maintain IPC set_pipeline_state order" #10868

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Revert "ipc4: handler: maintain IPC set_pipeline_state order" #10868

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c4f093b
ipc4: harden IPC4 pipeline triggering logic
serhiy-katsyuba-intel Jun 10, 2026
c291489
ipc4: assert IPC4 pipeline triggering logic
serhiy-katsyuba-intel Jun 10, 2026
e4ccefa
Revert "ipc4: handler: maintain IPC set_pipeline_state order"
serhiy-katsyuba-intel Jun 10, 2026
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2 changes: 1 addition & 1 deletion src/audio/pipeline/pipeline-graph.c
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Expand Up @@ -369,7 +369,7 @@ static int pipeline_comp_reset(struct comp_dev *current,
* scheduled together, except for IPC4, where each pipeline receives
* commands from the host separately
*/
if (!is_single_ppl && IPC4_MOD_ID(current->ipc_config.id))
if (!is_single_ppl && IS_ENABLED(CONFIG_IPC_MAJOR_4))
return 0;

/* Propagate reset across pipelines only in the same direction
Expand Down
2 changes: 1 addition & 1 deletion src/audio/pipeline/pipeline-params.c
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Expand Up @@ -267,7 +267,7 @@ static int pipeline_comp_prepare(struct comp_dev *current,

if (!comp_is_single_pipeline(current, ppl_data->start)) {
/* ipc4 module is only prepared in its parent pipeline */
if (IPC4_MOD_ID(current->ipc_config.id))
if (IS_ENABLED(CONFIG_IPC_MAJOR_4))
return 0;

/* Propagate prepare only to pipelines in the same direction */
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12 changes: 11 additions & 1 deletion src/audio/pipeline/pipeline-schedule.c
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Expand Up @@ -140,7 +140,7 @@ static enum task_state pipeline_task_cmd(struct pipeline *p,
err = SOF_TASK_STATE_RESCHEDULE;
} else if (p->status == COMP_STATE_PAUSED) {
/* reset the pipeline components for IPC4 after the STOP trigger */
if (cmd == COMP_TRIGGER_STOP && IPC4_MOD_ID(host->ipc_config.id)) {
if (cmd == COMP_TRIGGER_STOP && IS_ENABLED(CONFIG_IPC_MAJOR_4)) {
err = pipeline_reset(host->pipeline, host);
if (err < 0)
reply->error = err;
Expand Down Expand Up @@ -284,6 +284,16 @@ void pipeline_schedule_triggered(struct pipeline_walk_context *ctx,
struct pipeline *p;
uint32_t flags;

#ifdef CONFIG_IPC_MAJOR_4
/*
* With IPC4, each pipeline is triggered separately. Exactly 1 pipeline
* is expected in the pipelines list (it's unclear whether an empty list
* should be tolerated).
*/
assert(list_is_empty(&ctx->pipelines) ||

@lyakh lyakh Jun 12, 2026

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@serhiy-katsyuba-intel have you ever seen empty lists here?

@serhiy-katsyuba-intel serhiy-katsyuba-intel Jun 12, 2026

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No, but the function will work without errors if an empty list is passed as a parameter. So I decided to add this check just to avoid introducing a crash when accessing the first list element without checking whether it exists.

list_item_is_last(ctx->pipelines.next, &ctx->pipelines));
#endif

/*
* Interrupts have to be disabled while adding tasks to or removing them
* from the scheduler list. Without that scheduling can begin
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2 changes: 1 addition & 1 deletion src/audio/pipeline/pipeline-stream.c
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Expand Up @@ -229,7 +229,7 @@ static int pipeline_comp_list(struct comp_dev *current,
* component and we aren't using IPC4. With IPC4 each pipeline receives
* commands separately so we don't need to trigger them together
*/
if (!is_single_ppl && (!is_same_sched || IPC4_MOD_ID(current->ipc_config.id))) {
if (!is_single_ppl && (!is_same_sched || IS_ENABLED(CONFIG_IPC_MAJOR_4))) {
pipe_dbg(current->pipeline,
"current is from another pipeline");
return 0;
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11 changes: 0 additions & 11 deletions src/ipc/ipc4/handler-user.c
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Expand Up @@ -543,17 +543,6 @@ static int ipc4_set_pipeline_state(struct ipc4_message_request *ipc4)
ipc_compound_pre_start(state.primary.r.type);
ret = ipc4_pipeline_trigger(ppl_icd, cmd, &delayed);
ipc_compound_post_start(state.primary.r.type, ret, delayed);
if (delayed) {
/* To maintain pipeline order for triggers, we must
* do a blocking wait until trigger is processed.
* This will add a max delay of 'ppl_count' LL ticks
* to process the full trigger list.
*/
if (ipc_wait_for_compound_msg() != 0) {
ipc_cmd_err(&ipc_tr, "ipc4: fail with delayed trigger");
return IPC4_FAILURE;
}
}
}

if (ret != 0)
Expand Down
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