techomancer · techomancer · Jul 2, 2026 · Jul 1, 2026 · Jul 1, 2026
diff --git a/Cargo.toml b/Cargo.toml
@@ -76,7 +76,7 @@ camera = ["dep:nokhwa", "dep:v4l"]
 # Off by default — enable with `cargo build --features pcap`. Select at runtime
 # with `[network] mode = "pcap"` in iris.toml.
 pcap = ["dep:pcap"]
-# N64 development board IPC bridge: shared-memory RAMROM + cross-process semaphores.
+# N64 development board (Ultra64) — GIO slot 0 + shm IPC.
 ultra64 = ["dep:shared_memory", "dep:raw_sync"]
 
 [dependencies]
@@ -114,6 +114,7 @@ libchdman-rs = { version = "0.287.0-l7", features = ["prebuilt"], optional = tru
 pcap = { version = "2", optional = true }
 shared_memory = { version = "0.12", optional = true }
 raw_sync      = { version = "0.1",  optional = true }
+windows-sys = { version = "0.52", features = ["Win32_System_Threading"] }
 
 [target.'cfg(target_os = "macos")'.dependencies]
 nokhwa = { version = "0.10", features = ["input-avfoundation"], optional = true }

diff --git a/HELP.md b/HELP.md
@@ -15,6 +15,40 @@ Serial ports are on ports 8880 and 8881 (connect to 8881 for IRIX serial term)
 
 ---
 
+## Performance vs inventory (MHz vs MIPS)
+
+IRIX **System Manager** and `hinv` report a **CPU MHz** line (e.g. 166 MHz). That
+is **guest inventory** from the PROM and kernel — not how fast your PC is
+emulating the Indy.
+
+The **iris-gui status bar MIPS** figure (or the CLI window title `MIPS` readout)
+is **real throughput**: MIPS instructions executed per wall-clock second on the
+host. Enable the JIT stack (`IRIS_JIT=1`, `--features jit,rex-jit`) for higher
+MIPS; the hinv MHz string stays the same.
+
+The status bar **Hz** value is the CP0 Compare tick rate (kernel scheduler
+cadence), not CPU MHz.
+
+---
+
+## RAM banks (config vs guest)
+
+`banks` in `iris.toml` / iris-gui is applied only when you **Start** the VM.
+Changing RAM while IRIX is running updates the config but not the live guest —
+**Stop → change banks → Start**.
+
+| Layout | `banks` | Typical guest RAM |
+|--------|---------|-------------------|
+| Authentic Indy max | `[128, 128, 0, 0]` | 256 MB |
+| IRIX 6.5 extended | `[128, 128, 64, 64]` | 384 MB |
+| IRIX 5.3 / emulator max | `[128, 128, 128, 128]` | 512 MB |
+
+If extended himem banks are configured but IRIX still reports 256 MB, check
+monitor `mc status` for MEMCFG on banks 2–3. IRIS synthesizes himem MEMCFG when
+the PROM skips them (see `rules/irix/extended-ram-memcfg.md`).
+
+---
+
 ## First-time setup — Ethernet MAC address
 
 The Indy stores its Ethernet MAC address in NVRAM (the DS1386 RTC chip).  A

diff --git a/README.md b/README.md
@@ -3,12 +3,44 @@ Me and my homies Claude and Gemini present:
 
 # IRIS — Irresponsible Rust IRIX Simulator
 
-An SGI Indy emulator, vibed into existence with Rust and AI assistance.
+An SGI Indy / Indigo2 emulator, vibed into existence with Rust and AI assistance.
 Boots IRIX 6.5 and 5.3. Has networking. Has a framebuffer.
 
 ![IRIS running IRIX 6.5](screen.png)
 
 
+## About this fork
+
+**This repo ([chronic8000/iris](https://github.com/chronic8000/iris)) is actively maintained and
+runs well ahead of the upstream project it was forked from
+([techomancer/iris](https://github.com/techomancer/iris)).** If you landed here from an older
+clone or a third-party release build, check the commit date and the sections below — a lot of
+hardware, GUI, and Windows workflow work lives only on this fork today.
+
+Upstream IRIS is an excellent Indy-focused baseline. **This fork adds:**
+
+| Area | What's new |
+|------|------------|
+| **Platforms** | **Indigo2 IP22** (fullhouse MC/IOC, dual GIO64, Newport XL on GIO) alongside Indy IP24; dual-head GUI preview; IMPACT/MGRAS + XZ/Elan scaffolds |
+| **iris-gui** | Machine profiles, premiere build profile, framebuffer compositor fixes, partial frame upload, serial-console reconnect after Stop→Start, config autosave, extended RAM presets (384/512 MB) |
+| **Graphics / IRQ** | Fullhouse vblank via extio `SG_RETRACE`, VC2 bootstrap for Indigo2, REX3 GFIFO/Graphics IRQ routing, tile dirty rects |
+| **Performance** | HAL2 dedicated pump thread, idle-pause, REX3 SIMD paths, JIT store-isolation branch, status-bar-only idle refresh |
+| **Windows 11** | One-click `.bat` launchers, premiere/JIT workflow, smoke tests, crash capture — see [wsl/README.md](wsl/README.md) |
+| **CI / configs** | `irix-install/*.toml` smoke configs, Indigo2 headless smoke, `tools/tests/indigo2-prom-smoke.yaml` |
+| **Docs / rules** | [docs/indigo2-ip22.md](docs/indigo2-ip22.md), [rules/perf/hardware-profiles.md](rules/perf/hardware-profiles.md), accumulated JIT/irix/snapshot notes under `rules/` |
+
+**Status snapshot (this fork):**
+
+- **Indy IP24** — primary daily-driver; IRIX desktop, X11, networking, JIT all work.
+- **Indigo2 IP22** — boots to serial console; framebuffer/desktop path still in progress (use `console=d` + serial for debugging; see Indigo2 doc).
+- **Upstream** — merge/rebase from `techomancer/iris` as needed; fork-specific work is on `main` here.
+
+Pre-built binaries and the Mac App Store GUI remain at
+[danifunker/iris releases](https://github.com/danifunker/iris/releases) (upstream packaging).
+For **this fork's** latest code, build from source or watch
+[chronic8000/iris](https://github.com/chronic8000/iris).
+
+
 ## Q&A
 
 **Q: What is it?**
@@ -45,7 +77,8 @@ boots to a usable system: shell, networking, X11, the works.
 
 - IRIX 6.5 boots to multiuser, networking works (ping, telnet, ftp)
 - IRIX 5.3 works too
-- X11 / Newport (REX3) graphics works, with mouse and keyboard input
+- **Indy IP24:** X11 / Newport (REX3) graphics works, with mouse and keyboard input
+- **Indigo2 IP22:** hardware emulation + serial boot (see [docs/indigo2-ip22.md](docs/indigo2-ip22.md)); GUI framebuffer still maturing
 - Cranelift JIT compiler for MIPS to x86_64 translation (optional)
 - Copy-on-write disk overlay. Crash all day, base image stays clean
 - Headless mode for CI/automation
@@ -100,6 +133,8 @@ before.
 See [HELP.md](HELP.md) for the full rundown: serial ports, monitor console,
 NVRAM/MAC address setup, disk image prep, and more.
 
+**Windows 11:** full build/launch guide in [wsl/README.md](wsl/README.md).
+
 
 ## PCAP bridged networking (`--features pcap`)
 

diff --git a/TODO.md b/TODO.md
@@ -3,15 +3,15 @@ DONE net - ftp hangs at 48K, examine tcp window handling
 rex
 skip first/last for blocks?
 
-line stipple
+DONE line stipple + lsadvlast (connected I_LINE continuation; rex3.rs pixel_count + setup-on-axis-mismatch)
 
 DONE why is inactive terminal caret slanted and login picture frame too, bresenham innacuracy or something else?
 
 logicop=src fastpath
 
-fract lines
+DONE fract lines (draw_fline + fline_apply_fract)
 
-aa lines
+DONE aa lines (draw_aline + endptfilter / aweight)
 
 DONE dithering
 
@@ -37,15 +37,10 @@ look at ide fpu test, convert to user space test, compile and run on irix, fix f
 watchhi/watchlo register support for debugging, translate variants that fire exception when hit
 
 
-vino — basic pixel pipeline, CDMC stub, and macOS UVC camera capture are
-       in (see [vino] in iris.toml).  Remaining work:
-       - per-port routing via SELECT_D1: today both VINO channels see the
-         same source; the real chip selects between SAA7191 composite (D0)
-         and CDMC IndyCam (D1) per channel
-       - I2C repeated-start so IRIX drivers that skip the subaddr resend
-         for reads (the standard protocol) work without a workaround
-       - end-to-end visual verification under IRIX (needs vl_eoe /
-         vino_eoe / indycam_eoe installed)
+vino — SELECT_D1 per-channel routing + I2C repeated-start in vino.rs.
+       Remaining: CDMC register fidelity beyond basic UYVY tweak;
+       end-to-end visual verification under IRIX (vl_eoe / vino_eoe /
+       indycam_eoe on 5.3 and 6.5) — see rules/irix/vino-verification-checklist.md
 
 DONE scsi - eject, load cd
 

diff --git a/docs/hal2.md b/docs/hal2.md
@@ -277,9 +277,7 @@ Example from Test_Rx_Clock: `IDR0 = 0x213` → channel 3, BRES clock 2, stereo.
   is unlikely to cause failures in practice, but is not strictly correct.
 - **`HAL2_DMA_ENDIAN_W`** — always treated as big-endian (correct default).
 - **`HAL2_RELAY_CONTROL_W`** — headphone relay, no analog hardware to emulate.
-- **Dual-stream quad mode** (`ISR.CODEC_MODE = 1`) — both Codec A and Codec B would
-  need independent output streams running simultaneously.  Currently only Codec A's
-  stream is opened; Codec B input is drained to silence.
+- **Dual-stream quad mode** (`ISR.CODEC_MODE = 1`) — Codec B can open a second cpal stream when quad layout is enabled; rear channels play from Codec B DMA.
 - **AES TX/RX clock locking** — AESRX recovered clock as BRES master (mode `0x2` in
   CTRL1) is not implemented; the emulator falls back to 44100 Hz.
 - **Codec CTRL2 (gain/atten/mute)** — not emulated; all analog processing is bypassed.

diff --git a/docs/impact-mgras-research.md b/docs/impact-mgras-research.md
@@ -0,0 +1,80 @@
+# IMPACT / MGRAS graphics — research notes
+
+IRIS emulates **Newport (REX3)** on Indy and Indigo2 XL paths. IMPACT is a separate
+post-1995 architecture (on-board geometry + TRAM). A **preview register stub** lives in
+`src/mgras.rs` (Wave 5).
+
+## Implementation status (IRIS)
+
+| Component | Status |
+|-----------|--------|
+| `src/mgras.rs` | Preview — per-slot register file, GIO mapping for gfx/exp0/exp1 |
+| `config::ImpactSection` | `[impact]` TOML: `gfx`, `exp0`, `exp1` → `none` / `solid` / `high` / `max` |
+| `physical.rs` | Maps MGRAS stub across populated GIO slots when `profile = indigo2_ip22` |
+| Command processing / TRAM / GL | **Not implemented** |
+| IRIX `impact` driver attach | **Not expected** to reach a working console |
+
+Monitor commands: `mgras` (slot summary), `impact` (hinv-style inventory preview).
+
+Example (preview only — Indigo2 profile):
+
+```toml
+[machine]
+profile = "indigo2_ip22"
+
+[impact]
+gfx = "solid"
+# exp0 = "high"   # second board for High IMPACT
+# exp1 = "max"    # third board for Maximum IMPACT
+```
+
+## Hardware families
+
+| Option | GIO64 slots | Geometry | Texture RAM | IRIX driver class |
+|--------|-------------|----------|-------------|-------------------|
+| Newport XL | 1 | CPU (FPU) | system RAM Z-buffer | `gfx` / REX3 |
+| Solid IMPACT | 1 | on-board GE | TRAM | `impact` / MGRAS |
+| High IMPACT | 2 | on-board GE | TRAM | `impact` |
+| Maximum IMPACT | 3 | dual GE | TRAM | `impact` |
+
+Valid dual-head combos with Newport: Solid+Solid, Solid+High, Solid+Max — not High+High.
+
+## Reference sources
+
+- MAME: `impact.c`, `newport.cpp`, `ip22.cpp` — register maps and IRQ fan-out
+- Linux MIPS: `arch/mips/include/asm/sgi/ip22.h`, `drivers/video/impact`
+- IRIX: `impact` kernel module, `libGL` IMPACT path, `hinv -c graphics`
+- Hardware overview: [Wikipedia SGI Indigo2](https://en.wikipedia.org/wiki/SGI_Indigo2), [sgistuff.net Newport](http://www.sgistuff.net/hardware/graphics/newport.html)
+
+## Estimated emulation scope (if pursued)
+
+1. GIO multi-slot board model + IMPACT PSU/riser constraints
+2. MGRAS geometry engine + raster engine + TRAM ASICs
+3. IRIX PROM revision checks for IMPACT-ready systems
+4. Dual-head policy separate from dual Newport
+
+**Recommendation:** Complete Indigo2 Newport boot + dual-head before pursuing full IMPACT.
+Orders of magnitude more work than REX3.
+
+## Stub register map (`src/mgras.rs`)
+
+Each populated GIO slot exposes an 8 KB window at `slot_base + 0x0F0000` (same offset
+pattern as Newport/XZ until a verified MGRAS map is available):
+
+| Offset | Name | Notes |
+|--------|------|-------|
+| `0x0000` | `BOARD_ID` | ASCII-tagged placeholder per slot kind |
+| `0x0004` | `REVISION` | class revision placeholder |
+| `0x0008` | `STATUS` | idle / FIFO-empty defaults |
+| `0x000C` | `INTR_STATUS` | write-1-to-clear storage |
+| `0x0010` | `INTR_ENABLE` | stored |
+| `0x0018` | `FIFO_WRITE` | accepted, not executed |
+| `0x0024` | `SLOT_ROLE` | slot index (0=gfx, 1=exp0, 2=exp1) |
+
+GIO physical bases (IP22):
+
+| Slot | Range |
+|------|-------|
+| gfx  | `0x1F000000`–`0x1F3FFFFF` |
+| exp0 | `0x1F400000`–`0x1F5FFFFF` |
+| exp1 | `0x1F600000`–`0x1F9FFFFF` |
diff --git a/docs/indigo2-ip22.md b/docs/indigo2-ip22.md
@@ -0,0 +1,66 @@
+# Indigo2 IP22
+
+Select in the GUI (**Platform → SGI Indigo2 (IP22)**) or set:
+
+```toml
+[machine]
+profile = "indigo2_ip22"
+```
+
+No separate build is required — the same `iris` / `iris-gui` binary supports Indy IP24 and Indigo2 IP22.
+
+## Hardware deltas vs Indy IP24
+
+| Item | Indy (Guinness) | Indigo2 (fullhouse) |
+|------|-----------------|---------------------|
+| MC SYSID | `0x00000013` | `0x00000010` |
+| MC GIO64_ARB ONE_GIO | set (`0x400`) | clear (dual GIO64 bus) |
+| IOC sys_id | `0x26` | `0x11` |
+| MAP bits 6–7 | GIO expansion IRQs | GFX DRAIN0/1 feedback |
+| Primary vblank IRQ | L1 `VERTICAL_RETRACE` (extio `SG_RETRACE` on fullhouse) | same — MAP `GFX_DRAIN0` is FIFO drain only |
+| Graphics | Integrated Newport @ `0x1F000000` | XL card in GIO slot (same REX3 stack) |
+| Audio | HAL2 (shared A2 architecture) | HAL2 |
+
+## Boot checklist
+
+1. Build: `cargo build --release --features lightning,rex-jit` (same as Indy)
+2. **Stop → Start** after changing platform (cold start picks up IRQ + VC2 bootstrap)
+3. Monitor `mc status` → SYSID `00000010`, GIO64_ARB without `0x400`
+3. Monitor `ioc status` → `sys_id=11`, `gc_select`/`extio` visible on fullhouse
+4. Guest `hinv` → one XL graphics board (embedded Indy PROM may mis-report inventory)
+5. X11 login on primary head (`/dev/gfx` / head 0)
+
+With **Guest** display resolution, iris bootstraps **1280×1024** on fullhouse at Start so the GUI shows a framebuffer before IRIX programs VC2 (embedded Indy PROM often delays or skips gfx init on Indigo2-class hardware).
+
+6. Dual-head (`graphics.heads = 2`): guest `hinv` shows two XL boards; iris-gui shows side-by-side heads; CI `screenshot` accepts `"head": 0` or `1`
+
+## Headless smoke (CI)
+
+```powershell
+iris.exe --config irix-install/iris-indigo2-smoke-ci.toml
+iris-ci ping
+# monitor: mc status → SYSID 00000010
+```
+
+## Dual-head Newport
+
+```toml
+[graphics]
+heads = 2
+```
+
+Second REX3 maps at GIO slot 1 (`0x1F600000`). Snapshots include `rex3_head1.bin` and `rex3_head1_rgb.bin` / `rex3_head1_aux.bin`.
+
+Head 0 vblank → `VerticalRetrace` (Indy direct L1; fullhouse via extio `SG_RETRACE`). Head 1 vblank → `GioExp1` (Indy) or `GioExp0Retrace` / extio `S0_RETRACE` (fullhouse dual-head).
+
+## IRQ routing (fullhouse)
+
+Shared GIO interrupt lines (FIFO full, graphics, retrace) are latched in the IOC `extio` shadow and muxed by `gc_select` bit 0 (0 = graphics/SG slot, 1 = expansion S0). MAP bits 6–7 carry GFX drain feedback for Newport heads.
+
+## Not implemented
+
+- IMPACT / MGRAS preview stub (`src/mgras.rs`, `[impact]` config) — see `docs/impact-mgras-research.md`
+- Full EXTIO bus-error and EISA interrupt paths
+- Indigo2-specific PROM (embedded Indy PROM may need replacement for inventory)
+
+See also [`docs/interrupt_map.md`](interrupt_map.md) and [`rules/gui/machine-profile-vs-guest-ip22.md`](../rules/gui/machine-profile-vs-guest-ip22.md).