UART-Project

Universal Asynchronous Receiver-Transmitter. Semester project of Digital Logic and System Design course of fall 2017, IIT Delhi.

Name		Name	Last commit message	Last commit date
Latest commit History 13 Commits
Mini Project report 3.docx		Mini Project report 3.docx
Mini-Project Question statement.txt		Mini-Project Question statement.txt
New Doc 2017-11-06_1.jpg		New Doc 2017-11-06_1.jpg
New Doc 2017-11-06_2.jpg		New Doc 2017-11-06_2.jpg
New Doc 2017-11-06_3.jpg		New Doc 2017-11-06_3.jpg
README.md		README.md
UART.xdc		UART.xdc
UART_main.bit		UART_main.bit
UART_main.vhd		UART_main.vhd
lab4_seven_segment_display.vhf		lab4_seven_segment_display.vhf
mini_project_uart_RX.vhd		mini_project_uart_RX.vhd
mini_project_uart_TB.vhd		mini_project_uart_TB.vhd
mini_project_uart_TX.vhd		mini_project_uart_TX.vhd
project-report.md		project-report.md
~$ni Project report 3.docx		~$ni Project report 3.docx

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