arm64: dts: qcom: Shikra Ethernet enablement (EMAC0/EMAC1)ernet dt#1318
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arm64: dts: qcom: Shikra Ethernet enablement (EMAC0/EMAC1)ernet dt#1318ayaan-anwar wants to merge 4 commits into
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qli-2.0 GA Critical Fix |
Add device tree nodes for the two Gigabit Ethernet controllers (ethernet0 at 0x5d00000, ethernet1 at 0x5d20000) present on Shikra. Each node includes: - Register map for the GMAC core and RGMII IO-macro - GIC interrupt - Seven-clock list: stmmaceth/pclk/ptp_ref/rgmii and the three NOC clocks (axi, axi-noc, pcie-tile-axi-noc); the AXI clock is listed twice as required by the qcom,shikra-ethqos binding - Power domain and reset via the EMAC GDSCs - IOMMU mapping through apps_smmu - Interconnect paths for CPU→config and MAC→DRAM traffic - TSO, 32-descriptor prefetch burst, and 8 KiB TX/RX FIFOs Both nodes are left disabled; board files enable them and supply the PHY handle, pin-control, and queue-configuration. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Enable the first Gigabit Ethernet controller on the Shikra CQM EVK. Add: - Fixed regulator for the PHY power supply rail (GPIO 149, active-high) with its pinctrl state - Pin-control state for the RGMII RX/TX data+clock and MDIO bus (GPIOs 121-134) - ethernet0 overlay: PHY at MDIO address 7, rgmii-id mode, GPIO 120 interrupt, GPIO 135 reset, and a single TX/RX queue configuration Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Enable the first Gigabit Ethernet controller on the Shikra CQS EVK. The board layout is identical to the CQM EVK for ethernet: PHY power rail on GPIO 149, RGMII data/clock/MDIO on GPIOs 121-134, PHY at MDIO address 7 with GPIO 120 interrupt and GPIO 135 reset. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Enable both Gigabit Ethernet controllers on the Shikra IQS EVK. The IQS EVK populates both EMAC instances with a dedicated PHY and power rail on each port: EMAC0 (ethernet0): - PHY power rail on GPIO 66 (active-high) - RGMII RX/TX data+clock: GPIOs 121-132, MDIO: GPIOs 133-134 - PHY at MDIO address 7, GPIO 135 reset EMAC1 (ethernet1): - PHY power rail on GPIO 53 (active-high) - RGMII RX/TX data+clock: GPIOs 137-148, MDIO: GPIOs 149-150 - PHY at MDIO address 7, GPIO 151 reset Both ports use rgmii-id mode and a single TX/RX queue configuration. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
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This series adds device tree support for the Qualcomm Shikra SoC Ethernet controllers and enables EMAC instances across Shikra EVKs.
Summary of changes
Base SoC support
ethernet0andethernet1nodes inshikra.dtsiethernet0:0x5d00000ethernet1:0x5d20000Board enablement
Shikra CQM EVK
EMAC0rgmii-idmodeShikra CQS EVK
EMAC0Shikra IQS EVK
EMAC0
EMAC1
PHY power: GPIO 53 (active-high)
RGMII + MDIO: GPIOs 137–150
PHY @ addr 7, reset GPIO 151
Both ports:
rgmii-idResult