FEAT-050 (v3.0): tool-qualification dossier (DO-330 TQL-5 / ISO 26262-8 §11)

[avrabe]

The G-005 capstone (CA-011). docs/qualification-dossier-v1.md maps every
DO-330 TQL-5 objective and every ISO 26262-8:2018 §11 (TCL) objective to a
concrete scry artifact — a mechanized proof, a runnable test, a CI gate, or an
explicit scope statement.

Honesty-first (the roadmap audit's mandate)

• §4 mechanized inventory names all 17 admit-free Rocq proofs + the semantic
  Verus join proof, each re-checked by bazel test in CI. Evidence that is
  test-/γ-sweep-validated but not machine-proven (MC/DC, the value-level
  transfers, float rounding) is labelled as such — never as mechanized.
• §5 scope/limitation is fed by the FEAT-040 gap report (the per-artifact
  conservative-site oracle) + each domain's known precision limits.
• §6 honesty notes record the deltas: REQ-002 is now literally true for
  i32.add (WrapAdd.v) but not tool-wide; float rounding is γ-sweep not
  Rocq; the Verus join proof's false-then-repaired history is recorded.
• §7 ISO 26262-8 derives TCL1 (TI2 × TD1) with the proof + MC/DC +
  per-release falsification-statement argument for TD1.

Depends on the substance (FEAT-045/046/048) having shipped — it has. Doc +
roadmap status only; rivet validate PASS.

🤖 Generated with Claude Code

[github-actions]

📐 rivet artifact delta

PR: #89 Base SHA: 13091c6c

Validation

head — `rivet validate` result

      → a `sw-integration-verification` `verifies` `sw-arch-component` or `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-arch-component` or `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `sw-integration-verification`
      → a `unit-verification` `verifies` `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `unit-verification`
  SR-7 (sw-req, status: accepted) — missing: sw-integration-verification, unit-verification
      → a `sw-integration-verification` `verifies` `sw-arch-component` or `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-arch-component` or `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `sw-integration-verification`
      → a `unit-verification` `verifies` `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `unit-verification`
  SR-8 (sw-req, status: accepted) — missing: sw-integration-verification, unit-verification
      → a `sw-integration-verification` `verifies` `sw-arch-component` or `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-arch-component` or `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `sw-integration-verification`
      → a `unit-verification` `verifies` `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `unit-verification`
  SR-9 (sw-req, status: accepted) — missing: sw-integration-verification, unit-verification
      → a `sw-integration-verification` `verifies` `sw-arch-component` or `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-arch-component` or `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `sw-integration-verification`
      → a `unit-verification` `verifies` `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `unit-verification`
  SYS-1 (system-req, status: accepted) — missing: sys-integration-verification
  SYS-2 (system-req, status: accepted) — missing: sys-integration-verification
  SYS-3 (system-req, status: accepted) — missing: sys-integration-verification
  SYS-4 (system-req, status: accepted) — missing: sys-integration-verification
  SYS-5 (system-req, status: accepted) — missing: sys-integration-verification
  → run `rivet validate --explain SR-1` to see which link type and source types satisfy a gap

Result: PASS (80 warnings)
Schemas: common@0.3.0 (embedded), dev@0.2.0 (embedded), research@0.1.0 (embedded), research-ext@0.1.0 (on-disk), safety-case@0.1.0 (embedded), aspice@0.2.0 (embedded)

base — `rivet validate` result (for comparison)

      → a `sw-integration-verification` `verifies` `sw-arch-component` or `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-arch-component` or `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `sw-integration-verification`
      → a `unit-verification` `verifies` `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `unit-verification`
  SR-7 (sw-req, status: accepted) — missing: sw-integration-verification, unit-verification
      → a `sw-integration-verification` `verifies` `sw-arch-component` or `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-arch-component` or `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `sw-integration-verification`
      → a `unit-verification` `verifies` `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `unit-verification`
  SR-8 (sw-req, status: accepted) — missing: sw-integration-verification, unit-verification
      → a `sw-integration-verification` `verifies` `sw-arch-component` or `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-arch-component` or `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `sw-integration-verification`
      → a `unit-verification` `verifies` `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `unit-verification`
  SR-9 (sw-req, status: accepted) — missing: sw-integration-verification, unit-verification
      → a `sw-integration-verification` `verifies` `sw-arch-component` or `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-arch-component` or `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `sw-integration-verification`
      → a `unit-verification` `verifies` `sw-detail-design`, not `sw-req` directly — add an intermediate `sw-detail-design` that traces to this artifact and is `verifies`-linked by the `unit-verification`
  SYS-1 (system-req, status: accepted) — missing: sys-integration-verification
  SYS-2 (system-req, status: accepted) — missing: sys-integration-verification
  SYS-3 (system-req, status: accepted) — missing: sys-integration-verification
  SYS-4 (system-req, status: accepted) — missing: sys-integration-verification
  SYS-5 (system-req, status: accepted) — missing: sys-integration-verification
  → run `rivet validate --explain SR-1` to see which link type and source types satisfy a gap

Result: PASS (80 warnings)
Schemas: common@0.3.0 (embedded), dev@0.2.0 (embedded), research@0.1.0 (embedded), research-ext@0.1.0 (on-disk), safety-case@0.1.0 (embedded), aspice@0.2.0 (embedded)

Artifact stats

	base	head
Total artifacts	203	203

full stats — head

Artifact summary:
  academic-reference               24
  competitive-analysis             11
  design-decision                  17
  feature                          58
  market-finding                    7
  requirement                      17
  safety-context                    3
  safety-goal                       5
  safety-justification              3
  safety-solution                   6
  safety-strategy                   1
  stakeholder-req                   3
  sw-req                           13
  sw-verification                  13
  sys-verification                  5
  system-req                        5
  technology-evaluation            12
  TOTAL                           203

Orphan artifacts (no links): 11
  CA-001
  CA-002
  CA-003
  CA-004
  CA-005
  CA-006
  CA-007
  CA-008
  CA-009
  CA-010
  CA-011

Diagnostics: 0 error(s), 80 warning(s), 16 info(s)

Diff (base → head)

~ FEAT-050
  status: - proposed -> + accepted

0 added, 0 removed, 1 modified, 202 unchanged

AADL model — head

spar/scry.aadl: OK

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Posted by the rivet-delta workflow. Informational only — does not gate the PR.