Perf(l2-swimlane): drop per-task wmb in AICPU complete_task

[ChaoWao]

What

l2_swimlane_aicpu_complete_task issued one wmb() (ARM64 dsb st) per
AICPU task record, right after l2_swimlane_buf->count = new_count. This
removes it — it is the only record-writer on the AICPU collector still doing a
per-record barrier.

Why it's safe

The host never reads an AicpuTask buffer until the AICPU publishes it to
the per-thread ready queue. Both publication paths — rotation
(switch_records_buffer) and end-of-run flush (l2_swimlane_aicpu_flush) —
funnel through L2SwimlaneTaskEngine::enqueue_ready
(profiler_device_engine.h), which already issues wmb() (dsb st) before
the ready-queue tail advance. That barrier drains the record + count stores
of every buffer before the tail the host polls (with rmb()). The AICore never
reads the AicpuTask buffer (it owns a separate pool), so there is no
concurrent observer between complete_task returning and publication.

The phase-record and aicore_rotate paths already defer their barrier
to publication — this makes the task-record path uniform with them
(complete_task was the outlier).

Why now (and the honest caveat on benefit)

The benefit is below the hardware noise floor — this is a uniformity
cleanup, not a measured speedup. Back-of-envelope ≈ 30 ns × N-records, swamped
by per-iteration variance; the AICPU dsb st is the cheaper of swimlane's two
per-record barriers (the load-bearing one is the AICore-side per-record
write-back, which is not removable — AICore cache is non-coherent with the
consumer).

This exact change was investigated in 2026-06 and dropped as "no win above
noise". It is re-landed here for uniformity; docs/investigations/2026-06-l2-swimlane-defer-wmb.md
is updated in this PR (verdict → landed) with the full rationale, per the
repo's investigation-tracking rule. Note the code was since unified into
src/common/... (#1262) so, unlike the 2026-06 3-hunk patch, only the removal
is needed — the publication barrier already lives in enqueue_ready.

Validation

• Onboard a2a3 (task-submit, device 4): tests/st/a2a3/tensormap_and_ringbuffer/dfx/l2_swimlane
  at @scene_test(level=2) — the level where complete_task runs and writes
  the AICPU task record. 2 passed. The DFX suite validates record-count
  reconciliation (no silent loss), which is exactly what a missing barrier would
  break.
• Equivalent change was also validated onboard at level 4 in the 2026-06
  investigation.

Risk note

A sibling barrier change (hoisting wmb across distinct tasks in one pop) once
caused a spmd_sync_start_stress 507018 drain-barrier hang (see
docs/investigations/2026-06-cross-task-batched-publish.md). This change is
narrower — a single per-record barrier whose only observer publishes through its
own barrier — and was validated onboard as above.

🤖 Generated with Claude Code

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📝 Walkthrough

Walkthrough

This PR removes the per-record wmb() call from l2_swimlane_aicpu_complete_task in the AICPU collector, relying instead on the barrier already provided by the enqueue_ready_buffer publication path. The accompanying investigation doc is updated with rationale and re-validation caveats.

Changes

Barrier Removal and Rationale

Layer / File(s)	Summary
Remove per-record wmb() in complete_task src/common/platform/shared/aicpu/l2_swimlane_collector_aicpu.cpp	The wmb() call after updating the task record and buffer count is removed, with comments added stating the enqueue_ready_buffer publication path already provides the required store ordering.
Update investigation doc rationale docs/investigations/2026-06-l2-swimlane-defer-wmb.md	The header verdict is replaced with a "landed for uniformity" update explaining the barrier removal, a section on collector unification and publication funneling through L2SwimlaneTaskEngine::enqueue_ready, a reaffirmed correctness argument on enqueue/host ordering, and a carried-forward caution note requiring onboard re-validation before merge.

Estimated code review effort: 3 (Moderate) | ~20 minutes

Possibly related PRs

• hw-native-sys/simpler#942: Refactors the same l2_swimlane_aicpu_complete_task/buffer publication logic in l2_swimlane_collector_aicpu.cpp.
• hw-native-sys/simpler#1293: Introduces the ACK-gated buffer publication/ready-queue enqueue flow this PR's barrier removal now relies upon.

Poem

A wmb once stood in the way,
guarding stores each busy day.
Now enqueue_ready takes the load,
one barrier tames the whole road.
This rabbit hops, docs in tow,
re-validate, then off we go! 🐇📄

🚥 Pre-merge checks | ✅ 5

✅ Passed checks (5 passed)

Check name	Status	Explanation
Title check	✅ Passed	It clearly summarizes the main change: removing the per-task wmb in AICPU complete_task for l2-swimlane.
Description check	✅ Passed	It directly describes the code change, rationale, and validation, and is clearly related to the changeset.
Docstring Coverage	✅ Passed	No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.

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[gemini-code-assist]

Code Review

This pull request removes the per-task 'wmb()' write memory barrier from the commit fast path in 'l2_swimlane_aicpu_complete_task' to improve uniformity across the collector paths, as the barrier is already handled during publication in 'enqueue_ready()'. The documentation in 'docs/investigations/2026-06-l2-swimlane-defer-wmb.md' has been updated to reflect this decision and its correctness. There are no review comments, so no feedback is provided.

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