[WIP] feat(kernels): thread runtime lane id into TPipe via setSubBlockId#1241
[WIP] feat(kernels): thread runtime lane id into TPipe via setSubBlockId#1241yanghaoran29 wants to merge 1 commit into
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Under simpler PTO2 dispatch the CCE sub-block register is not programmed, so get_subblockid() returns 0 for both AIV lanes and TILE_UP_DOWN auto-split picks the wrong ring-buffer half. Replace direct get_subblockid() reads and manual cons/prod.setEntryOffset(lane * tile_bytes) workarounds with TPipe::setSubBlockId(get_sub_block_id(args)) from pto-isa PR hw-native-sys#186. Kernel changes (4 files): - examples/a5/.../bgemm/kernels/mix/kernel_bgemm.cpp get_subblockid() -> get_sub_block_id(args) + mPipe.setSubBlockId; +intrinsic.h - examples/a2a3/.../qwen3_14b_decode/kernels/aiv/fa_fused_aiv.cpp v36 setEntryOffset workaround -> v36.setSubBlockId(sub_block_id) - examples/a2a3/.../qwen3_14b_decode/kernels/aic/fa_fused_aic.cpp dead __DAV_VEC__ block: sub_block_id param + setSubBlockId (consistency only) - tests/st/a2a3/.../spmd_paged_attention/.../paged_attention_parallel.cpp sij/pij/oi pipe setEntryOffset workaround -> setSubBlockId(sub_block_id) Excluded per instruction: src/{a2a3,a5}/platform/onboard/aicore/kernel.cpp. Onboard 3-state verification (pto-isa 5d211ba8, task-submit): - a2a3 qwen3_14b_decode: A PASS / B FAIL (k_cache max_diff=nan) / C PASS - a5 bgemm: A PASS / B PASS / C PASS Execution plan and verification report are kept outside this repo: ../setsubblockid_plan.md, ../setsubblockid_verify_report.md
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📝 WalkthroughWalkthroughMultiple AIC/AIV kernel files switch from internally querying the sub-block id via get_subblockid() to threading a runtime-provided sub_block_id (or derived from args) into TPipe objects via setSubBlockId(), replacing prior manual cons/prod entry-offset computations for GM ring-buffer/lane placement. ChangesRuntime sub-block id propagation
Estimated code review effort: 3 (Moderate) | ~25 minutes Possibly related PRs
Suggested labels: Poem
🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
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Related Sample Test ResultsThe table below summarizes the actual measured results of all executed test cases under the three-state verification matrix. Status code definitions: Definition of Three-State Versions (Logic varies slightly across test cases)
Summary Table of Three-State Test Results
Fix Description of Original Markdown Errors
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Code Review
This pull request refactors how the AIV lane/sub-block ID is handled across several kernels, including Qwen3 decode, BGEMM, and SPMD paged attention. Instead of relying on the hardware get_subblockid() (which can be stale or 0 in certain runtimes) or manually calculating entry offsets, the runtime-provided sub-block ID is now threaded directly into the TPipe instances using setSubBlockId(). This allows the library's TILE_UP_DOWN auto-split mechanism to correctly place each lane in its own GM ring-buffer half. I have no feedback to provide as there are no review comments.
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Under simpler PTO2 dispatch the CCE sub-block register is not programmed, so get_subblockid() returns 0 for both AIV lanes and TILE_UP_DOWN auto-split picks the wrong ring-buffer half. Replace direct get_subblockid() reads and manual cons/prod.setEntryOffset(lane * tile_bytes) workarounds with TPipe::setSubBlockId(get_sub_block_id(args)) from pto-isa PR #186.
Kernel changes (4 files):
Excluded per instruction: src/{a2a3,a5}/platform/onboard/aicore/kernel.cpp.
Onboard 3-state verification (pto-isa 5d211ba8, task-submit):
Execution plan and verification report are kept outside this repo:
../setsubblockid_plan.md, ../setsubblockid_verify_report.md