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Request IEEE fp32 division for SYCL kernels #752

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Merged
sayakpaul merged 4 commits into from
Aug 13, 2026
Merged

Request IEEE fp32 division for SYCL kernels #752

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9782793
Request IEEE fp32 division for SYCL kernels
jiqing-feng Aug 10, 2026
504cafb
Merge branch 'main' into xpu-fp32-prec-div
jiqing-feng Aug 10, 2026
c3ad81a
Merge branch 'main' into xpu-fp32-prec-div
sayakpaul Aug 13, 2026
83200df
Merge branch 'main' into xpu-fp32-prec-div
sayakpaul Aug 13, 2026
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6 changes: 4 additions & 2 deletions kernel-builder/src/pyproject/templates/torch/preamble.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -205,8 +205,10 @@ elseif(GPU_LANG STREQUAL "SYCL")
endif()


set(sycl_link_flags "-Wl,-z,noexecstack;-fsycl;--offload-compress;-fsycl-targets=spir64_gen,spir64;-Xs;-device pvc,xe-lpg,ats-m150 -options ' -cl-intel-enable-auto-large-GRF-mode -cl-poison-unsupported-fp64-kernels -cl-intel-greater-than-4GB-buffer-required';")
set(sycl_flags "-fPIC;-fsycl;-fhonor-nans;-fhonor-infinities;-fno-associative-math;-fno-approx-func;-fno-sycl-instrument-device-code;--offload-compress;-fsycl-targets=spir64_gen,spir64;")
# -foffload-fp32-prec-* keeps fp32 division and sqrt IEEE correctly rounded,
# matching PyTorch; both the compile and the link step need them.
set(sycl_link_flags "-Wl,-z,noexecstack;-fsycl;--offload-compress;-foffload-fp32-prec-div;-foffload-fp32-prec-sqrt;-fsycl-targets=spir64_gen,spir64;-Xs;-device pvc,xe-lpg,ats-m150 -options ' -cl-intel-enable-auto-large-GRF-mode -cl-poison-unsupported-fp64-kernels -cl-intel-greater-than-4GB-buffer-required';")
set(sycl_flags "-fPIC;-fsycl;-fhonor-nans;-fhonor-infinities;-fno-associative-math;-fno-approx-func;-foffload-fp32-prec-div;-foffload-fp32-prec-sqrt;-fno-sycl-instrument-device-code;--offload-compress;-fsycl-targets=spir64_gen,spir64;")
set(GPU_FLAGS "${sycl_flags}")


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6 changes: 4 additions & 2 deletions kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -136,8 +136,10 @@ elseif(GPU_LANG STREQUAL "SYCL")
message(STATUS "Using Intel SYCL C++ compiler: ${ICPX_COMPILER} and C compiler: ${ICX_COMPILER} Version: ${DPCPP_VERSION}")
endif()

set(sycl_link_flags "-Wl,-z,noexecstack;-fsycl;--offload-compress;-fsycl-targets=spir64_gen,spir64;-Xs;-device pvc,xe-lpg,ats-m150 -options ' -cl-intel-enable-auto-large-GRF-mode -cl-poison-unsupported-fp64-kernels -cl-intel-greater-than-4GB-buffer-required';")
set(sycl_flags "-fPIC;-fsycl;-fhonor-nans;-fhonor-infinities;-fno-associative-math;-fno-approx-func;-fno-sycl-instrument-device-code;--offload-compress;-fsycl-targets=spir64_gen,spir64;")
# -foffload-fp32-prec-* keeps fp32 division and sqrt IEEE correctly rounded,
# matching PyTorch; both the compile and the link step need them.
set(sycl_link_flags "-Wl,-z,noexecstack;-fsycl;--offload-compress;-foffload-fp32-prec-div;-foffload-fp32-prec-sqrt;-fsycl-targets=spir64_gen,spir64;-Xs;-device pvc,xe-lpg,ats-m150 -options ' -cl-intel-enable-auto-large-GRF-mode -cl-poison-unsupported-fp64-kernels -cl-intel-greater-than-4GB-buffer-required';")
set(sycl_flags "-fPIC;-fsycl;-fhonor-nans;-fhonor-infinities;-fno-associative-math;-fno-approx-func;-foffload-fp32-prec-div;-foffload-fp32-prec-sqrt;-fno-sycl-instrument-device-code;--offload-compress;-fsycl-targets=spir64_gen,spir64;")
set(GPU_FLAGS "${sycl_flags}")

add_compile_definitions(XPU_KERNEL)
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