Implement wasm codegen for sub-16 SIMD load/store by tannergooding · Pull Request #131000 · dotnet/runtime

tannergooding · 2026-07-17T21:45:17Z

Vector2 (TYP_SIMD8) and Vector3 (TYP_SIMD12) have no native wasm valtype, so they live as a v128 with the low 8/12 bytes populated. Previously the wasm JIT bailed out via the ins_Load/ins_Store NYIs for these types; this implements the split lane load/store sequences instead.

The emitted sequences are:

simd8 load: v128.load64_zero 0
simd8 store: v128.store64_lane 0, lane 0
simd12 load: local.get addr; v128.load64_zero 0; v128.load32_lane 8, lane 2
simd12 store: tee the value into a v128 temporary, v128.store64_lane 0, lane 0 for the low 8 bytes, then re-materialize the address and v128.store32_lane 8, lane 2 for the upper 4 bytes

v128.load64_zero fills lanes 0-1 (zeroing the rest); the trailing lane store/load handles bytes 8-11 for the Vector3 case.

The TYP_SIMD12 address is forced multiply-used (loads and heap stores re-materialize it for the trailing lane op). The local-to-stack store rewrite (RewriteLocalStackStore) produces a STOREIND(LCL_ADDR, value) whose address is a re-materializable GT_LCL_ADDR, so that case is excluded from multiply-use and codegen re-emits the frame pointer directly. Because that synthesized STOREIND is not revisited by the main collection walk, its internal v128 tee register is requested in RewriteLocalStackStore.

Measured on the corelib crossgen2 browser SuperPMI collection (27,540 contexts): hard asserts drop from 403 to 30, eliminating 373 SIMD8/SIMD12 load/store asserts with no regressions. The residual 30 are the pre-existing NYIRAW oper catch-all, unrelated to this change.

Full effectiveness requires #130866 (which removes the shadowing SIMD-ABI bailouts for SIMD params/locals/stores/call-args); standalone, this change already clears the 373 asserts above on that collection.

Note

This PR description was drafted with the assistance of GitHub Copilot.

Vector2 (TYP_SIMD8) and Vector3 (TYP_SIMD12) have no native wasm valtype, so they live as a v128 with the low 8/12 bytes populated. Emit the split lane loads/stores instead of bailing out via the ins_Load/ins_Store NYIs. Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com>

azure-pipelines · 2026-07-17T21:46:04Z

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dotnet-policy-service · 2026-07-17T21:46:29Z

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
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Copilot

Pull request overview

This PR extends the WASM JIT’s SIMD codegen to handle sub-16-byte SIMD memory operations by emitting lane-based load/store sequences for TYP_SIMD8 (Vector2) and TYP_SIMD12 (Vector3), and updates lowering/regalloc to ensure required multi-use addressing and internal v128 temporaries are available.

Changes:

Add SIMD8 load support via v128.load64_zero and route SIMD12 loads/stores through new split-lane helper sequences in WASM codegen.
Force multiply-use of SIMD12 addresses in lowering where codegen needs to re-materialize/re-push the address.
Ensure regalloc requests an internal v128 temp for SIMD12 stores (including the local-to-stack store rewrite path).

Show a summary per file

File	Description
src/coreclr/jit/regallocwasm.cpp	Requests an internal v128 register for SIMD12 store indirections (including rewrite-introduced STOREIND).
src/coreclr/jit/lowerwasm.cpp	Forces multiply-use of SIMD12 indir addresses when codegen needs to reuse/re-materialize them.
src/coreclr/jit/instr.cpp	Implements `ins_Load(TYP_SIMD8)` as `INS_v128_load64_zero` for WASM.
src/coreclr/jit/codegenwasm.cpp	Implements split-lane load/store sequences for SIMD12 and lane store for SIMD8 storeind; adds helper routines.

Copilot's findings

Files reviewed: 4/4 changed files
Comments generated: 2

Casting the frame offset to unsigned before passing it as a wasm memarg defeated the emitter's offset >= 0 invariant, silently turning an unexpected negative offset into a large positive one. Compute a signed offset and noway_assert it, matching emitter::emitIns_S. Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com>

Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com>

Copilot

Copilot's findings

Files reviewed: 4/4 changed files
Comments generated: 0 new

Copilot

Copilot's findings

Files reviewed: 4/4 changed files
Comments generated: 4

Assert the wasm frame address is FP-based before re-emitting the frame pointer in the simd12 lane helpers, matching the block-copy codegen. Update the multiply-use DEBUGARG reasons since simd12 now forces it regardless of faulting. Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com>

Copilot

Copilot's findings

Files reviewed: 4/4 changed files
Comments generated: 1

lewing · 2026-07-18T00:38:52Z

End-to-end validation on the wasm R2R prototype tree (which actually runs wasm R2R crossgen, complementary to the SuperPMI assert numbers):

Stacked this on #130866 with a matched crossgen2 + wasm cross-jit and crossgen'd the built JIT/Regression SIMD tests with no punt flags:

9/23 → 21/23 previously-failing SIMD tests now crossgen clean. All 12 sub-16 SIMD8/SIMD12 load/store cases clear.
Emitted sequences confirmed: Vector2 → v128.load64_zero / store64_lane; Vector3 → load64_zero + load32_lane (and the tee'd store64_lane + store32_lane).

The 2 still-failing are unrelated to this PR: one harness/reference artifact, and one nested try/catch-with-filter EH case (Runtime_129972.M()) that asserts in fgwasm.cpp BBF_CATCH_RESUMPTION — separate wasm EH work.

LGTM from the end-to-end side.

Note

This comment (and its validation run) was generated with GitHub Copilot.

lewing

LGTM

Copilot AI review requested due to automatic review settings July 17, 2026 21:45

github-actions Bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jul 17, 2026

dotnet-policy-service Bot assigned tannergooding Jul 17, 2026

Copilot started reviewing on behalf of tannergooding July 17, 2026 21:45 View session

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Copilot AI review requested due to automatic review settings July 17, 2026 22:04

Copilot started reviewing on behalf of tannergooding July 17, 2026 22:04 View session

Reword the simd12 load note to not reference genConsumeAddress

0475c66

Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com>

Copilot AI reviewed Jul 17, 2026

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Copilot AI review requested due to automatic review settings July 17, 2026 22:14

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Copilot AI review requested due to automatic review settings July 17, 2026 22:34

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tannergooding enabled auto-merge (squash) July 18, 2026 00:40

lewing approved these changes Jul 18, 2026

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build-analysis Bot mentioned this pull request Jul 18, 2026

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Implement wasm codegen for sub-16 SIMD load/store#131000

Implement wasm codegen for sub-16 SIMD load/store#131000
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