Sofronio 0g stuck fix#76
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## Root cause: GPIO back-feed through ESD diodes The `TPS22860` load switch that gates `3V3_PERIPH` (power for OLED, ADS1232, REF5025, ADS1115) does not fully isolate when off. During deep sleep, ESP32 GPIOs connected to these devices leak current through their internal ESD protection diodes into the `3V3_PERIPH` rail, keeping it at a small residual voltage: | Battery | 3V3_PERIPH residual | |---------|---------------------| | 3.5V | 0.295V | | 3.6V | 0.308V | | 3.7V | 0.319V | | 3.8V | 0.331V | | 3.9V | 0.342V | | 4.0V | 0.356V | | 4.1V | 0.365V | | 4.2V | 0.377V | On cold boot (battery physically disconnected then reconnected) the ADS1232 starts from **true 0V** and its internal power-on reset fires correctly. But after deep sleep the `3V3_PERIPH` rail only drops to the residual voltage above — **not low enough to trigger POR**. The ADC analog front-end (PGA, modulator) wakes up in a latched state and outputs frozen mid-scale values, which the firmware reads as `0g`. Testing shows the threshold is **~0.33V**: any residual above this causes the ADC to stick at 0g on wake. ### Reproduction 1. Set bench supply to **3.5V**. Place 100g on scale → reads **100g**. 2. Raise supply to **4.0V**. Reading stays **100g** (ADC not power-cycled). 3. **Sleep → wake**. `3V3_PERIPH` starts from **0.356V** (≥ 0.33V → POR skipped). 100g now reads **0g**. 4. Lower supply to **3.5V** (while running). Still reads **0g**. 5. **Sleep → wake**. `3V3_PERIPH` starts from **0.295V** (< 0.33V → POR fires). 100g now reads **100g** correctly. ### Fix Before deep sleep, drive every GPIO in the `PWR_CTRL` domain `LOW` (`INPUT` for DOUT pins) and enable `gpio_hold`. This forces `3V3_PERIPH` to **0V** regardless of battery voltage, guaranteeing a clean POR on the next wake-up. No library changes required.
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Added gpio_deep_sleep_hold_dis(); to do proper GPIO hold during deepsleep.