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nuttx: rework atomic operations - #19802

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zhangyu-duck:atomic-upstream
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nuttx: rework atomic operations#19802
zhangyu-duck wants to merge 16 commits into
apache:masterfrom
zhangyu-duck:atomic-upstream

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@zhangyu-duck zhangyu-duck commented Aug 12, 2026

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Summary

This PR reworks the atomic operation implementation in <nuttx/atomic.h> to provide a unified, portable, and standard-conflict-free atomic interface.

Key changes:

  1. Use toolchain builtin atomic functions instead of /<stdatomic.h>. The original implementation relied on __has_include() and C11 version checks, which is not portable (e.g., Tasking compiler doesn't support __has_include). It
    also conflicts with third-party C++ libraries that include — the standard library expects template types while NuttX atomic_t is int32_t, causing compile errors. The new implementation calls compiler builtins (_atomic* / _c11_atomic*
    / _Interlocked*) directly, similar to Zephyr.
  2. Rename atomic_fetch_xxx to atomic_xxx (e.g., atomic_fetch_add → atomic_add). The atomic_fetch_xxx naming is reserved by the C/C++ standard. Since source files may directly or indirectly include <nuttx/atomic.h>, keeping the standard name
    causes function name conflicts and compile errors. Other non-standard API names (e.g., atomic_read, atomic_set, atomic_xchg) remain unchanged.
  3. Add four selectable atomic backends via Kconfig:
    - LIBC_ATOMIC_TOOLCHAIN — compiler builtins (default, lock-free)
    - LIBC_ATOMIC_ARCH — arch-native atomic instructions (lock-free)
    - LIBC_ATOMIC_HWSPINLOCK — hardware spinlock wrapping critical section (cross-core, for chips without atomic instructions but with hwspinlock peripheral)
    - LIBC_ATOMIC_IRQ — IRQ disable wrapping critical section (single-core only, fallback for ARMv6-M / ARM7TDMI / ARM926EJS etc.)
  4. Add hwspinlock-based atomic for cxd56, rp2040, and lc823450 (multi-core capable chips).
  5. Use _Atomic qualifier for atomic_t typedef when the compiler supports it, with a __Atomic(t) wrapper for clang compatibility.

@zhangyuduck
nuttx/libc: arch_atomic.c use irq switching instead of spinlock
5260e67 
The atomic implementation in machine/arch_atomic.c is now achieved by
switching interrupts (up_irq_save/up_irq_restore) instead of using a
spinlock. This version does not support SMP.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/include/atomic.h: adjust the logic of "defined(__has_include)"
9c1ca90 
Remove the defined(__has_include) check from the outer guard. Add a
fallback macro in compiler.h that defines __has_include(x) as 0 when the
compiler does not natively support it.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/include/atomic.h: adjust the logic of "__ATOMIC_xxx"
55783fe 
The memory order '__ATOMIC_xxx' is not a name specified by the standard. To achieve uniformity, if it is not defined, it will be defined one by one in the order of 0 to 5.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/libc: refine the atomic related Kconfig
f317cfa 
Refine the atomic Kconfig to support multiple backends:
LIBC_ATOMIC_TOOLCHAIN (compiler builtins), LIBC_ATOMIC_ARCH (arch
instructions), LIBC_ATOMIC_HWSPINLOCK (hardware spinlock), and
LIBC_ATOMIC_IRQ (interrupt disable). Rename arch_atomic_irq.c to
arch_atomic.c since it supports both IRQ and hwspinlock backends.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
sched/task: tg_nchildren is atomic type, correct the usage
b800465 
Use atomic_read and atomic_fetch_add_relaxed to access tg_nchildren,
which is now an atomic type.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx: use unified interface in <nuttx/atomic.h>
1500ce1 
Replace atomic_load/atomic_store with atomic_read/atomic_set in call
sites to use the unified interface defined in <nuttx/atomic.h>.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/atomic: select LIBC_ATOMIC_IRQ for chips without atomic support
1d1fcd1 
The following types are not supported:

1. ARCH_ARMV6M, ARCH_ARM7TDMI, and ARCH_ARM926EJS architectures are not supported by the architecture itself.
2. Single-core CPUs, such as ARCH_CHIP_BM3823.
3. Special chips are not supported, such as ARCH_CHIP_RV32M1(RISV32).

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/hwspinlock: hwspinlock should based on irq instead of spinlock_irq
61bf993 
Change the hwspinlock implementation to be based on IRQ disable/restore
instead of spinlock_irqsave, so it can be used in atomic lock/unlock
functions that may be called before the scheduler is initialized.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
arch/arm/src: add hwspinlock driver for cxd56, rp2040 and lc823450
712256d 
Add hardware spinlock driver implementations for cxd56, rp2040, and
lc823450 chips. These drivers provide the hwspinlock_ops_s interface used
by the atomic hwspinlock backend.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
libc/machine: realize atomic based on hwspinlock
1d24bed 
Implement atomic_lock/atomic_unlock using hwspinlock when
CONFIG_LIBC_ATOMIC_HWSPINLOCK is selected, and using up_irq_save/
up_irq_restore when CONFIG_LIBC_ATOMIC_IRQ is selected. Rename
arch_atomic_irq.c to arch_atomic.c.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
arch/arm/src: realize atomic for cxd56, rp2040 and lc823450
50e6dd6 
Add per-chip atomic hwspinlock device definitions for cxd56, rp2040,
and lc823450. Select LIBC_ATOMIC_HWSPINLOCK for SMP and
LIBC_ATOMIC_IRQ for !SMP on these chips.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/arch: add <nuttx/atomic.h> include for apache ci
2272917 
Add #include <nuttx/atomic.h> to source files that use atomic
operations but were missing the include, to pass the Apache CI build.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/atomic: for builtin atomic, a wrapper is used to unify the names.
90aa71d 
1. for tasking, map __c11_atomic_xxx as tasking_atomic_xxx
2. for msvc, map  _Interlocked_xxx as msvc_atomic_xxx
3. if no special map, use gcc/clang as default as they are most widely used.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/atomic: use toolchain builtin atomic function
9c9ea5e 
The reason for using builtin atomic is that in C++, when include <atomic> in <nuttx/atomic.h> easily conflicts with third-party function libraries. We wanted to completely separate the implementation of <nuttx/atomic.h>.

There are two points:
1. use builtin function directly.
2. Without the standard library implementation, need implement "atomic_fetch_xxx", leading conflicts with the standard library used by third-party programs, introducing redefinition issues and requiring name changes.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/atomic: replace atomic_fetch_xxx with atomic_xxx just like zephyr
e1826a7 
Rename atomic_fetch_add/sub/or/and/xor to atomic_add/sub/or/and/xor
to avoid conflicts with the C/C++ standard library naming. The
atomic_fetch_xxx naming is reserved by the standard; keeping it causes
function name conflicts when source files indirectly include both
<nuttx/atomic.h> and <atomic>/<stdatomic.h>.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyuduck
nuttx/atomic.h: use _Atomic define atomic_t.
29c889b 
1. use _atomic as wrapper because if _Atomic empty, may affects the compilation of other files:

2. for clang builtin function, it donot accept param with keyword "_Atomic"

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyu-duck
zhangyu-duck marked this pull request as draft August 12, 2026 07:52
@jerpelea jerpelea changed the title Atomic upstream nuttx: rework atomic operations Aug 12, 2026
jerpelea
jerpelea requested changes Aug 12, 2026
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please follow contribution guidelines and provide proper PR description, impact and testing

@github-actions github-actions Bot added Area: Bluetooth Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: simulator Issues related to the SIMulator Arch: sparc Issues related to the SPARC architecture Arch: xtensa Issues related to the Xtensa architecture Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. labels Aug 12, 2026
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github-actions Bot commented Aug 12, 2026

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MemBrowse Memory Report

arduino-mega2560

  • flash: .text +50 B (+0.1%, 67,672 B / 262,144 B, total: 26% used)

mirtoo

  • kseg0_progmem: .text -668 B (-1.0%, 66,808 B / 131,072 B, total: 51% used)

s698pm-dkit

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Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: simulator Issues related to the SIMulator Arch: sparc Issues related to the SPARC architecture Arch: xtensa Issues related to the Xtensa architecture Area: Bluetooth Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces.

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