Skip to content

Remove unnecessary slice (s) LogicNets from sign_extended and zero_extended.#496

Open
fdxmw wants to merge 6 commits into
UCSBarchlab:developmentfrom
fdxmw:extend
Open

Remove unnecessary slice (s) LogicNets from sign_extended and zero_extended.#496
fdxmw wants to merge 6 commits into
UCSBarchlab:developmentfrom
fdxmw:extend

Move `output_to_verilog`'s logic for repeated concat args to concat (…

376e0b6
Select commit
Loading
Failed to load commit list.
Sign in for the full log view

Annotations

1 warning
tests
succeeded Jul 20, 2026 in 55s