Removed portions of specify block from Verilog

test/au/spsram_256x256.au

@@ -4500,9 +4500,6 @@ module spsram_256x256
    // Timing check placeholders (will be replaced during SDF back-annotation)
    reg notifier;
    specify
-      // Delay from clk to rd_out
-      (posedge clk *> rd_out) = (0, 0);
-
       // Timing checks
       $width     (posedge clk,            0, 0, notifier);
       $width     (negedge clk,            0, 0, notifier);

test/au/spsram_256x32.au

@@ -807,9 +807,6 @@ module spsram_256x32
    // Timing check placeholders (will be replaced during SDF back-annotation)
    reg notifier;
    specify
-      // Delay from clk to rd_out
-      (posedge clk *> rd_out) = (0, 0);
-
       // Timing checks
       $width     (posedge clk,            0, 0, notifier);
       $width     (negedge clk,            0, 0, notifier);

test/au/spsram_256x32_h.au

@@ -814,9 +814,6 @@ module spsram_256x32_h
    // Timing check placeholders (will be replaced during SDF back-annotation)
    reg notifier;
    specify
-      // Delay from clk to rd_out
-      (posedge clk *> rd_out) = (0, 0);
-
       // Timing checks
       $width     (posedge clk,            0, 0, notifier);
       $width     (negedge clk,            0, 0, notifier);

utils/single_port_ram_verilog_exporter.py

@@ -111,9 +111,6 @@ def write_timing_check(self, out_fh):
         )
         out_fh.write("   reg notifier;\n")
         out_fh.write("   specify\n")
-        out_fh.write(f"      // Delay from {clk_pin} to {dout_bus}\n")
-        out_fh.write(f"      (posedge {clk_pin} *> {dout_bus}) = (0, 0);\n")
-        out_fh.write("\n")
         out_fh.write("      // Timing checks\n")
         out_fh.write(
             f"      $width     (posedge {clk_pin},            0, 0, notifier);\n"