gf180 opamp: route the mimcap on the PDK's own layers, and three cell fixes - #110
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carloscl03 wants to merge 4 commits into
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gf180 opamp: route the mimcap on the PDK's own layers, and three cell fixes#110carloscl03 wants to merge 4 commits into
carloscl03 wants to merge 4 commits into
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no_pin_labels() existe para que una subcelda no herede al padre pines que ahi dentro son redes internas. Pero el bucle de etiquetas de esta celda no consultaba la variable, asi que el interruptor no le llegaba: solo apagaba las del diff_pair de dentro, no las suyas. Se ve en el LVS de main: diff_pair falla por un pin SUB de mas, diff_pair_ibias por VTAIL, y el opamp por seis a la vez -- VDD1, VDD2, VN|VP, VN|VP$1, DIFFPAIR_BIAS|IBIAS y B|GND|VSS -- que son los pines de las dos instancias que lleva dentro. Con la guarda puesta y envolviendo la llamada del opamp, diff_pair y diff_pair_ibias pasan. En el opamp los seis pines desaparecen y los conjuntos de pines coinciden, 7 contra 7.
__connect_cs_netlist declara B = S = VSS y su comentario da por hecho que el anillo de welltie ya lo cumple. La extraccion dice que no: los pfets de salida salen con el sustrato en una red propia, separada de VDD, y con ellos el dummy de 200 um. Un pozo flotante. El anillo esta pegado al dispositivo y los dos puertos son met2, asi que el enlace es un tramo recto. DRC sin cambios (los 8 PP.5b/PP.5dii que ya traia), y el LVS baja de 16 mismatches a 8.
…o de comp se salia del implante
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Hi @carloscl03 Thanks for the fixes in the cells. This will be very helpful. Just a reminder to update the commit messages to English, and if you have comments in the source code also they should be in English. Thanks, |
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Four cell fixes that together take the gf180 opamp to a clean DRC and a
matching netlist. Depends on #108 and #109 for the runner and the mimcap
model.
The mimcap routing was hardcoded for sky130.
__add_mimcap_arrcarriedthe comment "V2 (cap_metalbottom) is glayout met4, V1 (cap_metaltop) is
met5". True there; on gf180 option A the MIM sits on met2/met3. The routes
landed two levels above the plates with no via to step down, so the whole
compensation cap array was floating --
via3count was zero anywhere nearit. The layers now come from
pdk.get_grule("capmet"), so both PDKs work.diff_to_singledescribed an internal node the cell does not build. Itsnetlist gave TOP1 and BOT1 a node of their own,
V1. In the layout that nodeand the output are one net, which the extractor reports with five terminals.
This is the cell's structure rather than a stray overlap: deleting the entire
strip where the two rails run over each other still leaves them connected,
whereas cutting an accidental short separates the nodes.
VSS2, thecounterpart node, already matched the netlist exactly on all three terminals.
The comp fill between the centre multipliers sat outside the implant. The
gap fill uses the
plusdopedports, which are on the implant layer, so attheir own width the fill's edges came out level with the implant instead of
inside it -- 0.01um of extension where PP.5b/PP.5dii ask for 0.16. Insetting
it by the implant enclosure clears all eight violations in the opamp and the
four in the converter, and still covers the 0.17um comp gap it exists for.
The output stage's well was not tied to its source, and
diff_pair_ibias's pin labels could not be suppressed the waydiff_pair'scan, so they leaked into the parent as extra top-level pins.