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Add Motorola CPU32 processor variant to the 68000 processor module. CPU32 is based on the 68020 with some instructions removed and table lookup/interpolation instructions added. Used in MC68330, MC68340, MC68360 and similar microcontrollers. Changes: - 68000.sinc: @ifdef/@ifndef CPU32 conditionals - Added: TBL instructions, LPSTOP, BGND - Excluded: BFxxx, CALLM, CAS, CAS2, PACK, RTM, UNPK - CPU32.slaspec: new language specification - 68000.ldefs: CPU32 variant definition - certification.manifest: CPU32.slaspec entry - Emulator test classes and pcode_defs.py configuration All 79 CPU32 instructions verified against CPU32 Reference Manual (Rev 1, Dec 1990). Pcode emulator tests pass: 16/16 O0, 16/16 O3.
'origin/GP-6642_ghidorahrex_HCS12_BRN_fix--SQUASHED' into patch (Closes #9001)
…instructions--SQUASHED' into patch
The msr instruction get the output register from the second 16-bit word, but it must come out of the first 16-bit word. This patch fixes the decoding.
…ctor_fix' into patch
…d DBTrace GZT file type.
…s--SQUASHED' into patch
tool that was used to import them
changed outside of the editor
into patch (Closes #9415)
'origin/GP-7118-dragonmacher-comp-editor-fix' into patch (Closes #9461)
UnwindInfoAddress in .pdata (Closing #9491)
structures (Closes #9486)
…rsion--SQUASHED' into patch
'origin/GP-7129_ghidra1_PR-9398_antoniovazquezblanco_SubAddressUnitOffset' into patch (Closes #9398)
branching like AARCH64 CSEL instruction.
'origin/GP-7018_ghidorahrex_x86_mov_sreg_opsize_fix' into patch (Closes #9326)
'origin/GP-6767_ghidorahrex_x86_shift_rotate_flag_fix--SQUASHED' into patch (Closes #9330)
'origin/GP-7133_ghidorahrex_MIPS_16e_ldefs_fix' into patch (Closes #9432)
'origin/GP-7017_ghidorahrex_pinsrw_count_mask_fix--SQUASHED' into patch (Closes #9328)
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