Name		Name	Last commit message	Last commit date
docs		docs
pipeline_reg		pipeline_reg
stage		stage
tests		tests
.gitignore		.gitignore
ALU.v		ALU.v
LICENSE		LICENSE
PC.v		PC.v
RAM.v		RAM.v
README.md		README.md
ROM.v		ROM.v
branch_detection_unit.v		branch_detection_unit.v
control_unit.v		control_unit.v
forwarding_unit.v		forwarding_unit.v
hazard_detection_unit.v		hazard_detection_unit.v
imm_gen.v		imm_gen.v
main.v		main.v
reg_file.v		reg_file.v

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SimpleCPU

RISC-V 32 CPU implemented in Verilog

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RISC-V 32 CPU implemented in Verilog

GPL-3.0 license

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