GitHub - MPEZZIN/uart_16750 · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 18 Commits
src		src
util		util
.gitignore		.gitignore
Bender.yml		Bender.yml
CHANGELOG.md		CHANGELOG.md
src_files.yml		src_files.yml

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VHDL 57.1%
SystemVerilog 42.2%
Tcl 0.7%