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Merged
Shanthipriya20 merged 10 commits into from
Jun 8, 2026
Merged

Add subckt and simulation files for IC_74LS31, IC_CD74AC174, IC_CD74H… #539

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892f0d7
Add subckt and simulation files for IC_74LS31
santhosh5116 Jun 8, 2026
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Add subckt and simulation files for IC_CD74AC174
santhosh5116 Jun 8, 2026
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Add subckt and simulation files for IC_CD74HC533
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Add subckt and simulation files for IC_DM8098
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Add subckt and simulation files for IC_GD74HCT58
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Add subckt and simulation files for IC_M74HC4024
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Add subckt and simulation files for IC_MC10E155
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Add subckt and simulation files for IC_MC10E156
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Add subckt and simulation files for IC_OR73
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Add subckt and simulation files for IC_NA53
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9 changes: 9 additions & 0 deletions library/SubcircuitLibrary/IC_74LS31/IC_74LS31.cir
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.title KiCad schematic
U4 Net-_U3-Pad2_ Net-_U4-Pad2_ d_inverter
U3 Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter
U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
U1 Net-_U1-Pad1_ Net-_U1-Pad2_ PORT
U7 Net-_U6-Pad2_ Net-_U1-Pad2_ d_inverter
U5 Net-_U4-Pad2_ Net-_U5-Pad2_ d_inverter
U6 Net-_U5-Pad2_ Net-_U6-Pad2_ d_inverter
.end
36 changes: 36 additions & 0 deletions library/SubcircuitLibrary/IC_74LS31/IC_74LS31.cir.out
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.title kicad schematic

* u4 net-_u3-pad2_ net-_u4-pad2_ d_inverter
* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter
* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
* u1 net-_u1-pad1_ net-_u1-pad2_ port
* u7 net-_u6-pad2_ net-_u1-pad2_ d_inverter
* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter
* u6 net-_u5-pad2_ net-_u6-pad2_ d_inverter
a1 net-_u3-pad2_ net-_u4-pad2_ u4
a2 net-_u2-pad2_ net-_u3-pad2_ u3
a3 net-_u1-pad1_ net-_u2-pad2_ u2
a4 net-_u6-pad2_ net-_u1-pad2_ u7
a5 net-_u4-pad2_ net-_u5-pad2_ u5
a6 net-_u5-pad2_ net-_u6-pad2_ u6
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
.tran 0e-00 0e-00 0e-00

* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
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