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Add 8 Verilog IPs to Digital-Verilog-IPs#11

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Add 8 Verilog IPs to Digital-Verilog-IPs#11
Vamshi143panda wants to merge 9 commits into
FOSSEE:Digital-Verilog-IPsfrom
Vamshi143panda:VAMSI-PR-V2

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This pull request adds the following Verilog IPs:

  1. Encoder 8b/10b
  2. Two Flip-Flop Synchronizer
  3. BIST Fault Free
  4. Clock Divider
  5. Glitch Filter
  6. Parity Generator and Checker
  7. Power Gating IP
  8. RLE Compressor

Each IP is submitted as a separate commit as per repository guidelines.

Included:

  • Verilog source files
  • eSim test circuit project files

Kindly review and provide feedback.

Thank you.

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