ALICE3 TRK add the simplified-realistic OT barrel layout - #15646
ALICE3 TRK add the simplified-realistic OT barrel layout#15646bulukutlu wants to merge 1 commit into
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More details on the changes can be found in https://indico.cern.ch/event/1713352/#25-update-on-structures-in-o2 |
Adds `TRKBase.layoutMLOT=kSimplifiedRealistic`: the ML is unchanged from kSegmented, but the OT barrel is built from the parts it is actually made of instead of solid silicon slabs. Geometry follows ALICE3 OT WP1 Material (26.06.2025); all tunable dimensions are in constants::OT in Specs.h. Module: cold plate, eight pure-silicon chips (2 in phi x 4 in z, read-out edges facing the module edges), FPC, one ZIF connector, SMD capacitors over the chip footprints and two mounting brackets, stacked flush about the chip mid-plane. Stave: two module rows overlapping in phi and staggered in r, with a cooling pipe between them and an end-of-stave FR4 readout card past the last module. The card is 120 x 80 mm in a fixed 1.5 mm envelope and carries four copper planes; the copper sets its material budget and is tunable through TRKBase.otEosCardCuThickness, which changes only the copper/FR4 split so the card dimensions stay put. The default of 122 um per plane puts the card at 4.0 % x/X0 perpendicular. Barrel: each layer is four quarter barrels, cut at mid-rapidity and on the vertical plane so the region of the beam-pipe supports stays free of staves. The stave count is no longer hard-coded; it is the smallest even number that still leaves rowActiveOverlap of active double coverage at the layer radius. The OT radii (440/615/793 mm) are therefore chosen at the top of a stave-count band, giving 30/42/54 staves per ring with 1.5-1.9 mm of overlap, and keeping the outermost stave envelope clear of the OT shell. Carbon fibre separation walls close the quarter barrels azimuthally and at mid-rapidity (TRKServices::createOTBarrelWalls, thickness configurable via TRKBase.otBarrelWallThickness). The layer envelopes are slotted along both cuts so the walls run continuously in r rather than being interrupted at every layer. Support half-rings carry the stave space frames, and the cooling pipes are shortened at mid-rapidity to make room for them. New passive materials: carbon fibre, FPC (Kapton+Cu), LCP+Cu, BaTiO3, PEEK, FR4 and copper. Also needed to make the layout work end to end: - ProcessHits resolves stave/half-stave/module from the TGeo path, since the realistic OT builds them as assembly volumes whose CurrentVolOffID copy numbers all read 0; - ClustererSpec passed a file name where loadGeometry expects a prefix, so the clusterer could not open the geometry for any layout; - CheckDigitsTRK split VD/ML/OT on hard-coded chip indices that no longer matched the layout; they are now read from GeometryTGeo.
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Rebased onto current dev. This needed more than a plain rebase because #15657 ("Split ALICE3 TRK and FT3 layout") landed in the meantime and moved every file this PR touches from Detectors/Upgrades/ALICE3/TRK/… to Detectors/Upgrades/ALICE3/TRKFT3/TRK/…, with the clusterer under TRKFT3/common/workflow/. The diff is unchanged in substance — same 11 files, +835/−102 — just at the new paths. Two small adaptations were required: layoutFT3 moved out of TRKBaseParam into FT3Base::FT3BaseParam, so the local copy was dropped; and CheckDigitsTRK now closes the OT chip-ID range at the top instead of leaving it open-ended, since the forward disks occupy the highest chip IDs and would otherwise be swept into the OT cuts. One geometry change beyond the rebase: the end-of-stave card is now 4.0 % x/X₀ perpendicular (122 µm copper per plane, up from 35 µm) rather than 1.78 %. The copper displaces FR4 inside the same fixed 1.5 mm board envelope, so card dimensions and layer envelopes are unchanged and only the radiation length moves. It is tunable via the new TRKBase.otEosCardCuThickness. |
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Adds
TRKBase.layoutMLOT=kSimplifiedRealistic: the ML is unchanged from kSegmented, but the OT barrel is built from the parts it is actually made of instead of solid silicon slabs. Geometry follows ALICE3 OT WP1 Material (26.06.2025); all tunable dimensions are in constants::OT in Specs.h.Module: cold plate, eight pure-silicon chips (2 in phi x 4 in z, read-out edges facing the module edges), FPC, one ZIF connector, SMD capacitors over the chip footprints and two mounting brackets, stacked flush about the chip mid-plane. Stave: two module rows overlapping in phi and staggered in r, with a cooling pipe between them and an end-of-stave FR4 readout card past the last module.
Barrel: each layer is four quarter barrels, cut at mid-rapidity and on the vertical plane so the region of the beam-pipe supports stays free of staves. The stave count is no longer hard-coded; it is the smallest even number that still leaves rowActiveOverlap of active double coverage at the layer radius. The OT radii (440/615/793 mm) are chosen to improve overlap uniformity, giving 30/42/54 staves per ring with 1.5-1.9 mm ofoverlap, and keeping the outermost stave envelope clear of the OT shell.
Carbon fibre separation walls close the quarter barrels azimuthally and at mid-rapidity (TRKServices::createOTBarrelWalls, thickness configurable via TRKBase.otBarrelWallThickness). The layer envelopes are slotted along both cuts so the walls run continuously in r rather than being interrupted at every layer. Support half-rings carry the stave space frames.
New passive materials: carbon fibre, FPC (Kapton+Cu), LCP+Cu, BaTiO3, PEEK, FR4 and copper.
Also needed to make the layout work end to end: