Add support for the Cadence SD6 SDHCI controller by renjithkumarnair · Pull Request #581 · sonic-net/sonic-linux-kernel

renjithkumarnair · 2026-05-26T15:47:11Z

What I did

Added support for Cadence Sdhci eMMC controller for octeon platform.
This includes enabling the Cadence SD6 controller, HS400/HS400ES modes,
ACPI integration, PHY delay tuning, and multiple fixes for timing,
tuning, and controller corner cases.
Also updated the OTX2 mailbox interface version and related structures.

Why I did it

Octeon platforms require specific controller handling and tuning for reliable
high-speed eMMC operation. Existing driver support lacked MMC
Controller-specific configurations, resulting in instability and incorrect
operation in HS400-class modes. Additionally, mailbox structure updates
were needed to align kernel and application interfaces

How I verified it

Booted Octeon platform with updated driver
Verified eMMC enumeration and initialisation
Tested HS400 / HS400ES mode transitions
Validated tuning execution and value population
Verified mailbox compatibility with updated structure

Details if related

Added Cadence SD6 SDHCI controller support
Enabled HS400 and HS400ES modes
Configured PHY delays and default tuning values when DT values are missing or invalid
Implemented delay element handling and Cadence-specific tuning logic, including multi-block read helpers
Improved handling of DDR, clocking, enhanced strobe, command delay, block gap, and interrupt corner cases
Added ACPI support for Octeon Cadence SDHCI instance
Updated OTX2_MBOX_VERSION to 0x000b
Extended struct nix_lf_alloc_rsp with hw_rx_tstamp_en

Patch upstreaming plan

These patches have to be upstreamed

mssonicbld · 2026-05-26T15:47:20Z

/azp run

azure-pipelines · 2026-05-26T15:47:30Z

Azure Pipelines successfully started running 1 pipeline(s).

linux-foundation-easycla · 2026-05-26T15:47:59Z

The committers listed above are authorized under a signed CLA.

✅ login: renjithkumarnair / name: Renjithkumar Raveendran Nair (8a7f142)

paulmenzel

Please send the patch upstream for review (the tool b4 helps, or normal git commands git format-patch … and git send-email …).

paulmenzel · 2026-05-26T15:50:56Z

@@ -0,0 +1,2902 @@
+From d1910de6f9c5de27eecf89dc12a165a600aac833 Mon Sep 17 00:00:00 2001
+From: rnair <rnair@marvell.com>


Please use your full name.

paulmenzel · 2026-05-26T15:51:07Z

+  struct nix_lf_alloc_rsp with hw_rx_tstamp_en to match the mbox
+  structure with applications.
+
+Signed-off-by: rnair <rnair@marvell.com>


mssonicbld · 2026-05-28T05:15:38Z

/azp run

azure-pipelines · 2026-05-28T05:15:46Z

Azure Pipelines successfully started running 1 pipeline(s).

mssonicbld · 2026-05-28T06:49:30Z

/azp run

azure-pipelines · 2026-05-28T06:49:40Z

Azure Pipelines successfully started running 1 pipeline(s).

mssonicbld · 2026-05-28T07:17:50Z

/azp run

azure-pipelines · 2026-05-28T07:17:59Z

Azure Pipelines successfully started running 1 pipeline(s).

renjithkumarnair

Review comments incorporated.

mssonicbld · 2026-06-03T07:15:24Z

/azp run

azure-pipelines · 2026-06-03T07:15:34Z

Azure Pipelines successfully started running 1 pipeline(s).

mssonicbld · 2026-06-03T07:21:11Z

/azp run

azure-pipelines · 2026-06-03T07:21:22Z

Azure Pipelines successfully started running 1 pipeline(s).

renjithkumarnair

The CLA has been signed now.

renjithkumarnair · 2026-06-05T14:08:32Z

Please send the patch upstream for review (the tool b4 helps, or normal git commands git format-patch … and git send-email …).

This patch is not to be upstreamed as it is. There is another Code change coming towards adding SD6 support by other party (which can overlap/clash over this) in progress in the linux-mmc forum. So basically, have to wait for that patch to reflect in upstream and only patch up this driver upon that as needed; else it would clash.

renjithkumarnair

Upstream task will be delayed - Given justification.

gbhatt07 · 2026-06-05T18:20:25Z

@lizhijianrd @Blueve please help in getting this PR reviewed. Thanks

saiarcot895 · 2026-06-08T17:35:46Z

/easycla

saiarcot895 · 2026-06-08T17:40:39Z

You'll need to fix the author on the commit for EasyCLA purposes.

----------- Added support for Cadence Sdhci eMMC controller for octeon platform This includes enabling the Cadence SD6 controller, HS400/HS400ES modes, ACPI integration, PHY delay tuning, and multiple fixes for timing, tuning, and controller corner cases. Also updated the OTX2 mailbox interface version and related structures. Why I did it ------------ Octeon platforms require specific controller handling and tuning for reliable high-speed eMMC operation. Existing driver support lacked MMC Controller-specific configurations, resulting in instability and incorrect operation in HS400-class modes. Additionally, mailbox structure updates were needed to align kernel and application interfaces How I verified it ----------------- - Booted Octeon platform with updated driver - Verified eMMC enumeration and initialization - Tested HS400 / HS400ES mode transitions - Validated tuning execution and value population - Verified mailbox compatibility with updated structure Details if related ------------------ - Added Cadence SD6 SDHCI controller support - Enabled HS400 and HS400ES modes - Configured PHY delays and default tuning values when DT values are missing or invalid - Implemented delay element handling and Cadence-specific tuning logic, including multi-block read helpers - Improved handling of DDR, clocking, enhanced strobe, command delay, block gap, and interrupt corner cases - Added ACPI support for Octeon Cadence SDHCI instance - Updated OTX2_MBOX_VERSION to 0x000b - Extended struct nix_lf_alloc_rsp with hw_rx_tstamp_en Patch upstreaming plan ---------------------- - These patches are not to be upstreamed. - There are parallel threads in Progress to give sd6hc support, which needs to be evaluated first: https://lkml.org/lkml/2026/5/11/2580 Signed-off-by: Renjithkumar Raveendran Nair <renjithkumar@gmail.com>

mssonicbld · 2026-06-09T11:12:01Z

/azp run

azure-pipelines · 2026-06-09T11:12:11Z

Azure Pipelines successfully started running 1 pipeline(s).

paulmenzel

The SONiC commit message is just wrong. Please amend it. Also, why did you change to Google Mail address?

Lastly, why not use the commit from Altera, and review this? I am against, adding a commit to SONiC which might be different, and then in the end has to be kept, because certain feature differ from upstream.

renjithkumarnair requested a review from a team as a code owner May 26, 2026 15:47

paulmenzel suggested changes May 26, 2026

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renjithkumarnair force-pushed the sonic_octeon_202605 branch from 20e778f to bcf1eb2 Compare May 28, 2026 05:15

renjithkumarnair force-pushed the sonic_octeon_202605 branch from bcf1eb2 to 033399b Compare May 28, 2026 06:49

renjithkumarnair force-pushed the sonic_octeon_202605 branch from 033399b to 66f48dd Compare May 28, 2026 07:17

renjithkumarnair commented May 28, 2026

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renjithkumarnair force-pushed the sonic_octeon_202605 branch from 66f48dd to 980a5ef Compare June 3, 2026 07:15

renjithkumarnair force-pushed the sonic_octeon_202605 branch from 980a5ef to 809e075 Compare June 3, 2026 07:21

renjithkumarnair requested a review from paulmenzel June 3, 2026 09:41

renjithkumarnair commented Jun 3, 2026

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renjithkumarnair commented Jun 5, 2026

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renjithkumarnair force-pushed the sonic_octeon_202605 branch from 809e075 to 8a7f142 Compare June 9, 2026 11:11

paulmenzel suggested changes Jun 9, 2026

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		@@ -0,0 +1,2902 @@
		From d1910de6f9c5de27eecf89dc12a165a600aac833 Mon Sep 17 00:00:00 2001
		From: rnair <rnair@marvell.com>

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renjithkumarnair commented May 26, 2026

What I did

Why I did it

How I verified it

Details if related

Patch upstreaming plan

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