Normative rule changes detected in commit f48c2c1

[github-actions]

Normative Rule Changes Detected

The normative tag validation has detected changes after merge to main.

Commit Details:

• SHA: f48c2c1
• Pushed by: Qian Jiayan (@keyon1992)
• Link: f48c2c1

---

Normative Tag Change Report

Comparing ref/ as of 79b241cb6d2f07167366747ae49df94b88ad4d3b against the tags built
from this revision's sources.

riscv-spec Specification

================================================================================
Tag Changes Report
================================================================================

Reference file: /home/runner/work/_temp/riscv-spec-base-norm-tags.json
Current file: build/riscv-spec-norm-tags.json
Added 1 tag:
  * "norm:hgatp_op_hfence_gvma": "Note that writing hgatp does not imply any ordering constraints between page-table updates and subse..."

Deleted 2 tags:
  * "norm:pm_family_extensions": "Pointer masking refers to a number of separate extensions, all of which are privileged."
  * "norm:pm_tag_check_impl": "The tag checks themselves can be implemented in software or hardware."

Modified 33 tags:
  * "norm:Zawrs_wrs-sto_stall_duration":
      Reference: "insn:wrs.sto[] (WRS-with-short-timeout) is
provided that works like insn:wrs.nto[] but bounds the st..."
      Current:   "insn:wrs.sto[] (WRS-with-short-timeout) is
provided that works like insn:wrs.nto[] but bounds the st..."
  * "norm:cycle_instret_hpmcounter_op_rdonly":
      Reference: "The cycle, instret, and hpmcountern CSRs are read-only shadows of mcycle, minstret, and mhpmcounter ..."
      Current:   "The csr:cycle[], csr:instret[], and hpmcountern CSRs are read-only shadows of csr:mcycle[], csr:mins..."
  * "norm:mhpmcounter_num":
      Reference: "The hardware performance monitor includes 29 additional 64-bit event
counters, mhpmcounter3-mhpmcoun..."
      Current:   "The hardware performance monitor includes 29 additional 64-bit event
counters, csr:mhpmcounter3[]{en..."
  * "norm:mhpmevent_sz_warl_op":
      Reference: "The event selector CSRs,
mhpmevent3-mhpmevent31, are 64-bit WARL registers that control which
event ..."
      Current:   "The event selector CSRs,
csr:mhpmevent3[]{endash}csr:mhpmevent31[], are 64-bit WARL registers that c..."
  * "norm:mip_seip_wrcsr":
      Reference: "the signal from the interrupt controller is not used to
calculate the value written to SEIP. Only th..."
      Current:   "the signal from the interrupt controller is not used to
calculate the value written to csr::[seip]. ..."
  * "norm:misa_mxl_enc":
      Reference: "MXL|XLEN
===
1
2
3|32
64
Reserved
==="
      Current:   "MXL|XLEN
===
1|32¶2|64¶3|Reserved
==="
  * "norm:misaligned_atomicity_granule_size":
      Reference: "The misaligned atomicity granule PMA, defined in <<sec:misaligned-atomicity-granule>>,
o..."
      Current:   "The misaligned atomicity granule PMA, defined in <<sec:misaligned-atomicity-granule>>,
o..."
  * "norm:mseccfg_mml_M_rule_op":
      Reference: "An M-mode-only rule is enforced on Machine mode and denied in Supervisor
or User mode. It also remai..."
      Current:   "An M-mode-only rule is enforced on accesses whose effective privilege
mode is Machine and denied to ..."
  * "norm:mseccfg_mml_SorU_rule_op":
      Reference: "An S/U-mode-only rule is enforced on Supervisor and User modes and
denied on Machine mode."
      Current:   "An S/U-mode-only rule is enforced on accesses whose effective privilege
mode is Supervisor or User a..."
  * "norm:mseccfg_rlb_op_warl":
      Reference: "When mseccfg.RLB (Rule Locking Bypass) a WARL field that provides a mechanism to temporarily modify ..."
      Current:   "mseccfg.RLB (Rule Locking Bypass) is a WARL field that provides a mechanism to temporarily modify Lo..."
  * "norm:mstatus_fs_op":
      Reference: "The FS field encodes the status of the
floating-point unit state, including the floating-point regis..."
      Current:   "The csr::[fs] field encodes the status of the
floating-point unit state, including the floating-poin..."
  * "norm:mstatus_fs_vs_xs_enc":
      Reference: "Status|FS and VS Meaning|XS Meaning
===
0
1
2
3|Off
Initial
Clean
Dirty|All off
None dirty or clean,..."
      Current:   "Status|FS and VS Meaning|XS Meaning
===
0|Off|All off¶1|Initial|None dirty or clean, some on¶2|Clean..."
  * "norm:mstatus_fs_vs_xs_update_indep_priv":
      Reference: "The status fields will
also be updated during execution of instructions, regardless of privilege mod..."
      Current:   "The status fields are
also updated during execution of instructions, regardless of privilege mode."
  * "norm:mstatus_mdt_clr_mnret":
      Reference: "When the Smdbltrp extension is implemented, the MNRET instruction, provided by the Smrnmi extension,..."
      Current:   "When the ext:smdbltrp[] extension is implemented, the insn:mnret[] instruction, provided by the ext:..."
  * "norm:mstatus_mprv_clr_mret_sret_less_priv":
      Reference: "An MRET or SRET instruction that changes the privilege mode to a mode
less privileged than M also se..."
      Current:   "An insn:mret[] or insn:sret[] instruction that changes the privilege mode to a mode
less privileged ..."
  * "norm:mstatus_sbe_change_fence":
      Reference: "Since changing SBE alters the implementation’s interpretation of these
data structures, if any such ..."
      Current:   "Since changing csr::[sbe] alters the implementation’s interpretation of these
data structures, if an..."
  * "norm:mstatus_sd_rdonly0":
      Reference: "If FS, XS, and VS are all read-only zero, then SD is also always zero."
      Current:   "If csr::[fs], csr::[vs], and csr::[xs] are all read-only zero, then csr::[sd] is also always zero."
  * "norm:mstatus_tsr_op":
      Reference: "When TSR=1, attempts to
execute SRET while executing in S-mode will raise an illegal-instruction
exc..."
      Current:   "When csr::[tsr]=1, attempts to
execute insn:sret[] while executing in S-mode will raise an illegal-i..."
  * "norm:mstatus_tsr_warl":
      Reference: "The TSR (Trap SRET) bit is a WARL field that supports intercepting the
supervisor exception return i..."
      Current:   "The csr::[tsr] (Trap insn:sret[]) bit is a WARL field that supports intercepting the
supervisor exce..."
  * "norm:mstatus_tvm_warl_op":
      Reference: "The TVM (Trap Virtual Memory) bit is a WARL field that supports intercepting supervisor virtual-memo..."
      Current:   "The csr::[tvm] (Trap Virtual Memory) bit is a WARL field that supports intercepting supervisor virtu..."
  * "norm:mstatus_tw_always_illegal":
      Reference: "An implementation may have WFI always
raise an illegal-instruction exception in modes less privilege..."
      Current:   "An implementation may have insn:wfi[] always
raise an illegal-instruction exception in modes less pr..."
  * "norm:mstatus_tw_op":
      Reference: "When TW=0, the WFI
instruction may execute in modes less privileged than M when not prevented for
so..."
      Current:   "When csr::[tw]=0, the insn:wfi[] instruction may execute in modes less privileged than M when not pr..."
  * "norm:mstatus_tw_umode_op":
      Reference: "When S-mode is implemented, then executing WFI in U-mode causes an
illegal-instruction exception, re..."
      Current:   "When S-mode is implemented, then executing insn:wfi[] in U-mode causes an
illegal-instruction except..."
  * "norm:mstatus_tw_warl":
      Reference: "The TW (Timeout Wait) bit is a WARL field that supports intercepting the WFI
instruction (see <&l..."
      Current:   "The csr::[tw] (Timeout Wait) bit is a WARL field that supports intercepting the
insn:wfi[] instructi..."
  * "norm:mstatus_vs_op":
      Reference: "The VS field encodes the status of the
vector extension state, including the vector
registers v0–v31..."
      Current:   "The csr::[vs] field encodes the status of the
vector extension state, including the vector
registers..."
  * "norm:pm_uxl_clear":
      Reference: "Setting UXL/SXL/MXL to 1 will clear the corresponding pointer masking configuration bits."
      Current:   "Setting UXL/SXL to 1 will clear the corresponding pointer masking configuration bits."
  * "norm:pma_mag_insts":
      Reference: "The misaligned atomicity granule PMA applies only to AMOs, loads and stores
defined in the base ISAs..."
      Current:   "The misaligned atomicity granule PMA applies only to AMOs; loads and stores
defined in the base ISAs..."
  * "norm:pmp_no_entry_match":
      Reference: "If no PMP entry matches an M-mode memory operation, the operation succeeds.
If no PMP entry matches ..."
      Current:   "If no PMP entry matches an M-mode memory operation, the operation succeeds.
If no PMP entry matches ..."
  * "norm:rvwmo_misaligned_in_atomic_pma":
      Reference: "if misaligned atomics are supported via the
misaligned atomicity granule PMA, then AMOs within an at..."
      Current:   "if misaligned atomics are supported via the
misaligned atomicity granule PMA, then AMOs within an at..."
  * "norm:rvwmo_ppo_sync2":
      Reference: "a has an acquire annotation annotation"
      Current:   "a has an acquire annotation"
  * "norm:sdrl_rcsc_semantics":
      Reference: "The instruction always has an release-RCsc annotation, and if the bit aq is set the instruction has ..."
      Current:   "The instruction always has a release-RCsc annotation, and if the bit aq is set the instruction has a..."
  * "norm:ssmp_ss_page_illegeal_access":
      Reference: "Should a shadow stack instruction access a page that is
not designated as a shadow stack page and is..."
      Current:   "Should a shadow stack instruction access a page that is
not designated as a shadow stack page and is..."
  * "norm:xlen_reduction_hint_op1":
      Reference: "Some HINT instructions are encoded as integer computational instructions that overwrite their destin..."
      Current:   "Some HINT instructions are encoded as integer computational instructions that overwrite their destin..."

================================================================================
Summary: 36 total changes
  Added:    1
  Deleted:  2
  Modified: 33
================================================================================

---

Action Required:

1. Review the normative rule changes in this commit
2. Verify that the changes are intentional and properly documented
3. If modifications or deletions need to be addressed, coordinate with the PR author or create a follow-up PR

Note: Reference files have been automatically updated for any new tag additions. This issue is for tracking modifications and deletions that may require CSC review.

cc: @riscv/csc

This issue was automatically created by the normative tag check workflow.