diff --git a/Bender.yml b/Bender.yml
index de23acc..b3bc15e 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -41,6 +41,7 @@ sources:
files:
- src/hyperbus_delay.sv
+ - src/regs/hyperbus_cfg_regblock_pkg.sv
- src/hyperbus_pkg.sv
- src/hyperbus_clk_gen.sv
- src/hyperbus_clock_diff_out.sv
@@ -48,6 +49,7 @@ sources:
- src/hyperbus_phy2r.sv
- src/hyperbus_ddr_out.sv
- src/hyperbus_trx.sv
+ - src/regs/hyperbus_cfg_regblock.sv
- src/hyperbus_cfg_regs.sv
- src/hyperbus_phy.sv
- src/hyperbus_phy_if.sv
@@ -63,4 +65,5 @@ sources:
- test/dut_if.sv
- test/hyperbus_tb_pkg.sv
- test/axi_hyper_tb.sv
+ - test/hyperbus_cfg_regs_tb.sv
- src/hyperbus.sv
diff --git a/Makefile b/Makefile
index 93b6d6f..e94ebbd 100644
--- a/Makefile
+++ b/Makefile
@@ -12,6 +12,9 @@ all: build run
clean: sim_clean
+update-regs:
+ bash scripts/gen_regs.sh
+
# Ensure half-built targets are purged
.DELETE_ON_ERROR:
diff --git a/docs/regs/hyperbus_cfg_regs.md b/docs/regs/hyperbus_cfg_regs.md
new file mode 100644
index 0000000..9458acf
--- /dev/null
+++ b/docs/regs/hyperbus_cfg_regs.md
@@ -0,0 +1,1135 @@
+
+
+## hyperbus_cfg_regs address map
+
+- Absolute Address: 0x0
+- Base Offset: 0x0
+- Size: 0x1000
+
+HyperBus controller configuration register map. Enabled chip ranges must be 4 MiB aligned, ordered by chip-select index, and non-overlapping.
+
+|Offset| Identifier |Name|
+|------|------------|----|
+| 0x000| global_cfg | — |
+| 0x100| frontend | — |
+| 0x200| backend | — |
+| 0x300| phy_0 | — |
+| 0x340| phy_1 | — |
+| 0x400| chip_0 | — |
+| 0x440| chip_1 | — |
+| 0x480| chip_2 | — |
+| 0x4C0| chip_3 | — |
+| 0x500| chip_4 | — |
+| 0x540| chip_5 | — |
+| 0x580| chip_6 | — |
+| 0x5C0| chip_7 | — |
+| 0xFFC|reserved_top| — |
+
+## global_cfg register file
+
+- Absolute Address: 0x0
+- Base Offset: 0x0
+- Size: 0x14
+
+|Offset| Identifier |Name|
+|------|--------------|----|
+| 0x00 | ip_version | — |
+| 0x04 |reg_if_version| — |
+| 0x08 | capability | — |
+| 0x0C | command | — |
+| 0x10 | status | — |
+
+### ip_version register
+
+- Absolute Address: 0x0
+- Base Offset: 0x0
+- Size: 0x4
+
+IP version (major.minor.patch.revision).
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+| 7:0 | revision | r | 0x0 | — |
+| 15:8| patch | r | 0x9 | — |
+|23:16| minor | r | 0x0 | — |
+|31:24| major | r | 0x0 | — |
+
+### reg_if_version register
+
+- Absolute Address: 0x4
+- Base Offset: 0x4
+- Size: 0x4
+
+Register interface version.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+| 15:0| minor | r | 0x0 | — |
+|31:16| major | r | 0x1 | — |
+
+### capability register
+
+- Absolute Address: 0x8
+- Base Offset: 0x8
+- Size: 0x4
+
+Hardware-provided implementation capabilities.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|------------------|------|-----|----|
+| 7:0| num_chips | r | 0x0 | — |
+|15:8| num_phys | r | 0x0 | — |
+| 16 | per_chip_cfg | r | 0x0 | — |
+| 17 | per_phy_cfg | r | 0x0 | — |
+| 18 | chip_enable | r | 0x0 | — |
+| 19 | clock_divider | r | 0x0 | — |
+| 20 | staged_apply | r | 0x0 | — |
+| 21 | error_status | r | 0x0 | — |
+| 22 |rwds_sample_timing| r | 0x0 | — |
+| 23 | rwds_oe_timing | r | 0x0 | — |
+
+#### num_chips field
+
+Number of implemented chip selects.
+
+#### num_phys field
+
+Number of implemented PHY lanes.
+
+#### per_chip_cfg field
+
+Each chip record controls its corresponding chip rather than chip 0 being shared.
+
+#### per_phy_cfg field
+
+Each PHY record controls its corresponding lane rather than PHY 0 being shared.
+
+#### chip_enable field
+
+Per-chip enable bits participate in address decoding.
+
+#### clock_divider field
+
+CLOCK_CFG controls an implemented backend clock divider.
+
+#### staged_apply field
+
+FLUSH and APPLY commands implement a staged configuration barrier.
+
+#### error_status field
+
+STATUS reports sticky controller errors.
+
+#### rwds_sample_timing field
+
+Per-chip RWDS sample timing is implemented.
+
+#### rwds_oe_timing field
+
+Per-PHY RWDS output-enable timing is implemented.
+
+### command register
+
+- Absolute Address: 0xC
+- Base Offset: 0xC
+- Size: 0x4
+
+Single-cycle write-one command strobes, active when capability.staged_apply is set; otherwise writes are retained only as inert pulses.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 0 | flush | rw | 0x0 | — |
+| 1 | apply | rw | 0x0 | — |
+
+### status register
+
+- Absolute Address: 0x10
+- Base Offset: 0x10
+- Size: 0x4
+
+Controller status.
+
+|Bits| Identifier | Access |Reset|Name|
+|----|------------|---------|-----|----|
+| 0 |decode_error|rw, woclr| 0x0 | — |
+| 1 | busy | r | 0x0 | — |
+| 2 | dirty | r | 0x0 | — |
+
+## frontend register file
+
+- Absolute Address: 0x100
+- Base Offset: 0x100
+- Size: 0x4
+
+|Offset| Identifier |Name|
+|------|------------|----|
+| 0x0 |frontend_cfg| — |
+
+### frontend_cfg register
+
+- Absolute Address: 0x100
+- Base Offset: 0x0
+- Size: 0x4
+
+Frontend configuration. dual_phy must be 0 or 1.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 0 | dual_phy | rw | 0x1 | — |
+
+## backend register file
+
+- Absolute Address: 0x200
+- Base Offset: 0x200
+- Size: 0x4
+
+|Offset|Identifier|Name|
+|------|----------|----|
+| 0x0 | clock_cfg| — |
+
+### clock_cfg register
+
+- Absolute Address: 0x200
+- Base Offset: 0x0
+- Size: 0x4
+
+Backend clock-divider configuration, active when capability.clock_divider is set; divider values must be at least 2.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| divider | rw | 0x8 | — |
+
+## phy_0 register file
+
+- Absolute Address: 0x300
+- Base Offset: 0x300
+- Size: 0x8
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x0 | tx_delay | — |
+| 0x4 |rwds_timing| — |
+
+### tx_delay register
+
+- Absolute Address: 0x300
+- Base Offset: 0x0
+- Size: 0x4
+
+PHY transmit delay. PHY 0 is shared when capability.per_phy_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+### rwds_timing register
+
+- Absolute Address: 0x304
+- Base Offset: 0x4
+- Size: 0x4
+
+PHY RWDS output-enable timing. rwds_oe_setup_cycles must be at most 15 and is active when capability.rwds_oe_timing is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|--------------------|------|-----|----|
+| 7:0|rwds_oe_setup_cycles| rw | 0x1 | — |
+
+## phy_1 register file
+
+- Absolute Address: 0x340
+- Base Offset: 0x340
+- Size: 0x8
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x0 | tx_delay | — |
+| 0x4 |rwds_timing| — |
+
+### tx_delay register
+
+- Absolute Address: 0x340
+- Base Offset: 0x0
+- Size: 0x4
+
+PHY transmit delay. PHY 0 is shared when capability.per_phy_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+### rwds_timing register
+
+- Absolute Address: 0x344
+- Base Offset: 0x4
+- Size: 0x4
+
+PHY RWDS output-enable timing. rwds_oe_setup_cycles must be at most 15 and is active when capability.rwds_oe_timing is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|--------------------|------|-----|----|
+| 7:0|rwds_oe_setup_cycles| rw | 0x1 | — |
+
+## chip_0 register file
+
+- Absolute Address: 0x400
+- Base Offset: 0x400
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x400
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x0 | — |
+
+### range_bound register
+
+- Absolute Address: 0x404
+- Base Offset: 0x4
+- Size: 0x4
+
+Exclusive 4 MiB-aligned chip address range bound.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x1 | — |
+
+### address_cfg register
+
+- Absolute Address: 0x408
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x40C
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x410
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x414
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x418
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_1 register file
+
+- Absolute Address: 0x440
+- Base Offset: 0x440
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x440
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x1 | — |
+
+### range_bound register
+
+- Absolute Address: 0x444
+- Base Offset: 0x4
+- Size: 0x4
+
+Exclusive 4 MiB-aligned chip address range bound.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x2 | — |
+
+### address_cfg register
+
+- Absolute Address: 0x448
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x44C
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x450
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x454
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x458
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_2 register file
+
+- Absolute Address: 0x480
+- Base Offset: 0x480
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x480
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x2 | — |
+
+### range_bound register
+
+- Absolute Address: 0x484
+- Base Offset: 0x4
+- Size: 0x4
+
+Exclusive 4 MiB-aligned chip address range bound.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x3 | — |
+
+### address_cfg register
+
+- Absolute Address: 0x488
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x48C
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x490
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x494
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x498
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_3 register file
+
+- Absolute Address: 0x4C0
+- Base Offset: 0x4C0
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x4C0
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x3 | — |
+
+### range_bound register
+
+- Absolute Address: 0x4C4
+- Base Offset: 0x4
+- Size: 0x4
+
+Exclusive 4 MiB-aligned chip address range bound.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x4 | — |
+
+### address_cfg register
+
+- Absolute Address: 0x4C8
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x4CC
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x4D0
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x4D4
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x4D8
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_4 register file
+
+- Absolute Address: 0x500
+- Base Offset: 0x500
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x500
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x4 | — |
+
+### range_bound register
+
+- Absolute Address: 0x504
+- Base Offset: 0x4
+- Size: 0x4
+
+Exclusive 4 MiB-aligned chip address range bound.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x5 | — |
+
+### address_cfg register
+
+- Absolute Address: 0x508
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x50C
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x510
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x514
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x518
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_5 register file
+
+- Absolute Address: 0x540
+- Base Offset: 0x540
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x540
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x5 | — |
+
+### range_bound register
+
+- Absolute Address: 0x544
+- Base Offset: 0x4
+- Size: 0x4
+
+Exclusive 4 MiB-aligned chip address range bound.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x6 | — |
+
+### address_cfg register
+
+- Absolute Address: 0x548
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x54C
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x550
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x554
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x558
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_6 register file
+
+- Absolute Address: 0x580
+- Base Offset: 0x580
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x580
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x6 | — |
+
+### range_bound register
+
+- Absolute Address: 0x584
+- Base Offset: 0x4
+- Size: 0x4
+
+Exclusive 4 MiB-aligned chip address range bound.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x7 | — |
+
+### address_cfg register
+
+- Absolute Address: 0x588
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x58C
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x590
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x594
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x598
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+## chip_7 register file
+
+- Absolute Address: 0x5C0
+- Base Offset: 0x5C0
+- Size: 0x1C
+
+|Offset| Identifier|Name|
+|------|-----------|----|
+| 0x00 | range_base| — |
+| 0x04 |range_bound| — |
+| 0x08 |address_cfg| — |
+| 0x0C |latency_cfg| — |
+| 0x10 | burst_cfg | — |
+| 0x14 |chip_timing| — |
+| 0x18 | rx_delay | — |
+
+### range_base register
+
+- Absolute Address: 0x5C0
+- Base Offset: 0x0
+- Size: 0x4
+
+Inclusive 4 MiB-aligned chip address range base.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x7 | — |
+
+### range_bound register
+
+- Absolute Address: 0x5C4
+- Base Offset: 0x4
+- Size: 0x4
+
+Exclusive 4 MiB-aligned chip address range bound.
+
+| Bits|Identifier|Access|Reset|Name|
+|-----|----------|------|-----|----|
+|31:22| value | rw | 0x8 | — |
+
+### address_cfg register
+
+- Absolute Address: 0x5C8
+- Base Offset: 0x8
+- Size: 0x4
+
+Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|----------------|------|-----|----|
+| 7:0| address_space | rw | 0x0 | — |
+|15:8|address_mask_msb| rw | 0x19| — |
+| 16 | enable | rw | 0x1 | — |
+
+### latency_cfg register
+
+- Absolute Address: 0x5CC
+- Base Offset: 0xC
+- Size: 0x4
+
+Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier |Access|Reset|Name|
+|----|---------------------|------|-----|----|
+| 7:0| t_latency_access | rw | 0x6 | — |
+|15:8| rwds_sample_delay | rw | 0x0 | — |
+| 16 |en_latency_additional| rw | 0x0 | — |
+
+### burst_cfg register
+
+- Absolute Address: 0x5D0
+- Base Offset: 0x10
+- Size: 0x4
+
+Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|15:0|t_burst_max| rw |0x15E| — |
+
+### chip_timing register
+
+- Absolute Address: 0x5D4
+- Base Offset: 0x14
+- Size: 0x4
+
+Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+| Bits| Identifier |Access|Reset|Name|
+|-----|---------------------|------|-----|----|
+| 7:0 |t_read_write_recovery| rw | 0x6 | — |
+| 15:8| t_csh_cycles | rw | 0x1 | — |
+|23:16| csn_to_ck_cycles | rw | 0x0 | — |
+
+### rx_delay register
+
+- Absolute Address: 0x5D8
+- Base Offset: 0x18
+- Size: 0x4
+
+Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| value | rw | 0x10| — |
+
+### reserved_top register
+
+- Absolute Address: 0xFFC
+- Base Offset: 0xFFC
+- Size: 0x4
+
+Reserved endpoint that fixes the register window size to 4 KiB.
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0| value | r | 0x0 | — |
diff --git a/include/hyperbus_cfg_regs.h b/include/hyperbus_cfg_regs.h
new file mode 100644
index 0000000..25b7b58
--- /dev/null
+++ b/include/hyperbus_cfg_regs.h
@@ -0,0 +1,438 @@
+// Generated by PeakRDL-cheader - A free and open-source header generator
+// https://github.com/SystemRDL/PeakRDL-cheader
+
+#ifndef HYPERBUS_CFG_REGS_H
+#define HYPERBUS_CFG_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include
+#include
+
+// reg - hyperbus_cfg_regs::ip_version
+#define HYPERBUS_CFG_REGS__IP_VERSION__REVISION_bm 0xff
+#define HYPERBUS_CFG_REGS__IP_VERSION__REVISION_bp 0
+#define HYPERBUS_CFG_REGS__IP_VERSION__REVISION_bw 8
+#define HYPERBUS_CFG_REGS__IP_VERSION__REVISION_reset 0x0
+#define HYPERBUS_CFG_REGS__IP_VERSION__PATCH_bm 0xff00
+#define HYPERBUS_CFG_REGS__IP_VERSION__PATCH_bp 8
+#define HYPERBUS_CFG_REGS__IP_VERSION__PATCH_bw 8
+#define HYPERBUS_CFG_REGS__IP_VERSION__PATCH_reset 0x9
+#define HYPERBUS_CFG_REGS__IP_VERSION__MINOR_bm 0xff0000
+#define HYPERBUS_CFG_REGS__IP_VERSION__MINOR_bp 16
+#define HYPERBUS_CFG_REGS__IP_VERSION__MINOR_bw 8
+#define HYPERBUS_CFG_REGS__IP_VERSION__MINOR_reset 0x0
+#define HYPERBUS_CFG_REGS__IP_VERSION__MAJOR_bm 0xff000000
+#define HYPERBUS_CFG_REGS__IP_VERSION__MAJOR_bp 24
+#define HYPERBUS_CFG_REGS__IP_VERSION__MAJOR_bw 8
+#define HYPERBUS_CFG_REGS__IP_VERSION__MAJOR_reset 0x0
+
+// reg - hyperbus_cfg_regs::reg_if_version
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MINOR_bm 0xffff
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MINOR_bp 0
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MINOR_bw 16
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MINOR_reset 0x0
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MAJOR_bm 0xffff0000
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MAJOR_bp 16
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MAJOR_bw 16
+#define HYPERBUS_CFG_REGS__REG_IF_VERSION__MAJOR_reset 0x1
+
+// reg - hyperbus_cfg_regs::capability
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_CHIPS_bm 0xff
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_CHIPS_bp 0
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_CHIPS_bw 8
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_CHIPS_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_PHYS_bm 0xff00
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_PHYS_bp 8
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_PHYS_bw 8
+#define HYPERBUS_CFG_REGS__CAPABILITY__NUM_PHYS_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_CHIP_CFG_bm 0x10000
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_CHIP_CFG_bp 16
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_CHIP_CFG_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_CHIP_CFG_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_PHY_CFG_bm 0x20000
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_PHY_CFG_bp 17
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_PHY_CFG_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__PER_PHY_CFG_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__CHIP_ENABLE_bm 0x40000
+#define HYPERBUS_CFG_REGS__CAPABILITY__CHIP_ENABLE_bp 18
+#define HYPERBUS_CFG_REGS__CAPABILITY__CHIP_ENABLE_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__CHIP_ENABLE_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__CLOCK_DIVIDER_bm 0x80000
+#define HYPERBUS_CFG_REGS__CAPABILITY__CLOCK_DIVIDER_bp 19
+#define HYPERBUS_CFG_REGS__CAPABILITY__CLOCK_DIVIDER_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__CLOCK_DIVIDER_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__STAGED_APPLY_bm 0x100000
+#define HYPERBUS_CFG_REGS__CAPABILITY__STAGED_APPLY_bp 20
+#define HYPERBUS_CFG_REGS__CAPABILITY__STAGED_APPLY_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__STAGED_APPLY_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__ERROR_STATUS_bm 0x200000
+#define HYPERBUS_CFG_REGS__CAPABILITY__ERROR_STATUS_bp 21
+#define HYPERBUS_CFG_REGS__CAPABILITY__ERROR_STATUS_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__ERROR_STATUS_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_SAMPLE_TIMING_bm 0x400000
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_SAMPLE_TIMING_bp 22
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_SAMPLE_TIMING_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_SAMPLE_TIMING_reset 0x0
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_OE_TIMING_bm 0x800000
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_OE_TIMING_bp 23
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_OE_TIMING_bw 1
+#define HYPERBUS_CFG_REGS__CAPABILITY__RWDS_OE_TIMING_reset 0x0
+
+// reg - hyperbus_cfg_regs::command
+#define HYPERBUS_CFG_REGS__COMMAND__FLUSH_bm 0x1
+#define HYPERBUS_CFG_REGS__COMMAND__FLUSH_bp 0
+#define HYPERBUS_CFG_REGS__COMMAND__FLUSH_bw 1
+#define HYPERBUS_CFG_REGS__COMMAND__FLUSH_reset 0x0
+#define HYPERBUS_CFG_REGS__COMMAND__APPLY_bm 0x2
+#define HYPERBUS_CFG_REGS__COMMAND__APPLY_bp 1
+#define HYPERBUS_CFG_REGS__COMMAND__APPLY_bw 1
+#define HYPERBUS_CFG_REGS__COMMAND__APPLY_reset 0x0
+
+// reg - hyperbus_cfg_regs::status
+#define HYPERBUS_CFG_REGS__STATUS__DECODE_ERROR_bm 0x1
+#define HYPERBUS_CFG_REGS__STATUS__DECODE_ERROR_bp 0
+#define HYPERBUS_CFG_REGS__STATUS__DECODE_ERROR_bw 1
+#define HYPERBUS_CFG_REGS__STATUS__DECODE_ERROR_reset 0x0
+#define HYPERBUS_CFG_REGS__STATUS__BUSY_bm 0x2
+#define HYPERBUS_CFG_REGS__STATUS__BUSY_bp 1
+#define HYPERBUS_CFG_REGS__STATUS__BUSY_bw 1
+#define HYPERBUS_CFG_REGS__STATUS__BUSY_reset 0x0
+#define HYPERBUS_CFG_REGS__STATUS__DIRTY_bm 0x4
+#define HYPERBUS_CFG_REGS__STATUS__DIRTY_bp 2
+#define HYPERBUS_CFG_REGS__STATUS__DIRTY_bw 1
+#define HYPERBUS_CFG_REGS__STATUS__DIRTY_reset 0x0
+
+// regfile - hyperbus_cfg_regs::global_regs
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t ip_version;
+ uint32_t reg_if_version;
+ uint32_t capability;
+ uint32_t command;
+ uint32_t status;
+} hyperbus_cfg_regs__global_regs_t;
+
+// reg - hyperbus_cfg_regs::frontend_cfg
+#define HYPERBUS_CFG_REGS__FRONTEND_CFG__DUAL_PHY_bm 0x1
+#define HYPERBUS_CFG_REGS__FRONTEND_CFG__DUAL_PHY_bp 0
+#define HYPERBUS_CFG_REGS__FRONTEND_CFG__DUAL_PHY_bw 1
+#define HYPERBUS_CFG_REGS__FRONTEND_CFG__DUAL_PHY_reset 0x1
+
+// regfile - hyperbus_cfg_regs::frontend_regs
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t frontend_cfg;
+} hyperbus_cfg_regs__frontend_regs_t;
+
+// reg - hyperbus_cfg_regs::clock_cfg
+#define HYPERBUS_CFG_REGS__CLOCK_CFG__DIVIDER_bm 0xff
+#define HYPERBUS_CFG_REGS__CLOCK_CFG__DIVIDER_bp 0
+#define HYPERBUS_CFG_REGS__CLOCK_CFG__DIVIDER_bw 8
+#define HYPERBUS_CFG_REGS__CLOCK_CFG__DIVIDER_reset 0x8
+
+// regfile - hyperbus_cfg_regs::backend_regs
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t clock_cfg;
+} hyperbus_cfg_regs__backend_regs_t;
+
+// reg - hyperbus_cfg_regs::tx_delay
+#define HYPERBUS_CFG_REGS__TX_DELAY__VALUE_bm 0xff
+#define HYPERBUS_CFG_REGS__TX_DELAY__VALUE_bp 0
+#define HYPERBUS_CFG_REGS__TX_DELAY__VALUE_bw 8
+#define HYPERBUS_CFG_REGS__TX_DELAY__VALUE_reset 0x10
+
+// reg - hyperbus_cfg_regs::rwds_timing
+#define HYPERBUS_CFG_REGS__RWDS_TIMING__RWDS_OE_SETUP_CYCLES_bm 0xff
+#define HYPERBUS_CFG_REGS__RWDS_TIMING__RWDS_OE_SETUP_CYCLES_bp 0
+#define HYPERBUS_CFG_REGS__RWDS_TIMING__RWDS_OE_SETUP_CYCLES_bw 8
+#define HYPERBUS_CFG_REGS__RWDS_TIMING__RWDS_OE_SETUP_CYCLES_reset 0x1
+
+// regfile - hyperbus_cfg_regs::phy_regs
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t tx_delay;
+ uint32_t rwds_timing;
+} hyperbus_cfg_regs__phy_regs_t;
+
+// reg - hyperbus_cfg_regs::range_base
+#define HYPERBUS_CFG_REGS__RANGE_BASE__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE__VALUE_reset 0x0
+
+// reg - hyperbus_cfg_regs::range_bound
+#define HYPERBUS_CFG_REGS__RANGE_BOUND__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND__VALUE_reset 0x1
+
+// reg - hyperbus_cfg_regs::address_cfg
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_SPACE_bm 0xff
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_SPACE_bp 0
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_SPACE_bw 8
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_SPACE_reset 0x0
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_MASK_MSB_bm 0xff00
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_MASK_MSB_bp 8
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_MASK_MSB_bw 8
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ADDRESS_MASK_MSB_reset 0x19
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ENABLE_bm 0x10000
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ENABLE_bp 16
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ENABLE_bw 1
+#define HYPERBUS_CFG_REGS__ADDRESS_CFG__ENABLE_reset 0x1
+
+// reg - hyperbus_cfg_regs::latency_cfg
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__T_LATENCY_ACCESS_bm 0xff
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__T_LATENCY_ACCESS_bp 0
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__T_LATENCY_ACCESS_bw 8
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__T_LATENCY_ACCESS_reset 0x6
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__RWDS_SAMPLE_DELAY_bm 0xff00
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__RWDS_SAMPLE_DELAY_bp 8
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__RWDS_SAMPLE_DELAY_bw 8
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__RWDS_SAMPLE_DELAY_reset 0x0
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__EN_LATENCY_ADDITIONAL_bm 0x10000
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__EN_LATENCY_ADDITIONAL_bp 16
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__EN_LATENCY_ADDITIONAL_bw 1
+#define HYPERBUS_CFG_REGS__LATENCY_CFG__EN_LATENCY_ADDITIONAL_reset 0x0
+
+// reg - hyperbus_cfg_regs::burst_cfg
+#define HYPERBUS_CFG_REGS__BURST_CFG__T_BURST_MAX_bm 0xffff
+#define HYPERBUS_CFG_REGS__BURST_CFG__T_BURST_MAX_bp 0
+#define HYPERBUS_CFG_REGS__BURST_CFG__T_BURST_MAX_bw 16
+#define HYPERBUS_CFG_REGS__BURST_CFG__T_BURST_MAX_reset 0x15e
+
+// reg - hyperbus_cfg_regs::chip_timing
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_READ_WRITE_RECOVERY_bm 0xff
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_READ_WRITE_RECOVERY_bp 0
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_READ_WRITE_RECOVERY_bw 8
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_READ_WRITE_RECOVERY_reset 0x6
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_CSH_CYCLES_bm 0xff00
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_CSH_CYCLES_bp 8
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_CSH_CYCLES_bw 8
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__T_CSH_CYCLES_reset 0x1
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__CSN_TO_CK_CYCLES_bm 0xff0000
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__CSN_TO_CK_CYCLES_bp 16
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__CSN_TO_CK_CYCLES_bw 8
+#define HYPERBUS_CFG_REGS__CHIP_TIMING__CSN_TO_CK_CYCLES_reset 0x0
+
+// reg - hyperbus_cfg_regs::rx_delay
+#define HYPERBUS_CFG_REGS__RX_DELAY__VALUE_bm 0xff
+#define HYPERBUS_CFG_REGS__RX_DELAY__VALUE_bp 0
+#define HYPERBUS_CFG_REGS__RX_DELAY__VALUE_bw 8
+#define HYPERBUS_CFG_REGS__RX_DELAY__VALUE_reset 0x10
+
+// regfile - hyperbus_cfg_regs::chip_regs
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_aea1d0e1
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_AEA1D0E1__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_AEA1D0E1__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_AEA1D0E1__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_AEA1D0E1__VALUE_reset 0x1
+
+// reg - hyperbus_cfg_regs::range_bound_value_e30f0c3f
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_E30F0C3F__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_E30F0C3F__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_E30F0C3F__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_E30F0C3F__VALUE_reset 0x2
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_de2a4636_range_bound_d40fd139
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_de2a4636_range_bound_d40fd139_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_e30f0c3f
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_E30F0C3F__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_E30F0C3F__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_E30F0C3F__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_E30F0C3F__VALUE_reset 0x2
+
+// reg - hyperbus_cfg_regs::range_bound_value_2f629ec9
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_2F629EC9__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_2F629EC9__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_2F629EC9__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_2F629EC9__VALUE_reset 0x3
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_b054dd4c_range_bound_a4d5f83b
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_b054dd4c_range_bound_a4d5f83b_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_2f629ec9
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_2F629EC9__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_2F629EC9__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_2F629EC9__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_2F629EC9__VALUE_reset 0x3
+
+// reg - hyperbus_cfg_regs::range_bound_value_a1e733c2
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_A1E733C2__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_A1E733C2__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_A1E733C2__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_A1E733C2__VALUE_reset 0x4
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_f7266ded_range_bound_5bf260e9
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_f7266ded_range_bound_5bf260e9_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_a1e733c2
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_A1E733C2__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_A1E733C2__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_A1E733C2__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_A1E733C2__VALUE_reset 0x4
+
+// reg - hyperbus_cfg_regs::range_bound_value_342915db
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_342915DB__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_342915DB__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_342915DB__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_342915DB__VALUE_reset 0x5
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_0d543b99_range_bound_1fffc3a2
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_0d543b99_range_bound_1fffc3a2_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_342915db
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_342915DB__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_342915DB__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_342915DB__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_342915DB__VALUE_reset 0x5
+
+// reg - hyperbus_cfg_regs::range_bound_value_883c384f
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_883C384F__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_883C384F__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_883C384F__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_883C384F__VALUE_reset 0x6
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_e068ab2e_range_bound_9afa5911
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_e068ab2e_range_bound_9afa5911_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_883c384f
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_883C384F__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_883C384F__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_883C384F__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_883C384F__VALUE_reset 0x6
+
+// reg - hyperbus_cfg_regs::range_bound_value_d0d03147
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_D0D03147__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_D0D03147__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_D0D03147__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_D0D03147__VALUE_reset 0x7
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_ac4fb754_range_bound_24b9644b
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_ac4fb754_range_bound_24b9644b_t;
+
+// reg - hyperbus_cfg_regs::range_base_value_d0d03147
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_D0D03147__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_D0D03147__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_D0D03147__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BASE_VALUE_D0D03147__VALUE_reset 0x7
+
+// reg - hyperbus_cfg_regs::range_bound_value_971bab53
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_971BAB53__VALUE_bm 0xffc00000
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_971BAB53__VALUE_bp 22
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_971BAB53__VALUE_bw 10
+#define HYPERBUS_CFG_REGS__RANGE_BOUND_VALUE_971BAB53__VALUE_reset 0x8
+
+// regfile - hyperbus_cfg_regs::chip_regs_range_base_63c2ba90_range_bound_602aea67
+typedef struct __attribute__ ((__packed__)) {
+ uint32_t range_base;
+ uint32_t range_bound;
+ uint32_t address_cfg;
+ uint32_t latency_cfg;
+ uint32_t burst_cfg;
+ uint32_t chip_timing;
+ uint32_t rx_delay;
+} hyperbus_cfg_regs__chip_regs_range_base_63c2ba90_range_bound_602aea67_t;
+
+// reg - hyperbus_cfg_regs::reserved_top
+#define HYPERBUS_CFG_REGS__RESERVED_TOP__VALUE_bm 0xffffffff
+#define HYPERBUS_CFG_REGS__RESERVED_TOP__VALUE_bp 0
+#define HYPERBUS_CFG_REGS__RESERVED_TOP__VALUE_bw 32
+#define HYPERBUS_CFG_REGS__RESERVED_TOP__VALUE_reset 0x0
+
+// addrmap - hyperbus_cfg_regs
+typedef struct __attribute__ ((__packed__)) {
+ hyperbus_cfg_regs__global_regs_t global_cfg;
+ uint8_t RESERVED_14_ff[0xec];
+ hyperbus_cfg_regs__frontend_regs_t frontend;
+ uint8_t RESERVED_104_1ff[0xfc];
+ hyperbus_cfg_regs__backend_regs_t backend;
+ uint8_t RESERVED_204_2ff[0xfc];
+ hyperbus_cfg_regs__phy_regs_t phy_0;
+ uint8_t RESERVED_308_33f[0x38];
+ hyperbus_cfg_regs__phy_regs_t phy_1;
+ uint8_t RESERVED_348_3ff[0xb8];
+ hyperbus_cfg_regs__chip_regs_t chip_0;
+ uint8_t RESERVED_41c_43f[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_de2a4636_range_bound_d40fd139_t chip_1;
+ uint8_t RESERVED_45c_47f[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_b054dd4c_range_bound_a4d5f83b_t chip_2;
+ uint8_t RESERVED_49c_4bf[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_f7266ded_range_bound_5bf260e9_t chip_3;
+ uint8_t RESERVED_4dc_4ff[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_0d543b99_range_bound_1fffc3a2_t chip_4;
+ uint8_t RESERVED_51c_53f[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_e068ab2e_range_bound_9afa5911_t chip_5;
+ uint8_t RESERVED_55c_57f[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_ac4fb754_range_bound_24b9644b_t chip_6;
+ uint8_t RESERVED_59c_5bf[0x24];
+ hyperbus_cfg_regs__chip_regs_range_base_63c2ba90_range_bound_602aea67_t chip_7;
+ uint8_t RESERVED_5dc_ffb[0xa20];
+ uint32_t reserved_top;
+} hyperbus_cfg_regs_t;
+
+
+static_assert(sizeof(hyperbus_cfg_regs_t) == 0x1000, "Packing error");
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HYPERBUS_CFG_REGS_H */
diff --git a/scripts/gen_regs.sh b/scripts/gen_regs.sh
new file mode 100755
index 0000000..8ceb003
--- /dev/null
+++ b/scripts/gen_regs.sh
@@ -0,0 +1,48 @@
+#!/usr/bin/env bash
+# Copyright 2026 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+set -euo pipefail
+
+ROOT="$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)"
+UV_CACHE_DIR="${UV_CACHE_DIR:-/tmp/uv-cache}"
+UV_TOOL_DIR="${UV_TOOL_DIR:-/tmp/uv-tools}"
+export UV_CACHE_DIR
+export UV_TOOL_DIR
+
+RDL="${ROOT}/src/regs/hyperbus_cfg_regs.rdl"
+PEAKRDL_ARGS=(
+ --from "peakrdl-cli==1.5.0"
+ --with "peakrdl-regblock==1.3.1"
+ --with "peakrdl-cheader==1.1.0"
+ --with "peakrdl-markdown==1.0.3"
+)
+
+mkdir -p "${ROOT}/include" "${ROOT}/docs/regs"
+rm -rf "${ROOT}/docs/regs/hyperbus_cfg_regs"
+
+uvx "${PEAKRDL_ARGS[@]}" \
+ peakrdl regblock \
+ --cpuif apb4-flat \
+ --default-reset arst_n \
+ --module-name hyperbus_cfg_regblock \
+ --package-name hyperbus_cfg_regblock_pkg \
+ --addr-width 12 \
+ -o "${ROOT}/src/regs" \
+ "${RDL}"
+
+uvx "${PEAKRDL_ARGS[@]}" \
+ peakrdl c-header \
+ -o "${ROOT}/include/hyperbus_cfg_regs.h" \
+ "${RDL}"
+
+uvx "${PEAKRDL_ARGS[@]}" \
+ peakrdl markdown \
+ -o "${ROOT}/docs/regs/hyperbus_cfg_regs.md" \
+ "${RDL}"
+
+# Keep generated RTL compatible with the repository whitespace checks.
+sed -i 's/[[:space:]]\+$//' \
+ "${ROOT}/src/regs/hyperbus_cfg_regblock.sv" \
+ "${ROOT}/src/regs/hyperbus_cfg_regblock_pkg.sv"
diff --git a/scripts/start.tcl b/scripts/start.tcl
index 0488812..f4408ad 100644
--- a/scripts/start.tcl
+++ b/scripts/start.tcl
@@ -2,12 +2,42 @@
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
-vsim axi_hyper_tb -t 1ps -voptargs=+acc -classdebug
+set regression_failed 0
-set StdArithNoWarnings 1
-set NumericStdNoWarnings 1
-log -r /*
+proc run_test {top_name wlf_name} {
+ global regression_failed
-delete wave *
+ puts "=============================="
+ puts "= Running $top_name"
+ puts "=============================="
-run -all
+ set transcript_name "[file rootname $wlf_name].log"
+ file delete -force $transcript_name
+ transcript file $transcript_name
+
+ vsim $top_name -wlf $wlf_name -t 1ps -voptargs=+acc -classdebug
+
+ onfinish stop
+ set StdArithNoWarnings 1
+ set NumericStdNoWarnings 1
+ log -r /*
+
+ catch {delete wave *}
+
+ run -all
+ quit -sim
+
+ transcript file {}
+ set transcript_fd [open $transcript_name r]
+ set transcript_data [read $transcript_fd]
+ close $transcript_fd
+ if {[regexp -line {^# \*\* (Error|Fatal)( \([^)]*\))?:} $transcript_data]} {
+ puts "Regression errors detected in $transcript_name"
+ set regression_failed 1
+ }
+}
+
+run_test axi_hyper_tb sim_run_axi.wlf
+run_test hyperbus_cfg_regs_tb sim_run_cfg_regs.wlf
+
+quit -code $regression_failed -f
diff --git a/src/hyperbus.sv b/src/hyperbus.sv
index da287fa..e0889db 100644
--- a/src/hyperbus.sv
+++ b/src/hyperbus.sv
@@ -21,18 +21,14 @@ module hyperbus #(
parameter type axi_ar_chan_t = logic,
parameter type axi_r_chan_t = logic,
parameter type axi_aw_chan_t = logic,
- parameter int unsigned RegAddrWidth = -1,
parameter int unsigned RegDataWidth = -1,
- parameter int unsigned MinFreqMHz = 100,
+ parameter int unsigned RegAddrWidth = 32,
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic,
parameter type axi_rule_t = logic,
// The below have sensible defaults, but should be set on integration!
parameter int unsigned RxFifoLogDepth = 3,
parameter int unsigned TxFifoLogDepth = 3,
- parameter logic [RegDataWidth-1:0] RstChipBase = 'h0, // Base address for all chips
- parameter logic [RegDataWidth-1:0] RstChipSpace = 'h1_0000, // 64 KiB: Current maximum HyperBus device size
- parameter hyperbus_pkg::hyper_cfg_t RstCfg = hyperbus_pkg::gen_RstCfg(NumPhys,MinFreqMHz),
parameter int unsigned PhyStartupCycles = 300 * 200, /* us*MHz */ // Conservative maximum frequency estimate
parameter int unsigned SyncStages = 2
) (
@@ -85,9 +81,10 @@ module hyperbus #(
logic clk_phy_0, clk_phy_90, rst_phy;
// Register file
- hyperbus_pkg::hyper_cfg_t cfg;
- axi_rule_t [NumChips-1:0] chip_rules;
- logic trans_active;
+ hyperbus_pkg::frontend_cfg_t frontend_cfg;
+ hyperbus_pkg::phy_cfg_t phy_cfg;
+ axi_rule_t [NumChips-1:0] chip_rules;
+ logic trans_active;
// AXI slave
hyper_rx_t axi_rx;
@@ -121,22 +118,26 @@ module hyperbus #(
hyperbus_cfg_regs #(
.NumChips ( NumChips ),
.NumPhys ( NumPhys ),
- .RegAddrWidth ( RegAddrWidth ),
.RegDataWidth ( RegDataWidth ),
+ .RegAddrWidth ( RegAddrWidth ),
+ .CapabilityFeatures ( '0 ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
- .rule_t ( axi_rule_t ),
- .RstChipBase ( RstChipBase ),
- .RstChipSpace ( RstChipSpace ),
- .RstCfg ( RstCfg )
+ .rule_t ( axi_rule_t )
) i_cfg_regs (
.clk_i ( clk_sys_i ),
.rst_ni ( rst_sys_ni ),
.reg_req_i ( reg_req_i ),
.reg_rsp_o ( reg_rsp_o ),
- .cfg_o ( cfg ),
+ .frontend_cfg_o ( frontend_cfg ),
+ .phy_cfg_o ( phy_cfg ),
.chip_rules_o ( chip_rules ),
- .trans_active_i ( trans_active )
+ .trans_active_i ( trans_active ),
+ .cfg_busy_i ( trans_active ),
+ .decode_error_i ( 1'b0 ),
+ .cfg_dirty_i ( 1'b0 ),
+ .flush_req_o ( ),
+ .apply_req_o ( )
);
// AXI slave interfacing PHY
@@ -173,11 +174,8 @@ module hyperbus #(
.trans_valid_o ( axi_trans_valid ),
.trans_ready_i ( axi_trans_ready ),
+ .frontend_cfg_i ( frontend_cfg ),
.chip_rules_i ( chip_rules ),
- .which_phy_i ( cfg.which_phy ),
- .phys_in_use_i ( cfg.phys_in_use ),
- .addr_mask_msb_i ( cfg.address_mask_msb ),
- .addr_space_i ( cfg.address_space ),
.trans_active_o ( trans_active )
);
@@ -214,7 +212,7 @@ module hyperbus #(
.rst_phy_ni ( rst_phy ),
.test_mode_i ( test_mode_i ),
- .cfg_i ( cfg ),
+ .cfg_i ( phy_cfg ),
.rx_o ( phy_rx ),
.rx_valid_o ( phy_rx_valid ),
diff --git a/src/hyperbus_axi.sv b/src/hyperbus_axi.sv
index 78b3c7d..bac8778 100644
--- a/src/hyperbus_axi.sv
+++ b/src/hyperbus_axi.sv
@@ -44,11 +44,8 @@ module hyperbus_axi #(
output logic trans_valid_o,
input logic trans_ready_i,
- input rule_t [NumChips-1:0] chip_rules_i,
- input logic phys_in_use_i,
- input logic which_phy_i,
- input logic [4:0] addr_mask_msb_i,
- input logic addr_space_i,
+ input hyperbus_pkg::frontend_cfg_t frontend_cfg_i,
+ input rule_t [NumChips-1:0] chip_rules_i,
output logic trans_active_o
);
@@ -163,7 +160,7 @@ module hyperbus_axi #(
logic [1:0] phys_in_use;
- assign phys_in_use = (NumPhys==2) ? (phys_in_use_i + 1) : 1;
+ assign phys_in_use = (NumPhys==2) ? (frontend_cfg_i.phys_in_use + 1) : 1;
// ============================
// Serialize requests
@@ -305,12 +302,12 @@ module hyperbus_axi #(
// AX channel: forward, converting unmasked byte to masked word addresses
assign trans_o.write = rr_out_req_write;
assign trans_o.burst_type = 1'b1; // Wrapping bursts not (yet) supported
- assign trans_o.address_space = addr_space_i;
+ assign trans_o.address_space = frontend_cfg_i.address_space;
assign trans_o.address = (NumPhys == 2) ?
- (phys_in_use_i ?
- ((rr_out_req_ax.addr & ((32'b1 << addr_mask_msb_i) - 1)) >> 2) :
- (((rr_out_req_ax.addr & ((32'b1 << addr_mask_msb_i) - 1)) >> 2) << 1)) :
- ((rr_out_req_ax.addr & ((32'b1 << addr_mask_msb_i) - 1)) >> 1);
+ (frontend_cfg_i.phys_in_use ?
+ ((rr_out_req_ax.addr & ((32'b1 << frontend_cfg_i.address_mask_msb) - 1)) >> 2) :
+ (((rr_out_req_ax.addr & ((32'b1 << frontend_cfg_i.address_mask_msb) - 1)) >> 2) << 1)) :
+ ((rr_out_req_ax.addr & ((32'b1 << frontend_cfg_i.address_mask_msb) - 1)) >> 1);
// Convert burst length from decremented, unaligned beats to non-decremented, aligned 16-bit words
always_comb begin
@@ -365,11 +362,11 @@ module hyperbus_axi #(
s_rx_error = rx_i.error;
s_rx_data_lower_d = s_rx_data_lower_q;
merge_r_d = merge_r_q;
- if( (NumPhys==2) & (~phys_in_use_i) ) begin
+ if( (NumPhys==2) & (~frontend_cfg_i.phys_in_use) ) begin
if(rx_valid_i & s_rx_ready) begin
merge_r_d = merge_r_q + 1;
end
- if(~which_phy_i)
+ if(~frontend_cfg_i.which_phy)
s_rx_data = { rx_i.data[PhyDataWidth/2-1:0] , s_rx_data_lower_q };
else
s_rx_data = { rx_i.data[PhyDataWidth-1:PhyDataWidth/2] , s_rx_data_lower_q };
@@ -378,7 +375,7 @@ module hyperbus_axi #(
s_rx_last = rx_i.last & merge_r_q;
s_rx_error = rx_i.error;
if(~merge_r_q) begin
- if(~which_phy_i)
+ if(~frontend_cfg_i.which_phy)
s_rx_data_lower_d = rx_i.data[PhyDataWidth/2-1:0];
else
s_rx_data_lower_d = rx_i.data[PhyDataWidth-1:PhyDataWidth/2];
@@ -469,7 +466,7 @@ module hyperbus_axi #(
tx_valid_o = s_tx_valid;
s_tx_ready = tx_ready_i;
split_w_d = split_w_q;
- if( (NumPhys==2) & (~phys_in_use_i) ) begin
+ if( (NumPhys==2) & (~frontend_cfg_i.phys_in_use) ) begin
if(s_tx_valid & tx_ready_i) begin
split_w_d = split_w_q+1;
end
diff --git a/src/hyperbus_cfg_regs.sv b/src/hyperbus_cfg_regs.sv
index 70ac78e..22162c5 100644
--- a/src/hyperbus_cfg_regs.sv
+++ b/src/hyperbus_cfg_regs.sv
@@ -4,133 +4,314 @@
//
// Paul Scheffler
+`include "common_cells/assertions.svh"
+
module hyperbus_cfg_regs #(
parameter int unsigned NumChips = -1,
parameter int unsigned NumPhys = -1,
- parameter int unsigned RegAddrWidth = -1,
parameter int unsigned RegDataWidth = -1,
+ parameter int unsigned RegAddrWidth = 32,
+ parameter logic [7:0] CapabilityFeatures = '0,
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic,
- parameter type rule_t = logic,
- parameter logic [RegDataWidth-1:0] RstChipBase = -1, // Base address for all chips
- parameter logic [RegDataWidth-1:0] RstChipSpace = -1, // 64 KiB: Current maximum HyperBus device size
- parameter int unsigned MinFreqMHz = 100,
- parameter hyperbus_pkg::hyper_cfg_t RstCfg = hyperbus_pkg::gen_RstCfg(NumPhys,MinFreqMHz)
+ parameter type rule_t = logic
) (
- input logic clk_i,
- input logic rst_ni,
+ input logic clk_i,
+ input logic rst_ni,
input reg_req_t reg_req_i,
output reg_rsp_t reg_rsp_o,
- output hyperbus_pkg::hyper_cfg_t cfg_o,
+ output hyperbus_pkg::frontend_cfg_t frontend_cfg_o,
+ output hyperbus_pkg::phy_cfg_t phy_cfg_o,
output rule_t [NumChips-1:0] chip_rules_o,
- input trans_active_i
+ input logic trans_active_i,
+ input logic cfg_busy_i,
+ input logic decode_error_i,
+ input logic cfg_dirty_i,
+ output logic flush_req_o,
+ output logic apply_req_o
);
`include "common_cells/registers.svh"
- // Internal Parameters
- localparam int unsigned NumBaseRegs = 12;
- localparam int unsigned NumRegs = 2*NumChips + NumBaseRegs;
- localparam int unsigned RegsBits = cf_math_pkg::idx_width(NumRegs);
- localparam int unsigned RegStrbWidth = RegDataWidth/8;
-
- // Data and index types
- typedef logic [RegsBits-1:0] reg_idx_t;
- typedef logic [RegDataWidth-1:0] reg_data_t;
-
- // Local signals
- hyperbus_pkg::hyper_cfg_t cfg_d, cfg_q, cfg_rstval;
- reg_data_t [NumChips-1:0][1:0] crange_d, crange_q, crange_rstval;
- reg_idx_t sel_reg;
- logic sel_reg_mapped;
- reg_data_t wmask;
-
- assign sel_reg = reg_req_i.addr[$clog2(RegStrbWidth) +: RegsBits];
- assign sel_reg_mapped = (sel_reg < NumRegs);
-
- assign reg_rsp_o.ready = ~trans_active_i; // Config writeable unless currently in transfer
- assign reg_rsp_o.error = ~sel_reg_mapped;
-
- // Read from register
- always_comb begin : proc_comb_read
- reg_data_t [NumRegs-1:0] rfield;
- reg_rsp_o.rdata = '0;
- if (sel_reg_mapped) begin
- rfield = {
- crange_q,
- reg_data_t'(cfg_q.csn_to_ck_cycles),
- reg_data_t'(cfg_q.t_csh_cycles),
- reg_data_t'(cfg_q.which_phy),
- reg_data_t'(cfg_q.phys_in_use),
- reg_data_t'(cfg_q.address_space),
- reg_data_t'(cfg_q.address_mask_msb),
- reg_data_t'(cfg_q.t_tx_clk_delay),
- reg_data_t'(cfg_q.t_rx_clk_delay),
- reg_data_t'(cfg_q.t_read_write_recovery),
- reg_data_t'(cfg_q.t_burst_max),
- reg_data_t'(cfg_q.en_latency_additional),
- reg_data_t'(cfg_q.t_latency_access)
- };
- reg_rsp_o.rdata = rfield[sel_reg];
+ localparam int unsigned NumChipsMax = 8;
+ `ASSERT_INIT(NumChipsValid, NumChips >= 1 && NumChips <= NumChipsMax)
+ `ASSERT_INIT(NumPhysValid, NumPhys == 1 || NumPhys == 2)
+ `ASSERT_INIT(RegAddrWidthValid, RegAddrWidth >= 12)
+ `ASSERT_INIT(RegDataWidthValid, RegDataWidth == 32)
+
+ typedef logic [11:0] cfg_addr_t;
+ typedef logic [31:0] cfg_data_t;
+ typedef logic [3:0] cfg_strb_t;
+
+ typedef struct packed {
+ cfg_addr_t addr;
+ logic write;
+ cfg_data_t wdata;
+ cfg_strb_t wstrb;
+ logic valid;
+ } cfg_reg_req_t;
+
+ typedef struct packed {
+ cfg_data_t rdata;
+ logic error;
+ logic ready;
+ } cfg_reg_rsp_t;
+
+ typedef struct packed {
+ cfg_addr_t paddr;
+ logic [2:0] pprot;
+ logic psel;
+ logic penable;
+ logic pwrite;
+ cfg_data_t pwdata;
+ cfg_strb_t pstrb;
+ } cfg_apb_req_t;
+
+ typedef struct packed {
+ logic pready;
+ cfg_data_t prdata;
+ logic pslverr;
+ } cfg_apb_rsp_t;
+
+ hyperbus_cfg_regblock_pkg::hyperbus_cfg_regs__out_t cfg_hwif_out;
+ hyperbus_cfg_regblock_pkg::hyperbus_cfg_regs__in_t cfg_hwif_in;
+ rule_t [NumChipsMax-1:0] chip_rules_all;
+
+ cfg_addr_t cfg_addr;
+ logic cfg_addr_in_window;
+ logic sel_reg_mapped;
+ logic cfg_access_active_d, cfg_access_active_q;
+ logic cfg_access_open;
+ logic cfg_status_access;
+ logic cfg_value_valid;
+ logic unused_cfg_fields;
+
+ cfg_reg_req_t cfg_reg_req;
+ cfg_reg_rsp_t cfg_reg_rsp;
+ cfg_apb_req_t cfg_apb_req;
+ cfg_apb_rsp_t cfg_apb_rsp;
+
+ assign cfg_addr = cfg_addr_t'(reg_req_i.addr);
+ assign cfg_addr_in_window = reg_req_i.addr == RegAddrWidth'(cfg_addr);
+ assign cfg_status_access = reg_req_i.valid &&
+ cfg_addr_in_window && (cfg_addr == 12'h010);
+
+ always_comb begin : proc_cfg_addr_mapped
+ sel_reg_mapped = cfg_addr_in_window &&
+ ((cfg_addr == 12'h000) ||
+ (cfg_addr == 12'h004) ||
+ (cfg_addr == 12'h008) ||
+ (cfg_addr == 12'h00c) ||
+ (cfg_addr == 12'h010) ||
+ (cfg_addr == 12'h100) ||
+ (cfg_addr == 12'h200) ||
+ (cfg_addr == 12'hffc));
+ for (int unsigned i = 0; i < 2; i++) begin
+ sel_reg_mapped |= cfg_addr_in_window &&
+ ((cfg_addr == (12'h300 + i * 12'h40)) ||
+ (cfg_addr == (12'h304 + i * 12'h40)));
+ end
+ for (int unsigned i = 0; i < 8; i++) begin
+ sel_reg_mapped |= cfg_addr_in_window &&
+ ((cfg_addr == (12'h400 + i * 12'h40)) ||
+ (cfg_addr == (12'h404 + i * 12'h40)) ||
+ (cfg_addr == (12'h408 + i * 12'h40)) ||
+ (cfg_addr == (12'h40c + i * 12'h40)) ||
+ (cfg_addr == (12'h410 + i * 12'h40)) ||
+ (cfg_addr == (12'h414 + i * 12'h40)) ||
+ (cfg_addr == (12'h418 + i * 12'h40)));
end
end
+ assign cfg_access_open = ~trans_active_i | cfg_access_active_q | cfg_status_access;
- // Generate write mask
- for (genvar i = 0; unsigned'(i) < RegStrbWidth; ++i ) begin : gen_wmask
- assign wmask[8*i +: 8] = {8{reg_req_i.wstrb[i]}};
+ always_comb begin : proc_cfg_value_valid
+ cfg_value_valid = 1'b1;
+ if (reg_req_i.valid && reg_req_i.write && sel_reg_mapped) begin
+ // All byte-backed legacy values are range-checked only when their
+ // corresponding byte is written, preserving partial-write behavior.
+ if ((cfg_addr == 12'h100) && reg_req_i.wstrb[0]) begin
+ cfg_value_valid &= (reg_req_i.wdata[7:0] <= 8'd1);
+ end
+ if ((cfg_addr == 12'h200) && reg_req_i.wstrb[0]) begin
+ cfg_value_valid &= (reg_req_i.wdata[7:0] >= 8'd2);
+ end
+ if (((cfg_addr == 12'h304) || (cfg_addr == 12'h344)) &&
+ reg_req_i.wstrb[0]) begin
+ cfg_value_valid &= (reg_req_i.wdata[7:0] <= 8'd15);
+ end
+ for (int unsigned i = 0; i < 8; i++) begin
+ if (cfg_addr == (12'h408 + i * 12'h40)) begin
+ if (reg_req_i.wstrb[0]) cfg_value_valid &= (reg_req_i.wdata[7:0] <= 8'd1);
+ if (reg_req_i.wstrb[1]) cfg_value_valid &= (reg_req_i.wdata[15:8] <= 8'd31);
+ if (reg_req_i.wstrb[2]) cfg_value_valid &= (reg_req_i.wdata[23:16] <= 8'd1);
+ end
+ if (cfg_addr == (12'h40c + i * 12'h40)) begin
+ if (reg_req_i.wstrb[0]) cfg_value_valid &=
+ (reg_req_i.wdata[7:0] >= 8'd3 && reg_req_i.wdata[7:0] <= 8'd15);
+ if (reg_req_i.wstrb[1]) cfg_value_valid &= (reg_req_i.wdata[15:8] <= 8'd15);
+ if (reg_req_i.wstrb[2]) cfg_value_valid &= (reg_req_i.wdata[23:16] <= 8'd1);
+ end
+ if (cfg_addr == (12'h414 + i * 12'h40)) begin
+ if (reg_req_i.wstrb[0]) cfg_value_valid &= (reg_req_i.wdata[7:0] <= 8'd15);
+ if (reg_req_i.wstrb[1]) cfg_value_valid &= (reg_req_i.wdata[15:8] <= 8'd15);
+ if (reg_req_i.wstrb[2]) cfg_value_valid &= (reg_req_i.wdata[23:16] <= 8'd15);
+ end
+ end
+ end
end
- // Write to register
- always_comb begin : proc_comb_write
- logic chip_reg;
- logic [$clog2(NumChips)-1:0] sel_chip;
- cfg_d = cfg_q;
- crange_d = crange_q;
- if (reg_req_i.valid & reg_req_i.write & sel_reg_mapped) begin
- case (sel_reg)
- 'h0: cfg_d.t_latency_access = (~wmask & cfg_q.t_latency_access ) | (wmask & reg_req_i.wdata);
- 'h1: cfg_d.en_latency_additional = (~wmask & cfg_q.en_latency_additional ) | (wmask & reg_req_i.wdata);
- 'h2: cfg_d.t_burst_max = (~wmask & cfg_q.t_burst_max ) | (wmask & reg_req_i.wdata);
- 'h3: cfg_d.t_read_write_recovery = (~wmask & cfg_q.t_read_write_recovery ) | (wmask & reg_req_i.wdata);
- 'h4: cfg_d.t_rx_clk_delay = (~wmask & cfg_q.t_rx_clk_delay ) | (wmask & reg_req_i.wdata);
- 'h5: cfg_d.t_tx_clk_delay = (~wmask & cfg_q.t_tx_clk_delay ) | (wmask & reg_req_i.wdata);
- 'h6: cfg_d.address_mask_msb = (~wmask & cfg_q.address_mask_msb ) | (wmask & reg_req_i.wdata);
- 'h7: cfg_d.address_space = (~wmask & cfg_q.address_space ) | (wmask & reg_req_i.wdata);
- 'h8: cfg_d.phys_in_use = (NumPhys==1) ? 0 : ( (~wmask & cfg_q.phys_in_use ) | (wmask & reg_req_i.wdata) );
- 'h9: cfg_d.which_phy = (NumPhys==1) ? 0 : ( (~wmask & cfg_q.which_phy ) | (wmask & reg_req_i.wdata) );
- 'ha: cfg_d.t_csh_cycles = (~wmask & cfg_q.t_csh_cycles ) | (wmask & reg_req_i.wdata);
- 'hb: cfg_d.csn_to_ck_cycles = (~wmask & cfg_q.csn_to_ck_cycles ) | (wmask & reg_req_i.wdata);
- default: begin
- {sel_chip, chip_reg} = sel_reg - NumBaseRegs;
- crange_d[sel_chip][chip_reg] = (~wmask & crange_q[sel_chip][chip_reg]) | (wmask & reg_req_i.wdata);
- end
- endcase // sel_reg
+ assign reg_rsp_o.ready = cfg_access_open &
+ (~reg_req_i.valid | ~sel_reg_mapped | ~cfg_value_valid | cfg_reg_rsp.ready);
+ assign reg_rsp_o.error = (reg_req_i.valid && ~sel_reg_mapped) |
+ (reg_req_i.valid && reg_req_i.write && sel_reg_mapped && !cfg_value_valid) |
+ cfg_reg_rsp.error;
+ assign reg_rsp_o.rdata = sel_reg_mapped ? RegDataWidth'(cfg_reg_rsp.rdata) : '0;
+
+ assign cfg_reg_req.valid = reg_req_i.valid & sel_reg_mapped & cfg_access_open & cfg_value_valid;
+ assign cfg_reg_req.addr = cfg_addr;
+ assign cfg_reg_req.write = reg_req_i.write;
+ assign cfg_reg_req.wdata = 32'(reg_req_i.wdata);
+ assign cfg_reg_req.wstrb = cfg_strb_t'(reg_req_i.wstrb);
+
+ always_comb begin : proc_cfg_access
+ cfg_access_active_d = cfg_access_active_q;
+ if (!cfg_access_active_q && cfg_reg_req.valid && !cfg_status_access) begin
+ cfg_access_active_d = 1'b1;
+ end
+ if (cfg_access_active_q && cfg_reg_rsp.ready) begin
+ cfg_access_active_d = 1'b0;
end
end
- for (genvar i = 0; unsigned'(i) < NumChips; i++) begin : gen_crange_rstval
- assign crange_rstval[i][0] = RstChipBase + (RstChipSpace * i);
- assign crange_rstval[i][1] = RstChipBase + (RstChipSpace * (i+1)); // Address decoder: end noninclusive
+ `FFARN(cfg_access_active_q, cfg_access_active_d, 1'b0, clk_i, rst_ni);
+
+ always_comb begin : proc_chip_rules
+ chip_rules_all = '0;
+ for (int unsigned i = 0; i < NumChipsMax; i++) begin
+ chip_rules_all[i].idx = unsigned'(i);
+ end
+ chip_rules_all[0].start_addr = {cfg_hwif_out.chip_0.range_base.value.value, 22'b0};
+ chip_rules_all[0].end_addr = {cfg_hwif_out.chip_0.range_bound.value.value, 22'b0};
+ chip_rules_all[1].start_addr = {cfg_hwif_out.chip_1.range_base.value.value, 22'b0};
+ chip_rules_all[1].end_addr = {cfg_hwif_out.chip_1.range_bound.value.value, 22'b0};
+ chip_rules_all[2].start_addr = {cfg_hwif_out.chip_2.range_base.value.value, 22'b0};
+ chip_rules_all[2].end_addr = {cfg_hwif_out.chip_2.range_bound.value.value, 22'b0};
+ chip_rules_all[3].start_addr = {cfg_hwif_out.chip_3.range_base.value.value, 22'b0};
+ chip_rules_all[3].end_addr = {cfg_hwif_out.chip_3.range_bound.value.value, 22'b0};
+ chip_rules_all[4].start_addr = {cfg_hwif_out.chip_4.range_base.value.value, 22'b0};
+ chip_rules_all[4].end_addr = {cfg_hwif_out.chip_4.range_bound.value.value, 22'b0};
+ chip_rules_all[5].start_addr = {cfg_hwif_out.chip_5.range_base.value.value, 22'b0};
+ chip_rules_all[5].end_addr = {cfg_hwif_out.chip_5.range_bound.value.value, 22'b0};
+ chip_rules_all[6].start_addr = {cfg_hwif_out.chip_6.range_base.value.value, 22'b0};
+ chip_rules_all[6].end_addr = {cfg_hwif_out.chip_6.range_bound.value.value, 22'b0};
+ chip_rules_all[7].start_addr = {cfg_hwif_out.chip_7.range_base.value.value, 22'b0};
+ chip_rules_all[7].end_addr = {cfg_hwif_out.chip_7.range_bound.value.value, 22'b0};
end
- // Registers
- `FFARN(cfg_q, cfg_d, RstCfg, clk_i, rst_ni);
- `FFARN(crange_q, crange_d, crange_rstval, clk_i, rst_ni);
+ assign cfg_hwif_in.global_cfg.capability.num_chips.next = 8'(NumChips);
+ assign cfg_hwif_in.global_cfg.capability.num_phys.next = 8'(NumPhys);
+ assign cfg_hwif_in.global_cfg.capability.per_chip_cfg.next = CapabilityFeatures[0];
+ assign cfg_hwif_in.global_cfg.capability.per_phy_cfg.next = CapabilityFeatures[1];
+ assign cfg_hwif_in.global_cfg.capability.chip_enable.next = CapabilityFeatures[2];
+ assign cfg_hwif_in.global_cfg.capability.clock_divider.next = CapabilityFeatures[3];
+ assign cfg_hwif_in.global_cfg.capability.staged_apply.next = CapabilityFeatures[4];
+ assign cfg_hwif_in.global_cfg.capability.error_status.next = CapabilityFeatures[5];
+ assign cfg_hwif_in.global_cfg.capability.rwds_sample_timing.next =
+ CapabilityFeatures[6];
+ assign cfg_hwif_in.global_cfg.capability.rwds_oe_timing.next = CapabilityFeatures[7];
+ assign cfg_hwif_in.global_cfg.status.decode_error.next =
+ cfg_hwif_out.global_cfg.status.decode_error.value;
+ assign cfg_hwif_in.global_cfg.status.decode_error.hwset = decode_error_i;
+ assign cfg_hwif_in.global_cfg.status.busy.next = cfg_busy_i;
+ assign cfg_hwif_in.global_cfg.status.dirty.next = cfg_dirty_i;
+ assign flush_req_o = cfg_hwif_out.global_cfg.command.flush.value;
+ assign apply_req_o = cfg_hwif_out.global_cfg.command.apply.value;
+
+ reg_to_apb #(
+ .reg_req_t ( cfg_reg_req_t ),
+ .reg_rsp_t ( cfg_reg_rsp_t ),
+ .apb_req_t ( cfg_apb_req_t ),
+ .apb_rsp_t ( cfg_apb_rsp_t )
+ ) i_reg_to_apb (
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_ni ),
+ .reg_req_i ( cfg_reg_req ),
+ .reg_rsp_o ( cfg_reg_rsp ),
+ .apb_req_o ( cfg_apb_req ),
+ .apb_rsp_i ( cfg_apb_rsp )
+ );
- // Outputs
- assign cfg_o = cfg_q;
- for (genvar i = 0; unsigned'(i) < NumChips; ++i) begin : gen_crange_out
- assign chip_rules_o[i].idx = unsigned'(i); // No overlap: keep indices sequential
- assign chip_rules_o[i].start_addr = crange_q[i][0];
- assign chip_rules_o[i].end_addr = crange_q[i][1];
+ hyperbus_cfg_regblock i_cfg_regblock (
+ .clk ( clk_i ),
+ .arst_n ( rst_ni ),
+ .s_apb_psel ( cfg_apb_req.psel ),
+ .s_apb_penable ( cfg_apb_req.penable ),
+ .s_apb_pwrite ( cfg_apb_req.pwrite ),
+ .s_apb_pprot ( cfg_apb_req.pprot ),
+ .s_apb_paddr ( cfg_apb_req.paddr ),
+ .s_apb_pwdata ( cfg_apb_req.pwdata ),
+ .s_apb_pstrb ( cfg_apb_req.pstrb ),
+ .s_apb_pready ( cfg_apb_rsp.pready ),
+ .s_apb_prdata ( cfg_apb_rsp.prdata ),
+ .s_apb_pslverr ( cfg_apb_rsp.pslverr ),
+ .hwif_in ( cfg_hwif_in ),
+ .hwif_out ( cfg_hwif_out )
+ );
+
+ always_comb begin : proc_cfg_output
+ frontend_cfg_o = '0;
+ phy_cfg_o = '0;
+
+ frontend_cfg_o.address_mask_msb = cfg_hwif_out.chip_0.address_cfg.address_mask_msb.value;
+ frontend_cfg_o.address_space = cfg_hwif_out.chip_0.address_cfg.address_space.value[0];
+ frontend_cfg_o.phys_in_use = (NumPhys == 2) &&
+ cfg_hwif_out.frontend.frontend_cfg.dual_phy.value;
+ frontend_cfg_o.which_phy = 1'b0;
+
+ phy_cfg_o.chip.t_latency_access = cfg_hwif_out.chip_0.latency_cfg.t_latency_access.value;
+ phy_cfg_o.chip.en_latency_additional = cfg_hwif_out.chip_0.latency_cfg.en_latency_additional.value;
+ phy_cfg_o.chip.t_burst_max = cfg_hwif_out.chip_0.burst_cfg.t_burst_max.value;
+ phy_cfg_o.chip.t_read_write_recovery = cfg_hwif_out.chip_0.chip_timing.t_read_write_recovery.value;
+ phy_cfg_o.chip.t_rx_clk_delay = cfg_hwif_out.chip_0.rx_delay.value.value;
+ phy_cfg_o.chip.t_csh_cycles = cfg_hwif_out.chip_0.chip_timing.t_csh_cycles.value;
+ phy_cfg_o.chip.csn_to_ck_cycles = cfg_hwif_out.chip_0.chip_timing.csn_to_ck_cycles.value;
+ phy_cfg_o.t_tx_clk_delay = cfg_hwif_out.phy_0.tx_delay.value.value;
+ phy_cfg_o.phys_in_use = (NumPhys == 2) &&
+ cfg_hwif_out.frontend.frontend_cfg.dual_phy.value;
+ phy_cfg_o.which_phy = 1'b0;
end
- // pragma translate_off
- `ifndef VERILATOR
- initial assert (RegDataWidth >= 16 && $countones(RegDataWidth) == 1)
- else $error("RegDataWidth must be a power of two bigger than 16.");
- `endif
- // pragma translate_on
+ // The legacy PR34 interface has no destinations for these newer fields.
+ always_comb begin : proc_unused_cfg_fields
+ unused_cfg_fields = ^cfg_hwif_out.backend.clock_cfg.divider.value;
+ unused_cfg_fields |= ^cfg_hwif_out.phy_0.rwds_timing.rwds_oe_setup_cycles.value;
+ unused_cfg_fields |= ^cfg_hwif_out.phy_1.rwds_timing.rwds_oe_setup_cycles.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_0.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_0.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_1.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_1.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_2.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_2.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_3.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_3.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_4.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_4.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_5.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_5.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_6.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_6.latency_cfg.rwds_sample_delay.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_7.address_cfg.enable.value;
+ unused_cfg_fields |= ^cfg_hwif_out.chip_7.latency_cfg.rwds_sample_delay.value;
+ end
+
+ for (genvar i = 0; unsigned'(i) < NumChipsMax; i++) begin : gen_chip_rules
+ if (i < NumChips) begin : gen_active
+ assign chip_rules_o[i] = chip_rules_all[i];
+ end else begin : gen_inactive
+ logic unused_chip_rule;
+ assign unused_chip_rule = ^chip_rules_all[i];
+ end
+ end
endmodule : hyperbus_cfg_regs
diff --git a/src/hyperbus_phy.sv b/src/hyperbus_phy.sv
index 43a5a8d..11c9f84 100644
--- a/src/hyperbus_phy.sv
+++ b/src/hyperbus_phy.sv
@@ -22,7 +22,7 @@ module hyperbus_phy import hyperbus_pkg::*; #(
input logic rst_ni,
input logic test_mode_i,
// Config registers
- input hyper_cfg_t cfg_i,
+ input phy_cfg_t cfg_i,
// PHY control status
output logic busy_o,
// Transactions
@@ -133,7 +133,7 @@ module hyperbus_phy import hyperbus_pkg::*; #(
.tx_data_oe_i ( trx_tx_data_oe ),
.tx_rwds_i ( trx_tx_rwds ),
.tx_rwds_oe_i ( trx_tx_rwds_oe ),
- .rx_clk_delay_i ( cfg_i.t_rx_clk_delay ),
+ .rx_clk_delay_i ( cfg_i.chip.t_rx_clk_delay ),
.rx_clk_set_i ( trx_rx_clk_set ),
.rx_clk_reset_i ( trx_rx_clk_reset ),
.rx_data_o ( trx_rx_data ),
@@ -221,8 +221,8 @@ module hyperbus_phy import hyperbus_pkg::*; #(
// Auxiliary control signals
assign ctl_write_zero_lat = tf_q.address_space & tf_q.write;
- // cfg_i.en_latency_additional overwrites the sampled RWDS value.
- assign ctl_add_latency = trx_rwds_sample | cfg_i.en_latency_additional;
+ // cfg_i.chip.en_latency_additional overwrites the sampled RWDS value.
+ assign ctl_add_latency = trx_rwds_sample | cfg_i.chip.en_latency_additional;
assign ctl_tf_burst_last = (tf_q.burst == 1) || (tf_q.burst == phys_in_use);
assign ctl_tf_burst_done = (tf_q.burst == 0);
@@ -272,11 +272,11 @@ module hyperbus_phy import hyperbus_pkg::*; #(
cs_d = trans_cs_i;
add_latency_d = 1'b0;
- if(cfg_i.csn_to_ck_cycles != 0) begin
+ if(cfg_i.chip.csn_to_ck_cycles != 0) begin
// assert CS but delay hyper_ck to allow more time
// for memory to drive RWDS (to satisfy t_DSV)
state_d = DelayCK;
- timer_d = cfg_i.csn_to_ck_cycles -1;
+ timer_d = cfg_i.chip.csn_to_ck_cycles -1;
end else begin
// max throughput when memory RWDS signal arrives early
state_d = SendCA;
@@ -305,10 +305,10 @@ module hyperbus_phy import hyperbus_pkg::*; #(
trx_rwds_sample_ena = ~ctl_write_zero_lat;
if (ctl_timer_zero) begin
if (ctl_write_zero_lat) begin
- timer_d = cfg_i.t_burst_max;
+ timer_d = cfg_i.chip.t_burst_max;
state_d = Write;
end else begin
- timer_d = TimerWidth'(cfg_i.t_latency_access);
+ timer_d = TimerWidth'(cfg_i.chip.t_latency_access);
add_latency_d = ctl_add_latency;
state_d = WaitLatAccess;
end
@@ -325,7 +325,7 @@ module hyperbus_phy import hyperbus_pkg::*; #(
if (~add_latency_q) begin
// Substract cycle for last CA and another for state delay
if(ctl_timer_two) begin
- timer_d = cfg_i.t_burst_max;
+ timer_d = cfg_i.chip.t_burst_max;
// Switch to write or read phase and already start
// turnaround of tri-state driver (depending on latency
// config and if read or write transaction).
@@ -345,7 +345,7 @@ module hyperbus_phy import hyperbus_pkg::*; #(
end else if (ctl_timer_one) begin
// instead of going to 0, add another latency count
state_d = WaitAddLatAccess;
- timer_d = TimerWidth'(cfg_i.t_latency_access);
+ timer_d = TimerWidth'(cfg_i.chip.t_latency_access);
add_latency_d = 1'b0;
end
end
@@ -355,7 +355,7 @@ module hyperbus_phy import hyperbus_pkg::*; #(
trx_clk_ena = 1'b1;
trx_tx_data_oe = 1'b1;
if (ctl_timer_two) begin
- timer_d = cfg_i.t_burst_max;
+ timer_d = cfg_i.chip.t_burst_max;
if (tf_q.write) begin
state_d = Write;
trx_tx_data_oe = 1'b1;
@@ -376,13 +376,13 @@ module hyperbus_phy import hyperbus_pkg::*; #(
tf_d.burst = tf_q.burst - phys_in_use;
tf_d.address = tf_q.address + 1;
if (ctl_tf_burst_last) begin
- timer_d = cfg_i.t_csh_cycles;
+ timer_d = cfg_i.chip.t_csh_cycles;
state_d = WaitXfer;
end
end
// Force-terminate access on burst time limit
if (ctl_timer_one) begin
- timer_d = cfg_i.t_csh_cycles;
+ timer_d = cfg_i.chip.t_csh_cycles;
state_d = WaitXfer;
end
end
@@ -398,13 +398,13 @@ module hyperbus_phy import hyperbus_pkg::*; #(
tf_d.address = tf_q.address + 1;
if (ctl_tf_burst_last) begin
b_pending_set = 1'b1;
- timer_d = cfg_i.t_csh_cycles;
+ timer_d = cfg_i.chip.t_csh_cycles;
state_d = WaitXfer;
end
end
// Force-terminate access on burst time limit
if (ctl_timer_one) begin
- timer_d = cfg_i.t_csh_cycles;
+ timer_d = cfg_i.chip.t_csh_cycles;
state_d = WaitXfer;
end
end
@@ -412,7 +412,7 @@ module hyperbus_phy import hyperbus_pkg::*; #(
// Wait for FFed Clock and output to stop
// May have to be prolonged for potential future devices with t_CSH > 0
if (ctl_timer_zero) begin
- timer_d = cfg_i.t_read_write_recovery;
+ timer_d = cfg_i.chip.t_read_write_recovery;
state_d = WaitRWR;
end
end
diff --git a/src/hyperbus_phy_if.sv b/src/hyperbus_phy_if.sv
index ac165af..baf51f7 100644
--- a/src/hyperbus_phy_if.sv
+++ b/src/hyperbus_phy_if.sv
@@ -22,7 +22,7 @@ module hyperbus_phy_if import hyperbus_pkg::*; #(
input logic rst_phy_ni,
input logic test_mode_i,
// Config registers
- input hyper_cfg_t cfg_i,
+ input phy_cfg_t cfg_i,
// Transactions
input logic trans_valid_i,
output logic trans_ready_o,
diff --git a/src/hyperbus_pkg.sv b/src/hyperbus_pkg.sv
index 3f97a7a..49149ef 100644
--- a/src/hyperbus_pkg.sv
+++ b/src/hyperbus_pkg.sv
@@ -15,14 +15,23 @@ package hyperbus_pkg;
logic [15:0] t_burst_max;
logic [3:0] t_read_write_recovery;
logic [7:0] t_rx_clk_delay;
- logic [7:0] t_tx_clk_delay;
+ logic [3:0] t_csh_cycles; // configurable t_CSH for high-frequency operation (200 MHz HyperRAM)
+ logic [3:0] csn_to_ck_cycles; // delay hyper_ck after CS is asserted (more time for t_DSV)
+ } chip_phy_cfg_t;
+
+ typedef struct packed {
logic [4:0] address_mask_msb;
logic address_space;
logic phys_in_use;
logic which_phy;
- logic [3:0] t_csh_cycles; // configurable t_CSH for high-frequency operation (200 MHz HyperRAM)
- logic [3:0] csn_to_ck_cycles; // delay hyper_ck after CS is asserted (more time for t_DSV)
- } hyper_cfg_t;
+ } frontend_cfg_t;
+
+ typedef struct packed {
+ chip_phy_cfg_t chip;
+ logic [7:0] t_tx_clk_delay;
+ logic phys_in_use;
+ logic which_phy;
+ } phy_cfg_t;
typedef struct packed {
logic write; // transaction is a write
@@ -60,28 +69,4 @@ package hyperbus_pkg;
logic [2:0] addr_lower;
} hyper_phy_ca_t;
-
- // Register reset values
- function automatic hyper_cfg_t gen_RstCfg(input int unsigned NumPhys, input int unsigned MinFreqMhz);
- // MinFreqMHz = 100 is spec-compliant and should not be changed.
- // It can be lowered if this frequency is not reachable in operation (this may not work with certain HyperBus devices).
- // >200 is outside the spec and is unlikely to work with any HyperBus devices
- automatic hyper_cfg_t cfg = hyper_cfg_t'{
- t_latency_access: 'h6,
- en_latency_additional: 'b0,
- t_burst_max: ((MinFreqMhz*35)/10), // t_{csm}: At lowest legal clock (100 MHz) 3.5us (0.5us safety margin)
- t_read_write_recovery: 'h6,
- t_rx_clk_delay: 'h10,
- t_tx_clk_delay: 'h10,
- address_mask_msb: 'd25, // 2^(address mask MSB) = single chip size [bytes]
- address_space: 'b0,
- phys_in_use: NumPhys-1,
- which_phy: NumPhys-1,
- t_csh_cycles: 'h1,
- csn_to_ck_cycles: 4'h0 // additional cycles from CS_N going low to start of hyper_ck
- };
-
- return cfg;
- endfunction
-
endpackage
diff --git a/src/hyperbus_synth_wrap.sv b/src/hyperbus_synth_wrap.sv
index 8b1935e..ed9ccc4 100644
--- a/src/hyperbus_synth_wrap.sv
+++ b/src/hyperbus_synth_wrap.sv
@@ -145,8 +145,8 @@ module hyperbus_lint_wrap #(
.axi_ar_chan_t ( ar_chan_t ),
.axi_r_chan_t ( r_chan_t ),
.axi_aw_chan_t ( aw_chan_t ),
- .RegAddrWidth ( RegAddrWidth ),
.RegDataWidth ( RegDataWidth ),
+ .RegAddrWidth ( RegAddrWidth ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.axi_rule_t ( axi_rule_t )
diff --git a/src/regs/hyperbus_cfg_regblock.sv b/src/regs/hyperbus_cfg_regblock.sv
new file mode 100644
index 0000000..ec72f2c
--- /dev/null
+++ b/src/regs/hyperbus_cfg_regblock.sv
@@ -0,0 +1,4665 @@
+// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
+// https://github.com/SystemRDL/PeakRDL-regblock
+
+module hyperbus_cfg_regblock (
+ input wire clk,
+ input wire arst_n,
+
+ input wire s_apb_psel,
+ input wire s_apb_penable,
+ input wire s_apb_pwrite,
+ input wire [2:0] s_apb_pprot,
+ input wire [11:0] s_apb_paddr,
+ input wire [31:0] s_apb_pwdata,
+ input wire [3:0] s_apb_pstrb,
+ output logic s_apb_pready,
+ output logic [31:0] s_apb_prdata,
+ output logic s_apb_pslverr,
+
+ input hyperbus_cfg_regblock_pkg::hyperbus_cfg_regs__in_t hwif_in,
+ output hyperbus_cfg_regblock_pkg::hyperbus_cfg_regs__out_t hwif_out
+ );
+
+ //--------------------------------------------------------------------------
+ // CPU Bus interface logic
+ //--------------------------------------------------------------------------
+ logic cpuif_req;
+ logic cpuif_req_is_wr;
+ logic [11:0] cpuif_addr;
+ logic [31:0] cpuif_wr_data;
+ logic [31:0] cpuif_wr_biten;
+ logic cpuif_req_stall_wr;
+ logic cpuif_req_stall_rd;
+
+ logic cpuif_rd_ack;
+ logic cpuif_rd_err;
+ logic [31:0] cpuif_rd_data;
+
+ logic cpuif_wr_ack;
+ logic cpuif_wr_err;
+
+ // Request
+ logic is_active;
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ is_active <= '0;
+ cpuif_req <= '0;
+ cpuif_req_is_wr <= '0;
+ cpuif_addr <= '0;
+ cpuif_wr_data <= '0;
+ cpuif_wr_biten <= '0;
+ end else begin
+ if(~is_active) begin
+ if(s_apb_psel) begin
+ is_active <= '1;
+ cpuif_req <= '1;
+ cpuif_req_is_wr <= s_apb_pwrite;
+ cpuif_addr <= {s_apb_paddr[11:2], 2'b0};
+ cpuif_wr_data <= s_apb_pwdata;
+ for(int i=0; i<4; i++) begin
+ cpuif_wr_biten[i*8 +: 8] <= {8{s_apb_pstrb[i]}};
+ end
+ end
+ end else begin
+ cpuif_req <= '0;
+ if(cpuif_rd_ack || cpuif_wr_ack) begin
+ is_active <= '0;
+ end
+ end
+ end
+ end
+
+ // Response
+ assign s_apb_pready = cpuif_rd_ack | cpuif_wr_ack;
+ assign s_apb_prdata = cpuif_rd_data;
+ assign s_apb_pslverr = cpuif_rd_err | cpuif_wr_err;
+
+ logic cpuif_req_masked;
+
+ // Read & write latencies are balanced. Stalls not required
+ assign cpuif_req_stall_rd = '0;
+ assign cpuif_req_stall_wr = '0;
+ assign cpuif_req_masked = cpuif_req
+ & !(!cpuif_req_is_wr & cpuif_req_stall_rd)
+ & !(cpuif_req_is_wr & cpuif_req_stall_wr);
+
+ //--------------------------------------------------------------------------
+ // Address Decode
+ //--------------------------------------------------------------------------
+ typedef struct {
+ struct {
+ logic ip_version;
+ logic reg_if_version;
+ logic capability;
+ logic command;
+ logic status;
+ } global_cfg;
+ struct {
+ logic frontend_cfg;
+ } frontend;
+ struct {
+ logic clock_cfg;
+ } backend;
+ struct {
+ logic tx_delay;
+ logic rwds_timing;
+ } phy_0;
+ struct {
+ logic tx_delay;
+ logic rwds_timing;
+ } phy_1;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_0;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_1;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_2;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_3;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_4;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_5;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_6;
+ struct {
+ logic range_base;
+ logic range_bound;
+ logic address_cfg;
+ logic latency_cfg;
+ logic burst_cfg;
+ logic chip_timing;
+ logic rx_delay;
+ } chip_7;
+ logic reserved_top;
+ } decoded_reg_strb_t;
+ decoded_reg_strb_t decoded_reg_strb;
+ logic decoded_err;
+ logic [11:0] decoded_addr;
+ logic decoded_req;
+ logic decoded_req_is_wr;
+ logic [31:0] decoded_wr_data;
+ logic [31:0] decoded_wr_biten;
+
+ always_comb begin
+ automatic logic is_valid_addr;
+ automatic logic is_valid_rw;
+ is_valid_addr = '1; // No valid address check
+ is_valid_rw = '1; // No valid RW check
+ decoded_reg_strb.global_cfg.ip_version = cpuif_req_masked & (cpuif_addr == 12'h0) & !cpuif_req_is_wr;
+ decoded_reg_strb.global_cfg.reg_if_version = cpuif_req_masked & (cpuif_addr == 12'h4) & !cpuif_req_is_wr;
+ decoded_reg_strb.global_cfg.capability = cpuif_req_masked & (cpuif_addr == 12'h8) & !cpuif_req_is_wr;
+ decoded_reg_strb.global_cfg.command = cpuif_req_masked & (cpuif_addr == 12'hc);
+ decoded_reg_strb.global_cfg.status = cpuif_req_masked & (cpuif_addr == 12'h10);
+ decoded_reg_strb.frontend.frontend_cfg = cpuif_req_masked & (cpuif_addr == 12'h100);
+ decoded_reg_strb.backend.clock_cfg = cpuif_req_masked & (cpuif_addr == 12'h200);
+ decoded_reg_strb.phy_0.tx_delay = cpuif_req_masked & (cpuif_addr == 12'h300);
+ decoded_reg_strb.phy_0.rwds_timing = cpuif_req_masked & (cpuif_addr == 12'h304);
+ decoded_reg_strb.phy_1.tx_delay = cpuif_req_masked & (cpuif_addr == 12'h340);
+ decoded_reg_strb.phy_1.rwds_timing = cpuif_req_masked & (cpuif_addr == 12'h344);
+ decoded_reg_strb.chip_0.range_base = cpuif_req_masked & (cpuif_addr == 12'h400);
+ decoded_reg_strb.chip_0.range_bound = cpuif_req_masked & (cpuif_addr == 12'h404);
+ decoded_reg_strb.chip_0.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h408);
+ decoded_reg_strb.chip_0.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h40c);
+ decoded_reg_strb.chip_0.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h410);
+ decoded_reg_strb.chip_0.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h414);
+ decoded_reg_strb.chip_0.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h418);
+ decoded_reg_strb.chip_1.range_base = cpuif_req_masked & (cpuif_addr == 12'h440);
+ decoded_reg_strb.chip_1.range_bound = cpuif_req_masked & (cpuif_addr == 12'h444);
+ decoded_reg_strb.chip_1.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h448);
+ decoded_reg_strb.chip_1.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h44c);
+ decoded_reg_strb.chip_1.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h450);
+ decoded_reg_strb.chip_1.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h454);
+ decoded_reg_strb.chip_1.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h458);
+ decoded_reg_strb.chip_2.range_base = cpuif_req_masked & (cpuif_addr == 12'h480);
+ decoded_reg_strb.chip_2.range_bound = cpuif_req_masked & (cpuif_addr == 12'h484);
+ decoded_reg_strb.chip_2.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h488);
+ decoded_reg_strb.chip_2.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h48c);
+ decoded_reg_strb.chip_2.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h490);
+ decoded_reg_strb.chip_2.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h494);
+ decoded_reg_strb.chip_2.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h498);
+ decoded_reg_strb.chip_3.range_base = cpuif_req_masked & (cpuif_addr == 12'h4c0);
+ decoded_reg_strb.chip_3.range_bound = cpuif_req_masked & (cpuif_addr == 12'h4c4);
+ decoded_reg_strb.chip_3.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h4c8);
+ decoded_reg_strb.chip_3.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h4cc);
+ decoded_reg_strb.chip_3.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h4d0);
+ decoded_reg_strb.chip_3.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h4d4);
+ decoded_reg_strb.chip_3.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h4d8);
+ decoded_reg_strb.chip_4.range_base = cpuif_req_masked & (cpuif_addr == 12'h500);
+ decoded_reg_strb.chip_4.range_bound = cpuif_req_masked & (cpuif_addr == 12'h504);
+ decoded_reg_strb.chip_4.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h508);
+ decoded_reg_strb.chip_4.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h50c);
+ decoded_reg_strb.chip_4.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h510);
+ decoded_reg_strb.chip_4.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h514);
+ decoded_reg_strb.chip_4.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h518);
+ decoded_reg_strb.chip_5.range_base = cpuif_req_masked & (cpuif_addr == 12'h540);
+ decoded_reg_strb.chip_5.range_bound = cpuif_req_masked & (cpuif_addr == 12'h544);
+ decoded_reg_strb.chip_5.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h548);
+ decoded_reg_strb.chip_5.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h54c);
+ decoded_reg_strb.chip_5.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h550);
+ decoded_reg_strb.chip_5.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h554);
+ decoded_reg_strb.chip_5.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h558);
+ decoded_reg_strb.chip_6.range_base = cpuif_req_masked & (cpuif_addr == 12'h580);
+ decoded_reg_strb.chip_6.range_bound = cpuif_req_masked & (cpuif_addr == 12'h584);
+ decoded_reg_strb.chip_6.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h588);
+ decoded_reg_strb.chip_6.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h58c);
+ decoded_reg_strb.chip_6.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h590);
+ decoded_reg_strb.chip_6.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h594);
+ decoded_reg_strb.chip_6.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h598);
+ decoded_reg_strb.chip_7.range_base = cpuif_req_masked & (cpuif_addr == 12'h5c0);
+ decoded_reg_strb.chip_7.range_bound = cpuif_req_masked & (cpuif_addr == 12'h5c4);
+ decoded_reg_strb.chip_7.address_cfg = cpuif_req_masked & (cpuif_addr == 12'h5c8);
+ decoded_reg_strb.chip_7.latency_cfg = cpuif_req_masked & (cpuif_addr == 12'h5cc);
+ decoded_reg_strb.chip_7.burst_cfg = cpuif_req_masked & (cpuif_addr == 12'h5d0);
+ decoded_reg_strb.chip_7.chip_timing = cpuif_req_masked & (cpuif_addr == 12'h5d4);
+ decoded_reg_strb.chip_7.rx_delay = cpuif_req_masked & (cpuif_addr == 12'h5d8);
+ decoded_reg_strb.reserved_top = cpuif_req_masked & (cpuif_addr == 12'hffc) & !cpuif_req_is_wr;
+ decoded_err = '0;
+ end
+
+ // Pass down signals to next stage
+ assign decoded_addr = cpuif_addr;
+ assign decoded_req = cpuif_req_masked;
+ assign decoded_req_is_wr = cpuif_req_is_wr;
+ assign decoded_wr_data = cpuif_wr_data;
+ assign decoded_wr_biten = cpuif_wr_biten;
+
+ //--------------------------------------------------------------------------
+ // Field logic
+ //--------------------------------------------------------------------------
+ typedef struct {
+ struct {
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } num_chips;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } num_phys;
+ struct {
+ logic next;
+ logic load_next;
+ } per_chip_cfg;
+ struct {
+ logic next;
+ logic load_next;
+ } per_phy_cfg;
+ struct {
+ logic next;
+ logic load_next;
+ } chip_enable;
+ struct {
+ logic next;
+ logic load_next;
+ } clock_divider;
+ struct {
+ logic next;
+ logic load_next;
+ } staged_apply;
+ struct {
+ logic next;
+ logic load_next;
+ } error_status;
+ struct {
+ logic next;
+ logic load_next;
+ } rwds_sample_timing;
+ struct {
+ logic next;
+ logic load_next;
+ } rwds_oe_timing;
+ } capability;
+ struct {
+ struct {
+ logic next;
+ logic load_next;
+ } flush;
+ struct {
+ logic next;
+ logic load_next;
+ } apply;
+ } command;
+ struct {
+ struct {
+ logic next;
+ logic load_next;
+ } decode_error;
+ struct {
+ logic next;
+ logic load_next;
+ } busy;
+ struct {
+ logic next;
+ logic load_next;
+ } dirty;
+ } status;
+ } global_cfg;
+ struct {
+ struct {
+ struct {
+ logic next;
+ logic load_next;
+ } dual_phy;
+ } frontend_cfg;
+ } frontend;
+ struct {
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } divider;
+ } clock_cfg;
+ } backend;
+ struct {
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } tx_delay;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_oe_setup_cycles;
+ } rwds_timing;
+ } phy_0;
+ struct {
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } tx_delay;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_oe_setup_cycles;
+ } rwds_timing;
+ } phy_1;
+ struct {
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_0;
+ struct {
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_1;
+ struct {
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_2;
+ struct {
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_3;
+ struct {
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_4;
+ struct {
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_5;
+ struct {
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_6;
+ struct {
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] next;
+ logic load_next;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_space;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } address_mask_msb;
+ struct {
+ logic next;
+ logic load_next;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_latency_access;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } rwds_sample_delay;
+ struct {
+ logic next;
+ logic load_next;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] next;
+ logic load_next;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] next;
+ logic load_next;
+ } value;
+ } rx_delay;
+ } chip_7;
+ } field_combo_t;
+ field_combo_t field_combo;
+
+ typedef struct {
+ struct {
+ struct {
+ struct {
+ logic [7:0] value;
+ } num_chips;
+ struct {
+ logic [7:0] value;
+ } num_phys;
+ struct {
+ logic value;
+ } per_chip_cfg;
+ struct {
+ logic value;
+ } per_phy_cfg;
+ struct {
+ logic value;
+ } chip_enable;
+ struct {
+ logic value;
+ } clock_divider;
+ struct {
+ logic value;
+ } staged_apply;
+ struct {
+ logic value;
+ } error_status;
+ struct {
+ logic value;
+ } rwds_sample_timing;
+ struct {
+ logic value;
+ } rwds_oe_timing;
+ } capability;
+ struct {
+ struct {
+ logic value;
+ } flush;
+ struct {
+ logic value;
+ } apply;
+ } command;
+ struct {
+ struct {
+ logic value;
+ } decode_error;
+ struct {
+ logic value;
+ } busy;
+ struct {
+ logic value;
+ } dirty;
+ } status;
+ } global_cfg;
+ struct {
+ struct {
+ struct {
+ logic value;
+ } dual_phy;
+ } frontend_cfg;
+ } frontend;
+ struct {
+ struct {
+ struct {
+ logic [7:0] value;
+ } divider;
+ } clock_cfg;
+ } backend;
+ struct {
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } tx_delay;
+ struct {
+ struct {
+ logic [7:0] value;
+ } rwds_oe_setup_cycles;
+ } rwds_timing;
+ } phy_0;
+ struct {
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } tx_delay;
+ struct {
+ struct {
+ logic [7:0] value;
+ } rwds_oe_setup_cycles;
+ } rwds_timing;
+ } phy_1;
+ struct {
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_0;
+ struct {
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_1;
+ struct {
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_2;
+ struct {
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_3;
+ struct {
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_4;
+ struct {
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_5;
+ struct {
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_6;
+ struct {
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_base;
+ struct {
+ struct {
+ logic [9:0] value;
+ } value;
+ } range_bound;
+ struct {
+ struct {
+ logic [7:0] value;
+ } address_space;
+ struct {
+ logic [7:0] value;
+ } address_mask_msb;
+ struct {
+ logic value;
+ } enable;
+ } address_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_latency_access;
+ struct {
+ logic [7:0] value;
+ } rwds_sample_delay;
+ struct {
+ logic value;
+ } en_latency_additional;
+ } latency_cfg;
+ struct {
+ struct {
+ logic [15:0] value;
+ } t_burst_max;
+ } burst_cfg;
+ struct {
+ struct {
+ logic [7:0] value;
+ } t_read_write_recovery;
+ struct {
+ logic [7:0] value;
+ } t_csh_cycles;
+ struct {
+ logic [7:0] value;
+ } csn_to_ck_cycles;
+ } chip_timing;
+ struct {
+ struct {
+ logic [7:0] value;
+ } value;
+ } rx_delay;
+ } chip_7;
+ } field_storage_t;
+ field_storage_t field_storage;
+
+ assign hwif_out.global_cfg.ip_version.revision.value = 8'h0;
+ assign hwif_out.global_cfg.ip_version.patch.value = 8'h9;
+ assign hwif_out.global_cfg.ip_version.minor.value = 8'h0;
+ assign hwif_out.global_cfg.ip_version.major.value = 8'h0;
+ assign hwif_out.global_cfg.reg_if_version.minor.value = 16'h0;
+ assign hwif_out.global_cfg.reg_if_version.major.value = 16'h1;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.num_chips
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.num_chips.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.num_chips.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.num_chips.next = next_c;
+ field_combo.global_cfg.capability.num_chips.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.num_chips.value <= 8'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.num_chips.load_next) begin
+ field_storage.global_cfg.capability.num_chips.value <= field_combo.global_cfg.capability.num_chips.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.capability.num_chips.value = field_storage.global_cfg.capability.num_chips.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.num_phys
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.num_phys.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.num_phys.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.num_phys.next = next_c;
+ field_combo.global_cfg.capability.num_phys.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.num_phys.value <= 8'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.num_phys.load_next) begin
+ field_storage.global_cfg.capability.num_phys.value <= field_combo.global_cfg.capability.num_phys.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.capability.num_phys.value = field_storage.global_cfg.capability.num_phys.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.per_chip_cfg
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.per_chip_cfg.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.per_chip_cfg.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.per_chip_cfg.next = next_c;
+ field_combo.global_cfg.capability.per_chip_cfg.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.per_chip_cfg.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.per_chip_cfg.load_next) begin
+ field_storage.global_cfg.capability.per_chip_cfg.value <= field_combo.global_cfg.capability.per_chip_cfg.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.capability.per_chip_cfg.value = field_storage.global_cfg.capability.per_chip_cfg.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.per_phy_cfg
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.per_phy_cfg.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.per_phy_cfg.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.per_phy_cfg.next = next_c;
+ field_combo.global_cfg.capability.per_phy_cfg.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.per_phy_cfg.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.per_phy_cfg.load_next) begin
+ field_storage.global_cfg.capability.per_phy_cfg.value <= field_combo.global_cfg.capability.per_phy_cfg.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.capability.per_phy_cfg.value = field_storage.global_cfg.capability.per_phy_cfg.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.chip_enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.chip_enable.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.chip_enable.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.chip_enable.next = next_c;
+ field_combo.global_cfg.capability.chip_enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.chip_enable.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.chip_enable.load_next) begin
+ field_storage.global_cfg.capability.chip_enable.value <= field_combo.global_cfg.capability.chip_enable.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.capability.chip_enable.value = field_storage.global_cfg.capability.chip_enable.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.clock_divider
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.clock_divider.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.clock_divider.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.clock_divider.next = next_c;
+ field_combo.global_cfg.capability.clock_divider.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.clock_divider.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.clock_divider.load_next) begin
+ field_storage.global_cfg.capability.clock_divider.value <= field_combo.global_cfg.capability.clock_divider.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.capability.clock_divider.value = field_storage.global_cfg.capability.clock_divider.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.staged_apply
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.staged_apply.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.staged_apply.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.staged_apply.next = next_c;
+ field_combo.global_cfg.capability.staged_apply.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.staged_apply.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.staged_apply.load_next) begin
+ field_storage.global_cfg.capability.staged_apply.value <= field_combo.global_cfg.capability.staged_apply.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.capability.staged_apply.value = field_storage.global_cfg.capability.staged_apply.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.error_status
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.error_status.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.error_status.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.error_status.next = next_c;
+ field_combo.global_cfg.capability.error_status.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.error_status.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.error_status.load_next) begin
+ field_storage.global_cfg.capability.error_status.value <= field_combo.global_cfg.capability.error_status.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.capability.error_status.value = field_storage.global_cfg.capability.error_status.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.rwds_sample_timing
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.rwds_sample_timing.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.rwds_sample_timing.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.rwds_sample_timing.next = next_c;
+ field_combo.global_cfg.capability.rwds_sample_timing.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.rwds_sample_timing.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.rwds_sample_timing.load_next) begin
+ field_storage.global_cfg.capability.rwds_sample_timing.value <= field_combo.global_cfg.capability.rwds_sample_timing.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.capability.rwds_sample_timing.value = field_storage.global_cfg.capability.rwds_sample_timing.value;
+ // Field: hyperbus_cfg_regs.global_cfg.capability.rwds_oe_timing
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.capability.rwds_oe_timing.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.capability.rwds_oe_timing.next;
+ load_next_c = '1;
+ field_combo.global_cfg.capability.rwds_oe_timing.next = next_c;
+ field_combo.global_cfg.capability.rwds_oe_timing.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.capability.rwds_oe_timing.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.capability.rwds_oe_timing.load_next) begin
+ field_storage.global_cfg.capability.rwds_oe_timing.value <= field_combo.global_cfg.capability.rwds_oe_timing.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.capability.rwds_oe_timing.value = field_storage.global_cfg.capability.rwds_oe_timing.value;
+ // Field: hyperbus_cfg_regs.global_cfg.command.flush
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.command.flush.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.global_cfg.command && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.global_cfg.command.flush.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ load_next_c = '1;
+ end else begin // singlepulse clears back to 0
+ next_c = '0;
+ load_next_c = '1;
+ end
+ field_combo.global_cfg.command.flush.next = next_c;
+ field_combo.global_cfg.command.flush.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.command.flush.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.command.flush.load_next) begin
+ field_storage.global_cfg.command.flush.value <= field_combo.global_cfg.command.flush.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.command.flush.value = field_storage.global_cfg.command.flush.value;
+ // Field: hyperbus_cfg_regs.global_cfg.command.apply
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.command.apply.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.global_cfg.command && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.global_cfg.command.apply.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
+ load_next_c = '1;
+ end else begin // singlepulse clears back to 0
+ next_c = '0;
+ load_next_c = '1;
+ end
+ field_combo.global_cfg.command.apply.next = next_c;
+ field_combo.global_cfg.command.apply.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.command.apply.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.command.apply.load_next) begin
+ field_storage.global_cfg.command.apply.value <= field_combo.global_cfg.command.apply.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.command.apply.value = field_storage.global_cfg.command.apply.value;
+ // Field: hyperbus_cfg_regs.global_cfg.status.decode_error
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.status.decode_error.value;
+ load_next_c = '0;
+ if(hwif_in.global_cfg.status.decode_error.hwset) begin // HW Set
+ next_c = '1;
+ load_next_c = '1;
+ end else if(decoded_reg_strb.global_cfg.status && decoded_req_is_wr) begin // SW write 1 clear
+ next_c = field_storage.global_cfg.status.decode_error.value & ~(decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ load_next_c = '1;
+ end else begin // HW Write
+ next_c = hwif_in.global_cfg.status.decode_error.next;
+ load_next_c = '1;
+ end
+ field_combo.global_cfg.status.decode_error.next = next_c;
+ field_combo.global_cfg.status.decode_error.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.status.decode_error.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.status.decode_error.load_next) begin
+ field_storage.global_cfg.status.decode_error.value <= field_combo.global_cfg.status.decode_error.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.status.decode_error.value = field_storage.global_cfg.status.decode_error.value;
+ // Field: hyperbus_cfg_regs.global_cfg.status.busy
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.status.busy.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.status.busy.next;
+ load_next_c = '1;
+ field_combo.global_cfg.status.busy.next = next_c;
+ field_combo.global_cfg.status.busy.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.status.busy.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.status.busy.load_next) begin
+ field_storage.global_cfg.status.busy.value <= field_combo.global_cfg.status.busy.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.status.busy.value = field_storage.global_cfg.status.busy.value;
+ // Field: hyperbus_cfg_regs.global_cfg.status.dirty
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.global_cfg.status.dirty.value;
+ load_next_c = '0;
+
+ // HW Write
+ next_c = hwif_in.global_cfg.status.dirty.next;
+ load_next_c = '1;
+ field_combo.global_cfg.status.dirty.next = next_c;
+ field_combo.global_cfg.status.dirty.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.global_cfg.status.dirty.value <= 1'h0;
+ end else begin
+ if(field_combo.global_cfg.status.dirty.load_next) begin
+ field_storage.global_cfg.status.dirty.value <= field_combo.global_cfg.status.dirty.next;
+ end
+ end
+ end
+ assign hwif_out.global_cfg.status.dirty.value = field_storage.global_cfg.status.dirty.value;
+ // Field: hyperbus_cfg_regs.frontend.frontend_cfg.dual_phy
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.frontend.frontend_cfg.dual_phy.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.frontend.frontend_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.frontend.frontend_cfg.dual_phy.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ load_next_c = '1;
+ end
+ field_combo.frontend.frontend_cfg.dual_phy.next = next_c;
+ field_combo.frontend.frontend_cfg.dual_phy.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.frontend.frontend_cfg.dual_phy.value <= 1'h1;
+ end else begin
+ if(field_combo.frontend.frontend_cfg.dual_phy.load_next) begin
+ field_storage.frontend.frontend_cfg.dual_phy.value <= field_combo.frontend.frontend_cfg.dual_phy.next;
+ end
+ end
+ end
+ assign hwif_out.frontend.frontend_cfg.dual_phy.value = field_storage.frontend.frontend_cfg.dual_phy.value;
+ // Field: hyperbus_cfg_regs.backend.clock_cfg.divider
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.backend.clock_cfg.divider.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.backend.clock_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.backend.clock_cfg.divider.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.backend.clock_cfg.divider.next = next_c;
+ field_combo.backend.clock_cfg.divider.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.backend.clock_cfg.divider.value <= 8'h8;
+ end else begin
+ if(field_combo.backend.clock_cfg.divider.load_next) begin
+ field_storage.backend.clock_cfg.divider.value <= field_combo.backend.clock_cfg.divider.next;
+ end
+ end
+ end
+ assign hwif_out.backend.clock_cfg.divider.value = field_storage.backend.clock_cfg.divider.value;
+ // Field: hyperbus_cfg_regs.phy_0.tx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.phy_0.tx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.phy_0.tx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.phy_0.tx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.phy_0.tx_delay.value.next = next_c;
+ field_combo.phy_0.tx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.phy_0.tx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.phy_0.tx_delay.value.load_next) begin
+ field_storage.phy_0.tx_delay.value.value <= field_combo.phy_0.tx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.phy_0.tx_delay.value.value = field_storage.phy_0.tx_delay.value.value;
+ // Field: hyperbus_cfg_regs.phy_0.rwds_timing.rwds_oe_setup_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.phy_0.rwds_timing.rwds_oe_setup_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.phy_0.rwds_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.phy_0.rwds_timing.rwds_oe_setup_cycles.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.phy_0.rwds_timing.rwds_oe_setup_cycles.next = next_c;
+ field_combo.phy_0.rwds_timing.rwds_oe_setup_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.phy_0.rwds_timing.rwds_oe_setup_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.phy_0.rwds_timing.rwds_oe_setup_cycles.load_next) begin
+ field_storage.phy_0.rwds_timing.rwds_oe_setup_cycles.value <= field_combo.phy_0.rwds_timing.rwds_oe_setup_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.phy_0.rwds_timing.rwds_oe_setup_cycles.value = field_storage.phy_0.rwds_timing.rwds_oe_setup_cycles.value;
+ // Field: hyperbus_cfg_regs.phy_1.tx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.phy_1.tx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.phy_1.tx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.phy_1.tx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.phy_1.tx_delay.value.next = next_c;
+ field_combo.phy_1.tx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.phy_1.tx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.phy_1.tx_delay.value.load_next) begin
+ field_storage.phy_1.tx_delay.value.value <= field_combo.phy_1.tx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.phy_1.tx_delay.value.value = field_storage.phy_1.tx_delay.value.value;
+ // Field: hyperbus_cfg_regs.phy_1.rwds_timing.rwds_oe_setup_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.phy_1.rwds_timing.rwds_oe_setup_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.phy_1.rwds_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.phy_1.rwds_timing.rwds_oe_setup_cycles.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.phy_1.rwds_timing.rwds_oe_setup_cycles.next = next_c;
+ field_combo.phy_1.rwds_timing.rwds_oe_setup_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.phy_1.rwds_timing.rwds_oe_setup_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.phy_1.rwds_timing.rwds_oe_setup_cycles.load_next) begin
+ field_storage.phy_1.rwds_timing.rwds_oe_setup_cycles.value <= field_combo.phy_1.rwds_timing.rwds_oe_setup_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.phy_1.rwds_timing.rwds_oe_setup_cycles.value = field_storage.phy_1.rwds_timing.rwds_oe_setup_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_0.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.range_base.value.next = next_c;
+ field_combo.chip_0.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.range_base.value.value <= 10'h0;
+ end else begin
+ if(field_combo.chip_0.range_base.value.load_next) begin
+ field_storage.chip_0.range_base.value.value <= field_combo.chip_0.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.range_base.value.value = field_storage.chip_0.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_0.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.range_bound.value.next = next_c;
+ field_combo.chip_0.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.range_bound.value.value <= 10'h1;
+ end else begin
+ if(field_combo.chip_0.range_bound.value.load_next) begin
+ field_storage.chip_0.range_bound.value.value <= field_combo.chip_0.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.range_bound.value.value = field_storage.chip_0.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_0.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.address_cfg.address_space.next = next_c;
+ field_combo.chip_0.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_0.address_cfg.address_space.load_next) begin
+ field_storage.chip_0.address_cfg.address_space.value <= field_combo.chip_0.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.address_cfg.address_space.value = field_storage.chip_0.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_0.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_0.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_0.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_0.address_cfg.address_mask_msb.value <= field_combo.chip_0.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.address_cfg.address_mask_msb.value = field_storage.chip_0.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_0.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.address_cfg.enable.next = next_c;
+ field_combo.chip_0.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_0.address_cfg.enable.load_next) begin
+ field_storage.chip_0.address_cfg.enable.value <= field_combo.chip_0.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.address_cfg.enable.value = field_storage.chip_0.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_0.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_0.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_0.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_0.latency_cfg.t_latency_access.value <= field_combo.chip_0.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.latency_cfg.t_latency_access.value = field_storage.chip_0.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_0.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_0.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_0.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_0.latency_cfg.rwds_sample_delay.value <= field_combo.chip_0.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.latency_cfg.rwds_sample_delay.value = field_storage.chip_0.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_0.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_0.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_0.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_0.latency_cfg.en_latency_additional.value <= field_combo.chip_0.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.latency_cfg.en_latency_additional.value = field_storage.chip_0.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_0.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_0.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_0.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_0.burst_cfg.t_burst_max.value <= field_combo.chip_0.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.burst_cfg.t_burst_max.value = field_storage.chip_0.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_0.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_0.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_0.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_0.chip_timing.t_read_write_recovery.value <= field_combo.chip_0.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.chip_timing.t_read_write_recovery.value = field_storage.chip_0.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_0.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_0.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_0.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_0.chip_timing.t_csh_cycles.value <= field_combo.chip_0.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.chip_timing.t_csh_cycles.value = field_storage.chip_0.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_0.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_0.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_0.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_0.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_0.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.chip_timing.csn_to_ck_cycles.value = field_storage.chip_0.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_0.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_0.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_0.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_0.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_0.rx_delay.value.next = next_c;
+ field_combo.chip_0.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_0.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_0.rx_delay.value.load_next) begin
+ field_storage.chip_0.rx_delay.value.value <= field_combo.chip_0.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_0.rx_delay.value.value = field_storage.chip_0.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_1.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.range_base.value.next = next_c;
+ field_combo.chip_1.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.range_base.value.value <= 10'h1;
+ end else begin
+ if(field_combo.chip_1.range_base.value.load_next) begin
+ field_storage.chip_1.range_base.value.value <= field_combo.chip_1.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.range_base.value.value = field_storage.chip_1.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_1.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.range_bound.value.next = next_c;
+ field_combo.chip_1.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.range_bound.value.value <= 10'h2;
+ end else begin
+ if(field_combo.chip_1.range_bound.value.load_next) begin
+ field_storage.chip_1.range_bound.value.value <= field_combo.chip_1.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.range_bound.value.value = field_storage.chip_1.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_1.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.address_cfg.address_space.next = next_c;
+ field_combo.chip_1.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_1.address_cfg.address_space.load_next) begin
+ field_storage.chip_1.address_cfg.address_space.value <= field_combo.chip_1.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.address_cfg.address_space.value = field_storage.chip_1.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_1.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_1.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_1.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_1.address_cfg.address_mask_msb.value <= field_combo.chip_1.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.address_cfg.address_mask_msb.value = field_storage.chip_1.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_1.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.address_cfg.enable.next = next_c;
+ field_combo.chip_1.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_1.address_cfg.enable.load_next) begin
+ field_storage.chip_1.address_cfg.enable.value <= field_combo.chip_1.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.address_cfg.enable.value = field_storage.chip_1.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_1.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_1.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_1.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_1.latency_cfg.t_latency_access.value <= field_combo.chip_1.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.latency_cfg.t_latency_access.value = field_storage.chip_1.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_1.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_1.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_1.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_1.latency_cfg.rwds_sample_delay.value <= field_combo.chip_1.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.latency_cfg.rwds_sample_delay.value = field_storage.chip_1.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_1.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_1.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_1.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_1.latency_cfg.en_latency_additional.value <= field_combo.chip_1.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.latency_cfg.en_latency_additional.value = field_storage.chip_1.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_1.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_1.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_1.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_1.burst_cfg.t_burst_max.value <= field_combo.chip_1.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.burst_cfg.t_burst_max.value = field_storage.chip_1.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_1.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_1.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_1.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_1.chip_timing.t_read_write_recovery.value <= field_combo.chip_1.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.chip_timing.t_read_write_recovery.value = field_storage.chip_1.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_1.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_1.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_1.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_1.chip_timing.t_csh_cycles.value <= field_combo.chip_1.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.chip_timing.t_csh_cycles.value = field_storage.chip_1.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_1.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_1.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_1.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_1.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_1.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.chip_timing.csn_to_ck_cycles.value = field_storage.chip_1.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_1.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_1.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_1.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_1.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_1.rx_delay.value.next = next_c;
+ field_combo.chip_1.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_1.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_1.rx_delay.value.load_next) begin
+ field_storage.chip_1.rx_delay.value.value <= field_combo.chip_1.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_1.rx_delay.value.value = field_storage.chip_1.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_2.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.range_base.value.next = next_c;
+ field_combo.chip_2.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.range_base.value.value <= 10'h2;
+ end else begin
+ if(field_combo.chip_2.range_base.value.load_next) begin
+ field_storage.chip_2.range_base.value.value <= field_combo.chip_2.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.range_base.value.value = field_storage.chip_2.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_2.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.range_bound.value.next = next_c;
+ field_combo.chip_2.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.range_bound.value.value <= 10'h3;
+ end else begin
+ if(field_combo.chip_2.range_bound.value.load_next) begin
+ field_storage.chip_2.range_bound.value.value <= field_combo.chip_2.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.range_bound.value.value = field_storage.chip_2.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_2.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.address_cfg.address_space.next = next_c;
+ field_combo.chip_2.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_2.address_cfg.address_space.load_next) begin
+ field_storage.chip_2.address_cfg.address_space.value <= field_combo.chip_2.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.address_cfg.address_space.value = field_storage.chip_2.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_2.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_2.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_2.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_2.address_cfg.address_mask_msb.value <= field_combo.chip_2.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.address_cfg.address_mask_msb.value = field_storage.chip_2.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_2.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.address_cfg.enable.next = next_c;
+ field_combo.chip_2.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_2.address_cfg.enable.load_next) begin
+ field_storage.chip_2.address_cfg.enable.value <= field_combo.chip_2.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.address_cfg.enable.value = field_storage.chip_2.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_2.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_2.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_2.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_2.latency_cfg.t_latency_access.value <= field_combo.chip_2.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.latency_cfg.t_latency_access.value = field_storage.chip_2.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_2.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_2.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_2.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_2.latency_cfg.rwds_sample_delay.value <= field_combo.chip_2.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.latency_cfg.rwds_sample_delay.value = field_storage.chip_2.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_2.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_2.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_2.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_2.latency_cfg.en_latency_additional.value <= field_combo.chip_2.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.latency_cfg.en_latency_additional.value = field_storage.chip_2.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_2.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_2.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_2.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_2.burst_cfg.t_burst_max.value <= field_combo.chip_2.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.burst_cfg.t_burst_max.value = field_storage.chip_2.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_2.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_2.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_2.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_2.chip_timing.t_read_write_recovery.value <= field_combo.chip_2.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.chip_timing.t_read_write_recovery.value = field_storage.chip_2.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_2.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_2.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_2.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_2.chip_timing.t_csh_cycles.value <= field_combo.chip_2.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.chip_timing.t_csh_cycles.value = field_storage.chip_2.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_2.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_2.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_2.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_2.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_2.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.chip_timing.csn_to_ck_cycles.value = field_storage.chip_2.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_2.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_2.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_2.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_2.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_2.rx_delay.value.next = next_c;
+ field_combo.chip_2.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_2.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_2.rx_delay.value.load_next) begin
+ field_storage.chip_2.rx_delay.value.value <= field_combo.chip_2.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_2.rx_delay.value.value = field_storage.chip_2.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_3.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.range_base.value.next = next_c;
+ field_combo.chip_3.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.range_base.value.value <= 10'h3;
+ end else begin
+ if(field_combo.chip_3.range_base.value.load_next) begin
+ field_storage.chip_3.range_base.value.value <= field_combo.chip_3.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.range_base.value.value = field_storage.chip_3.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_3.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.range_bound.value.next = next_c;
+ field_combo.chip_3.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.range_bound.value.value <= 10'h4;
+ end else begin
+ if(field_combo.chip_3.range_bound.value.load_next) begin
+ field_storage.chip_3.range_bound.value.value <= field_combo.chip_3.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.range_bound.value.value = field_storage.chip_3.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_3.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.address_cfg.address_space.next = next_c;
+ field_combo.chip_3.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_3.address_cfg.address_space.load_next) begin
+ field_storage.chip_3.address_cfg.address_space.value <= field_combo.chip_3.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.address_cfg.address_space.value = field_storage.chip_3.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_3.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_3.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_3.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_3.address_cfg.address_mask_msb.value <= field_combo.chip_3.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.address_cfg.address_mask_msb.value = field_storage.chip_3.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_3.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.address_cfg.enable.next = next_c;
+ field_combo.chip_3.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_3.address_cfg.enable.load_next) begin
+ field_storage.chip_3.address_cfg.enable.value <= field_combo.chip_3.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.address_cfg.enable.value = field_storage.chip_3.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_3.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_3.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_3.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_3.latency_cfg.t_latency_access.value <= field_combo.chip_3.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.latency_cfg.t_latency_access.value = field_storage.chip_3.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_3.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_3.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_3.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_3.latency_cfg.rwds_sample_delay.value <= field_combo.chip_3.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.latency_cfg.rwds_sample_delay.value = field_storage.chip_3.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_3.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_3.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_3.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_3.latency_cfg.en_latency_additional.value <= field_combo.chip_3.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.latency_cfg.en_latency_additional.value = field_storage.chip_3.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_3.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_3.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_3.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_3.burst_cfg.t_burst_max.value <= field_combo.chip_3.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.burst_cfg.t_burst_max.value = field_storage.chip_3.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_3.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_3.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_3.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_3.chip_timing.t_read_write_recovery.value <= field_combo.chip_3.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.chip_timing.t_read_write_recovery.value = field_storage.chip_3.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_3.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_3.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_3.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_3.chip_timing.t_csh_cycles.value <= field_combo.chip_3.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.chip_timing.t_csh_cycles.value = field_storage.chip_3.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_3.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_3.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_3.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_3.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_3.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.chip_timing.csn_to_ck_cycles.value = field_storage.chip_3.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_3.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_3.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_3.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_3.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_3.rx_delay.value.next = next_c;
+ field_combo.chip_3.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_3.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_3.rx_delay.value.load_next) begin
+ field_storage.chip_3.rx_delay.value.value <= field_combo.chip_3.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_3.rx_delay.value.value = field_storage.chip_3.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_4.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.range_base.value.next = next_c;
+ field_combo.chip_4.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.range_base.value.value <= 10'h4;
+ end else begin
+ if(field_combo.chip_4.range_base.value.load_next) begin
+ field_storage.chip_4.range_base.value.value <= field_combo.chip_4.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.range_base.value.value = field_storage.chip_4.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_4.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.range_bound.value.next = next_c;
+ field_combo.chip_4.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.range_bound.value.value <= 10'h5;
+ end else begin
+ if(field_combo.chip_4.range_bound.value.load_next) begin
+ field_storage.chip_4.range_bound.value.value <= field_combo.chip_4.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.range_bound.value.value = field_storage.chip_4.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_4.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.address_cfg.address_space.next = next_c;
+ field_combo.chip_4.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_4.address_cfg.address_space.load_next) begin
+ field_storage.chip_4.address_cfg.address_space.value <= field_combo.chip_4.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.address_cfg.address_space.value = field_storage.chip_4.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_4.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_4.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_4.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_4.address_cfg.address_mask_msb.value <= field_combo.chip_4.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.address_cfg.address_mask_msb.value = field_storage.chip_4.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_4.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.address_cfg.enable.next = next_c;
+ field_combo.chip_4.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_4.address_cfg.enable.load_next) begin
+ field_storage.chip_4.address_cfg.enable.value <= field_combo.chip_4.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.address_cfg.enable.value = field_storage.chip_4.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_4.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_4.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_4.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_4.latency_cfg.t_latency_access.value <= field_combo.chip_4.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.latency_cfg.t_latency_access.value = field_storage.chip_4.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_4.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_4.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_4.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_4.latency_cfg.rwds_sample_delay.value <= field_combo.chip_4.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.latency_cfg.rwds_sample_delay.value = field_storage.chip_4.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_4.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_4.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_4.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_4.latency_cfg.en_latency_additional.value <= field_combo.chip_4.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.latency_cfg.en_latency_additional.value = field_storage.chip_4.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_4.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_4.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_4.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_4.burst_cfg.t_burst_max.value <= field_combo.chip_4.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.burst_cfg.t_burst_max.value = field_storage.chip_4.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_4.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_4.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_4.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_4.chip_timing.t_read_write_recovery.value <= field_combo.chip_4.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.chip_timing.t_read_write_recovery.value = field_storage.chip_4.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_4.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_4.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_4.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_4.chip_timing.t_csh_cycles.value <= field_combo.chip_4.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.chip_timing.t_csh_cycles.value = field_storage.chip_4.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_4.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_4.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_4.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_4.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_4.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.chip_timing.csn_to_ck_cycles.value = field_storage.chip_4.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_4.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_4.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_4.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_4.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_4.rx_delay.value.next = next_c;
+ field_combo.chip_4.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_4.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_4.rx_delay.value.load_next) begin
+ field_storage.chip_4.rx_delay.value.value <= field_combo.chip_4.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_4.rx_delay.value.value = field_storage.chip_4.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_5.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.range_base.value.next = next_c;
+ field_combo.chip_5.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.range_base.value.value <= 10'h5;
+ end else begin
+ if(field_combo.chip_5.range_base.value.load_next) begin
+ field_storage.chip_5.range_base.value.value <= field_combo.chip_5.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.range_base.value.value = field_storage.chip_5.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_5.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.range_bound.value.next = next_c;
+ field_combo.chip_5.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.range_bound.value.value <= 10'h6;
+ end else begin
+ if(field_combo.chip_5.range_bound.value.load_next) begin
+ field_storage.chip_5.range_bound.value.value <= field_combo.chip_5.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.range_bound.value.value = field_storage.chip_5.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_5.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.address_cfg.address_space.next = next_c;
+ field_combo.chip_5.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_5.address_cfg.address_space.load_next) begin
+ field_storage.chip_5.address_cfg.address_space.value <= field_combo.chip_5.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.address_cfg.address_space.value = field_storage.chip_5.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_5.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_5.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_5.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_5.address_cfg.address_mask_msb.value <= field_combo.chip_5.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.address_cfg.address_mask_msb.value = field_storage.chip_5.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_5.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.address_cfg.enable.next = next_c;
+ field_combo.chip_5.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_5.address_cfg.enable.load_next) begin
+ field_storage.chip_5.address_cfg.enable.value <= field_combo.chip_5.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.address_cfg.enable.value = field_storage.chip_5.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_5.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_5.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_5.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_5.latency_cfg.t_latency_access.value <= field_combo.chip_5.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.latency_cfg.t_latency_access.value = field_storage.chip_5.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_5.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_5.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_5.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_5.latency_cfg.rwds_sample_delay.value <= field_combo.chip_5.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.latency_cfg.rwds_sample_delay.value = field_storage.chip_5.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_5.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_5.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_5.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_5.latency_cfg.en_latency_additional.value <= field_combo.chip_5.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.latency_cfg.en_latency_additional.value = field_storage.chip_5.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_5.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_5.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_5.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_5.burst_cfg.t_burst_max.value <= field_combo.chip_5.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.burst_cfg.t_burst_max.value = field_storage.chip_5.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_5.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_5.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_5.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_5.chip_timing.t_read_write_recovery.value <= field_combo.chip_5.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.chip_timing.t_read_write_recovery.value = field_storage.chip_5.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_5.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_5.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_5.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_5.chip_timing.t_csh_cycles.value <= field_combo.chip_5.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.chip_timing.t_csh_cycles.value = field_storage.chip_5.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_5.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_5.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_5.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_5.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_5.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.chip_timing.csn_to_ck_cycles.value = field_storage.chip_5.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_5.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_5.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_5.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_5.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_5.rx_delay.value.next = next_c;
+ field_combo.chip_5.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_5.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_5.rx_delay.value.load_next) begin
+ field_storage.chip_5.rx_delay.value.value <= field_combo.chip_5.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_5.rx_delay.value.value = field_storage.chip_5.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_6.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.range_base.value.next = next_c;
+ field_combo.chip_6.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.range_base.value.value <= 10'h6;
+ end else begin
+ if(field_combo.chip_6.range_base.value.load_next) begin
+ field_storage.chip_6.range_base.value.value <= field_combo.chip_6.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.range_base.value.value = field_storage.chip_6.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_6.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.range_bound.value.next = next_c;
+ field_combo.chip_6.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.range_bound.value.value <= 10'h7;
+ end else begin
+ if(field_combo.chip_6.range_bound.value.load_next) begin
+ field_storage.chip_6.range_bound.value.value <= field_combo.chip_6.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.range_bound.value.value = field_storage.chip_6.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_6.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.address_cfg.address_space.next = next_c;
+ field_combo.chip_6.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_6.address_cfg.address_space.load_next) begin
+ field_storage.chip_6.address_cfg.address_space.value <= field_combo.chip_6.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.address_cfg.address_space.value = field_storage.chip_6.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_6.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_6.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_6.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_6.address_cfg.address_mask_msb.value <= field_combo.chip_6.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.address_cfg.address_mask_msb.value = field_storage.chip_6.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_6.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.address_cfg.enable.next = next_c;
+ field_combo.chip_6.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_6.address_cfg.enable.load_next) begin
+ field_storage.chip_6.address_cfg.enable.value <= field_combo.chip_6.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.address_cfg.enable.value = field_storage.chip_6.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_6.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_6.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_6.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_6.latency_cfg.t_latency_access.value <= field_combo.chip_6.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.latency_cfg.t_latency_access.value = field_storage.chip_6.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_6.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_6.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_6.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_6.latency_cfg.rwds_sample_delay.value <= field_combo.chip_6.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.latency_cfg.rwds_sample_delay.value = field_storage.chip_6.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_6.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_6.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_6.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_6.latency_cfg.en_latency_additional.value <= field_combo.chip_6.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.latency_cfg.en_latency_additional.value = field_storage.chip_6.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_6.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_6.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_6.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_6.burst_cfg.t_burst_max.value <= field_combo.chip_6.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.burst_cfg.t_burst_max.value = field_storage.chip_6.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_6.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_6.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_6.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_6.chip_timing.t_read_write_recovery.value <= field_combo.chip_6.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.chip_timing.t_read_write_recovery.value = field_storage.chip_6.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_6.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_6.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_6.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_6.chip_timing.t_csh_cycles.value <= field_combo.chip_6.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.chip_timing.t_csh_cycles.value = field_storage.chip_6.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_6.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_6.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_6.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_6.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_6.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.chip_timing.csn_to_ck_cycles.value = field_storage.chip_6.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_6.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_6.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_6.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_6.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_6.rx_delay.value.next = next_c;
+ field_combo.chip_6.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_6.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_6.rx_delay.value.load_next) begin
+ field_storage.chip_6.rx_delay.value.value <= field_combo.chip_6.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_6.rx_delay.value.value = field_storage.chip_6.rx_delay.value.value;
+ // Field: hyperbus_cfg_regs.chip_7.range_base.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.range_base.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.range_base && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.range_base.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.range_base.value.next = next_c;
+ field_combo.chip_7.range_base.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.range_base.value.value <= 10'h7;
+ end else begin
+ if(field_combo.chip_7.range_base.value.load_next) begin
+ field_storage.chip_7.range_base.value.value <= field_combo.chip_7.range_base.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.range_base.value.value = field_storage.chip_7.range_base.value.value;
+ // Field: hyperbus_cfg_regs.chip_7.range_bound.value
+ always_comb begin
+ automatic logic [9:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.range_bound.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.range_bound && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.range_bound.value.value & ~decoded_wr_biten[31:22]) | (decoded_wr_data[31:22] & decoded_wr_biten[31:22]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.range_bound.value.next = next_c;
+ field_combo.chip_7.range_bound.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.range_bound.value.value <= 10'h8;
+ end else begin
+ if(field_combo.chip_7.range_bound.value.load_next) begin
+ field_storage.chip_7.range_bound.value.value <= field_combo.chip_7.range_bound.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.range_bound.value.value = field_storage.chip_7.range_bound.value.value;
+ // Field: hyperbus_cfg_regs.chip_7.address_cfg.address_space
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.address_cfg.address_space.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.address_cfg.address_space.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.address_cfg.address_space.next = next_c;
+ field_combo.chip_7.address_cfg.address_space.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.address_cfg.address_space.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_7.address_cfg.address_space.load_next) begin
+ field_storage.chip_7.address_cfg.address_space.value <= field_combo.chip_7.address_cfg.address_space.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.address_cfg.address_space.value = field_storage.chip_7.address_cfg.address_space.value;
+ // Field: hyperbus_cfg_regs.chip_7.address_cfg.address_mask_msb
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.address_cfg.address_mask_msb.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.address_cfg.address_mask_msb.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.address_cfg.address_mask_msb.next = next_c;
+ field_combo.chip_7.address_cfg.address_mask_msb.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.address_cfg.address_mask_msb.value <= 8'h19;
+ end else begin
+ if(field_combo.chip_7.address_cfg.address_mask_msb.load_next) begin
+ field_storage.chip_7.address_cfg.address_mask_msb.value <= field_combo.chip_7.address_cfg.address_mask_msb.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.address_cfg.address_mask_msb.value = field_storage.chip_7.address_cfg.address_mask_msb.value;
+ // Field: hyperbus_cfg_regs.chip_7.address_cfg.enable
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.address_cfg.enable.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.address_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.address_cfg.enable.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.address_cfg.enable.next = next_c;
+ field_combo.chip_7.address_cfg.enable.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.address_cfg.enable.value <= 1'h1;
+ end else begin
+ if(field_combo.chip_7.address_cfg.enable.load_next) begin
+ field_storage.chip_7.address_cfg.enable.value <= field_combo.chip_7.address_cfg.enable.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.address_cfg.enable.value = field_storage.chip_7.address_cfg.enable.value;
+ // Field: hyperbus_cfg_regs.chip_7.latency_cfg.t_latency_access
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.latency_cfg.t_latency_access.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.latency_cfg.t_latency_access.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.latency_cfg.t_latency_access.next = next_c;
+ field_combo.chip_7.latency_cfg.t_latency_access.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.latency_cfg.t_latency_access.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_7.latency_cfg.t_latency_access.load_next) begin
+ field_storage.chip_7.latency_cfg.t_latency_access.value <= field_combo.chip_7.latency_cfg.t_latency_access.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.latency_cfg.t_latency_access.value = field_storage.chip_7.latency_cfg.t_latency_access.value;
+ // Field: hyperbus_cfg_regs.chip_7.latency_cfg.rwds_sample_delay
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.latency_cfg.rwds_sample_delay.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.latency_cfg.rwds_sample_delay.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.latency_cfg.rwds_sample_delay.next = next_c;
+ field_combo.chip_7.latency_cfg.rwds_sample_delay.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.latency_cfg.rwds_sample_delay.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_7.latency_cfg.rwds_sample_delay.load_next) begin
+ field_storage.chip_7.latency_cfg.rwds_sample_delay.value <= field_combo.chip_7.latency_cfg.rwds_sample_delay.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.latency_cfg.rwds_sample_delay.value = field_storage.chip_7.latency_cfg.rwds_sample_delay.value;
+ // Field: hyperbus_cfg_regs.chip_7.latency_cfg.en_latency_additional
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.latency_cfg.en_latency_additional.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.latency_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.latency_cfg.en_latency_additional.value & ~decoded_wr_biten[16:16]) | (decoded_wr_data[16:16] & decoded_wr_biten[16:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.latency_cfg.en_latency_additional.next = next_c;
+ field_combo.chip_7.latency_cfg.en_latency_additional.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.latency_cfg.en_latency_additional.value <= 1'h0;
+ end else begin
+ if(field_combo.chip_7.latency_cfg.en_latency_additional.load_next) begin
+ field_storage.chip_7.latency_cfg.en_latency_additional.value <= field_combo.chip_7.latency_cfg.en_latency_additional.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.latency_cfg.en_latency_additional.value = field_storage.chip_7.latency_cfg.en_latency_additional.value;
+ // Field: hyperbus_cfg_regs.chip_7.burst_cfg.t_burst_max
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.burst_cfg.t_burst_max.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.burst_cfg && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.burst_cfg.t_burst_max.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.burst_cfg.t_burst_max.next = next_c;
+ field_combo.chip_7.burst_cfg.t_burst_max.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.burst_cfg.t_burst_max.value <= 16'h15e;
+ end else begin
+ if(field_combo.chip_7.burst_cfg.t_burst_max.load_next) begin
+ field_storage.chip_7.burst_cfg.t_burst_max.value <= field_combo.chip_7.burst_cfg.t_burst_max.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.burst_cfg.t_burst_max.value = field_storage.chip_7.burst_cfg.t_burst_max.value;
+ // Field: hyperbus_cfg_regs.chip_7.chip_timing.t_read_write_recovery
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.chip_timing.t_read_write_recovery.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.chip_timing.t_read_write_recovery.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.chip_timing.t_read_write_recovery.next = next_c;
+ field_combo.chip_7.chip_timing.t_read_write_recovery.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.chip_timing.t_read_write_recovery.value <= 8'h6;
+ end else begin
+ if(field_combo.chip_7.chip_timing.t_read_write_recovery.load_next) begin
+ field_storage.chip_7.chip_timing.t_read_write_recovery.value <= field_combo.chip_7.chip_timing.t_read_write_recovery.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.chip_timing.t_read_write_recovery.value = field_storage.chip_7.chip_timing.t_read_write_recovery.value;
+ // Field: hyperbus_cfg_regs.chip_7.chip_timing.t_csh_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.chip_timing.t_csh_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.chip_timing.t_csh_cycles.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.chip_timing.t_csh_cycles.next = next_c;
+ field_combo.chip_7.chip_timing.t_csh_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.chip_timing.t_csh_cycles.value <= 8'h1;
+ end else begin
+ if(field_combo.chip_7.chip_timing.t_csh_cycles.load_next) begin
+ field_storage.chip_7.chip_timing.t_csh_cycles.value <= field_combo.chip_7.chip_timing.t_csh_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.chip_timing.t_csh_cycles.value = field_storage.chip_7.chip_timing.t_csh_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_7.chip_timing.csn_to_ck_cycles
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.chip_timing.csn_to_ck_cycles.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.chip_timing && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.chip_timing.csn_to_ck_cycles.value & ~decoded_wr_biten[23:16]) | (decoded_wr_data[23:16] & decoded_wr_biten[23:16]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.chip_timing.csn_to_ck_cycles.next = next_c;
+ field_combo.chip_7.chip_timing.csn_to_ck_cycles.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.chip_timing.csn_to_ck_cycles.value <= 8'h0;
+ end else begin
+ if(field_combo.chip_7.chip_timing.csn_to_ck_cycles.load_next) begin
+ field_storage.chip_7.chip_timing.csn_to_ck_cycles.value <= field_combo.chip_7.chip_timing.csn_to_ck_cycles.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.chip_timing.csn_to_ck_cycles.value = field_storage.chip_7.chip_timing.csn_to_ck_cycles.value;
+ // Field: hyperbus_cfg_regs.chip_7.rx_delay.value
+ always_comb begin
+ automatic logic [7:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.chip_7.rx_delay.value.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.chip_7.rx_delay && decoded_req_is_wr) begin // SW write
+ next_c = (field_storage.chip_7.rx_delay.value.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+ load_next_c = '1;
+ end
+ field_combo.chip_7.rx_delay.value.next = next_c;
+ field_combo.chip_7.rx_delay.value.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge arst_n) begin
+ if(~arst_n) begin
+ field_storage.chip_7.rx_delay.value.value <= 8'h10;
+ end else begin
+ if(field_combo.chip_7.rx_delay.value.load_next) begin
+ field_storage.chip_7.rx_delay.value.value <= field_combo.chip_7.rx_delay.value.next;
+ end
+ end
+ end
+ assign hwif_out.chip_7.rx_delay.value.value = field_storage.chip_7.rx_delay.value.value;
+ assign hwif_out.reserved_top.value.value = 32'h0;
+
+ //--------------------------------------------------------------------------
+ // Write response
+ //--------------------------------------------------------------------------
+ assign cpuif_wr_ack = decoded_req & decoded_req_is_wr;
+ // Writes are always granted with no error response
+ assign cpuif_wr_err = '0;
+
+ //--------------------------------------------------------------------------
+ // Readback
+ //--------------------------------------------------------------------------
+
+ logic [11:0] rd_mux_addr;
+ assign rd_mux_addr = decoded_addr;
+
+ logic readback_err;
+ logic readback_done;
+ logic [31:0] readback_data;
+ always_comb begin
+ automatic logic [31:0] readback_data_var;
+ readback_data_var = '0;
+ if(rd_mux_addr == 12'h0) begin
+ readback_data_var[7:0] = 8'h0;
+ readback_data_var[15:8] = 8'h9;
+ readback_data_var[23:16] = 8'h0;
+ readback_data_var[31:24] = 8'h0;
+ end
+ if(rd_mux_addr == 12'h4) begin
+ readback_data_var[15:0] = 16'h0;
+ readback_data_var[31:16] = 16'h1;
+ end
+ if(rd_mux_addr == 12'h8) begin
+ readback_data_var[7:0] = field_storage.global_cfg.capability.num_chips.value;
+ readback_data_var[15:8] = field_storage.global_cfg.capability.num_phys.value;
+ readback_data_var[16] = field_storage.global_cfg.capability.per_chip_cfg.value;
+ readback_data_var[17] = field_storage.global_cfg.capability.per_phy_cfg.value;
+ readback_data_var[18] = field_storage.global_cfg.capability.chip_enable.value;
+ readback_data_var[19] = field_storage.global_cfg.capability.clock_divider.value;
+ readback_data_var[20] = field_storage.global_cfg.capability.staged_apply.value;
+ readback_data_var[21] = field_storage.global_cfg.capability.error_status.value;
+ readback_data_var[22] = field_storage.global_cfg.capability.rwds_sample_timing.value;
+ readback_data_var[23] = field_storage.global_cfg.capability.rwds_oe_timing.value;
+ end
+ if(rd_mux_addr == 12'hc) begin
+ readback_data_var[0] = field_storage.global_cfg.command.flush.value;
+ readback_data_var[1] = field_storage.global_cfg.command.apply.value;
+ end
+ if(rd_mux_addr == 12'h10) begin
+ readback_data_var[0] = field_storage.global_cfg.status.decode_error.value;
+ readback_data_var[1] = field_storage.global_cfg.status.busy.value;
+ readback_data_var[2] = field_storage.global_cfg.status.dirty.value;
+ end
+ if(rd_mux_addr == 12'h100) begin
+ readback_data_var[0] = field_storage.frontend.frontend_cfg.dual_phy.value;
+ end
+ if(rd_mux_addr == 12'h200) begin
+ readback_data_var[7:0] = field_storage.backend.clock_cfg.divider.value;
+ end
+ if(rd_mux_addr == 12'h300) begin
+ readback_data_var[7:0] = field_storage.phy_0.tx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h304) begin
+ readback_data_var[7:0] = field_storage.phy_0.rwds_timing.rwds_oe_setup_cycles.value;
+ end
+ if(rd_mux_addr == 12'h340) begin
+ readback_data_var[7:0] = field_storage.phy_1.tx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h344) begin
+ readback_data_var[7:0] = field_storage.phy_1.rwds_timing.rwds_oe_setup_cycles.value;
+ end
+ if(rd_mux_addr == 12'h400) begin
+ readback_data_var[31:22] = field_storage.chip_0.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h404) begin
+ readback_data_var[31:22] = field_storage.chip_0.range_bound.value.value;
+ end
+ if(rd_mux_addr == 12'h408) begin
+ readback_data_var[7:0] = field_storage.chip_0.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_0.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_0.address_cfg.enable.value;
+ end
+ if(rd_mux_addr == 12'h40c) begin
+ readback_data_var[7:0] = field_storage.chip_0.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_0.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_0.latency_cfg.en_latency_additional.value;
+ end
+ if(rd_mux_addr == 12'h410) begin
+ readback_data_var[15:0] = field_storage.chip_0.burst_cfg.t_burst_max.value;
+ end
+ if(rd_mux_addr == 12'h414) begin
+ readback_data_var[7:0] = field_storage.chip_0.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_0.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_0.chip_timing.csn_to_ck_cycles.value;
+ end
+ if(rd_mux_addr == 12'h418) begin
+ readback_data_var[7:0] = field_storage.chip_0.rx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h440) begin
+ readback_data_var[31:22] = field_storage.chip_1.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h444) begin
+ readback_data_var[31:22] = field_storage.chip_1.range_bound.value.value;
+ end
+ if(rd_mux_addr == 12'h448) begin
+ readback_data_var[7:0] = field_storage.chip_1.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_1.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_1.address_cfg.enable.value;
+ end
+ if(rd_mux_addr == 12'h44c) begin
+ readback_data_var[7:0] = field_storage.chip_1.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_1.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_1.latency_cfg.en_latency_additional.value;
+ end
+ if(rd_mux_addr == 12'h450) begin
+ readback_data_var[15:0] = field_storage.chip_1.burst_cfg.t_burst_max.value;
+ end
+ if(rd_mux_addr == 12'h454) begin
+ readback_data_var[7:0] = field_storage.chip_1.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_1.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_1.chip_timing.csn_to_ck_cycles.value;
+ end
+ if(rd_mux_addr == 12'h458) begin
+ readback_data_var[7:0] = field_storage.chip_1.rx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h480) begin
+ readback_data_var[31:22] = field_storage.chip_2.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h484) begin
+ readback_data_var[31:22] = field_storage.chip_2.range_bound.value.value;
+ end
+ if(rd_mux_addr == 12'h488) begin
+ readback_data_var[7:0] = field_storage.chip_2.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_2.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_2.address_cfg.enable.value;
+ end
+ if(rd_mux_addr == 12'h48c) begin
+ readback_data_var[7:0] = field_storage.chip_2.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_2.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_2.latency_cfg.en_latency_additional.value;
+ end
+ if(rd_mux_addr == 12'h490) begin
+ readback_data_var[15:0] = field_storage.chip_2.burst_cfg.t_burst_max.value;
+ end
+ if(rd_mux_addr == 12'h494) begin
+ readback_data_var[7:0] = field_storage.chip_2.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_2.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_2.chip_timing.csn_to_ck_cycles.value;
+ end
+ if(rd_mux_addr == 12'h498) begin
+ readback_data_var[7:0] = field_storage.chip_2.rx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h4c0) begin
+ readback_data_var[31:22] = field_storage.chip_3.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h4c4) begin
+ readback_data_var[31:22] = field_storage.chip_3.range_bound.value.value;
+ end
+ if(rd_mux_addr == 12'h4c8) begin
+ readback_data_var[7:0] = field_storage.chip_3.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_3.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_3.address_cfg.enable.value;
+ end
+ if(rd_mux_addr == 12'h4cc) begin
+ readback_data_var[7:0] = field_storage.chip_3.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_3.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_3.latency_cfg.en_latency_additional.value;
+ end
+ if(rd_mux_addr == 12'h4d0) begin
+ readback_data_var[15:0] = field_storage.chip_3.burst_cfg.t_burst_max.value;
+ end
+ if(rd_mux_addr == 12'h4d4) begin
+ readback_data_var[7:0] = field_storage.chip_3.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_3.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_3.chip_timing.csn_to_ck_cycles.value;
+ end
+ if(rd_mux_addr == 12'h4d8) begin
+ readback_data_var[7:0] = field_storage.chip_3.rx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h500) begin
+ readback_data_var[31:22] = field_storage.chip_4.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h504) begin
+ readback_data_var[31:22] = field_storage.chip_4.range_bound.value.value;
+ end
+ if(rd_mux_addr == 12'h508) begin
+ readback_data_var[7:0] = field_storage.chip_4.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_4.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_4.address_cfg.enable.value;
+ end
+ if(rd_mux_addr == 12'h50c) begin
+ readback_data_var[7:0] = field_storage.chip_4.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_4.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_4.latency_cfg.en_latency_additional.value;
+ end
+ if(rd_mux_addr == 12'h510) begin
+ readback_data_var[15:0] = field_storage.chip_4.burst_cfg.t_burst_max.value;
+ end
+ if(rd_mux_addr == 12'h514) begin
+ readback_data_var[7:0] = field_storage.chip_4.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_4.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_4.chip_timing.csn_to_ck_cycles.value;
+ end
+ if(rd_mux_addr == 12'h518) begin
+ readback_data_var[7:0] = field_storage.chip_4.rx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h540) begin
+ readback_data_var[31:22] = field_storage.chip_5.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h544) begin
+ readback_data_var[31:22] = field_storage.chip_5.range_bound.value.value;
+ end
+ if(rd_mux_addr == 12'h548) begin
+ readback_data_var[7:0] = field_storage.chip_5.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_5.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_5.address_cfg.enable.value;
+ end
+ if(rd_mux_addr == 12'h54c) begin
+ readback_data_var[7:0] = field_storage.chip_5.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_5.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_5.latency_cfg.en_latency_additional.value;
+ end
+ if(rd_mux_addr == 12'h550) begin
+ readback_data_var[15:0] = field_storage.chip_5.burst_cfg.t_burst_max.value;
+ end
+ if(rd_mux_addr == 12'h554) begin
+ readback_data_var[7:0] = field_storage.chip_5.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_5.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_5.chip_timing.csn_to_ck_cycles.value;
+ end
+ if(rd_mux_addr == 12'h558) begin
+ readback_data_var[7:0] = field_storage.chip_5.rx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h580) begin
+ readback_data_var[31:22] = field_storage.chip_6.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h584) begin
+ readback_data_var[31:22] = field_storage.chip_6.range_bound.value.value;
+ end
+ if(rd_mux_addr == 12'h588) begin
+ readback_data_var[7:0] = field_storage.chip_6.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_6.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_6.address_cfg.enable.value;
+ end
+ if(rd_mux_addr == 12'h58c) begin
+ readback_data_var[7:0] = field_storage.chip_6.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_6.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_6.latency_cfg.en_latency_additional.value;
+ end
+ if(rd_mux_addr == 12'h590) begin
+ readback_data_var[15:0] = field_storage.chip_6.burst_cfg.t_burst_max.value;
+ end
+ if(rd_mux_addr == 12'h594) begin
+ readback_data_var[7:0] = field_storage.chip_6.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_6.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_6.chip_timing.csn_to_ck_cycles.value;
+ end
+ if(rd_mux_addr == 12'h598) begin
+ readback_data_var[7:0] = field_storage.chip_6.rx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'h5c0) begin
+ readback_data_var[31:22] = field_storage.chip_7.range_base.value.value;
+ end
+ if(rd_mux_addr == 12'h5c4) begin
+ readback_data_var[31:22] = field_storage.chip_7.range_bound.value.value;
+ end
+ if(rd_mux_addr == 12'h5c8) begin
+ readback_data_var[7:0] = field_storage.chip_7.address_cfg.address_space.value;
+ readback_data_var[15:8] = field_storage.chip_7.address_cfg.address_mask_msb.value;
+ readback_data_var[16] = field_storage.chip_7.address_cfg.enable.value;
+ end
+ if(rd_mux_addr == 12'h5cc) begin
+ readback_data_var[7:0] = field_storage.chip_7.latency_cfg.t_latency_access.value;
+ readback_data_var[15:8] = field_storage.chip_7.latency_cfg.rwds_sample_delay.value;
+ readback_data_var[16] = field_storage.chip_7.latency_cfg.en_latency_additional.value;
+ end
+ if(rd_mux_addr == 12'h5d0) begin
+ readback_data_var[15:0] = field_storage.chip_7.burst_cfg.t_burst_max.value;
+ end
+ if(rd_mux_addr == 12'h5d4) begin
+ readback_data_var[7:0] = field_storage.chip_7.chip_timing.t_read_write_recovery.value;
+ readback_data_var[15:8] = field_storage.chip_7.chip_timing.t_csh_cycles.value;
+ readback_data_var[23:16] = field_storage.chip_7.chip_timing.csn_to_ck_cycles.value;
+ end
+ if(rd_mux_addr == 12'h5d8) begin
+ readback_data_var[7:0] = field_storage.chip_7.rx_delay.value.value;
+ end
+ if(rd_mux_addr == 12'hffc) begin
+ readback_data_var[31:0] = 32'h0;
+ end
+ readback_data = readback_data_var;
+ readback_done = decoded_req & ~decoded_req_is_wr;
+ readback_err = '0;
+ end
+
+ assign cpuif_rd_ack = readback_done;
+ assign cpuif_rd_data = readback_data;
+ assign cpuif_rd_err = readback_err;
+endmodule
diff --git a/src/regs/hyperbus_cfg_regblock_pkg.sv b/src/regs/hyperbus_cfg_regblock_pkg.sv
new file mode 100644
index 0000000..807817d
--- /dev/null
+++ b/src/regs/hyperbus_cfg_regblock_pkg.sv
@@ -0,0 +1,566 @@
+// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
+// https://github.com/SystemRDL/PeakRDL-regblock
+
+package hyperbus_cfg_regblock_pkg;
+
+ localparam HYPERBUS_CFG_REGBLOCK_DATA_WIDTH = 32;
+ localparam HYPERBUS_CFG_REGBLOCK_MIN_ADDR_WIDTH = 12;
+ localparam HYPERBUS_CFG_REGBLOCK_SIZE = 'h1000;
+
+ typedef struct {
+ logic [7:0] next;
+ } hyperbus_cfg_regs__capability__num_chips__in_t;
+
+ typedef struct {
+ logic [7:0] next;
+ } hyperbus_cfg_regs__capability__num_phys__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__per_chip_cfg__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__per_phy_cfg__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__chip_enable__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__clock_divider__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__staged_apply__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__error_status__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__rwds_sample_timing__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__capability__rwds_oe_timing__in_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__capability__num_chips__in_t num_chips;
+ hyperbus_cfg_regs__capability__num_phys__in_t num_phys;
+ hyperbus_cfg_regs__capability__per_chip_cfg__in_t per_chip_cfg;
+ hyperbus_cfg_regs__capability__per_phy_cfg__in_t per_phy_cfg;
+ hyperbus_cfg_regs__capability__chip_enable__in_t chip_enable;
+ hyperbus_cfg_regs__capability__clock_divider__in_t clock_divider;
+ hyperbus_cfg_regs__capability__staged_apply__in_t staged_apply;
+ hyperbus_cfg_regs__capability__error_status__in_t error_status;
+ hyperbus_cfg_regs__capability__rwds_sample_timing__in_t rwds_sample_timing;
+ hyperbus_cfg_regs__capability__rwds_oe_timing__in_t rwds_oe_timing;
+ } hyperbus_cfg_regs__capability__in_t;
+
+ typedef struct {
+ logic next;
+ logic hwset;
+ } hyperbus_cfg_regs__status__decode_error__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__status__busy__in_t;
+
+ typedef struct {
+ logic next;
+ } hyperbus_cfg_regs__status__dirty__in_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__status__decode_error__in_t decode_error;
+ hyperbus_cfg_regs__status__busy__in_t busy;
+ hyperbus_cfg_regs__status__dirty__in_t dirty;
+ } hyperbus_cfg_regs__status__in_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__capability__in_t capability;
+ hyperbus_cfg_regs__status__in_t status;
+ } hyperbus_cfg_regs__global_regs__in_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__global_regs__in_t global_cfg;
+ } hyperbus_cfg_regs__in_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__ip_version__revision__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__ip_version__patch__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__ip_version__minor__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__ip_version__major__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__ip_version__revision__out_t revision;
+ hyperbus_cfg_regs__ip_version__patch__out_t patch;
+ hyperbus_cfg_regs__ip_version__minor__out_t minor;
+ hyperbus_cfg_regs__ip_version__major__out_t major;
+ } hyperbus_cfg_regs__ip_version__out_t;
+
+ typedef struct {
+ logic [15:0] value;
+ } hyperbus_cfg_regs__reg_if_version__minor__out_t;
+
+ typedef struct {
+ logic [15:0] value;
+ } hyperbus_cfg_regs__reg_if_version__major__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__reg_if_version__minor__out_t minor;
+ hyperbus_cfg_regs__reg_if_version__major__out_t major;
+ } hyperbus_cfg_regs__reg_if_version__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__capability__num_chips__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__capability__num_phys__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__capability__per_chip_cfg__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__capability__per_phy_cfg__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__capability__chip_enable__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__capability__clock_divider__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__capability__staged_apply__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__capability__error_status__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__capability__rwds_sample_timing__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__capability__rwds_oe_timing__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__capability__num_chips__out_t num_chips;
+ hyperbus_cfg_regs__capability__num_phys__out_t num_phys;
+ hyperbus_cfg_regs__capability__per_chip_cfg__out_t per_chip_cfg;
+ hyperbus_cfg_regs__capability__per_phy_cfg__out_t per_phy_cfg;
+ hyperbus_cfg_regs__capability__chip_enable__out_t chip_enable;
+ hyperbus_cfg_regs__capability__clock_divider__out_t clock_divider;
+ hyperbus_cfg_regs__capability__staged_apply__out_t staged_apply;
+ hyperbus_cfg_regs__capability__error_status__out_t error_status;
+ hyperbus_cfg_regs__capability__rwds_sample_timing__out_t rwds_sample_timing;
+ hyperbus_cfg_regs__capability__rwds_oe_timing__out_t rwds_oe_timing;
+ } hyperbus_cfg_regs__capability__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__command__flush__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__command__apply__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__command__flush__out_t flush;
+ hyperbus_cfg_regs__command__apply__out_t apply;
+ } hyperbus_cfg_regs__command__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__status__decode_error__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__status__busy__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__status__dirty__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__status__decode_error__out_t decode_error;
+ hyperbus_cfg_regs__status__busy__out_t busy;
+ hyperbus_cfg_regs__status__dirty__out_t dirty;
+ } hyperbus_cfg_regs__status__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__ip_version__out_t ip_version;
+ hyperbus_cfg_regs__reg_if_version__out_t reg_if_version;
+ hyperbus_cfg_regs__capability__out_t capability;
+ hyperbus_cfg_regs__command__out_t command;
+ hyperbus_cfg_regs__status__out_t status;
+ } hyperbus_cfg_regs__global_regs__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__frontend_cfg__dual_phy__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__frontend_cfg__dual_phy__out_t dual_phy;
+ } hyperbus_cfg_regs__frontend_cfg__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__frontend_cfg__out_t frontend_cfg;
+ } hyperbus_cfg_regs__frontend_regs__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__clock_cfg__divider__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__clock_cfg__divider__out_t divider;
+ } hyperbus_cfg_regs__clock_cfg__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__clock_cfg__out_t clock_cfg;
+ } hyperbus_cfg_regs__backend_regs__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__tx_delay__value__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__tx_delay__value__out_t value;
+ } hyperbus_cfg_regs__tx_delay__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__rwds_timing__rwds_oe_setup_cycles__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__rwds_timing__rwds_oe_setup_cycles__out_t rwds_oe_setup_cycles;
+ } hyperbus_cfg_regs__rwds_timing__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__tx_delay__out_t tx_delay;
+ hyperbus_cfg_regs__rwds_timing__out_t rwds_timing;
+ } hyperbus_cfg_regs__phy_regs__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_base__value__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base__value__out_t value;
+ } hyperbus_cfg_regs__range_base__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_bound__value__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound__value__out_t value;
+ } hyperbus_cfg_regs__range_bound__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__address_cfg__address_space__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__address_cfg__address_mask_msb__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__address_cfg__enable__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__address_cfg__address_space__out_t address_space;
+ hyperbus_cfg_regs__address_cfg__address_mask_msb__out_t address_mask_msb;
+ hyperbus_cfg_regs__address_cfg__enable__out_t enable;
+ } hyperbus_cfg_regs__address_cfg__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__latency_cfg__t_latency_access__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__latency_cfg__rwds_sample_delay__out_t;
+
+ typedef struct {
+ logic value;
+ } hyperbus_cfg_regs__latency_cfg__en_latency_additional__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__latency_cfg__t_latency_access__out_t t_latency_access;
+ hyperbus_cfg_regs__latency_cfg__rwds_sample_delay__out_t rwds_sample_delay;
+ hyperbus_cfg_regs__latency_cfg__en_latency_additional__out_t en_latency_additional;
+ } hyperbus_cfg_regs__latency_cfg__out_t;
+
+ typedef struct {
+ logic [15:0] value;
+ } hyperbus_cfg_regs__burst_cfg__t_burst_max__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__burst_cfg__t_burst_max__out_t t_burst_max;
+ } hyperbus_cfg_regs__burst_cfg__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__chip_timing__t_read_write_recovery__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__chip_timing__t_csh_cycles__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__chip_timing__csn_to_ck_cycles__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__chip_timing__t_read_write_recovery__out_t t_read_write_recovery;
+ hyperbus_cfg_regs__chip_timing__t_csh_cycles__out_t t_csh_cycles;
+ hyperbus_cfg_regs__chip_timing__csn_to_ck_cycles__out_t csn_to_ck_cycles;
+ } hyperbus_cfg_regs__chip_timing__out_t;
+
+ typedef struct {
+ logic [7:0] value;
+ } hyperbus_cfg_regs__rx_delay__value__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__rx_delay__value__out_t value;
+ } hyperbus_cfg_regs__rx_delay__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base__out_t range_base;
+ hyperbus_cfg_regs__range_bound__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_base_value_aea1d0e1__value_reset_1__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_aea1d0e1__value_reset_1__out_t value;
+ } hyperbus_cfg_regs__range_base_value_aea1d0e1__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_bound_value_e30f0c3f__value_reset_2__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound_value_e30f0c3f__value_reset_2__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_e30f0c3f__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_aea1d0e1__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_e30f0c3f__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_de2a4636_range_bound_d40fd139__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_base_value_e30f0c3f__value_reset_2__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_e30f0c3f__value_reset_2__out_t value;
+ } hyperbus_cfg_regs__range_base_value_e30f0c3f__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_bound_value_2f629ec9__value_reset_3__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound_value_2f629ec9__value_reset_3__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_2f629ec9__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_e30f0c3f__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_2f629ec9__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_b054dd4c_range_bound_a4d5f83b__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_base_value_2f629ec9__value_reset_3__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_2f629ec9__value_reset_3__out_t value;
+ } hyperbus_cfg_regs__range_base_value_2f629ec9__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_bound_value_a1e733c2__value_reset_4__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound_value_a1e733c2__value_reset_4__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_a1e733c2__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_2f629ec9__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_a1e733c2__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_f7266ded_range_bound_5bf260e9__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_base_value_a1e733c2__value_reset_4__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_a1e733c2__value_reset_4__out_t value;
+ } hyperbus_cfg_regs__range_base_value_a1e733c2__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_bound_value_342915db__value_reset_5__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound_value_342915db__value_reset_5__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_342915db__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_a1e733c2__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_342915db__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_0d543b99_range_bound_1fffc3a2__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_base_value_342915db__value_reset_5__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_342915db__value_reset_5__out_t value;
+ } hyperbus_cfg_regs__range_base_value_342915db__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_bound_value_883c384f__value_reset_6__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound_value_883c384f__value_reset_6__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_883c384f__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_342915db__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_883c384f__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_e068ab2e_range_bound_9afa5911__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_base_value_883c384f__value_reset_6__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_883c384f__value_reset_6__out_t value;
+ } hyperbus_cfg_regs__range_base_value_883c384f__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_bound_value_d0d03147__value_reset_7__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound_value_d0d03147__value_reset_7__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_d0d03147__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_883c384f__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_d0d03147__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_ac4fb754_range_bound_24b9644b__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_base_value_d0d03147__value_reset_7__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_d0d03147__value_reset_7__out_t value;
+ } hyperbus_cfg_regs__range_base_value_d0d03147__out_t;
+
+ typedef struct {
+ logic [9:0] value;
+ } hyperbus_cfg_regs__range_bound_value_971bab53__value_reset_8__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_bound_value_971bab53__value_reset_8__out_t value;
+ } hyperbus_cfg_regs__range_bound_value_971bab53__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__range_base_value_d0d03147__out_t range_base;
+ hyperbus_cfg_regs__range_bound_value_971bab53__out_t range_bound;
+ hyperbus_cfg_regs__address_cfg__out_t address_cfg;
+ hyperbus_cfg_regs__latency_cfg__out_t latency_cfg;
+ hyperbus_cfg_regs__burst_cfg__out_t burst_cfg;
+ hyperbus_cfg_regs__chip_timing__out_t chip_timing;
+ hyperbus_cfg_regs__rx_delay__out_t rx_delay;
+ } hyperbus_cfg_regs__chip_regs_range_base_63c2ba90_range_bound_602aea67__out_t;
+
+ typedef struct {
+ logic [31:0] value;
+ } hyperbus_cfg_regs__reserved_top__value__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__reserved_top__value__out_t value;
+ } hyperbus_cfg_regs__reserved_top__out_t;
+
+ typedef struct {
+ hyperbus_cfg_regs__global_regs__out_t global_cfg;
+ hyperbus_cfg_regs__frontend_regs__out_t frontend;
+ hyperbus_cfg_regs__backend_regs__out_t backend;
+ hyperbus_cfg_regs__phy_regs__out_t phy_0;
+ hyperbus_cfg_regs__phy_regs__out_t phy_1;
+ hyperbus_cfg_regs__chip_regs__out_t chip_0;
+ hyperbus_cfg_regs__chip_regs_range_base_de2a4636_range_bound_d40fd139__out_t chip_1;
+ hyperbus_cfg_regs__chip_regs_range_base_b054dd4c_range_bound_a4d5f83b__out_t chip_2;
+ hyperbus_cfg_regs__chip_regs_range_base_f7266ded_range_bound_5bf260e9__out_t chip_3;
+ hyperbus_cfg_regs__chip_regs_range_base_0d543b99_range_bound_1fffc3a2__out_t chip_4;
+ hyperbus_cfg_regs__chip_regs_range_base_e068ab2e_range_bound_9afa5911__out_t chip_5;
+ hyperbus_cfg_regs__chip_regs_range_base_ac4fb754_range_bound_24b9644b__out_t chip_6;
+ hyperbus_cfg_regs__chip_regs_range_base_63c2ba90_range_bound_602aea67__out_t chip_7;
+ hyperbus_cfg_regs__reserved_top__out_t reserved_top;
+ } hyperbus_cfg_regs__out_t;
+endpackage
diff --git a/src/regs/hyperbus_cfg_regs.rdl b/src/regs/hyperbus_cfg_regs.rdl
new file mode 100644
index 0000000..a81f7f9
--- /dev/null
+++ b/src/regs/hyperbus_cfg_regs.rdl
@@ -0,0 +1,148 @@
+addrmap hyperbus_cfg_regs {
+ desc = "HyperBus controller configuration register map. Enabled chip ranges must be 4 MiB aligned, ordered by chip-select index, and non-overlapping.";
+
+ reg ip_version {
+ desc = "IP version (major.minor.patch.revision).";
+ field { sw = r; hw = r; reset = 8'd0; } major[31:24];
+ field { sw = r; hw = r; reset = 8'd0; } minor[23:16];
+ field { sw = r; hw = r; reset = 8'd9; } patch[15:8];
+ field { sw = r; hw = r; reset = 8'd0; } revision[7:0];
+ };
+ reg reg_if_version {
+ desc = "Register interface version.";
+ field { sw = r; hw = r; reset = 16'd1; } major[31:16];
+ field { sw = r; hw = r; reset = 16'd0; } minor[15:0];
+ };
+ reg capability {
+ desc = "Hardware-provided implementation capabilities.";
+ field { desc = "Number of implemented chip selects."; sw = r; hw = rw; reset = 8'd0; } num_chips[7:0];
+ field { desc = "Number of implemented PHY lanes."; sw = r; hw = rw; reset = 8'd0; } num_phys[15:8];
+ field { desc = "Each chip record controls its corresponding chip rather than chip 0 being shared."; sw = r; hw = rw; reset = 1'b0; } per_chip_cfg[16:16];
+ field { desc = "Each PHY record controls its corresponding lane rather than PHY 0 being shared."; sw = r; hw = rw; reset = 1'b0; } per_phy_cfg[17:17];
+ field { desc = "Per-chip enable bits participate in address decoding."; sw = r; hw = rw; reset = 1'b0; } chip_enable[18:18];
+ field { desc = "CLOCK_CFG controls an implemented backend clock divider."; sw = r; hw = rw; reset = 1'b0; } clock_divider[19:19];
+ field { desc = "FLUSH and APPLY commands implement a staged configuration barrier."; sw = r; hw = rw; reset = 1'b0; } staged_apply[20:20];
+ field { desc = "STATUS reports sticky controller errors."; sw = r; hw = rw; reset = 1'b0; } error_status[21:21];
+ field { desc = "Per-chip RWDS sample timing is implemented."; sw = r; hw = rw; reset = 1'b0; } rwds_sample_timing[22:22];
+ field { desc = "Per-PHY RWDS output-enable timing is implemented."; sw = r; hw = rw; reset = 1'b0; } rwds_oe_timing[23:23];
+ };
+ reg command {
+ desc = "Single-cycle write-one command strobes, active when capability.staged_apply is set; otherwise writes are retained only as inert pulses.";
+ field { sw = rw; hw = r; singlepulse = true; reset = 1'b0; } flush;
+ field { sw = rw; hw = r; singlepulse = true; reset = 1'b0; } apply;
+ };
+ reg status {
+ desc = "Controller status.";
+ field { sw = rw; hw = rw; onwrite = woclr; hwset = true; precedence = hw; reset = 1'b0; } decode_error;
+ field { sw = r; hw = rw; reset = 1'b0; } busy;
+ field { sw = r; hw = rw; reset = 1'b0; } dirty;
+ };
+ reg frontend_cfg {
+ desc = "Frontend configuration. dual_phy must be 0 or 1.";
+ field { sw = rw; hw = r; reset = 1'b1; } dual_phy;
+ };
+ reg clock_cfg {
+ desc = "Backend clock-divider configuration, active when capability.clock_divider is set; divider values must be at least 2.";
+ field { sw = rw; hw = r; reset = 8'd8; } divider[7:0];
+ };
+ reg tx_delay {
+ desc = "PHY transmit delay. PHY 0 is shared when capability.per_phy_cfg is clear.";
+ field { sw = rw; hw = r; reset = 8'h10; } value[7:0];
+ };
+ reg rwds_timing {
+ desc = "PHY RWDS output-enable timing. rwds_oe_setup_cycles must be at most 15 and is active when capability.rwds_oe_timing is set.";
+ field { sw = rw; hw = r; reset = 8'd1; } rwds_oe_setup_cycles[7:0];
+ };
+ reg range_base {
+ desc = "Inclusive 4 MiB-aligned chip address range base.";
+ field { sw = rw; hw = r; reset = 10'd0; } value[31:22];
+ };
+ reg range_bound {
+ desc = "Exclusive 4 MiB-aligned chip address range bound.";
+ field { sw = rw; hw = r; reset = 10'd1; } value[31:22];
+ };
+ reg address_cfg {
+ desc = "Chip address-space interpretation and enable. address_space and enable must be 0 or 1, and address_mask_msb must be at most 31. Chip 0 is shared when capability.per_chip_cfg is clear; enable is active when capability.chip_enable is set.";
+ field { sw = rw; hw = r; reset = 8'd0; } address_space[7:0];
+ field { sw = rw; hw = r; reset = 8'd25; } address_mask_msb[15:8];
+ field { sw = rw; hw = r; reset = 1'b1; } enable[16:16];
+ };
+ reg latency_cfg {
+ desc = "Chip latency configuration. t_latency_access must be 3 through 15; rwds_sample_delay must be at most 15 and is active when capability.rwds_sample_timing is set. Chip 0 is shared when capability.per_chip_cfg is clear.";
+ field { sw = rw; hw = r; reset = 8'd6; } t_latency_access[7:0];
+ field { sw = rw; hw = r; reset = 8'd0; } rwds_sample_delay[15:8];
+ field { sw = rw; hw = r; reset = 1'b0; } en_latency_additional[16:16];
+ };
+ reg burst_cfg {
+ desc = "Chip burst configuration. Chip 0 is shared when capability.per_chip_cfg is clear.";
+ field { sw = rw; hw = r; reset = 16'd350; } t_burst_max[15:0];
+ };
+ reg chip_timing {
+ desc = "Chip-select and read/write timing; byte-backed timing values must be at most 15. Chip 0 is shared when capability.per_chip_cfg is clear.";
+ field { sw = rw; hw = r; reset = 8'd6; } t_read_write_recovery[7:0];
+ field { sw = rw; hw = r; reset = 8'd1; } t_csh_cycles[15:8];
+ field { sw = rw; hw = r; reset = 8'd0; } csn_to_ck_cycles[23:16];
+ };
+ reg rx_delay {
+ desc = "Chip receive delay. Chip 0 is shared when capability.per_chip_cfg is clear.";
+ field { sw = rw; hw = r; reset = 8'h10; } value[7:0];
+ };
+ reg reserved_top {
+ desc = "Reserved endpoint that fixes the register window size to 4 KiB.";
+ field { sw = r; hw = r; reset = 32'd0; } value[31:0];
+ };
+ regfile phy_regs {
+ tx_delay tx_delay @0x00;
+ rwds_timing rwds_timing @0x04;
+ };
+ regfile chip_regs {
+ range_base range_base @0x00;
+ range_bound range_bound @0x04;
+ address_cfg address_cfg @0x08;
+ latency_cfg latency_cfg @0x0c;
+ burst_cfg burst_cfg @0x10;
+ chip_timing chip_timing @0x14;
+ rx_delay rx_delay @0x18;
+ };
+ regfile global_regs {
+ ip_version ip_version @0x000;
+ reg_if_version reg_if_version @0x004;
+ capability capability @0x008;
+ command command @0x00c;
+ status status @0x010;
+ };
+ regfile frontend_regs {
+ frontend_cfg frontend_cfg @0x000;
+ };
+ regfile backend_regs {
+ clock_cfg clock_cfg @0x000;
+ };
+ global_regs global_cfg @0x000;
+ frontend_regs frontend @0x100;
+ backend_regs backend @0x200;
+ phy_regs phy_0 @0x300;
+ phy_regs phy_1 @0x340;
+ chip_regs chip_0 @0x400;
+ chip_regs chip_1 @0x440;
+ chip_regs chip_2 @0x480;
+ chip_regs chip_3 @0x4c0;
+ chip_regs chip_4 @0x500;
+ chip_regs chip_5 @0x540;
+ chip_regs chip_6 @0x580;
+ chip_regs chip_7 @0x5c0;
+ chip_1.range_base.value->reset = 10'd1;
+ chip_1.range_bound.value->reset = 10'd2;
+ chip_2.range_base.value->reset = 10'd2;
+ chip_2.range_bound.value->reset = 10'd3;
+ chip_3.range_base.value->reset = 10'd3;
+ chip_3.range_bound.value->reset = 10'd4;
+ chip_4.range_base.value->reset = 10'd4;
+ chip_4.range_bound.value->reset = 10'd5;
+ chip_5.range_base.value->reset = 10'd5;
+ chip_5.range_bound.value->reset = 10'd6;
+ chip_6.range_base.value->reset = 10'd6;
+ chip_6.range_bound.value->reset = 10'd7;
+ chip_7.range_base.value->reset = 10'd7;
+ chip_7.range_bound.value->reset = 10'd8;
+ reserved_top reserved_top @0xffc;
+};
diff --git a/test/axi_hyper_tb.sv b/test/axi_hyper_tb.sv
index fcd42cd..fd1d57f 100644
--- a/test/axi_hyper_tb.sv
+++ b/test/axi_hyper_tb.sv
@@ -235,6 +235,10 @@ module axi_hyper_tb
// Address Ranges //
////////////////////
localparam axi_addr_t MemRegionStart = axi_addr_t'(32'h8000_0000);
+ localparam logic [31:0] CfgFrontendAddr = 32'h0000_0100;
+ localparam logic [31:0] CfgChip0AddressAddr = 32'h0000_0408;
+ localparam logic [31:0] CfgChip0Memory = 32'h0001_1900;
+ localparam logic [31:0] CfgChip0Register = 32'h0001_1901;
localparam axi_addr_t MemRegionLength = axi_addr_t'(TbDramDataWidth * TbDramLenWidth);
logic s_error;
@@ -378,7 +382,7 @@ module axi_hyper_tb
#600350ns;
// switch memory address space to register space
- reg_master.send_write(32'h7<<2, 1'b1, '1, s_reg_error);
+ reg_master.send_write(CfgChip0AddressAddr, CfgChip0Register, '1, s_reg_error);
if (s_reg_error != 1'b0) $error("unexpected error");
// enable variable latency so we can test RWDS sampling
@@ -386,7 +390,7 @@ module axi_hyper_tb
axi_write_32(32'h8000_0000 + S27KS_CFG0_REG_OFFSET, (s27ks_cfg0 | s27ks_cfg0 << 16));
// switch back to memory address space
- reg_master.send_write(32'h7<<2, 1'b0, '1, s_reg_error);
+ reg_master.send_write(CfgChip0AddressAddr, CfgChip0Memory, '1, s_reg_error);
if (s_reg_error != 1'b0) $error("unexpected error");
check_consecutive_reads(axi_ctrl_mst);
@@ -411,31 +415,7 @@ module axi_hyper_tb
$display("= Use only phy 0 =");
$display("===========================");
- reg_master.send_write(32'h20,1'b0,'1,s_reg_error);
- reg_master.send_write(32'h24,1'b0,'1,s_reg_error);
- if (s_reg_error != 1'b0) $error("unexpected error");
-
- axi_rand_mst.reset();
- axi_ctrl_mst.reset_master();
- check_odd_subword_accesses(axi_ctrl_mst);
-
- $display("===========================");
- $display("= Random AXI transactions =");
- $display("===========================");
-
- axi_rand_mst.run(TbNumReads, TbNumWrites);
-
- $display("===========================");
- $display("= Test finished =");
- $display("===========================");
-
- mst_scoreboard.clear_range(32'h8000_0000, 32'h8000_0000 + ( TbDramDataWidth * TbDramLenWidth ));
-
- $display("===========================");
- $display("= Use only phy 1 =");
- $display("===========================");
-
- reg_master.send_write(32'h24,1'b1,'1,s_reg_error);
+ reg_master.send_write(CfgFrontendAddr, 32'h0, '1, s_reg_error);
if (s_reg_error != 1'b0) $error("unexpected error");
axi_rand_mst.reset();
diff --git a/test/dut_if.sv b/test/dut_if.sv
index 232b541..e63d9e9 100644
--- a/test/dut_if.sv
+++ b/test/dut_if.sv
@@ -137,7 +137,6 @@ module dut_if
.axi_b_chan_t ( axi_b_chan_t ),
.axi_ar_chan_t ( axi_ar_chan_t ),
.axi_r_chan_t ( axi_r_chan_t ),
- .RegAddrWidth ( RegAw ),
.RegDataWidth ( RegDw ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
diff --git a/test/fixture_hyperbus.sv b/test/fixture_hyperbus.sv
index 9bd24b5..3967143 100644
--- a/test/fixture_hyperbus.sv
+++ b/test/fixture_hyperbus.sv
@@ -180,7 +180,6 @@ module fixture_hyperbus #(
.axi_b_chan_t ( b_chan_t ),
.axi_ar_chan_t ( ar_chan_t ),
.axi_r_chan_t ( r_chan_t ),
- .RegAddrWidth ( RegAw ),
.RegDataWidth ( RegDw ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
diff --git a/test/hyperbus_cfg_regs_tb.sv b/test/hyperbus_cfg_regs_tb.sv
new file mode 100644
index 0000000..a9e8f9f
--- /dev/null
+++ b/test/hyperbus_cfg_regs_tb.sv
@@ -0,0 +1,251 @@
+// Copyright 2026 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+module hyperbus_cfg_regs_tb;
+
+ localparam int unsigned NumChips = 8;
+
+ typedef struct packed {
+ logic [31:0] addr;
+ logic write;
+ logic [31:0] wdata;
+ logic [3:0] wstrb;
+ logic valid;
+ } reg_req_t;
+
+ typedef struct packed {
+ logic [31:0] rdata;
+ logic error;
+ logic ready;
+ } reg_rsp_t;
+
+ typedef struct packed {
+ logic [31:0] start_addr;
+ logic [31:0] end_addr;
+ logic [2:0] idx;
+ } rule_t;
+
+ logic clk;
+ logic rst_n;
+ reg_req_t reg_req;
+ reg_rsp_t reg_rsp;
+ hyperbus_pkg::frontend_cfg_t frontend_cfg;
+ hyperbus_pkg::phy_cfg_t phy_cfg;
+ rule_t [NumChips-1:0] chip_rules;
+ logic trans_active;
+ logic cfg_busy;
+ logic decode_error;
+ logic cfg_dirty;
+ logic flush_req;
+ logic apply_req;
+ int unsigned command_pulse_count;
+
+ task automatic reg_write_strobe(input logic [31:0] addr, input logic [31:0] data,
+ input logic [3:0] strb);
+ @(negedge clk);
+ reg_req = '{addr: addr, write: 1'b1, wdata: data, wstrb: strb, valid: 1'b1};
+ do @(posedge clk); while (!reg_rsp.ready);
+ if (reg_rsp.error) $error("Register write to 0x%0h failed", addr);
+ @(negedge clk);
+ reg_req.valid = 1'b0;
+ endtask
+
+ task automatic reg_write(input logic [31:0] addr, input logic [31:0] data);
+ reg_write_strobe(addr, data, 4'b1111);
+ endtask
+
+ task automatic reg_write_error(input logic [31:0] addr, input logic [31:0] data,
+ input logic [3:0] strb);
+ @(negedge clk);
+ reg_req = '{addr: addr, write: 1'b1, wdata: data, wstrb: strb, valid: 1'b1};
+ do @(posedge clk); while (!reg_rsp.ready);
+ if (!reg_rsp.error) $error("Invalid register write to 0x%0h was accepted", addr);
+ @(negedge clk);
+ reg_req.valid = 1'b0;
+ endtask
+
+ task automatic reg_read(input logic [31:0] addr, output logic [31:0] data);
+ @(negedge clk);
+ reg_req = '{addr: addr, write: 1'b0, wdata: '0, wstrb: '0, valid: 1'b1};
+ do @(posedge clk); while (!reg_rsp.ready);
+ data = reg_rsp.rdata;
+ if (reg_rsp.error) $error("Register read from 0x%0h failed", addr);
+ @(negedge clk);
+ reg_req.valid = 1'b0;
+ endtask
+
+ task automatic reg_read_error(input logic [31:0] addr);
+ logic [31:0] unused;
+ @(negedge clk);
+ reg_req = '{addr: addr, write: 1'b0, wdata: '0, wstrb: '0, valid: 1'b1};
+ do @(posedge clk); while (!reg_rsp.ready);
+ if (!reg_rsp.error) $error("Unmapped read from 0x%0h was accepted", addr);
+ unused = reg_rsp.rdata;
+ @(negedge clk);
+ reg_req.valid = 1'b0;
+ endtask
+
+ always #5ns clk = ~clk;
+
+ always @(posedge clk) begin
+ if (rst_n && flush_req && apply_req) command_pulse_count++;
+ end
+
+ hyperbus_cfg_regs #(
+ .NumChips ( NumChips ),
+ .NumPhys ( 2 ),
+ .RegDataWidth ( 32 ),
+ .RegAddrWidth ( 32 ),
+ .CapabilityFeatures ( 8'hff ),
+ .reg_req_t ( reg_req_t ),
+ .reg_rsp_t ( reg_rsp_t ),
+ .rule_t ( rule_t )
+ ) i_dut (
+ .clk_i ( clk ),
+ .rst_ni ( rst_n ),
+ .reg_req_i ( reg_req ),
+ .reg_rsp_o ( reg_rsp ),
+ .frontend_cfg_o ( frontend_cfg ),
+ .phy_cfg_o ( phy_cfg ),
+ .chip_rules_o ( chip_rules ),
+ .trans_active_i ( trans_active ),
+ .cfg_busy_i ( cfg_busy ),
+ .decode_error_i ( decode_error ),
+ .cfg_dirty_i ( cfg_dirty ),
+ .flush_req_o ( flush_req ),
+ .apply_req_o ( apply_req )
+ );
+
+ initial begin : proc_stimulus
+ logic [31:0] data;
+
+ clk = 1'b0;
+ rst_n = 1'b0;
+ reg_req = '0;
+ trans_active = 1'b0;
+ cfg_busy = 1'b0;
+ decode_error = 1'b0;
+ cfg_dirty = 1'b0;
+ command_pulse_count = 0;
+ repeat (4) @(posedge clk);
+ rst_n = 1'b1;
+ repeat (2) @(posedge clk);
+
+ reg_read(12'h000, data);
+ if (data != 32'h0000_0900) $error("Unexpected IP_VERSION reset: %h", data);
+ reg_read(12'h004, data);
+ if (data != 32'h0001_0000) $error("Unexpected REG_IF_VERSION reset: %h", data);
+ @(negedge clk);
+ reg_req = '{addr: 32'h00c, write: 1'b1, wdata: 32'h3, wstrb: 4'b1111, valid: 1'b1};
+ do @(posedge clk); while (!reg_rsp.ready);
+ if (reg_rsp.error) $error("COMMAND write failed");
+ @(negedge clk);
+ reg_req.valid = 1'b0;
+ repeat (2) @(posedge clk);
+ #1ns;
+ if (command_pulse_count != 1) begin
+ $error("COMMAND strobes were sampled %0d times", command_pulse_count);
+ end
+ if (flush_req || apply_req) $error("COMMAND strobes were not one-cycle pulses");
+ reg_read(12'h00c, data);
+ if (data != 32'h0) $error("COMMAND strobes did not clear after one cycle: %h", data);
+ reg_read(12'h008, data);
+ if (data != 32'h00ff_0208) $error("Unexpected CAPABILITY reset: %h", data);
+ reg_read(12'h010, data);
+ if (data != 32'h0) $error("Unexpected STATUS reset: %h", data);
+ reg_read(12'h100, data);
+ if ((data != 32'h1) || !frontend_cfg.phys_in_use) $error("Unexpected frontend reset");
+ reg_read(12'h200, data);
+ if (data != 32'h8) $error("Unexpected CLOCK_CFG reset: %h", data);
+ reg_write_error(32'h200, 32'h1, 4'b0001);
+ reg_read(32'h200, data);
+ if (data != 32'h8) $error("Invalid divider write modified the register: %h", data);
+ reg_read(12'h300, data);
+ if (data != 32'h10) $error("Unexpected PHY0 TX_DELAY reset: %h", data);
+ reg_read(12'h340, data);
+ if (data != 32'h10) $error("Unexpected PHY1 TX_DELAY reset: %h", data);
+ reg_read(12'h408, data);
+ if (data != 32'h0001_1900) $error("Unexpected chip0 ADDRESS_CFG reset: %h", data);
+ reg_read(12'h40c, data);
+ if (data != 32'h6) $error("Unexpected chip0 LATENCY_CFG reset: %h", data);
+ reg_read(12'h410, data);
+ if (data != 32'd350) $error("Unexpected chip0 BURST_CFG reset: %h", data);
+ reg_read(12'h414, data);
+ if (data != 32'h106) $error("Unexpected chip0 CHIP_TIMING reset: %h", data);
+ reg_read(12'h418, data);
+ if (data != 32'h10) $error("Unexpected chip0 RX_DELAY reset: %h", data);
+
+ for (int unsigned i = 0; i < NumChips; i++) begin
+ if ((chip_rules[i].start_addr != i * 32'h0040_0000) ||
+ (chip_rules[i].end_addr != (i + 1) * 32'h0040_0000)) begin
+ $error("Unexpected reset address range for chip %0d", i);
+ end
+ end
+
+ reg_write(12'h340, 32'h0000_00a5);
+ reg_read(12'h340, data);
+ if ((data != 8'ha5) || (phy_cfg.t_tx_clk_delay != 8'h10))
+ $error("PHY1 write/read or PHY0 mapping failed");
+ reg_write(12'h300, 32'h0000_005a);
+ if (phy_cfg.t_tx_clk_delay != 8'h5a) $error("PHY0 TX_DELAY mapping failed");
+
+ reg_write(12'h400 + 12'h1c0, 32'h8134_5678);
+ reg_read(12'h400 + 12'h1c0, data);
+ if ((data != 32'h8100_0000) || (chip_rules[7].start_addr != 32'h8100_0000))
+ $error("Chip7 address alignment was not applied");
+
+ reg_write(12'h40c, 32'h0001_0007);
+ reg_read(12'h40c, data);
+ if ((data != 32'h0001_0007) || (phy_cfg.chip.t_latency_access != 7) ||
+ !phy_cfg.chip.en_latency_additional) $error("Chip0 latency mapping failed");
+ reg_write(12'h414, 32'h0000_010a);
+ reg_write_strobe(32'h414, 32'h0000_0007, 4'b0001);
+ reg_read(32'h414, data);
+ if (data != 32'h0000_0107) $error("Partial timing write failed: %h", data);
+ reg_write_error(32'h414, 32'h0000_0010, 4'b0001);
+ reg_read(32'h414, data);
+ if (data != 32'h0000_0107) $error("Invalid timing write modified the register: %h", data);
+ reg_write_error(32'h40c, 32'h0000_0002, 4'b0001);
+ reg_read(32'h40c, data);
+ if (data != 32'h0001_0007) $error("Invalid latency write modified the register: %h", data);
+ reg_read_error(12'h415);
+
+ reg_read_error(12'h104);
+ reg_read_error(32'h0000_1000);
+ reg_read(12'hffc, data);
+ if (data != '0) $error("Reserved endpoint did not read as zero");
+
+ trans_active = 1'b1;
+ cfg_busy = 1'b1;
+ reg_read(32'h010, data);
+ if ((data & 32'h2) == 0) $error("STATUS read was blocked during active transfer");
+ decode_error = 1'b1;
+ cfg_dirty = 1'b1;
+ reg_read(32'h010, data);
+ if ((data & 32'h5) != 32'h5) $error("STATUS hardware bits were not set: %h", data);
+ trans_active = 1'b0;
+ reg_write(32'h010, 32'h1);
+ reg_read(32'h010, data);
+ if ((data & 32'h1) == 0) $error("STATUS hwset did not win over W1C");
+ decode_error = 1'b0;
+ cfg_dirty = 1'b0;
+ reg_write(32'h010, 32'h1);
+ reg_read(32'h010, data);
+ if ((data & 32'h1) != 0) $error("STATUS W1C did not clear decode_error");
+ trans_active = 1'b1;
+ @(negedge clk);
+ reg_req = '{addr: 32'h000, write: 1'b0, wdata: '0, wstrb: '0, valid: 1'b1};
+ repeat (3) begin
+ @(posedge clk);
+ if (reg_rsp.ready) $error("Access completed during active transfer");
+ end
+ trans_active = 1'b0;
+ cfg_busy = 1'b0;
+ do @(posedge clk); while (!reg_rsp.ready);
+ @(negedge clk);
+ reg_req.valid = 1'b0;
+
+ $finish;
+ end
+endmodule