Add missing files for ASIC implementations

[phsauter]

Inspired by #35 we have some annoying gaps if people want to use this IP in ASICs.

• Synthesizable delay line model (generator)
• Constraints
• Tech cell mapping for open-source technologies (at least one as an example)
• Expected synthesis results
• A simpler setup to read in all files for synthesis? Maybe we can checkout bender, generate the scripts and make a release with this as artifacts?
• Better documentation of parameters and registers (also constraints, limitation etc)
• Hardened PHY/backend
• A Verilator setup might be nice