diff --git a/Cargo.lock b/Cargo.lock index 4801f92c63e5a..ffa9a6302ef84 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -146,9 +146,9 @@ dependencies = [ [[package]] name = "libc" -version = "0.2.178" +version = "0.2.183" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "37c93d8daa9d8a012fd8ab92f088405fb202ea0b6ab73ee2482ae66af4f42091" +checksum = "b5b646652bf6661599e1da8901b3b9522896f01e736bad5f723fe7a3a27f899d" dependencies = [ "rustc-std-workspace-core", ] diff --git a/alloc/Cargo.toml b/alloc/Cargo.toml index 541257b6cda6e..b32e5e991cc74 100644 --- a/alloc/Cargo.toml +++ b/alloc/Cargo.toml @@ -16,7 +16,7 @@ bench = false [dependencies] core = { path = "../core", public = true } -compiler_builtins = { path = "../compiler-builtins/compiler-builtins", features = ["rustc-dep-of-std"] } +compiler_builtins = { path = "../compiler-builtins/compiler-builtins", features = ["compiler-builtins"] } [features] compiler-builtins-mem = ['compiler_builtins/mem'] diff --git a/alloc/src/alloc.rs b/alloc/src/alloc.rs index cd1c2ea8fcd1e..52f099e77255b 100644 --- a/alloc/src/alloc.rs +++ b/alloc/src/alloc.rs @@ -5,6 +5,7 @@ #[stable(feature = "alloc_module", since = "1.28.0")] #[doc(inline)] pub use core::alloc::*; +use core::mem::Alignment; use core::ptr::{self, NonNull}; use core::{cmp, hint}; @@ -18,19 +19,24 @@ unsafe extern "Rust" { #[rustc_nounwind] #[rustc_std_internal_symbol] #[rustc_allocator_zeroed_variant = "__rust_alloc_zeroed"] - fn __rust_alloc(size: usize, align: usize) -> *mut u8; + fn __rust_alloc(size: usize, align: Alignment) -> *mut u8; #[rustc_deallocator] #[rustc_nounwind] #[rustc_std_internal_symbol] - fn __rust_dealloc(ptr: *mut u8, size: usize, align: usize); + fn __rust_dealloc(ptr: NonNull, size: usize, align: Alignment); #[rustc_reallocator] #[rustc_nounwind] #[rustc_std_internal_symbol] - fn __rust_realloc(ptr: *mut u8, old_size: usize, align: usize, new_size: usize) -> *mut u8; + fn __rust_realloc( + ptr: NonNull, + old_size: usize, + align: Alignment, + new_size: usize, + ) -> *mut u8; #[rustc_allocator_zeroed] #[rustc_nounwind] #[rustc_std_internal_symbol] - fn __rust_alloc_zeroed(size: usize, align: usize) -> *mut u8; + fn __rust_alloc_zeroed(size: usize, align: Alignment) -> *mut u8; #[rustc_nounwind] #[rustc_std_internal_symbol] @@ -92,7 +98,7 @@ pub unsafe fn alloc(layout: Layout) -> *mut u8 { // stable code until it is actually stabilized. __rust_no_alloc_shim_is_unstable_v2(); - __rust_alloc(layout.size(), layout.align()) + __rust_alloc(layout.size(), layout.alignment()) } } @@ -112,7 +118,14 @@ pub unsafe fn alloc(layout: Layout) -> *mut u8 { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { - unsafe { __rust_dealloc(ptr, layout.size(), layout.align()) } + unsafe { dealloc_nonnull(NonNull::new_unchecked(ptr), layout) } +} + +/// Same as [`dealloc`] but when you already have a non-null pointer +#[inline] +#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces +unsafe fn dealloc_nonnull(ptr: NonNull, layout: Layout) { + unsafe { __rust_dealloc(ptr, layout.size(), layout.alignment()) } } /// Reallocates memory with the global allocator. @@ -132,7 +145,14 @@ pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - unsafe { __rust_realloc(ptr, layout.size(), layout.align(), new_size) } + unsafe { realloc_nonnull(NonNull::new_unchecked(ptr), layout, new_size) } +} + +/// Same as [`realloc`] but when you already have a non-null pointer +#[inline] +#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces +unsafe fn realloc_nonnull(ptr: NonNull, layout: Layout, new_size: usize) -> *mut u8 { + unsafe { __rust_realloc(ptr, layout.size(), layout.alignment(), new_size) } } /// Allocates zero-initialized memory with the global allocator. @@ -175,7 +195,7 @@ pub unsafe fn alloc_zeroed(layout: Layout) -> *mut u8 { // stable code until it is actually stabilized. __rust_no_alloc_shim_is_unstable_v2(); - __rust_alloc_zeroed(layout.size(), layout.align()) + __rust_alloc_zeroed(layout.size(), layout.alignment()) } } @@ -206,7 +226,7 @@ impl Global { // allocation than requested. // * Other conditions must be upheld by the caller, as per `Allocator::deallocate()`'s // safety documentation. - unsafe { dealloc(ptr.as_ptr(), layout) } + unsafe { dealloc_nonnull(ptr, layout) } } } @@ -236,7 +256,7 @@ impl Global { // `realloc` probably checks for `new_size >= old_layout.size()` or something similar. hint::assert_unchecked(new_size >= old_layout.size()); - let raw_ptr = realloc(ptr.as_ptr(), old_layout, new_size); + let raw_ptr = realloc_nonnull(ptr, old_layout, new_size); let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?; if zeroed { raw_ptr.add(old_size).write_bytes(0, new_size - old_size); @@ -285,7 +305,7 @@ impl Global { // `realloc` probably checks for `new_size <= old_layout.size()` or something similar. hint::assert_unchecked(new_size <= old_layout.size()); - let raw_ptr = realloc(ptr.as_ptr(), old_layout, new_size); + let raw_ptr = realloc_nonnull(ptr, old_layout, new_size); let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?; Ok(NonNull::slice_from_raw_parts(ptr, new_size)) }, @@ -479,19 +499,6 @@ unsafe impl const Allocator for Global { } } -/// The allocator for `Box`. -#[cfg(not(no_global_oom_handling))] -#[lang = "exchange_malloc"] -#[inline] -#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn exchange_malloc(size: usize, align: usize) -> *mut u8 { - let layout = unsafe { Layout::from_size_align_unchecked(size, align) }; - match Global.allocate(layout) { - Ok(ptr) => ptr.as_mut_ptr(), - Err(_) => handle_alloc_error(layout), - } -} - // # Allocation error handler #[cfg(not(no_global_oom_handling))] diff --git a/alloc/src/boxed.rs b/alloc/src/boxed.rs index 0844239826bf5..ae16a8401552d 100644 --- a/alloc/src/boxed.rs +++ b/alloc/src/boxed.rs @@ -236,14 +236,34 @@ pub struct Box< #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global, >(Unique, A); -/// Constructs a `Box` by calling the `exchange_malloc` lang item and moving the argument into -/// the newly allocated memory. This is an intrinsic to avoid unnecessary copies. +/// Monomorphic function for allocating an uninit `Box`. +#[inline] +// The is a separate function to avoid doing it in every generic version, but it +// looks small to the mir inliner (particularly in panic=abort) so leave it to +// the backend to decide whether pulling it in everywhere is worth doing. +#[rustc_no_mir_inline] +#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces +#[cfg(not(no_global_oom_handling))] +fn box_new_uninit(layout: Layout) -> *mut u8 { + match Global.allocate(layout) { + Ok(ptr) => ptr.as_mut_ptr(), + Err(_) => handle_alloc_error(layout), + } +} + +/// Helper for `vec!`. /// -/// This is the surface syntax for `box ` expressions. +/// This is unsafe, but has to be marked as safe or else we couldn't use it in `vec!`. #[doc(hidden)] -#[rustc_intrinsic] #[unstable(feature = "liballoc_internals", issue = "none")] -pub fn box_new(x: T) -> Box; +#[inline(always)] +#[cfg(not(no_global_oom_handling))] +#[rustc_diagnostic_item = "box_assume_init_into_vec_unsafe"] +pub fn box_assume_init_into_vec_unsafe( + b: Box>, +) -> crate::vec::Vec { + unsafe { (b.assume_init() as Box<[T]>).into_vec() } +} impl Box { /// Allocates memory on the heap and then places `x` into it. @@ -262,7 +282,13 @@ impl Box { #[rustc_diagnostic_item = "box_new"] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub fn new(x: T) -> Self { - return box_new(x); + // This is `Box::new_uninit` but inlined to avoid build time regressions. + let ptr = box_new_uninit(::LAYOUT) as *mut T; + // Nothing below can panic so we do not have to worry about deallocating `ptr`. + // SAFETY: we just allocated the box to store `x`. + unsafe { core::intrinsics::write_via_move(ptr, x) }; + // SAFETY: we just initialized `b`. + unsafe { mem::transmute(ptr) } } /// Constructs a new box with uninitialized contents. @@ -280,9 +306,15 @@ impl Box { #[cfg(not(no_global_oom_handling))] #[stable(feature = "new_uninit", since = "1.82.0")] #[must_use] - #[inline] + #[inline(always)] + #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub fn new_uninit() -> Box> { - Self::new_uninit_in(Global) + // This is the same as `Self::new_uninit_in(Global)`, but manually inlined (just like + // `Box::new`). + + // SAFETY: + // - If `allocate` succeeds, the returned pointer exactly matches what `Box` needs. + unsafe { mem::transmute(box_new_uninit(::LAYOUT)) } } /// Constructs a new `Box` with uninitialized contents, with the memory @@ -1142,10 +1174,12 @@ impl Box, A> { /// assert_eq!(*five, 5) /// ``` #[stable(feature = "new_uninit", since = "1.82.0")] - #[inline] + #[inline(always)] pub unsafe fn assume_init(self) -> Box { - let (raw, alloc) = Box::into_raw_with_allocator(self); - unsafe { Box::from_raw_in(raw as *mut T, alloc) } + // This is used in the `vec!` macro, so we optimize for minimal IR generation + // even in debug builds. + // SAFETY: `Box` and `Box>` have the same layout. + unsafe { core::intrinsics::transmute_unchecked(self) } } /// Writes the value and converts to `Box`. @@ -1514,7 +1548,7 @@ impl Box { /// Recreate a `Box` which was previously converted to a `NonNull` pointer /// using [`Box::into_non_null_with_allocator`]: /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::System; /// @@ -1524,7 +1558,7 @@ impl Box { /// ``` /// Manually create a `Box` from scratch by using the system allocator: /// ``` - /// #![feature(allocator_api, box_vec_non_null, slice_ptr_get)] + /// #![feature(allocator_api)] /// /// use std::alloc::{Allocator, Layout, System}; /// @@ -1629,7 +1663,7 @@ impl Box { /// Converting the `NonNull` pointer back into a `Box` with /// [`Box::from_non_null_in`] for automatic cleanup: /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::System; /// @@ -1640,7 +1674,7 @@ impl Box { /// Manual cleanup by explicitly running the destructor and deallocating /// the memory: /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::{Allocator, Layout, System}; /// diff --git a/alloc/src/boxed/thin.rs b/alloc/src/boxed/thin.rs index b50810b8d923d..2a34537f58e31 100644 --- a/alloc/src/boxed/thin.rs +++ b/alloc/src/boxed/thin.rs @@ -430,3 +430,12 @@ impl Error for ThinBox { self.deref().source() } } + +#[cfg(not(no_global_oom_handling))] +#[unstable(feature = "thin_box", issue = "92791")] +impl From for ThinBox { + #[inline(always)] + fn from(value: T) -> Self { + Self::new(value) + } +} diff --git a/alloc/src/bstr.rs b/alloc/src/bstr.rs index 338c7ac7f8876..e0d88b27672e0 100644 --- a/alloc/src/bstr.rs +++ b/alloc/src/bstr.rs @@ -477,9 +477,8 @@ impl PartialEq for ByteString { macro_rules! impl_partial_eq_ord_cow { ($lhs:ty, $rhs:ty) => { - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { let other: &[u8] = (&**other).as_ref(); @@ -487,9 +486,8 @@ macro_rules! impl_partial_eq_ord_cow { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { let this: &[u8] = (&**self).as_ref(); @@ -497,9 +495,8 @@ macro_rules! impl_partial_eq_ord_cow { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { let other: &[u8] = (&**other).as_ref(); @@ -507,9 +504,8 @@ macro_rules! impl_partial_eq_ord_cow { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { let this: &[u8] = (&**self).as_ref(); @@ -667,9 +663,9 @@ impl From> for Arc<[u8]> { impl_partial_eq!(ByteStr, Vec); // PartialOrd with `String` omitted to avoid inference failures impl_partial_eq!(ByteStr, String); -impl_partial_eq_ord_cow!(&'a ByteStr, Cow<'a, ByteStr>); -impl_partial_eq_ord_cow!(&'a ByteStr, Cow<'a, str>); -impl_partial_eq_ord_cow!(&'a ByteStr, Cow<'a, [u8]>); +impl_partial_eq_ord_cow!(&ByteStr, Cow<'_, ByteStr>); +impl_partial_eq_ord_cow!(&ByteStr, Cow<'_, str>); +impl_partial_eq_ord_cow!(&ByteStr, Cow<'_, [u8]>); #[unstable(feature = "bstr", issue = "134915")] impl<'a> TryFrom<&'a ByteStr> for String { diff --git a/alloc/src/collections/binary_heap/mod.rs b/alloc/src/collections/binary_heap/mod.rs index 97aafbc7b6994..d46b1972b5b00 100644 --- a/alloc/src/collections/binary_heap/mod.rs +++ b/alloc/src/collections/binary_heap/mod.rs @@ -581,6 +581,40 @@ impl BinaryHeap { pub fn with_capacity_in(capacity: usize, alloc: A) -> BinaryHeap { BinaryHeap { data: Vec::with_capacity_in(capacity, alloc) } } + + /// Creates a `BinaryHeap` using the supplied `vec`. This does not rebuild the heap, + /// so `vec` must already be a max-heap. + /// + /// # Safety + /// + /// The supplied `vec` must be a max-heap, i.e. for all indices `0 < i < vec.len()`, + /// `vec[(i - 1) / 2] >= vec[i]`. + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(binary_heap_from_raw_vec)] + /// + /// use std::collections::BinaryHeap; + /// let heap = BinaryHeap::from([1, 2, 3]); + /// let vec = heap.into_vec(); + /// + /// // Safety: vec is the output of heap.from_vec(), so is a max-heap. + /// let mut new_heap = unsafe { + /// BinaryHeap::from_raw_vec(vec) + /// }; + /// assert_eq!(new_heap.pop(), Some(3)); + /// assert_eq!(new_heap.pop(), Some(2)); + /// assert_eq!(new_heap.pop(), Some(1)); + /// assert_eq!(new_heap.pop(), None); + /// ``` + #[unstable(feature = "binary_heap_from_raw_vec", issue = "152500")] + #[must_use] + pub unsafe fn from_raw_vec(vec: Vec) -> BinaryHeap { + BinaryHeap { data: vec } + } } impl BinaryHeap { @@ -1330,6 +1364,37 @@ impl BinaryHeap { self.data.as_slice() } + /// Returns a mutable slice of all values in the underlying vector. + /// + /// # Safety + /// + /// The caller must ensure that the slice remains a max-heap, i.e. for all indices + /// `0 < i < slice.len()`, `slice[(i - 1) / 2] >= slice[i]`, before the borrow ends + /// and the binary heap is used. + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(binary_heap_as_mut_slice)] + /// + /// use std::collections::BinaryHeap; + /// + /// let mut heap = BinaryHeap::::from([1, 2, 3, 4, 5, 6, 7]); + /// + /// unsafe { + /// for value in heap.as_mut_slice() { + /// *value = (*value).saturating_mul(2); + /// } + /// } + /// ``` + #[must_use] + #[unstable(feature = "binary_heap_as_mut_slice", issue = "154009")] + pub unsafe fn as_mut_slice(&mut self) -> &mut [T] { + self.data.as_mut_slice() + } + /// Consumes the `BinaryHeap` and returns the underlying vector /// in arbitrary order. /// diff --git a/alloc/src/collections/btree/append.rs b/alloc/src/collections/btree/append.rs index 66ea22e75247c..cc8d793e98e4d 100644 --- a/alloc/src/collections/btree/append.rs +++ b/alloc/src/collections/btree/append.rs @@ -1,38 +1,8 @@ use core::alloc::Allocator; -use core::iter::FusedIterator; -use super::merge_iter::MergeIterInner; use super::node::{self, Root}; impl Root { - /// Appends all key-value pairs from the union of two ascending iterators, - /// incrementing a `length` variable along the way. The latter makes it - /// easier for the caller to avoid a leak when a drop handler panicks. - /// - /// If both iterators produce the same key, this method drops the pair from - /// the left iterator and appends the pair from the right iterator. - /// - /// If you want the tree to end up in a strictly ascending order, like for - /// a `BTreeMap`, both iterators should produce keys in strictly ascending - /// order, each greater than all keys in the tree, including any keys - /// already in the tree upon entry. - pub(super) fn append_from_sorted_iters( - &mut self, - left: I, - right: I, - length: &mut usize, - alloc: A, - ) where - K: Ord, - I: Iterator + FusedIterator, - { - // We prepare to merge `left` and `right` into a sorted sequence in linear time. - let iter = MergeIter(MergeIterInner::new(left, right)); - - // Meanwhile, we build a tree from the sorted sequence in linear time. - self.bulk_push(iter, length, alloc) - } - /// Pushes all key-value pairs to the end of the tree, incrementing a /// `length` variable along the way. The latter makes it easier for the /// caller to avoid a leak when the iterator panicks. @@ -94,24 +64,3 @@ impl Root { self.fix_right_border_of_plentiful(); } } - -// An iterator for merging two sorted sequences into one -struct MergeIter>(MergeIterInner); - -impl Iterator for MergeIter -where - I: Iterator + FusedIterator, -{ - type Item = (K, V); - - /// If two keys are equal, returns the key from the left and the value from the right. - fn next(&mut self) -> Option<(K, V)> { - let (a_next, b_next) = self.0.nexts(|a: &(K, V), b: &(K, V)| K::cmp(&a.0, &b.0)); - match (a_next, b_next) { - (Some((a_k, _)), Some((_, b_v))) => Some((a_k, b_v)), - (Some(a), None) => Some(a), - (None, Some(b)) => Some(b), - (None, None) => None, - } - } -} diff --git a/alloc/src/collections/btree/map.rs b/alloc/src/collections/btree/map.rs index 426be364a56b0..e3a6e90566f5e 100644 --- a/alloc/src/collections/btree/map.rs +++ b/alloc/src/collections/btree/map.rs @@ -693,6 +693,7 @@ impl BTreeMap { /// map.insert(1, "a"); /// ``` #[unstable(feature = "btreemap_alloc", issue = "32838")] + #[must_use] pub const fn new_in(alloc: A) -> BTreeMap { BTreeMap { root: None, length: 0, alloc: ManuallyDrop::new(alloc), _marker: PhantomData } } @@ -1214,6 +1215,61 @@ impl BTreeMap { /// ``` #[stable(feature = "btree_append", since = "1.11.0")] pub fn append(&mut self, other: &mut Self) + where + K: Ord, + A: Clone, + { + let other = mem::replace(other, Self::new_in((*self.alloc).clone())); + self.merge(other, |_key, _self_val, other_val| other_val); + } + + /// Moves all elements from `other` into `self`, leaving `other` empty. + /// + /// If a key from `other` is already present in `self`, then the `conflict` + /// closure is used to return a value to `self`. The `conflict` + /// closure takes in a borrow of `self`'s key, `self`'s value, and `other`'s value + /// in that order. + /// + /// An example of why one might use this method over [`append`] + /// is to combine `self`'s value with `other`'s value when their keys conflict. + /// + /// Similar to [`insert`], though, the key is not overwritten, + /// which matters for types that can be `==` without being identical. + /// + /// [`insert`]: BTreeMap::insert + /// [`append`]: BTreeMap::append + /// + /// # Examples + /// + /// ``` + /// #![feature(btree_merge)] + /// use std::collections::BTreeMap; + /// + /// let mut a = BTreeMap::new(); + /// a.insert(1, String::from("a")); + /// a.insert(2, String::from("b")); + /// a.insert(3, String::from("c")); // Note: Key (3) also present in b. + /// + /// let mut b = BTreeMap::new(); + /// b.insert(3, String::from("d")); // Note: Key (3) also present in a. + /// b.insert(4, String::from("e")); + /// b.insert(5, String::from("f")); + /// + /// // concatenate a's value and b's value + /// a.merge(b, |_, a_val, b_val| { + /// format!("{a_val}{b_val}") + /// }); + /// + /// assert_eq!(a.len(), 5); // all of b's keys in a + /// + /// assert_eq!(a[&1], "a"); + /// assert_eq!(a[&2], "b"); + /// assert_eq!(a[&3], "cd"); // Note: "c" has been combined with "d". + /// assert_eq!(a[&4], "e"); + /// assert_eq!(a[&5], "f"); + /// ``` + #[unstable(feature = "btree_merge", issue = "152152")] + pub fn merge(&mut self, mut other: Self, mut conflict: impl FnMut(&K, V, V) -> V) where K: Ord, A: Clone, @@ -1225,19 +1281,102 @@ impl BTreeMap { // We can just swap `self` and `other` if `self` is empty. if self.is_empty() { - mem::swap(self, other); + mem::swap(self, &mut other); return; } - let self_iter = mem::replace(self, Self::new_in((*self.alloc).clone())).into_iter(); - let other_iter = mem::replace(other, Self::new_in((*self.alloc).clone())).into_iter(); - let root = self.root.get_or_insert_with(|| Root::new((*self.alloc).clone())); - root.append_from_sorted_iters( - self_iter, - other_iter, - &mut self.length, - (*self.alloc).clone(), - ) + let mut other_iter = other.into_iter(); + let (first_other_key, first_other_val) = other_iter.next().unwrap(); + + // find the first gap that has the smallest key greater than or equal to + // the first key from other + let mut self_cursor = self.lower_bound_mut(Bound::Included(&first_other_key)); + + if let Some((self_key, _)) = self_cursor.peek_next() { + match K::cmp(self_key, &first_other_key) { + Ordering::Equal => { + // if `f` unwinds, the next entry is already removed leaving + // the tree in valid state. + // FIXME: Once `MaybeDangling` is implemented, we can optimize + // this through using a drop handler and transmutating CursorMutKey + // to CursorMutKey, ManuallyDrop> (see PR #152418) + if let Some((k, v)) = self_cursor.remove_next() { + // SAFETY: we remove the K, V out of the next entry, + // apply 'f' to get a new (K, V), and insert it back + // into the next entry that the cursor is pointing at + let v = conflict(&k, v, first_other_val); + unsafe { self_cursor.insert_after_unchecked(k, v) }; + } + } + Ordering::Greater => + // SAFETY: we know our other_key's ordering is less than self_key, + // so inserting before will guarantee sorted order + unsafe { + self_cursor.insert_before_unchecked(first_other_key, first_other_val); + }, + Ordering::Less => { + unreachable!("Cursor's peek_next should return None."); + } + } + } else { + // SAFETY: reaching here means our cursor is at the end + // self BTreeMap so we just insert other_key here + unsafe { + self_cursor.insert_before_unchecked(first_other_key, first_other_val); + } + } + + for (other_key, other_val) in other_iter { + loop { + if let Some((self_key, _)) = self_cursor.peek_next() { + match K::cmp(self_key, &other_key) { + Ordering::Equal => { + // if `f` unwinds, the next entry is already removed leaving + // the tree in valid state. + // FIXME: Once `MaybeDangling` is implemented, we can optimize + // this through using a drop handler and transmutating CursorMutKey + // to CursorMutKey, ManuallyDrop> (see PR #152418) + if let Some((k, v)) = self_cursor.remove_next() { + // SAFETY: we remove the K, V out of the next entry, + // apply 'f' to get a new (K, V), and insert it back + // into the next entry that the cursor is pointing at + let v = conflict(&k, v, other_val); + unsafe { self_cursor.insert_after_unchecked(k, v) }; + } + break; + } + Ordering::Greater => { + // SAFETY: we know our self_key's ordering is greater than other_key, + // so inserting before will guarantee sorted order + unsafe { + self_cursor.insert_before_unchecked(other_key, other_val); + } + break; + } + Ordering::Less => { + // FIXME: instead of doing a linear search here, + // this can be optimized to search the tree by starting + // from self_cursor and going towards the root and then + // back down to the proper node -- that should probably + // be a new method on Cursor*. + self_cursor.next(); + } + } + } else { + // FIXME: If we get here, that means all of other's keys are greater than + // self's keys. For performance, this should really do a bulk insertion of items + // from other_iter into the end of self `BTreeMap`. Maybe this should be + // a method for Cursor*? + + // SAFETY: reaching here means our cursor is at the end + // self BTreeMap so we just insert other_key here + unsafe { + self_cursor.insert_before_unchecked(other_key, other_val); + } + break; + } + } + } } /// Constructs a double-ended iterator over a sub-range of elements in the map. @@ -1963,7 +2102,9 @@ impl Default for Values<'_, K, V> { } } -/// An iterator produced by calling `extract_if` on BTreeMap. +/// This `struct` is created by the [`extract_if`] method on [`BTreeMap`]. +/// +/// [`extract_if`]: BTreeMap::extract_if #[stable(feature = "btree_extract_if", since = "1.91.0")] #[must_use = "iterators are lazy and do nothing unless consumed; \ use `retain` or `extract_if().for_each(drop)` to remove and discard elements"] diff --git a/alloc/src/collections/btree/map/tests.rs b/alloc/src/collections/btree/map/tests.rs index 938e867b85812..64348745aa07d 100644 --- a/alloc/src/collections/btree/map/tests.rs +++ b/alloc/src/collections/btree/map/tests.rs @@ -1,9 +1,9 @@ use core::assert_matches; -use std::iter; use std::ops::Bound::{Excluded, Included, Unbounded}; use std::panic::{AssertUnwindSafe, catch_unwind}; use std::sync::atomic::AtomicUsize; use std::sync::atomic::Ordering::SeqCst; +use std::{cmp, iter}; use super::*; use crate::boxed::Box; @@ -2128,6 +2128,86 @@ create_append_test!(test_append_239, 239); #[cfg(not(miri))] // Miri is too slow create_append_test!(test_append_1700, 1700); +// a inserts (0, 0)..(8, 8) to its own tree +// b inserts (5, 5 * 2)..($len, 2 * $len) to its own tree +// note that between a and b, there are duplicate keys +// between 5..min($len, 8), so on merge we add the values +// of these keys together +// we check that: +// - the merged tree 'a' has a length of max(8, $len) +// - all keys in 'a' have the correct value associated +// - removing and inserting an element into the merged +// tree 'a' still keeps it in valid tree form +macro_rules! create_merge_test { + ($name:ident, $len:expr) => { + #[test] + fn $name() { + let mut a = BTreeMap::new(); + for i in 0..8 { + a.insert(i, i); + } + + let mut b = BTreeMap::new(); + for i in 5..$len { + b.insert(i, 2 * i); + } + + a.merge(b, |_, a_val, b_val| a_val + b_val); + + assert_eq!(a.len(), cmp::max($len, 8)); + + for i in 0..cmp::max($len, 8) { + if i < 5 { + assert_eq!(a[&i], i); + } else { + if i < cmp::min($len, 8) { + assert_eq!(a[&i], i + 2 * i); + } else if i >= $len { + assert_eq!(a[&i], i); + } else { + assert_eq!(a[&i], 2 * i); + } + } + } + + a.check(); + assert_eq!( + a.remove(&($len - 1)), + if $len >= 5 && $len < 8 { + Some(($len - 1) + 2 * ($len - 1)) + } else { + Some(2 * ($len - 1)) + } + ); + assert_eq!(a.insert($len - 1, 20), None); + a.check(); + } + }; +} + +// These are mostly for testing the algorithm that "fixes" the right edge after insertion. +// Single node, merge conflicting key values. +create_merge_test!(test_merge_7, 7); +// Single node. +create_merge_test!(test_merge_9, 9); +// Two leafs that don't need fixing. +create_merge_test!(test_merge_17, 17); +// Two leafs where the second one ends up underfull and needs stealing at the end. +create_merge_test!(test_merge_14, 14); +// Two leafs where the second one ends up empty because the insertion finished at the root. +create_merge_test!(test_merge_12, 12); +// Three levels; insertion finished at the root. +create_merge_test!(test_merge_144, 144); +// Three levels; insertion finished at leaf while there is an empty node on the second level. +create_merge_test!(test_merge_145, 145); +// Tests for several randomly chosen sizes. +create_merge_test!(test_merge_170, 170); +create_merge_test!(test_merge_181, 181); +#[cfg(not(miri))] // Miri is too slow +create_merge_test!(test_merge_239, 239); +#[cfg(not(miri))] // Miri is too slow +create_merge_test!(test_merge_1700, 1700); + #[test] #[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] fn test_append_drop_leak() { @@ -2144,7 +2224,7 @@ fn test_append_drop_leak() { catch_unwind(move || left.append(&mut right)).unwrap_err(); assert_eq!(a.dropped(), 1); - assert_eq!(b.dropped(), 1); // should be 2 were it not for Rust issue #47949 + assert_eq!(b.dropped(), 2); assert_eq!(c.dropped(), 2); } @@ -2169,6 +2249,84 @@ fn test_append_ord_chaos() { map2.check(); } +#[test] +#[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] +fn test_merge_drop_leak() { + let a = CrashTestDummy::new(0); + let b = CrashTestDummy::new(1); + let c = CrashTestDummy::new(2); + let mut left = BTreeMap::new(); + let mut right = BTreeMap::new(); + left.insert(a.spawn(Panic::Never), ()); + left.insert(b.spawn(Panic::Never), ()); + left.insert(c.spawn(Panic::Never), ()); + right.insert(b.spawn(Panic::InDrop), ()); // first duplicate key, dropped during merge + right.insert(c.spawn(Panic::Never), ()); + + catch_unwind(move || left.merge(right, |_, _, _| ())).unwrap_err(); + assert_eq!(a.dropped(), 1); // this should not be dropped + assert_eq!(b.dropped(), 2); // key is dropped on panic + assert_eq!(c.dropped(), 2); // key is dropped on panic +} + +#[test] +#[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] +fn test_merge_conflict_drop_leak() { + let a = CrashTestDummy::new(0); + let a_val_left = CrashTestDummy::new(0); + + let b = CrashTestDummy::new(1); + let b_val_left = CrashTestDummy::new(1); + let b_val_right = CrashTestDummy::new(1); + + let c = CrashTestDummy::new(2); + let c_val_left = CrashTestDummy::new(2); + let c_val_right = CrashTestDummy::new(2); + + let mut left = BTreeMap::new(); + let mut right = BTreeMap::new(); + + left.insert(a.spawn(Panic::Never), a_val_left.spawn(Panic::Never)); + left.insert(b.spawn(Panic::Never), b_val_left.spawn(Panic::Never)); + left.insert(c.spawn(Panic::Never), c_val_left.spawn(Panic::Never)); + right.insert(b.spawn(Panic::Never), b_val_right.spawn(Panic::Never)); + right.insert(c.spawn(Panic::Never), c_val_right.spawn(Panic::Never)); + + // First key that conflicts should + catch_unwind(move || { + left.merge(right, |_, _, _| panic!("Panic in conflict function")); + assert_eq!(left.len(), 1); // only 1 entry should be left + }) + .unwrap_err(); + assert_eq!(a.dropped(), 1); // should not panic + assert_eq!(a_val_left.dropped(), 1); // should not panic + assert_eq!(b.dropped(), 2); // should drop from panic (conflict) + assert_eq!(b_val_left.dropped(), 1); // should be 2 were it not for Rust issue #47949 + assert_eq!(b_val_right.dropped(), 1); // should be 2 were it not for Rust issue #47949 + assert_eq!(c.dropped(), 2); // should drop from panic (conflict) + assert_eq!(c_val_left.dropped(), 1); // should be 2 were it not for Rust issue #47949 + assert_eq!(c_val_right.dropped(), 1); // should be 2 were it not for Rust issue #47949 +} + +#[test] +fn test_merge_ord_chaos() { + let mut map1 = BTreeMap::new(); + map1.insert(Cyclic3::A, ()); + map1.insert(Cyclic3::B, ()); + let mut map2 = BTreeMap::new(); + map2.insert(Cyclic3::A, ()); + map2.insert(Cyclic3::B, ()); + map2.insert(Cyclic3::C, ()); // lands first, before A + map2.insert(Cyclic3::B, ()); // lands first, before C + map1.check(); + map2.check(); // keys are not unique but still strictly ascending + assert_eq!(map1.len(), 2); + assert_eq!(map2.len(), 4); + map1.merge(map2, |_, _, _| ()); + assert_eq!(map1.len(), 5); + map1.check(); +} + fn rand_data(len: usize) -> Vec<(u32, u32)> { let mut rng = DeterministicRng::new(); Vec::from_iter((0..len).map(|_| (rng.next(), rng.next()))) @@ -2615,3 +2773,25 @@ fn test_id_based_append() { assert_eq!(lhs.pop_first().unwrap().0.name, "lhs_k".to_string()); } + +#[test] +fn test_id_based_merge() { + let mut lhs = BTreeMap::new(); + let mut rhs = BTreeMap::new(); + + lhs.insert(IdBased { id: 0, name: "lhs_k".to_string() }, "1".to_string()); + rhs.insert(IdBased { id: 0, name: "rhs_k".to_string() }, "2".to_string()); + + lhs.merge(rhs, |_, mut lhs_val, rhs_val| { + // confirming that lhs_val comes from lhs tree, + // rhs_val comes from rhs tree + assert_eq!(lhs_val, String::from("1")); + assert_eq!(rhs_val, String::from("2")); + lhs_val.push_str(&rhs_val); + lhs_val + }); + + let merged_kv_pair = lhs.pop_first().unwrap(); + assert_eq!(merged_kv_pair.0.id, 0); + assert_eq!(merged_kv_pair.0.name, "lhs_k".to_string()); +} diff --git a/alloc/src/collections/btree/set.rs b/alloc/src/collections/btree/set.rs index fd27e87b1f470..db8007834432c 100644 --- a/alloc/src/collections/btree/set.rs +++ b/alloc/src/collections/btree/set.rs @@ -361,6 +361,7 @@ impl BTreeSet { /// let mut set: BTreeSet = BTreeSet::new_in(Global); /// ``` #[unstable(feature = "btreemap_alloc", issue = "32838")] + #[must_use] pub const fn new_in(alloc: A) -> BTreeSet { BTreeSet { map: BTreeMap::new_in(alloc) } } @@ -1546,7 +1547,9 @@ impl<'a, T, A: Allocator + Clone> IntoIterator for &'a BTreeSet { } } -/// An iterator produced by calling `extract_if` on BTreeSet. +/// This `struct` is created by the [`extract_if`] method on [`BTreeSet`]. +/// +/// [`extract_if`]: BTreeSet::extract_if #[stable(feature = "btree_extract_if", since = "1.91.0")] #[must_use = "iterators are lazy and do nothing unless consumed; \ use `retain` or `extract_if().for_each(drop)` to remove and discard elements"] diff --git a/alloc/src/collections/linked_list.rs b/alloc/src/collections/linked_list.rs index 3889fca30bc87..1816349e45f4f 100644 --- a/alloc/src/collections/linked_list.rs +++ b/alloc/src/collections/linked_list.rs @@ -862,7 +862,7 @@ impl LinkedList { /// *ptr += 4; /// assert_eq!(dl.front().unwrap(), &6); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `LinkedList::push_front` instead"] pub fn push_front_mut(&mut self, elt: T) -> &mut T { let mut node = @@ -933,7 +933,7 @@ impl LinkedList { /// *ptr += 4; /// assert_eq!(dl.back().unwrap(), &6); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `LinkedList::push_back` instead"] pub fn push_back_mut(&mut self, elt: T) -> &mut T { let mut node = @@ -1942,7 +1942,9 @@ impl<'a, T, A: Allocator> CursorMut<'a, T, A> { } } -/// An iterator produced by calling `extract_if` on LinkedList. +/// This `struct` is created by the [`extract_if`] method on [`LinkedList`]. +/// +/// [`extract_if`]: LinkedList::extract_if #[stable(feature = "extract_if", since = "1.87.0")] #[must_use = "iterators are lazy and do nothing unless consumed; \ use `extract_if().for_each(drop)` to remove and discard elements"] diff --git a/alloc/src/collections/vec_deque/mod.rs b/alloc/src/collections/vec_deque/mod.rs index eda29db442572..3185fd56d8c08 100644 --- a/alloc/src/collections/vec_deque/mod.rs +++ b/alloc/src/collections/vec_deque/mod.rs @@ -2175,7 +2175,7 @@ impl VecDeque { /// *x -= 1; /// assert_eq!(d.front(), Some(&7)); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `VecDeque::push_front` instead"] pub fn push_front_mut(&mut self, value: T) -> &mut T { if self.is_full() { @@ -2218,7 +2218,7 @@ impl VecDeque { /// *x += 1; /// assert_eq!(d.back(), Some(&10)); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `VecDeque::push_back` instead"] pub fn push_back_mut(&mut self, value: T) -> &mut T { if self.is_full() { @@ -2425,7 +2425,7 @@ impl VecDeque { /// *x += 7; /// assert_eq!(vec_deque, &[1, 12, 2, 3]); /// ``` - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `VecDeque::insert` instead"] pub fn insert_mut(&mut self, index: usize, value: T) -> &mut T { assert!(index <= self.len(), "index out of bounds"); diff --git a/alloc/src/collections/vec_deque/splice.rs b/alloc/src/collections/vec_deque/splice.rs index d7b9a96291c39..b82f9fba7ceb3 100644 --- a/alloc/src/collections/vec_deque/splice.rs +++ b/alloc/src/collections/vec_deque/splice.rs @@ -138,8 +138,48 @@ impl Drain<'_, T, A> { /// self.deque must be valid. unsafe fn move_tail(&mut self, additional: usize) { let deque = unsafe { self.deque.as_mut() }; - let tail_start = deque.len + self.drain_len; - deque.buf.reserve(tail_start + self.tail_len, additional); + + // `Drain::new` modifies the deque's len (so does `Drain::fill` here) + // directly with the start bound of the range passed into + // `VecDeque::splice`. This causes a few different issue: + // - Most notably, there will be a hole at the end of the + // buffer when our buffer resizes in the case that our + // data wraps around. + // - We cannot use `VecDeque::reserve` directly because + // how it reserves more space and updates the `VecDeque`'s + // `head` field accordingly depends on the `VecDeque`'s + // actual `len`. + // - We cannot just directly modify `VecDeque`'s `len` and + // and call `VecDeque::reserve` afterward because if + // `VecDeque::reserve` panics on capacity overflow, + // well now our `VecDeque`'s head does not get updated + // and we still have a potential hole at the end of the + // buffer. + // Therefore, we manually reserve additional space (if necessary) + // based on calculating the actual `len` of the `VecDeque` and adjust + // `VecDeque`'s len right *after* the panicking region of `VecDeque::reserve` + // (that is `RawVec` `reserve()` call) + + let drain_start = deque.len; + let tail_start = drain_start + self.drain_len; + + // Actual VecDeque's len = drain_start + tail_len + drain_len + let actual_len = drain_start + self.tail_len + self.drain_len; + let new_cap = actual_len.checked_add(additional).expect("capacity overflow"); + let old_cap = deque.capacity(); + + if new_cap > old_cap { + deque.buf.reserve(actual_len, additional); + // If new_cap doesn't panic, we can safely set the `VecDeque` len to its + // actual len; this needs to be done in order to set deque.head correctly + // on `VecDeque::handle_capacity_increase` + deque.len = actual_len; + // SAFETY: this cannot panic since our internal buffer's new_cap should + // be bigger than the passed in old_cap + unsafe { + deque.handle_capacity_increase(old_cap); + } + } let new_tail_start = tail_start + additional; unsafe { @@ -149,6 +189,9 @@ impl Drain<'_, T, A> { self.tail_len, ); } + + // revert the `VecDeque` len to what it was before + deque.len = drain_start; self.drain_len += additional; } } diff --git a/alloc/src/ffi/c_str.rs b/alloc/src/ffi/c_str.rs index d6dcba7107a9c..b2f4277458f1c 100644 --- a/alloc/src/ffi/c_str.rs +++ b/alloc/src/ffi/c_str.rs @@ -103,6 +103,7 @@ use crate::vec::Vec; /// and other memory errors. #[derive(PartialEq, PartialOrd, Eq, Ord, Hash, Clone)] #[rustc_diagnostic_item = "cstring_type"] +#[rustc_insignificant_dtor] #[stable(feature = "alloc_c_string", since = "1.64.0")] pub struct CString { // Invariant 1: the slice ends with a zero byte and has a length of at least one. @@ -320,6 +321,10 @@ impl CString { /// assertion is made that `v` contains no 0 bytes, and it requires an /// actual byte vector, not anything that can be converted to one with Into. /// + /// # Safety + /// + /// The caller must ensure `v` contains no nul bytes in its contents. + /// /// # Examples /// /// ``` @@ -694,7 +699,6 @@ impl CString { // memory-unsafe code from working by accident. Inline // to prevent LLVM from optimizing it away in debug builds. #[stable(feature = "cstring_drop", since = "1.13.0")] -#[rustc_insignificant_dtor] impl Drop for CString { #[inline] fn drop(&mut self) { diff --git a/alloc/src/intrinsics.rs b/alloc/src/intrinsics.rs new file mode 100644 index 0000000000000..a1e358e077cb6 --- /dev/null +++ b/alloc/src/intrinsics.rs @@ -0,0 +1,15 @@ +//! Intrinsics that cannot be moved to `core` because they depend on `alloc` types. +#![unstable(feature = "liballoc_internals", issue = "none")] + +use core::mem::MaybeUninit; + +use crate::boxed::Box; + +/// Writes `x` into `b`. +/// +/// This is needed for `vec!`, which can't afford any extra copies of the argument (or else debug +/// builds regress), has to be written fully as a call chain without `let` (or else this breaks inference +/// of e.g. unsizing coercions), and can't use an `unsafe` block as that would then also +/// include the user-provided `$x`. +#[rustc_intrinsic] +pub fn write_box_via_move(b: Box>, x: T) -> Box>; diff --git a/alloc/src/lib.rs b/alloc/src/lib.rs index f7167650635d3..bcd9e092a310f 100644 --- a/alloc/src/lib.rs +++ b/alloc/src/lib.rs @@ -56,13 +56,14 @@ //! [`Rc`]: rc //! [`RefCell`]: core::cell +#![allow(unused_features)] #![allow(incomplete_features)] #![allow(unused_attributes)] #![stable(feature = "alloc", since = "1.36.0")] #![doc( html_playground_url = "https://play.rust-lang.org/", issue_tracker_base_url = "https://github.com/rust-lang/rust/issues/", - test(no_crate_inject, attr(allow(unused_variables), deny(warnings))) + test(no_crate_inject, attr(allow(unused_variables, duplicate_features), deny(warnings))) )] #![doc(auto_cfg(hide(no_global_oom_handling, no_rc, no_sync, target_has_atomic = "ptr")))] #![doc(rust_logo)] @@ -85,14 +86,11 @@ // // Library features: // tidy-alphabetical-start -#![cfg_attr(not(no_global_oom_handling), feature(string_replace_in_place))] #![feature(allocator_api)] #![feature(array_into_iter_constructors)] #![feature(ascii_char)] -#![feature(assert_matches)] #![feature(async_fn_traits)] #![feature(async_iterator)] -#![feature(box_vec_non_null)] #![feature(bstr)] #![feature(bstr_internals)] #![feature(cast_maybe_uninit)] @@ -149,8 +147,8 @@ #![feature(slice_ptr_get)] #![feature(slice_range)] #![feature(std_internals)] -#![feature(str_internals)] #![feature(temporary_niche_types)] +#![feature(titlecase)] #![feature(transmutability)] #![feature(trivial_clone)] #![feature(trusted_fused)] @@ -159,7 +157,6 @@ #![feature(try_blocks)] #![feature(try_trait_v2)] #![feature(try_trait_v2_residual)] -#![feature(try_with_capacity)] #![feature(tuple_trait)] #![feature(ub_checks)] #![feature(unicode_internals)] @@ -177,10 +174,8 @@ #![feature(const_trait_impl)] #![feature(coroutine_trait)] #![feature(decl_macro)] -#![feature(derive_const)] #![feature(dropck_eyepatch)] #![feature(fundamental)] -#![feature(hashmap_internals)] #![feature(intrinsics)] #![feature(lang_items)] #![feature(min_specialization)] @@ -188,7 +183,6 @@ #![feature(negative_impls)] #![feature(never_type)] #![feature(optimize_attribute)] -#![feature(rustc_allow_const_fn_unstable)] #![feature(rustc_attrs)] #![feature(slice_internals)] #![feature(staged_api)] @@ -230,6 +224,7 @@ pub mod collections; #[cfg(all(not(no_rc), not(no_sync), not(no_global_oom_handling)))] pub mod ffi; pub mod fmt; +pub mod intrinsics; #[cfg(not(no_rc))] pub mod rc; pub mod slice; diff --git a/alloc/src/macros.rs b/alloc/src/macros.rs index 1e6e2ae8c3675..b99107fb345a4 100644 --- a/alloc/src/macros.rs +++ b/alloc/src/macros.rs @@ -47,10 +47,16 @@ macro_rules! vec { $crate::vec::from_elem($elem, $n) ); ($($x:expr),+ $(,)?) => ( - <[_]>::into_vec( - // Using the intrinsic produces a dramatic improvement in stack usage for - // unoptimized programs using this code path to construct large Vecs. - $crate::boxed::box_new([$($x),+]) + // Using `write_box_via_move` produces a dramatic improvement in stack usage for unoptimized + // programs using this code path to construct large Vecs. We can't use `write_via_move` + // because this entire invocation has to remain a call chain without `let` bindings, or else + // inference and temporary lifetimes change and things break (see `vec-macro-rvalue-scope`, + // `vec-macro-coercions`, and `autoderef-vec-box-fn-36786` tests). + // + // `box_assume_init_into_vec_unsafe` isn't actually safe but the way we use it here is. We + // can't use an unsafe block as that would also wrap `$x`. + $crate::boxed::box_assume_init_into_vec_unsafe( + $crate::intrinsics::write_box_via_move($crate::boxed::Box::new_uninit(), [$($x),+]) ) ); } diff --git a/alloc/src/raw_vec/mod.rs b/alloc/src/raw_vec/mod.rs index ff996ba93cd7f..cabf6accf3b53 100644 --- a/alloc/src/raw_vec/mod.rs +++ b/alloc/src/raw_vec/mod.rs @@ -5,8 +5,8 @@ // run the tests. See the comment there for an explanation why this is the case. use core::marker::{Destruct, PhantomData}; -use core::mem::{ManuallyDrop, MaybeUninit, SizedTypeProperties}; -use core::ptr::{self, Alignment, NonNull, Unique}; +use core::mem::{Alignment, ManuallyDrop, MaybeUninit, SizedTypeProperties}; +use core::ptr::{self, NonNull, Unique}; use core::{cmp, hint}; #[cfg(not(no_global_oom_handling))] @@ -43,7 +43,7 @@ const ZERO_CAP: Cap = unsafe { Cap::new_unchecked(0) }; /// `Cap(cap)`, except if `T` is a ZST then `Cap::ZERO`. /// /// # Safety: cap must be <= `isize::MAX`. -unsafe fn new_cap(cap: usize) -> Cap { +const unsafe fn new_cap(cap: usize) -> Cap { if T::IS_ZST { ZERO_CAP } else { unsafe { Cap::new_unchecked(cap) } } } @@ -260,7 +260,7 @@ impl RawVec { /// If the `ptr` and `capacity` come from a `RawVec` created via `alloc`, then this is /// guaranteed. #[inline] - pub(crate) unsafe fn from_raw_parts_in(ptr: *mut T, capacity: usize, alloc: A) -> Self { + pub(crate) const unsafe fn from_raw_parts_in(ptr: *mut T, capacity: usize, alloc: A) -> Self { // SAFETY: Precondition passed to the caller unsafe { let ptr = ptr.cast(); @@ -278,7 +278,8 @@ impl RawVec { /// /// See [`RawVec::from_raw_parts_in`]. #[inline] - pub(crate) unsafe fn from_nonnull_in(ptr: NonNull, capacity: usize, alloc: A) -> Self { + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] + pub(crate) const unsafe fn from_nonnull_in(ptr: NonNull, capacity: usize, alloc: A) -> Self { // SAFETY: Precondition passed to the caller unsafe { let ptr = ptr.cast(); @@ -310,7 +311,7 @@ impl RawVec { /// Returns a shared reference to the allocator backing this `RawVec`. #[inline] - pub(crate) fn allocator(&self) -> &A { + pub(crate) const fn allocator(&self) -> &A { self.inner.allocator() } @@ -399,6 +400,21 @@ impl RawVec { // SAFETY: All calls on self.inner pass T::LAYOUT as the elem_layout unsafe { self.inner.shrink_to_fit(cap, T::LAYOUT) } } + + /// Shrinks the buffer down to the specified capacity. If the given amount + /// is 0, actually completely deallocates. + /// + /// # Errors + /// + /// This function returns an error if the allocator cannot shrink the allocation. + /// + /// # Panics + /// + /// Panics if the given amount is *larger* than the current capacity. + #[inline] + pub(crate) fn try_shrink_to_fit(&mut self, cap: usize) -> Result<(), TryReserveError> { + unsafe { self.inner.try_shrink_to_fit(cap, T::LAYOUT) } + } } unsafe impl<#[may_dangle] T, A: Allocator> Drop for RawVec { @@ -554,7 +570,7 @@ const impl RawVecInner { impl RawVecInner { #[inline] const fn new_in(alloc: A, align: Alignment) -> Self { - let ptr = Unique::from_non_null(NonNull::without_provenance(align.as_nonzero())); + let ptr = Unique::from_non_null(NonNull::without_provenance(align.as_nonzero_usize())); // `cap: 0` means "unallocated". zero-sized types are ignored. Self { ptr, cap: ZERO_CAP, alloc } } @@ -578,12 +594,13 @@ impl RawVecInner { } #[inline] - unsafe fn from_raw_parts_in(ptr: *mut u8, cap: Cap, alloc: A) -> Self { + const unsafe fn from_raw_parts_in(ptr: *mut u8, cap: Cap, alloc: A) -> Self { Self { ptr: unsafe { Unique::new_unchecked(ptr) }, cap, alloc } } #[inline] - unsafe fn from_nonnull_in(ptr: NonNull, cap: Cap, alloc: A) -> Self { + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] + const unsafe fn from_nonnull_in(ptr: NonNull, cap: Cap, alloc: A) -> Self { Self { ptr: Unique::from(ptr), cap, alloc } } @@ -603,7 +620,7 @@ impl RawVecInner { } #[inline] - fn allocator(&self) -> &A { + const fn allocator(&self) -> &A { &self.alloc } @@ -731,6 +748,20 @@ impl RawVecInner { } } + /// # Safety + /// + /// - `elem_layout` must be valid for `self`, i.e. it must be the same `elem_layout` used to + /// initially construct `self` + /// - `elem_layout`'s size must be a multiple of its alignment + /// - `cap` must be less than or equal to `self.capacity(elem_layout.size())` + unsafe fn try_shrink_to_fit( + &mut self, + cap: usize, + elem_layout: Layout, + ) -> Result<(), TryReserveError> { + unsafe { self.shrink(cap, elem_layout) } + } + #[inline] const fn needs_to_grow(&self, len: usize, additional: usize, elem_layout: Layout) -> bool { additional > self.capacity(elem_layout.size()).wrapping_sub(len) @@ -778,7 +809,6 @@ impl RawVecInner { /// initially construct `self` /// - `elem_layout`'s size must be a multiple of its alignment /// - `cap` must be less than or equal to `self.capacity(elem_layout.size())` - #[cfg(not(no_global_oom_handling))] #[inline] unsafe fn shrink(&mut self, cap: usize, elem_layout: Layout) -> Result<(), TryReserveError> { assert!(cap <= self.capacity(elem_layout.size()), "Tried to shrink to a larger capacity"); @@ -796,7 +826,6 @@ impl RawVecInner { /// /// # Safety /// `cap <= self.capacity()` - #[cfg(not(no_global_oom_handling))] unsafe fn shrink_unchecked( &mut self, cap: usize, diff --git a/alloc/src/rc.rs b/alloc/src/rc.rs index cec41524325e0..cfca2d9ec970e 100644 --- a/alloc/src/rc.rs +++ b/alloc/src/rc.rs @@ -252,7 +252,7 @@ use core::intrinsics::abort; #[cfg(not(no_global_oom_handling))] use core::iter; use core::marker::{PhantomData, Unsize}; -use core::mem::{self, ManuallyDrop}; +use core::mem::{self, Alignment, ManuallyDrop}; use core::num::NonZeroUsize; use core::ops::{CoerceUnsized, Deref, DerefMut, DerefPure, DispatchFromDyn, LegacyReceiver}; #[cfg(not(no_global_oom_handling))] @@ -261,7 +261,7 @@ use core::panic::{RefUnwindSafe, UnwindSafe}; #[cfg(not(no_global_oom_handling))] use core::pin::Pin; use core::pin::PinCoerceUnsized; -use core::ptr::{self, Alignment, NonNull, drop_in_place}; +use core::ptr::{self, NonNull, drop_in_place}; #[cfg(not(no_global_oom_handling))] use core::slice::from_raw_parts_mut; use core::{borrow, fmt, hint}; @@ -1430,29 +1430,32 @@ impl Rc { /// Constructs an `Rc` from a raw pointer. /// /// The raw pointer must have been previously returned by a call to - /// [`Rc::into_raw`][into_raw] with the following requirements: + /// [`Rc::into_raw`][into_raw] or [`Rc::into_raw_with_allocator`][into_raw_with_allocator]. /// + /// # Safety + /// + /// * Creating a `Rc` from a pointer other than one returned from + /// [`Rc::into_raw`][into_raw] or [`Rc::into_raw_with_allocator`][into_raw_with_allocator] + /// is undefined behavior. /// * If `U` is sized, it must have the same size and alignment as `T`. This /// is trivially true if `U` is `T`. /// * If `U` is unsized, its data pointer must have the same size and /// alignment as `T`. This is trivially true if `Rc` was constructed /// through `Rc` and then converted to `Rc` through an [unsized /// coercion]. - /// - /// Note that if `U` or `U`'s data pointer is not `T` but has the same size - /// and alignment, this is basically like transmuting references of - /// different types. See [`mem::transmute`][transmute] for more information - /// on what restrictions apply in this case. - /// - /// The raw pointer must point to a block of memory allocated by the global allocator - /// - /// The user of `from_raw` has to make sure a specific value of `T` is only - /// dropped once. + /// * Note that if `U` or `U`'s data pointer is not `T` but has the same size + /// and alignment, this is basically like transmuting references of + /// different types. See [`mem::transmute`][transmute] for more information + /// on what restrictions apply in this case. + /// * The raw pointer must point to a block of memory allocated by the global allocator + /// * The user of `from_raw` has to make sure a specific value of `T` is only + /// dropped once. /// /// This function is unsafe because improper use may lead to memory unsafety, /// even if the returned `Rc` is never accessed. /// /// [into_raw]: Rc::into_raw + /// [into_raw_with_allocator]: Rc::into_raw_with_allocator /// [transmute]: core::mem::transmute /// [unsized coercion]: https://doc.rust-lang.org/reference/type-coercions.html#unsized-coercions /// @@ -1662,29 +1665,32 @@ impl Rc { /// Constructs an `Rc` from a raw pointer in the provided allocator. /// /// The raw pointer must have been previously returned by a call to [`Rc::into_raw`][into_raw] with the following requirements: + /// A>::into_raw`][into_raw] or [`Rc::into_raw_with_allocator`][into_raw_with_allocator]. /// + /// # Safety + /// + /// * Creating a `Rc` from a pointer other than one returned from + /// [`Rc::into_raw`][into_raw] or [`Rc::into_raw_with_allocator`][into_raw_with_allocator] + /// is undefined behavior. /// * If `U` is sized, it must have the same size and alignment as `T`. This /// is trivially true if `U` is `T`. /// * If `U` is unsized, its data pointer must have the same size and - /// alignment as `T`. This is trivially true if `Rc` was constructed - /// through `Rc` and then converted to `Rc` through an [unsized + /// alignment as `T`. This is trivially true if `Rc` was constructed + /// through `Rc` and then converted to `Rc` through an [unsized /// coercion]. - /// - /// Note that if `U` or `U`'s data pointer is not `T` but has the same size - /// and alignment, this is basically like transmuting references of - /// different types. See [`mem::transmute`][transmute] for more information - /// on what restrictions apply in this case. - /// - /// The raw pointer must point to a block of memory allocated by `alloc` - /// - /// The user of `from_raw` has to make sure a specific value of `T` is only - /// dropped once. + /// * Note that if `U` or `U`'s data pointer is not `T` but has the same size + /// and alignment, this is basically like transmuting references of + /// different types. See [`mem::transmute`][transmute] for more information + /// on what restrictions apply in this case. + /// * The raw pointer must point to a block of memory allocated by `alloc` + /// * The user of `from_raw` has to make sure a specific value of `T` is only + /// dropped once. /// /// This function is unsafe because improper use may lead to memory unsafety, - /// even if the returned `Rc` is never accessed. + /// even if the returned `Rc` is never accessed. /// /// [into_raw]: Rc::into_raw + /// [into_raw_with_allocator]: Rc::into_raw_with_allocator /// [transmute]: core::mem::transmute /// [unsized coercion]: https://doc.rust-lang.org/reference/type-coercions.html#unsized-coercions /// @@ -2424,9 +2430,6 @@ unsafe impl PinCoerceUnsized for Rc {} #[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] unsafe impl PinCoerceUnsized for UniqueRc {} -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for Weak {} - #[unstable(feature = "deref_pure_trait", issue = "87121")] unsafe impl DerefPure for Rc {} @@ -3980,6 +3983,15 @@ impl AsMut for UniqueRc { #[unstable(feature = "unique_rc_arc", issue = "112566")] impl Unpin for UniqueRc {} +#[cfg(not(no_global_oom_handling))] +#[unstable(feature = "unique_rc_arc", issue = "112566")] +impl From for UniqueRc { + #[inline(always)] + fn from(value: T) -> Self { + Self::new(value) + } +} + #[unstable(feature = "unique_rc_arc", issue = "112566")] impl PartialEq for UniqueRc { /// Equality for two `UniqueRc`s. diff --git a/alloc/src/slice.rs b/alloc/src/slice.rs index cc8d80aee4569..39e72e383eacb 100644 --- a/alloc/src/slice.rs +++ b/alloc/src/slice.rs @@ -477,7 +477,6 @@ impl [T] { #[rustc_allow_incoherent_impl] #[stable(feature = "rust1", since = "1.0.0")] #[inline] - #[rustc_diagnostic_item = "slice_into_vec"] pub fn into_vec(self: Box) -> Vec { unsafe { let len = self.len(); diff --git a/alloc/src/str.rs b/alloc/src/str.rs index e772ac25a95c2..8a3326c7d76a7 100644 --- a/alloc/src/str.rs +++ b/alloc/src/str.rs @@ -411,9 +411,8 @@ impl str { fn map_uppercase_sigma(from: &str, i: usize) -> char { // See https://www.unicode.org/versions/Unicode7.0.0/ch03.pdf#G33992 // for the definition of `Final_Sigma`. - debug_assert!('Σ'.len_utf8() == 2); let is_word_final = case_ignorable_then_cased(from[..i].chars().rev()) - && !case_ignorable_then_cased(from[i + 2..].chars()); + && !case_ignorable_then_cased(from[i + const { 'Σ'.len_utf8() }..].chars()); if is_word_final { 'ς' } else { 'σ' } } diff --git a/alloc/src/string.rs b/alloc/src/string.rs index 4100ee55a4c7b..30e52f3e1be46 100644 --- a/alloc/src/string.rs +++ b/alloc/src/string.rs @@ -2661,8 +2661,7 @@ impl<'b> Pattern for &'b String { macro_rules! impl_eq { ($lhs:ty, $rhs: ty) => { #[stable(feature = "rust1", since = "1.0.0")] - #[allow(unused_lifetimes)] - impl<'a, 'b> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { PartialEq::eq(&self[..], &other[..]) @@ -2674,8 +2673,7 @@ macro_rules! impl_eq { } #[stable(feature = "rust1", since = "1.0.0")] - #[allow(unused_lifetimes)] - impl<'a, 'b> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { PartialEq::eq(&self[..], &other[..]) @@ -2689,13 +2687,13 @@ macro_rules! impl_eq { } impl_eq! { String, str } -impl_eq! { String, &'a str } +impl_eq! { String, &str } #[cfg(not(no_global_oom_handling))] -impl_eq! { Cow<'a, str>, str } +impl_eq! { Cow<'_, str>, str } #[cfg(not(no_global_oom_handling))] -impl_eq! { Cow<'a, str>, &'b str } +impl_eq! { Cow<'_, str>, &'_ str } #[cfg(not(no_global_oom_handling))] -impl_eq! { Cow<'a, str>, String } +impl_eq! { Cow<'_, str>, String } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] diff --git a/alloc/src/sync.rs b/alloc/src/sync.rs index a5e4fab916aba..b3e49af868b8c 100644 --- a/alloc/src/sync.rs +++ b/alloc/src/sync.rs @@ -19,14 +19,14 @@ use core::intrinsics::abort; #[cfg(not(no_global_oom_handling))] use core::iter; use core::marker::{PhantomData, Unsize}; -use core::mem::{self, ManuallyDrop}; +use core::mem::{self, Alignment, ManuallyDrop}; use core::num::NonZeroUsize; use core::ops::{CoerceUnsized, Deref, DerefMut, DerefPure, DispatchFromDyn, LegacyReceiver}; #[cfg(not(no_global_oom_handling))] use core::ops::{Residual, Try}; use core::panic::{RefUnwindSafe, UnwindSafe}; use core::pin::{Pin, PinCoerceUnsized}; -use core::ptr::{self, Alignment, NonNull}; +use core::ptr::{self, NonNull}; #[cfg(not(no_global_oom_handling))] use core::slice::from_raw_parts_mut; use core::sync::atomic::Ordering::{Acquire, Relaxed, Release}; @@ -1581,29 +1581,32 @@ impl Arc { /// Constructs an `Arc` from a raw pointer. /// /// The raw pointer must have been previously returned by a call to - /// [`Arc::into_raw`][into_raw] with the following requirements: + /// [`Arc::into_raw`][into_raw] or [`Arc::into_raw_with_allocator`][into_raw_with_allocator]. /// + /// # Safety + /// + /// * Creating a `Arc` from a pointer other than one returned from + /// [`Arc::into_raw`][into_raw] or [`Arc::into_raw_with_allocator`][into_raw_with_allocator] + /// is undefined behavior. /// * If `U` is sized, it must have the same size and alignment as `T`. This /// is trivially true if `U` is `T`. /// * If `U` is unsized, its data pointer must have the same size and /// alignment as `T`. This is trivially true if `Arc` was constructed /// through `Arc` and then converted to `Arc` through an [unsized /// coercion]. - /// - /// Note that if `U` or `U`'s data pointer is not `T` but has the same size - /// and alignment, this is basically like transmuting references of - /// different types. See [`mem::transmute`][transmute] for more information - /// on what restrictions apply in this case. - /// - /// The raw pointer must point to a block of memory allocated by the global allocator. - /// - /// The user of `from_raw` has to make sure a specific value of `T` is only - /// dropped once. + /// * Note that if `U` or `U`'s data pointer is not `T` but has the same size + /// and alignment, this is basically like transmuting references of + /// different types. See [`mem::transmute`][transmute] for more information + /// on what restrictions apply in this case. + /// * The raw pointer must point to a block of memory allocated by the global allocator. + /// * The user of `from_raw` has to make sure a specific value of `T` is only + /// dropped once. /// /// This function is unsafe because improper use may lead to memory unsafety, /// even if the returned `Arc` is never accessed. /// /// [into_raw]: Arc::into_raw + /// [into_raw_with_allocator]: Arc::into_raw_with_allocator /// [transmute]: core::mem::transmute /// [unsized coercion]: https://doc.rust-lang.org/reference/type-coercions.html#unsized-coercions /// @@ -1819,29 +1822,32 @@ impl Arc { /// Constructs an `Arc` from a raw pointer. /// /// The raw pointer must have been previously returned by a call to [`Arc::into_raw`][into_raw] with the following requirements: + /// A>::into_raw`][into_raw] or [`Arc::into_raw_with_allocator`][into_raw_with_allocator]. /// + /// # Safety + /// + /// * Creating a `Arc` from a pointer other than one returned from + /// [`Arc::into_raw`][into_raw] or [`Arc::into_raw_with_allocator`][into_raw_with_allocator] + /// is undefined behavior. /// * If `U` is sized, it must have the same size and alignment as `T`. This /// is trivially true if `U` is `T`. /// * If `U` is unsized, its data pointer must have the same size and - /// alignment as `T`. This is trivially true if `Arc` was constructed - /// through `Arc` and then converted to `Arc` through an [unsized + /// alignment as `T`. This is trivially true if `Arc` was constructed + /// through `Arc` and then converted to `Arc` through an [unsized /// coercion]. - /// - /// Note that if `U` or `U`'s data pointer is not `T` but has the same size - /// and alignment, this is basically like transmuting references of - /// different types. See [`mem::transmute`][transmute] for more information - /// on what restrictions apply in this case. - /// - /// The raw pointer must point to a block of memory allocated by `alloc` - /// - /// The user of `from_raw` has to make sure a specific value of `T` is only - /// dropped once. + /// * Note that if `U` or `U`'s data pointer is not `T` but has the same size + /// and alignment, this is basically like transmuting references of + /// different types. See [`mem::transmute`][transmute] for more information + /// on what restrictions apply in this case. + /// * The raw pointer must point to a block of memory allocated by `alloc` + /// * The user of `from_raw` has to make sure a specific value of `T` is only + /// dropped once. /// /// This function is unsafe because improper use may lead to memory unsafety, /// even if the returned `Arc` is never accessed. /// /// [into_raw]: Arc::into_raw + /// [into_raw_with_allocator]: Arc::into_raw_with_allocator /// [transmute]: core::mem::transmute /// [unsized coercion]: https://doc.rust-lang.org/reference/type-coercions.html#unsized-coercions /// @@ -2426,9 +2432,6 @@ impl Deref for Arc { #[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] unsafe impl PinCoerceUnsized for Arc {} -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for Weak {} - #[unstable(feature = "deref_pure_trait", issue = "87121")] unsafe impl DerefPure for Arc {} @@ -3270,7 +3273,7 @@ impl Weak { // Acquire is necessary for the success case to synchronise with `Arc::new_cyclic`, when the inner // value can be initialized after `Weak` references have already been created. In that case, we // expect to observe the fully initialized value. - if self.inner()?.strong.fetch_update(Acquire, Relaxed, checked_increment).is_ok() { + if self.inner()?.strong.try_update(Acquire, Relaxed, checked_increment).is_ok() { // SAFETY: pointer is not null, verified in checked_increment unsafe { Some(Arc::from_inner_in(self.ptr, self.alloc.clone())) } } else { @@ -4424,6 +4427,15 @@ impl AsMut for UniqueArc { } } +#[cfg(not(no_global_oom_handling))] +#[unstable(feature = "unique_rc_arc", issue = "112566")] +impl From for UniqueArc { + #[inline(always)] + fn from(value: T) -> Self { + Self::new(value) + } +} + #[unstable(feature = "unique_rc_arc", issue = "112566")] impl Unpin for UniqueArc {} diff --git a/alloc/src/task.rs b/alloc/src/task.rs index aa1901314e37c..bc668f78bf740 100644 --- a/alloc/src/task.rs +++ b/alloc/src/task.rs @@ -87,6 +87,7 @@ use crate::sync::Arc; /// ``` #[cfg(target_has_atomic = "ptr")] #[stable(feature = "wake_trait", since = "1.51.0")] +#[rustc_diagnostic_item = "Wake"] pub trait Wake { /// Wake this task. #[stable(feature = "wake_trait", since = "1.51.0")] diff --git a/alloc/src/vec/drain.rs b/alloc/src/vec/drain.rs index 8705a9c3d2679..9a6bfa823f2a5 100644 --- a/alloc/src/vec/drain.rs +++ b/alloc/src/vec/drain.rs @@ -1,8 +1,7 @@ -use core::fmt; use core::iter::{FusedIterator, TrustedLen}; use core::mem::{self, ManuallyDrop, SizedTypeProperties}; use core::ptr::{self, NonNull}; -use core::slice::{self}; +use core::{fmt, slice}; use super::Vec; use crate::alloc::{Allocator, Global}; diff --git a/alloc/src/vec/into_iter.rs b/alloc/src/vec/into_iter.rs index af1bd53179739..4f67a2c04fefc 100644 --- a/alloc/src/vec/into_iter.rs +++ b/alloc/src/vec/into_iter.rs @@ -9,8 +9,7 @@ use core::num::NonZero; use core::ops::Deref; use core::panic::UnwindSafe; use core::ptr::{self, NonNull}; -use core::slice::{self}; -use core::{array, fmt}; +use core::{array, fmt, slice}; #[cfg(not(no_global_oom_handling))] use super::AsVecIntoIter; diff --git a/alloc/src/vec/mod.rs b/alloc/src/vec/mod.rs index 6cbe89d9da4f2..942b2b9d2dadf 100644 --- a/alloc/src/vec/mod.rs +++ b/alloc/src/vec/mod.rs @@ -75,8 +75,6 @@ #[cfg(not(no_global_oom_handling))] use core::clone::TrivialClone; -#[cfg(not(no_global_oom_handling))] -use core::cmp; use core::cmp::Ordering; use core::hash::{Hash, Hasher}; #[cfg(not(no_global_oom_handling))] @@ -88,7 +86,7 @@ use core::mem::{self, Assume, ManuallyDrop, MaybeUninit, SizedTypeProperties, Tr use core::ops::{self, Index, IndexMut, Range, RangeBounds}; use core::ptr::{self, NonNull}; use core::slice::{self, SliceIndex}; -use core::{fmt, hint, intrinsics, ub_checks}; +use core::{cmp, fmt, hint, intrinsics, ub_checks}; #[stable(feature = "extract_if", since = "1.87.0")] pub use self::extract_if::ExtractIf; @@ -558,7 +556,7 @@ impl Vec { /// (`T` having a less strict alignment is not sufficient, the alignment really /// needs to be equal to satisfy the [`dealloc`] requirement that memory must be /// allocated and deallocated with the same layout.) - /// * The size of `T` times the `capacity` (ie. the allocated size in bytes), if + /// * The size of `T` times the `capacity` (i.e. the allocated size in bytes), if /// nonzero, needs to be the same size as the pointer was allocated with. /// (Because similar to alignment, [`dealloc`] must be called with the same /// layout `size`.) @@ -642,7 +640,8 @@ impl Vec { /// ``` #[inline] #[stable(feature = "rust1", since = "1.0.0")] - pub unsafe fn from_raw_parts(ptr: *mut T, length: usize, capacity: usize) -> Self { + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] + pub const unsafe fn from_raw_parts(ptr: *mut T, length: usize, capacity: usize) -> Self { unsafe { Self::from_raw_parts_in(ptr, length, capacity, Global) } } @@ -660,7 +659,7 @@ impl Vec { /// (`T` having a less strict alignment is not sufficient, the alignment really /// needs to be equal to satisfy the [`dealloc`] requirement that memory must be /// allocated and deallocated with the same layout.) - /// * The size of `T` times the `capacity` (ie. the allocated size in bytes) needs + /// * The size of `T` times the `capacity` (i.e. the allocated size in bytes) needs /// to be the same size as the pointer was allocated with. (Because similar to /// alignment, [`dealloc`] must be called with the same layout `size`.) /// * `length` needs to be less than or equal to `capacity`. @@ -744,7 +743,8 @@ impl Vec { /// ``` #[inline] #[unstable(feature = "box_vec_non_null", issue = "130364")] - pub unsafe fn from_parts(ptr: NonNull, length: usize, capacity: usize) -> Self { + #[rustc_const_unstable(feature = "box_vec_non_null", issue = "130364")] + pub const unsafe fn from_parts(ptr: NonNull, length: usize, capacity: usize) -> Self { unsafe { Self::from_parts_in(ptr, length, capacity, Global) } } @@ -838,7 +838,8 @@ impl Vec { /// ``` #[must_use = "losing the pointer will leak memory"] #[stable(feature = "vec_into_raw_parts", since = "1.93.0")] - pub fn into_raw_parts(self) -> (*mut T, usize, usize) { + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] + pub const fn into_raw_parts(self) -> (*mut T, usize, usize) { let mut me = ManuallyDrop::new(self); (me.as_mut_ptr(), me.len(), me.capacity()) } @@ -879,7 +880,8 @@ impl Vec { /// ``` #[must_use = "losing the pointer will leak memory"] #[unstable(feature = "box_vec_non_null", issue = "130364")] - pub fn into_parts(self) -> (NonNull, usize, usize) { + #[rustc_const_unstable(feature = "box_vec_non_null", issue = "130364")] + pub const fn into_parts(self) -> (NonNull, usize, usize) { let (ptr, len, capacity) = self.into_raw_parts(); // SAFETY: A `Vec` always has a non-null pointer. (unsafe { NonNull::new_unchecked(ptr) }, len, capacity) @@ -896,9 +898,17 @@ impl Vec { where T: Freeze, { - unsafe { core::intrinsics::const_make_global(self.as_mut_ptr().cast()) }; - let me = ManuallyDrop::new(self); - unsafe { slice::from_raw_parts(me.as_ptr(), me.len) } + // `const_make_global` requires the pointer to point to the beginning of a heap allocation, + // which is not the case when `self.capacity()` is 0, or if `T::IS_ZST`, + // which is why we instead return a new slice in this case. + if self.capacity() == 0 || T::IS_ZST { + let me = ManuallyDrop::new(self); + unsafe { slice::from_raw_parts(NonNull::::dangling().as_ptr(), me.len) } + } else { + unsafe { core::intrinsics::const_make_global(self.as_mut_ptr().cast()) }; + let me = ManuallyDrop::new(self); + unsafe { slice::from_raw_parts(me.as_ptr(), me.len) } + } } } @@ -1020,7 +1030,7 @@ const impl Vec { /// vector's elements to a larger allocation. This expensive operation is /// offset by the *capacity* *O*(1) insertions it allows. #[inline] - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[must_use = "if you don't need a reference to the value, use `Vec::push` instead"] pub fn push_mut(&mut self, value: T) -> &mut T { // Inform codegen that the length does not change across grow_one(). @@ -1092,7 +1102,7 @@ impl Vec { /// (`T` having a less strict alignment is not sufficient, the alignment really /// needs to be equal to satisfy the [`dealloc`] requirement that memory must be /// allocated and deallocated with the same layout.) - /// * The size of `T` times the `capacity` (ie. the allocated size in bytes) needs + /// * The size of `T` times the `capacity` (i.e. the allocated size in bytes) needs /// to be the same size as the pointer was allocated with. (Because similar to /// alignment, [`dealloc`] must be called with the same layout `size`.) /// * `length` needs to be less than or equal to `capacity`. @@ -1180,7 +1190,13 @@ impl Vec { /// ``` #[inline] #[unstable(feature = "allocator_api", issue = "32838")] - pub unsafe fn from_raw_parts_in(ptr: *mut T, length: usize, capacity: usize, alloc: A) -> Self { + #[rustc_const_unstable(feature = "allocator_api", issue = "32838")] + pub const unsafe fn from_raw_parts_in( + ptr: *mut T, + length: usize, + capacity: usize, + alloc: A, + ) -> Self { ub_checks::assert_unsafe_precondition!( check_library_ub, "Vec::from_raw_parts_in requires that length <= capacity", @@ -1203,7 +1219,7 @@ impl Vec { /// (`T` having a less strict alignment is not sufficient, the alignment really /// needs to be equal to satisfy the [`dealloc`] requirement that memory must be /// allocated and deallocated with the same layout.) - /// * The size of `T` times the `capacity` (ie. the allocated size in bytes) needs + /// * The size of `T` times the `capacity` (i.e. the allocated size in bytes) needs /// to be the same size as the pointer was allocated with. (Because similar to /// alignment, [`dealloc`] must be called with the same layout `size`.) /// * `length` needs to be less than or equal to `capacity`. @@ -1238,7 +1254,7 @@ impl Vec { /// # Examples /// /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::System; /// @@ -1265,7 +1281,7 @@ impl Vec { /// Using memory that was allocated elsewhere: /// /// ```rust - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::{AllocError, Allocator, Global, Layout}; /// @@ -1289,8 +1305,14 @@ impl Vec { /// ``` #[inline] #[unstable(feature = "allocator_api", issue = "32838")] + #[rustc_const_unstable(feature = "allocator_api", issue = "32838")] // #[unstable(feature = "box_vec_non_null", issue = "130364")] - pub unsafe fn from_parts_in(ptr: NonNull, length: usize, capacity: usize, alloc: A) -> Self { + pub const unsafe fn from_parts_in( + ptr: NonNull, + length: usize, + capacity: usize, + alloc: A, + ) -> Self { ub_checks::assert_unsafe_precondition!( check_library_ub, "Vec::from_parts_in requires that length <= capacity", @@ -1338,7 +1360,8 @@ impl Vec { /// ``` #[must_use = "losing the pointer will leak memory"] #[unstable(feature = "allocator_api", issue = "32838")] - pub fn into_raw_parts_with_alloc(self) -> (*mut T, usize, usize, A) { + #[rustc_const_unstable(feature = "allocator_api", issue = "32838")] + pub const fn into_raw_parts_with_alloc(self) -> (*mut T, usize, usize, A) { let mut me = ManuallyDrop::new(self); let len = me.len(); let capacity = me.capacity(); @@ -1365,7 +1388,7 @@ impl Vec { /// # Examples /// /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::System; /// @@ -1387,8 +1410,9 @@ impl Vec { /// ``` #[must_use = "losing the pointer will leak memory"] #[unstable(feature = "allocator_api", issue = "32838")] + #[rustc_const_unstable(feature = "allocator_api", issue = "32838")] // #[unstable(feature = "box_vec_non_null", issue = "130364")] - pub fn into_parts_with_alloc(self) -> (NonNull, usize, usize, A) { + pub const fn into_parts_with_alloc(self) -> (NonNull, usize, usize, A) { let (ptr, len, capacity, alloc) = self.into_raw_parts_with_alloc(); // SAFETY: A `Vec` always has a non-null pointer. (unsafe { NonNull::new_unchecked(ptr) }, len, capacity, alloc) @@ -1613,6 +1637,73 @@ impl Vec { } } + /// Tries to shrink the capacity of the vector as much as possible + /// + /// The behavior of this method depends on the allocator, which may either shrink the vector + /// in-place or reallocate. The resulting vector might still have some excess capacity, just as + /// is the case for [`with_capacity`]. See [`Allocator::shrink`] for more details. + /// + /// [`with_capacity`]: Vec::with_capacity + /// + /// # Errors + /// + /// This function returns an error if the allocator fails to shrink the allocation, + /// the vector thereafter is still safe to use, the capacity remains unchanged + /// however. See [`Allocator::shrink`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(vec_fallible_shrink)] + /// + /// let mut vec = Vec::with_capacity(10); + /// vec.extend([1, 2, 3]); + /// assert!(vec.capacity() >= 10); + /// vec.try_shrink_to_fit().expect("why is the test harness failing to shrink to 12 bytes"); + /// assert!(vec.capacity() >= 3); + /// ``` + #[unstable(feature = "vec_fallible_shrink", issue = "152350")] + #[inline] + pub fn try_shrink_to_fit(&mut self) -> Result<(), TryReserveError> { + if self.capacity() > self.len { self.buf.try_shrink_to_fit(self.len) } else { Ok(()) } + } + + /// Shrinks the capacity of the vector with a lower bound. + /// + /// The capacity will remain at least as large as both the length + /// and the supplied value. + /// + /// If the current capacity is less than the lower limit, this is a no-op. + /// + /// # Errors + /// + /// This function returns an error if the allocator fails to shrink the allocation, + /// the vector thereafter is still safe to use, the capacity remains unchanged + /// however. See [`Allocator::shrink`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(vec_fallible_shrink)] + /// + /// let mut vec = Vec::with_capacity(10); + /// vec.extend([1, 2, 3]); + /// assert!(vec.capacity() >= 10); + /// vec.try_shrink_to(4).expect("why is the test harness failing to shrink to 12 bytes"); + /// assert!(vec.capacity() >= 4); + /// vec.try_shrink_to(0).expect("this is a no-op and thus the allocator isn't involved."); + /// assert!(vec.capacity() >= 3); + /// ``` + #[unstable(feature = "vec_fallible_shrink", issue = "152350")] + #[inline] + pub fn try_shrink_to(&mut self, min_capacity: usize) -> Result<(), TryReserveError> { + if self.capacity() > min_capacity { + self.buf.try_shrink_to_fit(cmp::max(self.len, min_capacity)) + } else { + Ok(()) + } + } + /// Converts the vector into [`Box<[T]>`][owned slice]. /// /// Before doing the conversion, this method discards excess capacity like [`shrink_to_fit`]. @@ -1770,7 +1861,7 @@ impl Vec { // SAFETY: `slice::from_raw_parts_mut` requires pointee is a contiguous, aligned buffer of // size `len` containing properly-initialized `T`s. Data must not be accessed through any // other pointer for the returned lifetime. Further, `len * size_of::` <= - // `ISIZE::MAX` and allocation does not "wrap" through overflowing memory addresses. + // `isize::MAX` and allocation does not "wrap" through overflowing memory addresses. // // * Vec API guarantees that self.buf: // * contains only properly-initialized items within 0..len @@ -2000,8 +2091,9 @@ impl Vec { /// Returns a reference to the underlying allocator. #[unstable(feature = "allocator_api", issue = "32838")] + #[rustc_const_unstable(feature = "const_heap", issue = "79597")] #[inline] - pub fn allocator(&self) -> &A { + pub const fn allocator(&self) -> &A { self.buf.allocator() } @@ -2206,7 +2298,7 @@ impl Vec { /// the insertion index is 0. #[cfg(not(no_global_oom_handling))] #[inline] - #[stable(feature = "push_mut", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "push_mut", since = "1.95.0")] #[track_caller] #[must_use = "if you don't need a reference to the value, use `Vec::insert` instead"] pub fn insert_mut(&mut self, index: usize, element: T) -> &mut T { diff --git a/alloc/src/vec/spec_extend.rs b/alloc/src/vec/spec_extend.rs index 7c908841c90ec..de6ef3d803263 100644 --- a/alloc/src/vec/spec_extend.rs +++ b/alloc/src/vec/spec_extend.rs @@ -1,6 +1,6 @@ use core::clone::TrivialClone; use core::iter::TrustedLen; -use core::slice::{self}; +use core::slice; use super::{IntoIter, Vec}; use crate::alloc::Allocator; diff --git a/alloc/src/vec/spec_from_iter.rs b/alloc/src/vec/spec_from_iter.rs index e1f0b639bdfd6..ccbc2936fb4e8 100644 --- a/alloc/src/vec/spec_from_iter.rs +++ b/alloc/src/vec/spec_from_iter.rs @@ -1,5 +1,5 @@ use core::mem::ManuallyDrop; -use core::ptr::{self}; +use core::ptr; use super::{IntoIter, SpecExtend, SpecFromIterNested, Vec}; diff --git a/alloc/src/vec/splice.rs b/alloc/src/vec/splice.rs index 46611f611dc2c..99ebcb4ada296 100644 --- a/alloc/src/vec/splice.rs +++ b/alloc/src/vec/splice.rs @@ -1,5 +1,4 @@ -use core::ptr::{self}; -use core::slice::{self}; +use core::ptr; use super::{Drain, Vec}; use crate::alloc::{Allocator, Global}; @@ -108,15 +107,13 @@ impl Drain<'_, T, A> { let vec = unsafe { self.vec.as_mut() }; let range_start = vec.len; let range_end = self.tail_start; - let range_slice = unsafe { - slice::from_raw_parts_mut(vec.as_mut_ptr().add(range_start), range_end - range_start) - }; + // The elements in this range are not initialized so we avoid creating a slice. - for place in range_slice { + for idx in range_start..range_end { let Some(new_item) = replace_with.next() else { return false; }; - unsafe { ptr::write(place, new_item) }; + unsafe { vec.as_mut_ptr().add(idx).write(new_item) }; vec.len += 1; } true diff --git a/alloc/src/wtf8/mod.rs b/alloc/src/wtf8/mod.rs index e4834a24bf430..394c41bf36727 100644 --- a/alloc/src/wtf8/mod.rs +++ b/alloc/src/wtf8/mod.rs @@ -342,14 +342,18 @@ impl Wtf8Buf { /// Shortens a string to the specified length. /// + /// If `new_len` is greater than the string's current length, this has no + /// effect. + /// /// # Panics /// - /// Panics if `new_len` > current length, - /// or if `new_len` is not a code point boundary. + /// Panics if `new_len` does not lie on a code point boundary. #[inline] pub fn truncate(&mut self, new_len: usize) { - assert!(self.is_code_point_boundary(new_len)); - self.bytes.truncate(new_len) + if new_len <= self.len() { + assert!(self.is_code_point_boundary(new_len)); + self.bytes.truncate(new_len) + } } /// Consumes the WTF-8 string and tries to convert it to a vec of bytes. diff --git a/alloc/src/wtf8/tests.rs b/alloc/src/wtf8/tests.rs index a72ad0837d11e..79e0bbdef50f6 100644 --- a/alloc/src/wtf8/tests.rs +++ b/alloc/src/wtf8/tests.rs @@ -308,10 +308,10 @@ fn wtf8buf_truncate_fail_code_point_boundary() { } #[test] -#[should_panic] -fn wtf8buf_truncate_fail_longer() { +fn wtf8buf_truncate_invalid_len() { let mut string = Wtf8Buf::from_str("aé"); string.truncate(4); + assert_eq!(string, Wtf8Buf::from_str("aé")); } #[test] diff --git a/alloctests/benches/lib.rs b/alloctests/benches/lib.rs index 721d685527fec..4a25778d88c83 100644 --- a/alloctests/benches/lib.rs +++ b/alloctests/benches/lib.rs @@ -1,4 +1,4 @@ -// Disabling in Miri as these would take too long. +// This is marked as `test = true` and hence picked up by `./x miri`, but that would be too slow. #![cfg(not(miri))] #![feature(iter_next_chunk)] #![feature(repr_simd)] diff --git a/alloctests/benches/vec_deque_append.rs b/alloctests/benches/vec_deque_append.rs index 7c805da973763..180981abc06f6 100644 --- a/alloctests/benches/vec_deque_append.rs +++ b/alloctests/benches/vec_deque_append.rs @@ -6,11 +6,6 @@ const WARMUP_N: usize = 100; const BENCH_N: usize = 1000; fn main() { - if cfg!(miri) { - // Don't benchmark Miri... - // (Due to bootstrap quirks, this gets picked up by `x.py miri library/alloc --no-doc`.) - return; - } let a: VecDeque = (0..VECDEQUE_LEN).collect(); let b: VecDeque = (0..VECDEQUE_LEN).collect(); diff --git a/alloctests/lib.rs b/alloctests/lib.rs index fe14480102e32..e09d8495fdeac 100644 --- a/alloctests/lib.rs +++ b/alloctests/lib.rs @@ -16,8 +16,6 @@ // tidy-alphabetical-start #![feature(allocator_api)] #![feature(array_into_iter_constructors)] -#![feature(assert_matches)] -#![feature(box_vec_non_null)] #![feature(char_internals)] #![feature(const_alloc_error)] #![feature(const_cmp)] @@ -56,16 +54,12 @@ // // Language features: // tidy-alphabetical-start -#![feature(cfg_sanitize)] #![feature(const_trait_impl)] #![feature(dropck_eyepatch)] -#![feature(lang_items)] #![feature(min_specialization)] -#![feature(negative_impls)] #![feature(never_type)] #![feature(optimize_attribute)] #![feature(prelude_import)] -#![feature(rustc_allow_const_fn_unstable)] #![feature(rustc_attrs)] #![feature(staged_api)] #![feature(test)] diff --git a/alloctests/tests/lib.rs b/alloctests/tests/lib.rs index e15c86496cf1b..699a5010282b0 100644 --- a/alloctests/tests/lib.rs +++ b/alloctests/tests/lib.rs @@ -3,8 +3,6 @@ #![feature(const_heap)] #![feature(deque_extend_front)] #![feature(iter_array_chunks)] -#![feature(assert_matches)] -#![feature(wtf8_internals)] #![feature(cow_is_borrowed)] #![feature(core_intrinsics)] #![feature(downcast_unchecked)] @@ -31,8 +29,6 @@ #![feature(string_remove_matches)] #![feature(const_btree_len)] #![feature(const_trait_impl)] -#![feature(panic_update_hook)] -#![feature(pointer_is_aligned_to)] #![feature(test)] #![feature(thin_box)] #![feature(drain_keep_rest)] diff --git a/alloctests/tests/slice.rs b/alloctests/tests/slice.rs index 1e15d54d979a2..1194e48f38cfa 100644 --- a/alloctests/tests/slice.rs +++ b/alloctests/tests/slice.rs @@ -909,7 +909,8 @@ fn test_split_iterators_size_hint() { // become maximally long, so the size_hint upper bounds are tight ((|_| true) as fn(&_) -> _, Bounds::Upper), ] { - use {assert_tight_size_hints as a, format_args as f}; + use assert_tight_size_hints as a; + use format_args as f; a(v.split(p), b, "split"); a(v.split_mut(p), b, "split_mut"); diff --git a/alloctests/tests/str.rs b/alloctests/tests/str.rs index fcc4aaaa1dcd1..c0bcdb8500af6 100644 --- a/alloctests/tests/str.rs +++ b/alloctests/tests/str.rs @@ -612,14 +612,14 @@ mod slice_index { data: "abcdef"; good: data[4..4] == ""; bad: data[4..3]; - message: "begin <= end (4 <= 3)"; + message: "byte range starts at 4 but ends at 3"; } in mod rangeinclusive_neg_width { data: "abcdef"; good: data[4..=3] == ""; bad: data[4..=2]; - message: "begin <= end (4 <= 3)"; + message: "byte range starts at 4 but ends at 3"; } } @@ -630,13 +630,13 @@ mod slice_index { // note: using 0 specifically ensures that the result of overflowing is 0..0, // so that `get` doesn't simply return None for the wrong reason. bad: data[0..=usize::MAX]; - message: "maximum usize"; + message: "out of bounds"; } in mod rangetoinclusive { data: "hello"; bad: data[..=usize::MAX]; - message: "maximum usize"; + message: "out of bounds"; } } } @@ -659,49 +659,49 @@ mod slice_index { data: super::DATA; bad: data[super::BAD_START..super::GOOD_END]; message: - "byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5) of"; + "start byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5 of string)"; } in mod range_2 { data: super::DATA; bad: data[super::GOOD_START..super::BAD_END]; message: - "byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; + "end byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7 of string)"; } in mod rangefrom { data: super::DATA; bad: data[super::BAD_START..]; message: - "byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5) of"; + "start byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5 of string)"; } in mod rangeto { data: super::DATA; bad: data[..super::BAD_END]; message: - "byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; + "end byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7 of string)"; } in mod rangeinclusive_1 { data: super::DATA; bad: data[super::BAD_START..=super::GOOD_END_INCL]; message: - "byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5) of"; + "start byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5 of string)"; } in mod rangeinclusive_2 { data: super::DATA; bad: data[super::GOOD_START..=super::BAD_END_INCL]; message: - "byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; + "end byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7 of string)"; } in mod rangetoinclusive { data: super::DATA; bad: data[..=super::BAD_END_INCL]; message: - "byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; + "end byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7 of string)"; } } } @@ -716,16 +716,10 @@ mod slice_index { // check the panic includes the prefix of the sliced string #[test] - #[should_panic(expected = "byte index 1024 is out of bounds of `Lorem ipsum dolor sit amet")] + #[should_panic(expected = "end byte index 1024 is out of bounds for string of length 416")] fn test_slice_fail_truncated_1() { let _ = &LOREM_PARAGRAPH[..1024]; } - // check the truncation in the panic message - #[test] - #[should_panic(expected = "luctus, im`[...]")] - fn test_slice_fail_truncated_2() { - let _ = &LOREM_PARAGRAPH[..1024]; - } } #[test] diff --git a/alloctests/tests/vec.rs b/alloctests/tests/vec.rs index 5ab305f7a5048..db7da0db47d74 100644 --- a/alloctests/tests/vec.rs +++ b/alloctests/tests/vec.rs @@ -2764,3 +2764,25 @@ fn const_heap() { assert_eq!([1, 2, 4, 8, 16, 32], X); } + +// regression test for issue #153158. `const_make_global` previously assumed `Vec`'s buf +// always has a heap allocation, which lead to compilation errors. +#[test] +fn const_make_global_empty_or_zst_regression() { + const EMPTY_SLICE: &'static [i32] = { + let empty_vec: Vec = Vec::new(); + empty_vec.const_make_global() + }; + + assert_eq!(EMPTY_SLICE, &[]); + + const ZST_SLICE: &'static [()] = { + let mut zst_vec: Vec<()> = Vec::new(); + zst_vec.push(()); + zst_vec.push(()); + zst_vec.push(()); + zst_vec.const_make_global() + }; + + assert_eq!(ZST_SLICE, &[(), (), ()]); +} diff --git a/alloctests/tests/vec_deque.rs b/alloctests/tests/vec_deque.rs index 92853fe00fd63..91843dfd00585 100644 --- a/alloctests/tests/vec_deque.rs +++ b/alloctests/tests/vec_deque.rs @@ -2347,3 +2347,16 @@ fn test_splice_wrapping() { assert_eq!(Vec::from(vec), [7, 8, 9]); } + +#[test] +fn test_splice_wrapping_and_resize() { + let mut vec = VecDeque::new(); + + for i in [1; 6] { + vec.push_front(i); + } + + vec.splice(1..1, [2, 3, 4]); + + assert_eq!(Vec::from(vec), [1, 2, 3, 4, 1, 1, 1, 1, 1]) +} diff --git a/compiler-builtins/.github/workflows/main.yaml b/compiler-builtins/.github/workflows/main.yaml index 699a9c417ddef..261b1619f1c5f 100644 --- a/compiler-builtins/.github/workflows/main.yaml +++ b/compiler-builtins/.github/workflows/main.yaml @@ -13,7 +13,7 @@ env: RUSTDOCFLAGS: -Dwarnings RUSTFLAGS: -Dwarnings RUST_BACKTRACE: full - BENCHMARK_RUSTC: nightly-2025-12-01 # Pin the toolchain for reproducable results + BENCHMARK_RUSTC: nightly-2026-02-10 # Pin the toolchain for reproducable results jobs: # Determine which tests should be run based on changed files. @@ -228,7 +228,27 @@ jobs: # poorly with build scripts) cargo build -p compiler_builtins -p libm \ --target etc/thumbv7em-none-eabi-renamed.json \ - -Zbuild-std=core + -Zbuild-std=core \ + -Zjson-target-spec + + # FIXME: move this target to test job once https://github.com/rust-lang/rust/pull/150138 merged. + build-thumbv6k: + name: Build thumbv6k + runs-on: ubuntu-24.04 + timeout-minutes: 10 + steps: + - uses: actions/checkout@v4 + - name: Install Rust + run: | + rustup update nightly --no-self-update + rustup default nightly + rustup component add rust-src + - uses: Swatinem/rust-cache@v2 + - run: | + cargo build -p compiler_builtins -p libm \ + --target etc/thumbv6-none-eabi.json \ + -Zbuild-std=core \ + -Zjson-target-spec benchmarks: name: Benchmarks @@ -267,7 +287,7 @@ jobs: path: ${{ env.BASELINE_NAME }}.tar.xz - name: Run wall time benchmarks - run: ./ci/bench-runtime.sh + run: ./ci/bench-walltime.sh - name: Print test logs if available if: always() @@ -281,7 +301,9 @@ jobs: steps: - uses: actions/checkout@v4 - name: Install Rust (rustup) - run: rustup update nightly --no-self-update && rustup default nightly + # FIXME(ci): not working in the 2026-02-11 nightly + # https://rust-lang.zulipchat.com/#narrow/channel/269128-miri/topic/build-script-build.20contains.20outdated.20or.20invalid.20JSON/with/573426109 + run: rustup update nightly-2026-02-10 --no-self-update && rustup default nightly-2026-02-10 shell: bash - run: rustup component add miri - run: cargo miri setup @@ -354,6 +376,7 @@ jobs: needs: - benchmarks - build-custom + - build-thumbv6k - clippy - extensive - miri diff --git a/compiler-builtins/.github/workflows/rustc-pull.yml b/compiler-builtins/.github/workflows/rustc-pull.yml index 617db14f46eea..8e88213332de4 100644 --- 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+checksum = "4122cd3169e94605190e77839c9a40d40ed048d305bfdc146e7df40ab0f3e517" +dependencies = [ + "proc-macro2", + "quote", + "syn", +] + +[[package]] +name = "zmij" +version = "1.0.21" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b8848ee67ecc8aedbaf3e4122217aff892639231befc6a1b58d29fff4c2cabaa" diff --git a/compiler-builtins/Cargo.toml b/compiler-builtins/Cargo.toml index 8501f4e630b55..26a056f434967 100644 --- a/compiler-builtins/Cargo.toml +++ b/compiler-builtins/Cargo.toml @@ -31,6 +31,41 @@ exclude = [ "compiler-builtins", ] +[workspace.dependencies] +anyhow = "1.0.101" +assert_cmd = "2.1.2" +cc = "1.2.56" +cfg-if = "1.0.4" +compiler_builtins = { path = "builtins-shim", default-features = false } +criterion = { version = "0.8.2", default-features = false, features = ["cargo_bench_support"] } +getopts = "0.2.24" +getrandom = "0.4.1" +gmp-mpfr-sys = { version = "1.6.8", default-features = false } +gungraun = "0.17.2" +heck = "0.5.0" +indicatif = { version = "0.18.3", default-features = false } +libm = { path = "libm", default-features = false } +libm-macros = { path = "crates/libm-macros" } +libm-test = { path = "libm-test", default-features = false } +libtest-mimic = "0.8.1" +musl-math-sys = { path = "crates/musl-math-sys" } +no-panic = "0.1.36" +object = { version = "0.38.1", features = ["wasm"] } +panic-handler = { path = "crates/panic-handler" } +paste = "1.0.15" +proc-macro2 = "1.0.106" +quote = "1.0.44" +rand = "0.10.0" +rand_chacha = "0.10.0" +rand_xoshiro = "0.8" +rayon = "1.11.0" +regex = "1.12.3" +rug = { version = "1.28.1", default-features = false, features = ["float", "integer", "std"] } +rustc_apfloat = "0.2.3" +serde_json = "1.0.149" +syn = "2.0.115" +tempfile = "3.25.0" + [profile.release] panic = "abort" @@ -51,6 +86,7 @@ codegen-units = 1 lto = "fat" [profile.bench] +codegen-units = 1 # Required for gungraun debug = true strip = false diff --git a/compiler-builtins/builtins-shim/Cargo.toml b/compiler-builtins/builtins-shim/Cargo.toml index 746d5b21dc3f1..32b0308a7b3c9 100644 --- a/compiler-builtins/builtins-shim/Cargo.toml +++ b/compiler-builtins/builtins-shim/Cargo.toml @@ -7,6 +7,9 @@ # manifest that is identical except for the `core` dependency and forwards # to the same sources, which acts as the `compiler-builtins` Cargo entrypoint # for out of tree testing +# +# Ideally we can eventually replace this with a patch in the workspace +# manifest . [package] name = "compiler_builtins" @@ -33,10 +36,10 @@ doctest = false test = false [build-dependencies] -cc = { optional = true, version = "1.2" } +cc = { version = "1.2", optional = true } [features] -default = ["compiler-builtins"] +default = [] # Enable compilation of C code in compiler-rt, filling in some more optimized # implementations and also filling in unimplemented intrinsics @@ -47,7 +50,8 @@ c = ["dep:cc"] # the generic versions on all platforms. no-asm = [] -# Flag this library as the unstable compiler-builtins lib +# Flag this library as the unstable compiler-builtins lib. This must be enabled +# when using as `std`'s dependency.' compiler-builtins = [] # Generate memory-related intrinsics like memcpy @@ -57,9 +61,6 @@ mem = [] # compiler-rt implementations. Also used for testing mangled-names = [] -# Only used in the compiler's build system -rustc-dep-of-std = ["compiler-builtins"] - # This makes certain traits and function specializations public that # are not normally public but are required by the `builtins-test` unstable-public-internals = [] diff --git a/compiler-builtins/builtins-test-intrinsics/src/main.rs b/compiler-builtins/builtins-test-intrinsics/src/main.rs index b9d19ea77256e..a3df2c98376cb 100644 --- a/compiler-builtins/builtins-test-intrinsics/src/main.rs +++ b/compiler-builtins/builtins-test-intrinsics/src/main.rs @@ -3,10 +3,8 @@ // compiling a C implementation and forget to implement that intrinsic in Rust, this file will fail // to link due to the missing intrinsic (symbol). -#![allow(unused_features)] -#![allow(internal_features)] +#![allow(internal_features, unused_features)] #![deny(dead_code)] -#![feature(allocator_api)] #![feature(f128)] #![feature(f16)] #![feature(lang_items)] diff --git a/compiler-builtins/builtins-test/Cargo.toml b/compiler-builtins/builtins-test/Cargo.toml index 550f736a76dbb..b2313bb9d140e 100644 --- a/compiler-builtins/builtins-test/Cargo.toml +++ b/compiler-builtins/builtins-test/Cargo.toml @@ -6,23 +6,22 @@ publish = false license = "MIT AND Apache-2.0 WITH LLVM-exception AND (MIT OR Apache-2.0)" [dependencies] +compiler_builtins = { workspace = true, features = ["unstable-public-internals"] } + # For fuzzing tests we want a deterministic seedable RNG. We also eliminate potential # problems with system RNGs on the variety of platforms this crate is tested on. # `xoshiro128**` is used for its quality, size, and speed at generating `u32` shift amounts. -rand_xoshiro = "0.7" +rand_xoshiro.workspace = true + # To compare float builtins against -rustc_apfloat = "0.2.3" -# Really a dev dependency, but dev dependencies can't be optional -gungraun = { version = "0.17.0", optional = true } +rustc_apfloat.workspace = true -[dependencies.compiler_builtins] -path = "../builtins-shim" -default-features = false -features = ["unstable-public-internals"] +# Really dev dependencies, but those can't be optional +criterion = { workspace = true, optional = true } +gungraun = { workspace = true, optional = true } [dev-dependencies] -criterion = { version = "0.6.0", default-features = false, features = ["cargo_bench_support"] } -paste = "1.0.15" +paste.workspace = true [target.'cfg(all(target_arch = "arm", not(any(target_env = "gnu", target_env = "musl")), target_os = "linux"))'.dev-dependencies] test = { git = "https://github.com/japaric/utest" } @@ -47,8 +46,10 @@ no-sys-f16 = ["no-sys-f16-f64-convert"] # Enable icount benchmarks (requires gungraun-runner and valgrind locally) icount = ["dep:gungraun"] -# Enable report generation without bringing in more dependencies by default -benchmarking-reports = ["criterion/plotters", "criterion/html_reports"] +# Config for wall time benchmarks. Plotters and html_reports bring in extra +# deps so are off by default for CI. +benchmarking-reports = ["walltime", "criterion/plotters", "criterion/html_reports"] +walltime = ["dep:criterion"] # NOTE: benchmarks must be run with `--no-default-features` or with # `-p builtins-test`, otherwise the default `compiler-builtins` feature @@ -58,38 +59,47 @@ benchmarking-reports = ["criterion/plotters", "criterion/html_reports"] [[bench]] name = "float_add" harness = false +required-features = ["walltime"] [[bench]] name = "float_sub" harness = false +required-features = ["walltime"] [[bench]] name = "float_mul" harness = false +required-features = ["walltime"] [[bench]] name = "float_div" harness = false +required-features = ["walltime"] [[bench]] name = "float_cmp" harness = false +required-features = ["walltime"] [[bench]] name = "float_conv" harness = false +required-features = ["walltime"] [[bench]] name = "float_extend" harness = false +required-features = ["walltime"] [[bench]] name = "float_trunc" harness = false +required-features = ["walltime"] [[bench]] name = "float_pow" harness = false +required-features = ["walltime"] [[bench]] name = "mem_icount" diff --git a/compiler-builtins/builtins-test/src/lib.rs b/compiler-builtins/builtins-test/src/lib.rs index f1673133be27d..b9ad649f88dd7 100644 --- a/compiler-builtins/builtins-test/src/lib.rs +++ b/compiler-builtins/builtins-test/src/lib.rs @@ -22,7 +22,7 @@ extern crate alloc; use compiler_builtins::float::Float; use compiler_builtins::int::{Int, MinInt}; use rand_xoshiro::Xoshiro128StarStar; -use rand_xoshiro::rand_core::{RngCore, SeedableRng}; +use rand_xoshiro::rand_core::{Rng, SeedableRng}; /// Sets the number of fuzz iterations run for most tests. In practice, the vast majority of bugs /// are caught by the edge case testers. Most of the remaining bugs triggered by more complex diff --git a/compiler-builtins/builtins-test/tests/addsub.rs b/compiler-builtins/builtins-test/tests/addsub.rs index f3334bd0e2d3a..410967967d2a3 100644 --- a/compiler-builtins/builtins-test/tests/addsub.rs +++ b/compiler-builtins/builtins-test/tests/addsub.rs @@ -1,4 +1,4 @@ -#![allow(unused_macros)] +#![allow(unused_macros, unused_features)] #![cfg_attr(f16_enabled, feature(f16))] #![cfg_attr(f128_enabled, feature(f128))] diff --git a/compiler-builtins/builtins-test/tests/conv.rs b/compiler-builtins/builtins-test/tests/conv.rs index 9b04295d2efe8..0fd15ad3ee662 100644 --- a/compiler-builtins/builtins-test/tests/conv.rs +++ b/compiler-builtins/builtins-test/tests/conv.rs @@ -1,8 +1,9 @@ #![cfg_attr(f128_enabled, feature(f128))] #![cfg_attr(f16_enabled, feature(f16))] // makes configuration easier -#![allow(unused_macros)] +#![allow(unused_features)] #![allow(unused_imports)] +#![allow(unused_macros)] use builtins_test::*; use compiler_builtins::float::Float; diff --git a/compiler-builtins/builtins-test/tests/div_rem.rs b/compiler-builtins/builtins-test/tests/div_rem.rs index caee4166c9958..4ff86385a9630 100644 --- a/compiler-builtins/builtins-test/tests/div_rem.rs +++ b/compiler-builtins/builtins-test/tests/div_rem.rs @@ -1,5 +1,5 @@ #![feature(f128)] -#![allow(unused_macros)] +#![allow(unused_macros, unused_features)] use builtins_test::*; use compiler_builtins::int::sdiv::{__divmoddi4, __divmodsi4, __divmodti4}; diff --git a/compiler-builtins/builtins-test/tests/float_pow.rs b/compiler-builtins/builtins-test/tests/float_pow.rs index a17dff27c105a..3cea83a255c8c 100644 --- a/compiler-builtins/builtins-test/tests/float_pow.rs +++ b/compiler-builtins/builtins-test/tests/float_pow.rs @@ -1,4 +1,4 @@ -#![allow(unused_macros)] +#![allow(unused_macros, unused_features)] #![cfg_attr(f128_enabled, feature(f128))] #[cfg_attr(x86_no_sse, allow(unused))] diff --git a/compiler-builtins/builtins-test/tests/lse.rs b/compiler-builtins/builtins-test/tests/lse.rs index 56891be8a8ac1..d408fe193bcff 100644 --- a/compiler-builtins/builtins-test/tests/lse.rs +++ b/compiler-builtins/builtins-test/tests/lse.rs @@ -1,30 +1,71 @@ +#![allow(unused_features)] #![feature(decl_macro)] // so we can use pub(super) #![feature(macro_metavar_expr_concat)] -#![cfg(all(target_arch = "aarch64", target_os = "linux"))] +#![cfg(all(target_arch = "aarch64", feature = "mangled-names"))] + +use std::sync::Mutex; + +use compiler_builtins::aarch64_outline_atomics::{get_have_lse_atomics, set_have_lse_atomics}; +use compiler_builtins::int::{Int, MinInt}; +use compiler_builtins::{foreach_bytes, foreach_ordering}; + +#[track_caller] +fn with_maybe_lse_atomics(use_lse: bool, f: impl FnOnce()) { + // Ensure tests run in parallel don't interleave global settings + static LOCK: Mutex<()> = Mutex::new(()); + let _g = LOCK.lock().unwrap(); + let old = get_have_lse_atomics(); + // safety: as the caller of the unsafe fn `set_have_lse_atomics`, we + // have to ensure the CPU supports LSE. This is why we make this assertion. + if use_lse || old { + assert!(std::arch::is_aarch64_feature_detected!("lse")); + } + unsafe { set_have_lse_atomics(use_lse) }; + f(); + unsafe { set_have_lse_atomics(old) }; +} + +pub fn run_fuzz_tests_with_lse_variants(n: u32, f: F) +where + ::Unsigned: Int, +{ + // We use `fuzz_2` because our subject function `f` requires two inputs + let test_fn = || { + builtins_test::fuzz_2(n, f); + }; + // Always run without LSE + with_maybe_lse_atomics(false, test_fn); + + // Conditionally run with LSE + if std::arch::is_aarch64_feature_detected!("lse") { + with_maybe_lse_atomics(true, test_fn); + } +} /// Translate a byte size to a Rust type. macro int_ty { - (1) => { i8 }, - (2) => { i16 }, - (4) => { i32 }, - (8) => { i64 }, - (16) => { i128 } + (1) => { u8 }, + (2) => { u16 }, + (4) => { u32 }, + (8) => { u64 }, + (16) => { u128 } } mod cas { pub(super) macro test($_ordering:ident, $bytes:tt, $name:ident) { #[test] fn $name() { - builtins_test::fuzz_2(10000, |expected: super::int_ty!($bytes), new| { + crate::run_fuzz_tests_with_lse_variants(10000, |expected: super::int_ty!($bytes), new| { let mut target = expected.wrapping_add(10); + let ret: super::int_ty!($bytes) = unsafe { + compiler_builtins::aarch64_outline_atomics::$name::$name( + expected, + new, + &mut target, + ) + }; assert_eq!( - unsafe { - compiler_builtins::aarch64_outline_atomics::$name::$name( - expected, - new, - &mut target, - ) - }, + ret, expected.wrapping_add(10), "return value should always be the previous value", ); @@ -35,15 +76,17 @@ mod cas { ); target = expected; + let ret: super::int_ty!($bytes) = unsafe { + compiler_builtins::aarch64_outline_atomics::$name::$name( + expected, + new, + &mut target, + ) + }; assert_eq!( - unsafe { - compiler_builtins::aarch64_outline_atomics::$name::$name( - expected, - new, - &mut target, - ) - }, - expected + ret, + expected, + "the new return value should always be the previous value (i.e. the first parameter passed to the function)", ); assert_eq!(target, new, "should have updated target"); }); @@ -59,16 +102,21 @@ mod swap { pub(super) macro test($_ordering:ident, $bytes:tt, $name:ident) { #[test] fn $name() { - builtins_test::fuzz_2(10000, |left: super::int_ty!($bytes), mut right| { - let orig_right = right; - assert_eq!( - unsafe { - compiler_builtins::aarch64_outline_atomics::$name::$name(left, &mut right) - }, - orig_right - ); - assert_eq!(left, right); - }); + crate::run_fuzz_tests_with_lse_variants( + 10000, + |left: super::int_ty!($bytes), mut right| { + let orig_right = right; + assert_eq!( + unsafe { + compiler_builtins::aarch64_outline_atomics::$name::$name( + left, &mut right, + ) + }, + orig_right + ); + assert_eq!(left, right); + }, + ); } } } @@ -80,7 +128,7 @@ macro_rules! test_op { ($_ordering:ident, $bytes:tt, $name:ident) => { #[test] fn $name() { - builtins_test::fuzz_2(10000, |old, val| { + crate::run_fuzz_tests_with_lse_variants(10000, |old, val| { let mut target = old; let op: fn(super::int_ty!($bytes), super::int_ty!($bytes)) -> _ = $($op)*; let expected = op(old, val); @@ -98,7 +146,6 @@ test_op!(add, |left, right| left.wrapping_add(right)); test_op!(clr, |left, right| left & !right); test_op!(xor, std::ops::BitXor::bitxor); test_op!(or, std::ops::BitOr::bitor); -use compiler_builtins::{foreach_bytes, foreach_ordering}; compiler_builtins::foreach_cas!(cas::test); compiler_builtins::foreach_cas16!(test_cas16); compiler_builtins::foreach_swp!(swap::test); diff --git a/compiler-builtins/builtins-test/tests/mul.rs b/compiler-builtins/builtins-test/tests/mul.rs index bbf1157db42f9..30516ebaf7866 100644 --- a/compiler-builtins/builtins-test/tests/mul.rs +++ b/compiler-builtins/builtins-test/tests/mul.rs @@ -1,6 +1,6 @@ #![cfg_attr(f16_enabled, feature(f16))] #![cfg_attr(f128_enabled, feature(f128))] -#![allow(unused_macros)] +#![allow(unused_macros, unused_features)] use builtins_test::*; diff --git a/compiler-builtins/ci/bench-runtime.sh b/compiler-builtins/ci/bench-walltime.sh similarity index 77% rename from compiler-builtins/ci/bench-runtime.sh rename to compiler-builtins/ci/bench-walltime.sh index d272cf33463ed..0393d02dfc452 100755 --- a/compiler-builtins/ci/bench-runtime.sh +++ b/compiler-builtins/ci/bench-walltime.sh @@ -6,4 +6,4 @@ export LIBM_SEED=benchesbenchesbenchesbencheswoo! cargo bench --package libm-test \ --no-default-features \ - --features short-benchmarks,build-musl,libm/force-soft-floats + --features walltime,short-benchmarks,build-musl,libm/force-soft-floats diff --git a/compiler-builtins/ci/ci-util.py b/compiler-builtins/ci/ci-util.py index ef9ce455178ec..392f83c219e7a 100755 --- a/compiler-builtins/ci/ci-util.py +++ b/compiler-builtins/ci/ci-util.py @@ -11,7 +11,7 @@ import re import subprocess as sp import sys -from dataclasses import dataclass +from dataclasses import dataclass, field from functools import cache from glob import glob from inspect import cleandoc @@ -19,8 +19,7 @@ from pathlib import Path from typing import TypedDict, Self -USAGE = cleandoc( - """ +USAGE = cleandoc(""" usage: ./ci/ci-util.py [flags] @@ -44,8 +43,7 @@ Exit with success if the pull request contains a line starting with `ci: allow-regressions`, indicating that regressions in benchmarks should be accepted. Otherwise, exit 1. - """ -) + """) REPO_ROOT = Path(__file__).parent.parent GIT = ["git", "-C", REPO_ROOT] @@ -73,17 +71,21 @@ def eprint(*args, **kwargs): print(*args, file=sys.stderr, **kwargs) -@dataclass(init=False) +@dataclass(kw_only=True) class PrCfg: """Directives that we allow in the commit body to control test behavior. These are of the form `ci: foo`, at the start of a line. """ + # The PR body + body: str # Skip regression checks (must be at the start of a line). allow_regressions: bool = False # Don't run extensive tests skip_extensive: bool = False + # Add these extensive tests to the list + extra_extensive: list[str] = field(default_factory=list, init=False) # Allow running a large number of extensive tests. If not set, this script # will error out if a threshold is exceeded in order to avoid accidentally @@ -101,11 +103,17 @@ class PrCfg: DIR_SKIP_EXTENSIVE: str = "skip-extensive" DIR_ALLOW_MANY_EXTENSIVE: str = "allow-many-extensive" DIR_TEST_LIBM: str = "test-libm" + DIR_EXTRA_EXTENSIVE: str = "extra-extensive" - def __init__(self, body: str): - directives = re.finditer(r"^\s*ci:\s*(?P\S*)", body, re.MULTILINE) + def __post_init__(self): + directives = re.finditer( + r"^\s*ci:\s*(?P[^\s=]*)(?:\s*=\s*(?P.*))?", + self.body, + re.MULTILINE, + ) for dir in directives: name = dir.group("dir_name") + args = dir.group("args") if name == self.DIR_ALLOW_REGRESSIONS: self.allow_regressions = True elif name == self.DIR_SKIP_EXTENSIVE: @@ -114,11 +122,18 @@ def __init__(self, body: str): self.allow_many_extensive = True elif name == self.DIR_TEST_LIBM: self.always_test_libm = True + elif name == self.DIR_EXTRA_EXTENSIVE: + self.extra_extensive = [x.strip() for x in args.split(",")] + args = None else: eprint(f"Found unexpected directive `{name}`") exit(1) - pprint.pp(self) + if args is not None: + eprint("Found arguments where not expected") + exit(1) + + eprint(pprint.pformat(self)) @dataclass @@ -158,7 +173,7 @@ def from_pr(cls, pr_number: int | str) -> Self: ) pr_json = json.loads(pr_info) eprint("PR info:", json.dumps(pr_json, indent=4)) - return cls(**json.loads(pr_info), cfg=PrCfg(pr_json["body"])) + return cls(**pr_json, cfg=PrCfg(body=pr_json["body"])) class FunctionDef(TypedDict): @@ -276,29 +291,35 @@ def emit_workflow_output(self): skip_tests = False error_on_many_tests = False + extra_tests = {} pr = PrInfo.from_env() if pr is not None: skip_tests = pr.cfg.skip_extensive error_on_many_tests = not pr.cfg.allow_many_extensive + for fn_name in pr.cfg.extra_extensive: + extra_tests.setdefault(base_name(fn_name)[1], []).append(fn_name) if skip_tests: eprint("Skipping all extensive tests") changed = self.changed_routines() + eprint(f"Changed: {changed}") + matrix = [] total_to_test = 0 # Figure out which extensive tests need to run for ty in TYPES: ty_changed = changed.get(ty, []) - ty_to_test = [] if skip_tests else ty_changed + ty_to_test = [] if skip_tests else ty_changed.copy() + ty_to_test.extend(extra_tests.get(ty, [])) total_to_test += len(ty_to_test) item = { "ty": ty, - "changed": ",".join(ty_changed), - "to_test": ",".join(ty_to_test), + "changed": ",".join(sorted(set(ty_changed))), + "to_test": ",".join(sorted(set(ty_to_test))), } matrix.append(item) @@ -319,6 +340,33 @@ def emit_workflow_output(self): exit(1) +def base_name(name: str) -> tuple[str, str]: + """Return the basename and type from a full function name. Keep in sync with Rust's + `fn base_name`. + """ + known_mappings = [ + ("erff", ("erf", "f32")), + ("erf", ("erf", "f64")), + ("modff", ("modf", "f32")), + ("modf", ("modf", "f64")), + ("lgammaf_r", ("lgamma_r", "f32")), + ("lgamma_r", ("lgamma_r", "f64")), + ] + + found = next((base for (full, base) in known_mappings if full == name), None) + if found is not None: + return found + + if name.endswith("f"): + return (name.rstrip("f"), "f32") + elif name.endswith("f16"): + return (name.rstrip("f16"), "f16") + elif name.endswith("f128"): + return (name.rstrip("f128"), "f128") + + return (name, "f64") + + def locate_baseline(flags: list[str]) -> None: """Find the most recent baseline from CI, download it if specified. diff --git a/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile index 69b99f5b6b328..683bd07fd47ef 100644 --- a/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ gcc-aarch64-linux-gnu m4 make libc6-dev-arm64-cross \ - qemu-user-static + qemu-user ENV TOOLCHAIN_PREFIX=aarch64-linux-gnu- ENV CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER=qemu-aarch64-static \ + CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER=qemu-aarch64 \ AR_aarch64_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_aarch64_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/aarch64-linux-gnu \ diff --git a/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile b/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile index 2fa6f85205206..781abd1b6e888 100644 --- a/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile +++ b/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile @@ -1,14 +1,14 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ - gcc-arm-linux-gnueabi libc6-dev-armel-cross qemu-user-static + gcc-arm-linux-gnueabi libc6-dev-armel-cross qemu-user ENV TOOLCHAIN_PREFIX=arm-linux-gnueabi- ENV CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABI_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABI_RUNNER=qemu-arm-static \ + CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABI_RUNNER=qemu-arm \ AR_arm_unknown_linux_gnueabi="$TOOLCHAIN_PREFIX"ar \ CC_arm_unknown_linux_gnueabi="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/arm-linux-gnueabi \ diff --git a/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile b/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile index 85f7335f5a85b..36ea4827dc52f 100644 --- a/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile +++ b/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile @@ -1,14 +1,14 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ - gcc-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user-static + gcc-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user ENV TOOLCHAIN_PREFIX=arm-linux-gnueabihf- ENV CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_RUNNER=qemu-arm-static \ + CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_RUNNER=qemu-arm \ AR_arm_unknown_linux_gnueabihf="$TOOLCHAIN_PREFIX"ar \ CC_arm_unknown_linux_gnueabihf="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/arm-linux-gnueabihf \ diff --git a/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile b/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile index 42511479f36ff..8b76693b2799e 100644 --- a/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile +++ b/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile @@ -1,14 +1,14 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ - gcc-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user-static + gcc-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user ENV TOOLCHAIN_PREFIX=arm-linux-gnueabihf- ENV CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER=qemu-arm-static \ + CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER=qemu-arm \ AR_armv7_unknown_linux_gnueabihf="$TOOLCHAIN_PREFIX"ar \ CC_armv7_unknown_linux_gnueabihf="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/arm-linux-gnueabihf \ diff --git a/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile index 35488c4774933..9125038acbde5 100644 --- a/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile index 35488c4774933..9125038acbde5 100644 --- a/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile index e95a1b9163ff9..a652235958777 100644 --- a/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile @@ -1,13 +1,13 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ - gcc libc6-dev qemu-user-static ca-certificates \ + gcc libc6-dev qemu-user ca-certificates \ gcc-14-loongarch64-linux-gnu libc6-dev-loong64-cross ENV CARGO_TARGET_LOONGARCH64_UNKNOWN_LINUX_GNU_LINKER=loongarch64-linux-gnu-gcc-14 \ - CARGO_TARGET_LOONGARCH64_UNKNOWN_LINUX_GNU_RUNNER=qemu-loongarch64-static \ + CARGO_TARGET_LOONGARCH64_UNKNOWN_LINUX_GNU_RUNNER=qemu-loongarch64 \ AR_loongarch64_unknown_linux_gnu=loongarch64-linux-gnu-ar \ CC_loongarch64_unknown_linux_gnu=loongarch64-linux-gnu-gcc-14 \ QEMU_LD_PREFIX=/usr/loongarch64-linux-gnu \ diff --git a/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile index fd1877603100a..0913f33c05ce4 100644 --- a/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ gcc-mips-linux-gnu libc6-dev-mips-cross \ - binfmt-support qemu-user-static qemu-system-mips + binfmt-support qemu-user qemu-system-mips ENV TOOLCHAIN_PREFIX=mips-linux-gnu- ENV CARGO_TARGET_MIPS_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_MIPS_UNKNOWN_LINUX_GNU_RUNNER=qemu-mips-static \ + CARGO_TARGET_MIPS_UNKNOWN_LINUX_GNU_RUNNER=qemu-mips \ AR_mips_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_mips_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/mips-linux-gnu \ diff --git a/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile b/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile index 4e542ce6858c3..d2f4e484b1aab 100644 --- a/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile +++ b/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ @@ -8,12 +8,12 @@ RUN apt-get update && \ gcc-mips64-linux-gnuabi64 \ libc6-dev \ libc6-dev-mips64-cross \ - qemu-user-static \ + qemu-user \ qemu-system-mips ENV TOOLCHAIN_PREFIX=mips64-linux-gnuabi64- ENV CARGO_TARGET_MIPS64_UNKNOWN_LINUX_GNUABI64_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_MIPS64_UNKNOWN_LINUX_GNUABI64_RUNNER=qemu-mips64-static \ + CARGO_TARGET_MIPS64_UNKNOWN_LINUX_GNUABI64_RUNNER=qemu-mips64 \ AR_mips64_unknown_linux_gnuabi64="$TOOLCHAIN_PREFIX"ar \ CC_mips64_unknown_linux_gnuabi64="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/mips64-linux-gnuabi64 \ diff --git a/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile b/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile index 528dfd8940d5e..873754b2793e9 100644 --- a/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile +++ b/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ @@ -8,11 +8,11 @@ RUN apt-get update && \ gcc-mips64el-linux-gnuabi64 \ libc6-dev \ libc6-dev-mips64el-cross \ - qemu-user-static + qemu-user ENV TOOLCHAIN_PREFIX=mips64el-linux-gnuabi64- ENV CARGO_TARGET_MIPS64EL_UNKNOWN_LINUX_GNUABI64_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_MIPS64EL_UNKNOWN_LINUX_GNUABI64_RUNNER=qemu-mips64el-static \ + CARGO_TARGET_MIPS64EL_UNKNOWN_LINUX_GNUABI64_RUNNER=qemu-mips64el \ AR_mips64el_unknown_linux_gnuabi64="$TOOLCHAIN_PREFIX"ar \ CC_mips64el_unknown_linux_gnuabi64="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/mips64el-linux-gnuabi64 \ diff --git a/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile index 2572180238e23..5768b68d6c950 100644 --- a/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ gcc-mipsel-linux-gnu libc6-dev-mipsel-cross \ - binfmt-support qemu-user-static + binfmt-support qemu-user ENV TOOLCHAIN_PREFIX=mipsel-linux-gnu- ENV CARGO_TARGET_MIPSEL_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_MIPSEL_UNKNOWN_LINUX_GNU_RUNNER=qemu-mipsel-static \ + CARGO_TARGET_MIPSEL_UNKNOWN_LINUX_GNU_RUNNER=qemu-mipsel \ AR_mipsel_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_mipsel_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/mipsel-linux-gnu \ diff --git a/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile index cac1f23610aa9..c625a4bcd5d7c 100644 --- a/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ - gcc libc6-dev qemu-user-static ca-certificates \ + gcc libc6-dev qemu-user ca-certificates \ gcc-powerpc-linux-gnu libc6-dev-powerpc-cross \ qemu-system-ppc ENV TOOLCHAIN_PREFIX=powerpc-linux-gnu- ENV CARGO_TARGET_POWERPC_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_POWERPC_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc-static \ + CARGO_TARGET_POWERPC_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc \ AR_powerpc_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_powerpc_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/powerpc-linux-gnu \ diff --git a/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile index 76127b7dbb8c1..86a7a8cd46e4e 100644 --- a/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ gcc-powerpc64-linux-gnu libc6-dev-ppc64-cross \ - binfmt-support qemu-user-static qemu-system-ppc + binfmt-support qemu-user qemu-system-ppc ENV TOOLCHAIN_PREFIX=powerpc64-linux-gnu- ENV CARGO_TARGET_POWERPC64_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_POWERPC64_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc64-static \ + CARGO_TARGET_POWERPC64_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc64 \ AR_powerpc64_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_powerpc64_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/powerpc64-linux-gnu \ diff --git a/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile index da1d56ca66f27..722b10b0a7349 100644 --- a/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ - gcc libc6-dev qemu-user-static ca-certificates \ + gcc libc6-dev qemu-user ca-certificates \ gcc-powerpc64le-linux-gnu libc6-dev-ppc64el-cross \ qemu-system-ppc ENV TOOLCHAIN_PREFIX=powerpc64le-linux-gnu- ENV CARGO_TARGET_POWERPC64LE_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_POWERPC64LE_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc64le-static \ + CARGO_TARGET_POWERPC64LE_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc64le \ AR_powerpc64le_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_powerpc64le_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/powerpc64le-linux-gnu \ diff --git a/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile index 513efacd6d968..7a721ba05416e 100644 --- a/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ - gcc libc6-dev qemu-user-static ca-certificates \ + gcc libc6-dev qemu-user ca-certificates \ gcc-riscv64-linux-gnu libc6-dev-riscv64-cross \ qemu-system-riscv64 ENV TOOLCHAIN_PREFIX=riscv64-linux-gnu- ENV CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_RUNNER=qemu-riscv64-static \ + CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_RUNNER=qemu-riscv64 \ AR_riscv64gc_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_riscv64gc_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/riscv64-linux-gnu \ diff --git a/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile b/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile index a9a172a21137d..a1a6b3cf5cfd2 100644 --- a/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile +++ b/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile b/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile index a9a172a21137d..a1a6b3cf5cfd2 100644 --- a/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile +++ b/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile b/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile index a9a172a21137d..a1a6b3cf5cfd2 100644 --- a/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile +++ b/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile b/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile index a9a172a21137d..a1a6b3cf5cfd2 100644 --- a/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile +++ b/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile b/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile index 2813d318670ea..b646a72bb37cc 100644 --- a/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile +++ b/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:20.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile index 2ef800129d675..927515f90f329 100644 --- a/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/miri.sh b/compiler-builtins/ci/miri.sh index 7b0ea44c690f3..aae474d884638 100755 --- a/compiler-builtins/ci/miri.sh +++ b/compiler-builtins/ci/miri.sh @@ -14,5 +14,9 @@ targets=( ) for target in "${targets[@]}"; do # Only run the `mem` tests to avoid this taking too long. - cargo miri test --manifest-path builtins-test/Cargo.toml --features no-asm --target "$target" -- mem + cargo miri test \ + --manifest-path builtins-test/Cargo.toml \ + --features no-asm \ + --target "$target" \ + -- mem done diff --git a/compiler-builtins/ci/run-docker.sh b/compiler-builtins/ci/run-docker.sh index 4c1fe0fe26445..e65ada271904f 100755 --- a/compiler-builtins/ci/run-docker.sh +++ b/compiler-builtins/ci/run-docker.sh @@ -97,7 +97,7 @@ if [ "${1:-}" = "--help" ] || [ "$#" -gt 1 ]; then usage: ./ci/run-docker.sh [target] you can also set DOCKER_BASE_IMAGE to use something other than the default - ubuntu:25.04 (or rustlang/rust:nightly). + ubuntu:25.10 (or rustlang/rust:nightly). " exit fi diff --git a/compiler-builtins/ci/run.sh b/compiler-builtins/ci/run.sh index 0c07b32c74b93..b9a21d555c9e5 100755 --- a/compiler-builtins/ci/run.sh +++ b/compiler-builtins/ci/run.sh @@ -13,11 +13,6 @@ if [ -z "$target" ]; then target="$host_target" fi -if [[ "$target" = *"wasm"* ]]; then - # Enable the random backend - export RUSTFLAGS="${RUSTFLAGS:-} --cfg getrandom_backend=\"wasm_js\"" -fi - if [ "${USING_CONTAINER_RUSTC:-}" = 1 ]; then # Install nonstandard components if we have control of the environment rustup target list --installed | @@ -51,23 +46,26 @@ fi # Ensure there are no duplicate symbols or references to `core` when # `compiler-builtins` is built with various features. Symcheck invokes Cargo to # build with the arguments we provide it, then validates the built artifacts. +SYMCHECK_TEST_TARGET="$target" cargo test -p symbol-check --release symcheck=(cargo run -p symbol-check --release) -[[ "$target" = "wasm"* ]] && symcheck+=(--features wasm) -symcheck+=(-- build-and-check) +symcheck+=(-- --build-and-check --target "$target") + +# Executable section checks are meaningless on no-std targets +[[ "$target" == *"-none"* ]] && symcheck+=(--no-os) -"${symcheck[@]}" "$target" -- -p compiler_builtins -"${symcheck[@]}" "$target" -- -p compiler_builtins --release -"${symcheck[@]}" "$target" -- -p compiler_builtins --features c -"${symcheck[@]}" "$target" -- -p compiler_builtins --features c --release -"${symcheck[@]}" "$target" -- -p compiler_builtins --features no-asm -"${symcheck[@]}" "$target" -- -p compiler_builtins --features no-asm --release +"${symcheck[@]}" -- -p compiler_builtins +"${symcheck[@]}" -- -p compiler_builtins --release +"${symcheck[@]}" -- -p compiler_builtins --features c +"${symcheck[@]}" -- -p compiler_builtins --features c --release +"${symcheck[@]}" -- -p compiler_builtins --features no-asm +"${symcheck[@]}" -- -p compiler_builtins --features no-asm --release run_intrinsics_test() { build_args=(--verbose --manifest-path builtins-test-intrinsics/Cargo.toml) build_args+=("$@") # symcheck also checks the results of builtins-test-intrinsics - "${symcheck[@]}" "$target" -- "${build_args[@]}" + "${symcheck[@]}" -- "${build_args[@]}" # FIXME: we get access violations on Windows, our entrypoint may need to # be tweaked. @@ -157,7 +155,8 @@ if [ "${BUILD_ONLY:-}" = "1" ]; then echo "can't run tests on $target; skipping" else - mflags+=(--workspace --target "$target") + # symcheck tests need specific env setup, and is already tested above + mflags+=(--workspace --exclude symbol-check --target "$target") cmd=(cargo test "${mflags[@]}") profile_flag="--profile" diff --git a/compiler-builtins/compiler-builtins/Cargo.toml b/compiler-builtins/compiler-builtins/Cargo.toml index 496dde2d4cf25..d9acb8341d483 100644 --- a/compiler-builtins/compiler-builtins/Cargo.toml +++ b/compiler-builtins/compiler-builtins/Cargo.toml @@ -31,10 +31,10 @@ doc = false core = { path = "../../core", optional = true } [build-dependencies] -cc = { optional = true, version = "1.2" } +cc = { version = "1.2", optional = true } [features] -default = ["compiler-builtins"] +default = [] # Enable compilation of C code in compiler-rt, filling in some more optimized # implementations and also filling in unimplemented intrinsics @@ -45,8 +45,9 @@ c = ["dep:cc"] # the generic versions on all platforms. no-asm = [] -# Flag this library as the unstable compiler-builtins lib -compiler-builtins = [] +# Flag this library as the unstable compiler-builtins lib. This must be enabled +# when using as `std`'s dependency.' +compiler-builtins = ["dep:core"] # Generate memory-related intrinsics like memcpy mem = [] @@ -55,9 +56,6 @@ mem = [] # compiler-rt implementations. Also used for testing mangled-names = [] -# Only used in the compiler's build system -rustc-dep-of-std = ["compiler-builtins", "dep:core"] - # This makes certain traits and function specializations public that # are not normally public but are required by the `builtins-test` unstable-public-internals = [] diff --git a/compiler-builtins/compiler-builtins/README.md b/compiler-builtins/compiler-builtins/README.md index a12bd2ee73499..63cbf33d2aea2 100644 --- a/compiler-builtins/compiler-builtins/README.md +++ b/compiler-builtins/compiler-builtins/README.md @@ -22,7 +22,7 @@ See `build.rs` for details. ## Contributing -See [CONTRIBUTING.md](CONTRIBUTING.md). +See [CONTRIBUTING.md](../CONTRIBUTING.md). ## Progress diff --git a/compiler-builtins/compiler-builtins/src/aarch64.rs b/compiler-builtins/compiler-builtins/src/aarch64.rs index 1b230a214eefe..2c12cb7f3095b 100644 --- a/compiler-builtins/compiler-builtins/src/aarch64.rs +++ b/compiler-builtins/compiler-builtins/src/aarch64.rs @@ -1,7 +1,3 @@ -#![allow(unused_imports)] - -use core::intrinsics; - intrinsics! { #[unsafe(naked)] #[cfg(any(all(windows, target_env = "gnu"), target_os = "uefi"))] diff --git a/compiler-builtins/compiler-builtins/src/aarch64_outline_atomics.rs b/compiler-builtins/compiler-builtins/src/aarch64_outline_atomics.rs index df0cf76502223..100b67150772a 100644 --- a/compiler-builtins/compiler-builtins/src/aarch64_outline_atomics.rs +++ b/compiler-builtins/compiler-builtins/src/aarch64_outline_atomics.rs @@ -34,14 +34,27 @@ intrinsics! { } } +/// Function to enable/disable LSE. To be used only for testing purposes. +#[cfg(feature = "mangled-names")] +pub unsafe fn set_have_lse_atomics(has_lse: bool) { + let lse_flag = if has_lse { 1 } else { 0 }; + HAVE_LSE_ATOMICS.store(lse_flag, Ordering::Relaxed); +} + +/// Function to obtain whether LSE is enabled or not. To be used only for testing purposes. +#[cfg(feature = "mangled-names")] +pub fn get_have_lse_atomics() -> bool { + HAVE_LSE_ATOMICS.load(Ordering::Relaxed) != 0 +} + /// Translate a byte size to a Rust type. #[rustfmt::skip] macro_rules! int_ty { - (1) => { i8 }; - (2) => { i16 }; - (4) => { i32 }; - (8) => { i64 }; - (16) => { i128 }; + (1) => { u8 }; + (2) => { u16 }; + (4) => { u32 }; + (8) => { u64 }; + (16) => { u128 }; } /// Given a byte size and a register number, return a register of the appropriate size. @@ -135,18 +148,73 @@ macro_rules! stxp { }; } +// The AArch64 assembly syntax for relocation specifiers +// when accessing symbols changes depending on the target executable format. +// In ELF (used in Linux), we have a prefix notation surrounded by colons (:specifier:sym), +// while in Mach-O object files (used in MacOS), a postfix notation is used (sym@specifier). + +/// AArch64 ELF position-independent addressing: +/// +/// adrp xN, symbol +/// add xN, xN, :lo12:symbol +/// +/// The :lo12: modifier selects the low 12 bits of the symbol address +/// and emits an ELF relocation such as R_AARCH64_ADD_ABS_LO12_NC. +/// +/// Defined by the AArch64 ELF psABI. +/// See: . +#[cfg(not(target_vendor = "apple"))] +macro_rules! sym { + ($sym:literal) => { + $sym + }; +} + +#[cfg(not(target_vendor = "apple"))] +macro_rules! sym_off { + ($sym:literal) => { + concat!(":lo12:", $sym) + }; +} + +/// Mach-O ARM64 relocation types: +/// ARM64_RELOC_PAGE21 +/// ARM64_RELOC_PAGEOFF12 +/// +/// These relocations implement the @PAGE / @PAGEOFF split used by +/// adrp + add sequences on Apple platforms. +/// +/// adrp xN, symbol@PAGE -> ARM64_RELOC_PAGE21 +/// add xN, xN, symbol@PAGEOFF -> ARM64_RELOC_PAGEOFF12 +/// +/// Relocation types defined by Apple in XNU: . +/// See: . +#[cfg(target_vendor = "apple")] +macro_rules! sym { + ($sym:literal) => { + concat!($sym, "@PAGE") + }; +} + +#[cfg(target_vendor = "apple")] +macro_rules! sym_off { + ($sym:literal) => { + concat!($sym, "@PAGEOFF") + }; +} + // If supported, perform the requested LSE op and return, or fallthrough. macro_rules! try_lse_op { ($op: literal, $ordering:ident, $bytes:tt, $($reg:literal,)* [ $mem:ident ] ) => { concat!( - ".arch_extension lse; ", - "adrp x16, {have_lse}; ", - "ldrb w16, [x16, :lo12:{have_lse}]; ", - "cbz w16, 8f; ", + ".arch_extension lse\n", + concat!("adrp x16, ", sym!("{have_lse}"), "\n"), + concat!("ldrb w16, [x16, ", sym_off!("{have_lse}"), "]\n"), + "cbz w16, 8f\n", // LSE_OP s(reg),* [$mem] - concat!(lse!($op, $ordering, $bytes), $( " ", reg!($bytes, $reg), ", " ,)* "[", stringify!($mem), "]; ",), - "ret; ", - "8:" + concat!(lse!($op, $ordering, $bytes), $( " ", reg!($bytes, $reg), ", " ,)* "[", stringify!($mem), "]\n",), + "ret + 8:" ) }; } @@ -203,15 +271,15 @@ macro_rules! compare_and_swap { }; } -// i128 uses a completely different impl, so it has its own macro. -macro_rules! compare_and_swap_i128 { +// u128 uses a completely different impl, so it has its own macro. +macro_rules! compare_and_swap_u128 { ($ordering:ident, $name:ident) => { intrinsics! { #[maybe_use_optimized_c_shim] #[unsafe(naked)] pub unsafe extern "C" fn $name ( - expected: i128, desired: i128, ptr: *mut i128 - ) -> i128 { + expected: u128, desired: u128, ptr: *mut u128 + ) -> u128 { core::arch::naked_asm! { // CASP x0, x1, x2, x3, [x4]; if LSE supported. try_lse_op!("cas", $ordering, 16, 0, 1, 2, 3, [x4]), @@ -391,7 +459,7 @@ macro_rules! foreach_ldset { } foreach_cas!(compare_and_swap); -foreach_cas16!(compare_and_swap_i128); +foreach_cas16!(compare_and_swap_u128); foreach_swp!(swap); foreach_ldadd!(add); foreach_ldclr!(and); diff --git a/compiler-builtins/compiler-builtins/src/hexagon/dffma.s b/compiler-builtins/compiler-builtins/src/hexagon/dffma.s index 97d05eb1839ee..6cd1f1b79f87a 100644 --- a/compiler-builtins/compiler-builtins/src/hexagon/dffma.s +++ b/compiler-builtins/compiler-builtins/src/hexagon/dffma.s @@ -7,7 +7,7 @@ .p2align 5 __hexagon_fmadf4: __hexagon_fmadf5: -fma: +.Lfma: { p0 = dfclass(r1:0,#2) p0 = dfclass(r3:2,#2) @@ -400,7 +400,7 @@ fma: r3:2 = insert(r11:10,#63,#0) r1 -= asl(r28,#20) } - jump fma + jump .Lfma .Lfma_ab_tiny: r9:8 = combine(##0x00100000,#0) @@ -408,7 +408,7 @@ fma: r1:0 = insert(r9:8,#63,#0) r3:2 = insert(r9:8,#63,#0) } - jump fma + jump .Lfma .Lab_inf: { @@ -531,4 +531,3 @@ fma: r5 = insert(r28,#11,#20) jump .Lfma_abnormal_c_restart } -.size fma,.-fma diff --git a/compiler-builtins/compiler-builtins/src/lib.rs b/compiler-builtins/compiler-builtins/src/lib.rs index 342427aca9c7d..07960222f20f0 100644 --- a/compiler-builtins/compiler-builtins/src/lib.rs +++ b/compiler-builtins/compiler-builtins/src/lib.rs @@ -7,15 +7,14 @@ #![feature(compiler_builtins)] #![feature(core_intrinsics)] #![feature(linkage)] -#![feature(naked_functions)] #![feature(repr_simd)] #![feature(macro_metavar_expr_concat)] #![feature(rustc_attrs)] -#![feature(float_bits_const)] #![cfg_attr(f16_enabled, feature(f16))] #![cfg_attr(f128_enabled, feature(f128))] #![no_builtins] #![no_std] +#![allow(unstable_name_collisions)] // FIXME(float_bits_const): remove when stable #![allow(unused_features)] #![allow(internal_features)] // `mem::swap` cannot be used because it may generate references to memcpy in unoptimized code. @@ -46,6 +45,7 @@ pub mod float; pub mod int; pub mod math; pub mod mem; +pub mod sync; // `libm` expects its `support` module to be available in the crate root. use math::libm_math::support; @@ -56,15 +56,13 @@ pub mod arm; #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] pub mod aarch64; -#[cfg(all(target_arch = "aarch64", target_feature = "outline-atomics"))] -pub mod aarch64_outline_atomics; - +// Note that we enable the module on "mangled-names" because that is the default feature +// in the builtins-test tests. So this is a way of enabling the module during testing. #[cfg(all( - kernel_user_helpers, - any(target_os = "linux", target_os = "android"), - target_arch = "arm" + target_arch = "aarch64", + any(target_feature = "outline-atomics", feature = "mangled-names") ))] -pub mod arm_linux; +pub mod aarch64_outline_atomics; #[cfg(target_arch = "avr")] pub mod avr; diff --git a/compiler-builtins/compiler-builtins/src/math/mod.rs b/compiler-builtins/compiler-builtins/src/math/mod.rs index 62d7296741057..61dfad213cbe3 100644 --- a/compiler-builtins/compiler-builtins/src/math/mod.rs +++ b/compiler-builtins/compiler-builtins/src/math/mod.rs @@ -28,8 +28,10 @@ pub mod full_availability { fn fdimf16(x: f16, y: f16) -> f16; fn floorf16(x: f16) -> f16; fn fmaxf16(x: f16, y: f16) -> f16; + fn fmaximum_numf16(x: f16, y: f16) -> f16; fn fmaximumf16(x: f16, y: f16) -> f16; fn fminf16(x: f16, y: f16) -> f16; + fn fminimum_numf16(x: f16, y: f16) -> f16; fn fminimumf16(x: f16, y: f16) -> f16; fn fmodf16(x: f16, y: f16) -> f16; fn rintf16(x: f16) -> f16; @@ -81,8 +83,12 @@ pub mod full_availability { // however, so we still provide a fallback. libm_intrinsics! { fn fmaximum(x: f64, y: f64) -> f64; + fn fmaximum_num(x: f64, y: f64) -> f64; + fn fmaximum_numf(x: f32, y: f32) -> f32; fn fmaximumf(x: f32, y: f32) -> f32; fn fminimum(x: f64, y: f64) -> f64; + fn fminimum_num(x: f64, y: f64) -> f64; + fn fminimum_numf(x: f32, y: f32) -> f32; fn fminimumf(x: f32, y: f32) -> f32; fn roundeven(x: f64) -> f64; fn roundevenf(x: f32) -> f32; @@ -97,8 +103,10 @@ pub mod full_availability { fn floorf128(x: f128) -> f128; fn fmaf128(x: f128, y: f128, z: f128) -> f128; fn fmaxf128(x: f128, y: f128) -> f128; + fn fmaximum_numf128(x: f128, y: f128) -> f128; fn fmaximumf128(x: f128, y: f128) -> f128; fn fminf128(x: f128, y: f128) -> f128; + fn fminimum_numf128(x: f128, y: f128) -> f128; fn fminimumf128(x: f128, y: f128) -> f128; fn fmodf128(x: f128, y: f128) -> f128; fn rintf128(x: f128) -> f128; diff --git a/compiler-builtins/compiler-builtins/src/mem/impls.rs b/compiler-builtins/compiler-builtins/src/mem/impls.rs index da16dee25ce54..9681f5d6dac6e 100644 --- a/compiler-builtins/compiler-builtins/src/mem/impls.rs +++ b/compiler-builtins/compiler-builtins/src/mem/impls.rs @@ -16,7 +16,8 @@ // crate doing wrapping pointer arithmetic with a method that must not wrap won't be the problem if // something does go wrong at runtime. use core::ffi::c_int; -use core::intrinsics::likely; + +use crate::support::cold_path; const WORD_SIZE: usize = core::mem::size_of::(); const WORD_MASK: usize = WORD_SIZE - 1; @@ -209,9 +210,10 @@ pub unsafe fn copy_forward(mut dest: *mut u8, mut src: *const u8, mut n: usize) let n_words = n & !WORD_MASK; let src_misalignment = src as usize & WORD_MASK; - if likely(src_misalignment == 0) { + if src_misalignment == 0 { copy_forward_aligned_words(dest, src, n_words); } else { + cold_path(); copy_forward_misaligned_words(dest, src, n_words); } dest = dest.wrapping_add(n_words); @@ -327,9 +329,10 @@ pub unsafe fn copy_backward(dest: *mut u8, src: *const u8, mut n: usize) { let n_words = n & !WORD_MASK; let src_misalignment = src as usize & WORD_MASK; - if likely(src_misalignment == 0) { + if src_misalignment == 0 { copy_backward_aligned_words(dest, src, n_words); } else { + cold_path(); copy_backward_misaligned_words(dest, src, n_words); } dest = dest.wrapping_sub(n_words); @@ -368,7 +371,7 @@ pub unsafe fn set_bytes(mut s: *mut u8, c: u8, mut n: usize) { } } - if likely(n >= WORD_COPY_THRESHOLD) { + if n >= WORD_COPY_THRESHOLD { // Align s // Because of n >= 2 * WORD_SIZE, dst_misalignment < n let misalignment = (s as usize).wrapping_neg() & WORD_MASK; @@ -380,6 +383,8 @@ pub unsafe fn set_bytes(mut s: *mut u8, c: u8, mut n: usize) { set_bytes_words(s, c, n_words); s = s.wrapping_add(n_words); n -= n_words; + } else { + cold_path(); } set_bytes_bytes(s, c, n); } diff --git a/compiler-builtins/compiler-builtins/src/arm_linux.rs b/compiler-builtins/compiler-builtins/src/sync/arm_linux.rs similarity index 59% rename from compiler-builtins/compiler-builtins/src/arm_linux.rs rename to compiler-builtins/compiler-builtins/src/sync/arm_linux.rs index ab9f868073908..7edd76c0b8b7c 100644 --- a/compiler-builtins/compiler-builtins/src/arm_linux.rs +++ b/compiler-builtins/compiler-builtins/src/sync/arm_linux.rs @@ -125,14 +125,16 @@ unsafe fn atomic_cmpxchg(ptr: *mut T, oldval: u32, newval: u32) -> u32 { let (shift, mask) = get_shift_mask(ptr); loop { - // FIXME(safety): preconditions review needed + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. let curval_aligned = unsafe { atomic_load_aligned::(aligned_ptr) }; let curval = extract_aligned(curval_aligned, shift, mask); if curval != oldval { return curval; } let newval_aligned = insert_aligned(curval_aligned, newval, shift, mask); - // FIXME(safety): preconditions review needed + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. if unsafe { __kuser_cmpxchg(curval_aligned, newval_aligned, aligned_ptr) } { return oldval; } @@ -143,7 +145,8 @@ macro_rules! atomic_rmw { ($name:ident, $ty:ty, $op:expr, $fetch:expr) => { intrinsics! { pub unsafe extern "C" fn $name(ptr: *mut $ty, val: $ty) -> $ty { - // FIXME(safety): preconditions review needed + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. unsafe { atomic_rmw( ptr, @@ -167,140 +170,15 @@ macro_rules! atomic_cmpxchg { ($name:ident, $ty:ty) => { intrinsics! { pub unsafe extern "C" fn $name(ptr: *mut $ty, oldval: $ty, newval: $ty) -> $ty { - // FIXME(safety): preconditions review needed + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. unsafe { atomic_cmpxchg(ptr, oldval as u32, newval as u32) as $ty } } } }; } -atomic_rmw!(@old __sync_fetch_and_add_1, u8, |a: u8, b: u8| a.wrapping_add(b)); -atomic_rmw!(@old __sync_fetch_and_add_2, u16, |a: u16, b: u16| a - .wrapping_add(b)); -atomic_rmw!(@old __sync_fetch_and_add_4, u32, |a: u32, b: u32| a - .wrapping_add(b)); - -atomic_rmw!(@new __sync_add_and_fetch_1, u8, |a: u8, b: u8| a.wrapping_add(b)); -atomic_rmw!(@new __sync_add_and_fetch_2, u16, |a: u16, b: u16| a - .wrapping_add(b)); -atomic_rmw!(@new __sync_add_and_fetch_4, u32, |a: u32, b: u32| a - .wrapping_add(b)); - -atomic_rmw!(@old __sync_fetch_and_sub_1, u8, |a: u8, b: u8| a.wrapping_sub(b)); -atomic_rmw!(@old __sync_fetch_and_sub_2, u16, |a: u16, b: u16| a - .wrapping_sub(b)); -atomic_rmw!(@old __sync_fetch_and_sub_4, u32, |a: u32, b: u32| a - .wrapping_sub(b)); - -atomic_rmw!(@new __sync_sub_and_fetch_1, u8, |a: u8, b: u8| a.wrapping_sub(b)); -atomic_rmw!(@new __sync_sub_and_fetch_2, u16, |a: u16, b: u16| a - .wrapping_sub(b)); -atomic_rmw!(@new __sync_sub_and_fetch_4, u32, |a: u32, b: u32| a - .wrapping_sub(b)); - -atomic_rmw!(@old __sync_fetch_and_and_1, u8, |a: u8, b: u8| a & b); -atomic_rmw!(@old __sync_fetch_and_and_2, u16, |a: u16, b: u16| a & b); -atomic_rmw!(@old __sync_fetch_and_and_4, u32, |a: u32, b: u32| a & b); - -atomic_rmw!(@new __sync_and_and_fetch_1, u8, |a: u8, b: u8| a & b); -atomic_rmw!(@new __sync_and_and_fetch_2, u16, |a: u16, b: u16| a & b); -atomic_rmw!(@new __sync_and_and_fetch_4, u32, |a: u32, b: u32| a & b); - -atomic_rmw!(@old __sync_fetch_and_or_1, u8, |a: u8, b: u8| a | b); -atomic_rmw!(@old __sync_fetch_and_or_2, u16, |a: u16, b: u16| a | b); -atomic_rmw!(@old __sync_fetch_and_or_4, u32, |a: u32, b: u32| a | b); - -atomic_rmw!(@new __sync_or_and_fetch_1, u8, |a: u8, b: u8| a | b); -atomic_rmw!(@new __sync_or_and_fetch_2, u16, |a: u16, b: u16| a | b); -atomic_rmw!(@new __sync_or_and_fetch_4, u32, |a: u32, b: u32| a | b); - -atomic_rmw!(@old __sync_fetch_and_xor_1, u8, |a: u8, b: u8| a ^ b); -atomic_rmw!(@old __sync_fetch_and_xor_2, u16, |a: u16, b: u16| a ^ b); -atomic_rmw!(@old __sync_fetch_and_xor_4, u32, |a: u32, b: u32| a ^ b); - -atomic_rmw!(@new __sync_xor_and_fetch_1, u8, |a: u8, b: u8| a ^ b); -atomic_rmw!(@new __sync_xor_and_fetch_2, u16, |a: u16, b: u16| a ^ b); -atomic_rmw!(@new __sync_xor_and_fetch_4, u32, |a: u32, b: u32| a ^ b); - -atomic_rmw!(@old __sync_fetch_and_nand_1, u8, |a: u8, b: u8| !(a & b)); -atomic_rmw!(@old __sync_fetch_and_nand_2, u16, |a: u16, b: u16| !(a & b)); -atomic_rmw!(@old __sync_fetch_and_nand_4, u32, |a: u32, b: u32| !(a & b)); - -atomic_rmw!(@new __sync_nand_and_fetch_1, u8, |a: u8, b: u8| !(a & b)); -atomic_rmw!(@new __sync_nand_and_fetch_2, u16, |a: u16, b: u16| !(a & b)); -atomic_rmw!(@new __sync_nand_and_fetch_4, u32, |a: u32, b: u32| !(a & b)); - -atomic_rmw!(@old __sync_fetch_and_max_1, i8, |a: i8, b: i8| if a > b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_max_2, i16, |a: i16, b: i16| if a > b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_max_4, i32, |a: i32, b: i32| if a > b { - a -} else { - b -}); - -atomic_rmw!(@old __sync_fetch_and_umax_1, u8, |a: u8, b: u8| if a > b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_umax_2, u16, |a: u16, b: u16| if a > b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_umax_4, u32, |a: u32, b: u32| if a > b { - a -} else { - b -}); - -atomic_rmw!(@old __sync_fetch_and_min_1, i8, |a: i8, b: i8| if a < b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_min_2, i16, |a: i16, b: i16| if a < b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_min_4, i32, |a: i32, b: i32| if a < b { - a -} else { - b -}); - -atomic_rmw!(@old __sync_fetch_and_umin_1, u8, |a: u8, b: u8| if a < b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_umin_2, u16, |a: u16, b: u16| if a < b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_umin_4, u32, |a: u32, b: u32| if a < b { - a -} else { - b -}); - -atomic_rmw!(@old __sync_lock_test_and_set_1, u8, |_: u8, b: u8| b); -atomic_rmw!(@old __sync_lock_test_and_set_2, u16, |_: u16, b: u16| b); -atomic_rmw!(@old __sync_lock_test_and_set_4, u32, |_: u32, b: u32| b); - -atomic_cmpxchg!(__sync_val_compare_and_swap_1, u8); -atomic_cmpxchg!(__sync_val_compare_and_swap_2, u16); -atomic_cmpxchg!(__sync_val_compare_and_swap_4, u32); +include!("arm_thumb_shared.rs"); intrinsics! { pub unsafe extern "C" fn __sync_synchronize() { diff --git a/compiler-builtins/compiler-builtins/src/sync/arm_thumb_shared.rs b/compiler-builtins/compiler-builtins/src/sync/arm_thumb_shared.rs new file mode 100644 index 0000000000000..812989c7bc85a --- /dev/null +++ b/compiler-builtins/compiler-builtins/src/sync/arm_thumb_shared.rs @@ -0,0 +1,134 @@ +// Used by both arm_linux.rs and thumbv6k.rs. + +// References: +// - https://llvm.org/docs/Atomics.html#libcalls-sync +// - https://gcc.gnu.org/onlinedocs/gcc/_005f_005fsync-Builtins.html +// - https://refspecs.linuxfoundation.org/elf/IA64-SysV-psABI.pdf#page=58 + +atomic_rmw!(@old __sync_fetch_and_add_1, u8, |a: u8, b: u8| a.wrapping_add(b)); +atomic_rmw!(@old __sync_fetch_and_add_2, u16, |a: u16, b: u16| a + .wrapping_add(b)); +atomic_rmw!(@old __sync_fetch_and_add_4, u32, |a: u32, b: u32| a + .wrapping_add(b)); + +atomic_rmw!(@new __sync_add_and_fetch_1, u8, |a: u8, b: u8| a.wrapping_add(b)); +atomic_rmw!(@new __sync_add_and_fetch_2, u16, |a: u16, b: u16| a + .wrapping_add(b)); +atomic_rmw!(@new __sync_add_and_fetch_4, u32, |a: u32, b: u32| a + .wrapping_add(b)); + +atomic_rmw!(@old __sync_fetch_and_sub_1, u8, |a: u8, b: u8| a.wrapping_sub(b)); +atomic_rmw!(@old __sync_fetch_and_sub_2, u16, |a: u16, b: u16| a + .wrapping_sub(b)); +atomic_rmw!(@old __sync_fetch_and_sub_4, u32, |a: u32, b: u32| a + .wrapping_sub(b)); + +atomic_rmw!(@new __sync_sub_and_fetch_1, u8, |a: u8, b: u8| a.wrapping_sub(b)); +atomic_rmw!(@new __sync_sub_and_fetch_2, u16, |a: u16, b: u16| a + .wrapping_sub(b)); +atomic_rmw!(@new __sync_sub_and_fetch_4, u32, |a: u32, b: u32| a + .wrapping_sub(b)); + +atomic_rmw!(@old __sync_fetch_and_and_1, u8, |a: u8, b: u8| a & b); +atomic_rmw!(@old __sync_fetch_and_and_2, u16, |a: u16, b: u16| a & b); +atomic_rmw!(@old __sync_fetch_and_and_4, u32, |a: u32, b: u32| a & b); + +atomic_rmw!(@new __sync_and_and_fetch_1, u8, |a: u8, b: u8| a & b); +atomic_rmw!(@new __sync_and_and_fetch_2, u16, |a: u16, b: u16| a & b); +atomic_rmw!(@new __sync_and_and_fetch_4, u32, |a: u32, b: u32| a & b); + +atomic_rmw!(@old __sync_fetch_and_or_1, u8, |a: u8, b: u8| a | b); +atomic_rmw!(@old __sync_fetch_and_or_2, u16, |a: u16, b: u16| a | b); +atomic_rmw!(@old __sync_fetch_and_or_4, u32, |a: u32, b: u32| a | b); + +atomic_rmw!(@new __sync_or_and_fetch_1, u8, |a: u8, b: u8| a | b); +atomic_rmw!(@new __sync_or_and_fetch_2, u16, |a: u16, b: u16| a | b); +atomic_rmw!(@new __sync_or_and_fetch_4, u32, |a: u32, b: u32| a | b); + +atomic_rmw!(@old __sync_fetch_and_xor_1, u8, |a: u8, b: u8| a ^ b); +atomic_rmw!(@old __sync_fetch_and_xor_2, u16, |a: u16, b: u16| a ^ b); +atomic_rmw!(@old __sync_fetch_and_xor_4, u32, |a: u32, b: u32| a ^ b); + +atomic_rmw!(@new __sync_xor_and_fetch_1, u8, |a: u8, b: u8| a ^ b); +atomic_rmw!(@new __sync_xor_and_fetch_2, u16, |a: u16, b: u16| a ^ b); +atomic_rmw!(@new __sync_xor_and_fetch_4, u32, |a: u32, b: u32| a ^ b); + +atomic_rmw!(@old __sync_fetch_and_nand_1, u8, |a: u8, b: u8| !(a & b)); +atomic_rmw!(@old __sync_fetch_and_nand_2, u16, |a: u16, b: u16| !(a & b)); +atomic_rmw!(@old __sync_fetch_and_nand_4, u32, |a: u32, b: u32| !(a & b)); + +atomic_rmw!(@new __sync_nand_and_fetch_1, u8, |a: u8, b: u8| !(a & b)); +atomic_rmw!(@new __sync_nand_and_fetch_2, u16, |a: u16, b: u16| !(a & b)); +atomic_rmw!(@new __sync_nand_and_fetch_4, u32, |a: u32, b: u32| !(a & b)); + +atomic_rmw!(@old __sync_fetch_and_max_1, i8, |a: i8, b: i8| if a > b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_max_2, i16, |a: i16, b: i16| if a > b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_max_4, i32, |a: i32, b: i32| if a > b { + a +} else { + b +}); + +atomic_rmw!(@old __sync_fetch_and_umax_1, u8, |a: u8, b: u8| if a > b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_umax_2, u16, |a: u16, b: u16| if a > b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_umax_4, u32, |a: u32, b: u32| if a > b { + a +} else { + b +}); + +atomic_rmw!(@old __sync_fetch_and_min_1, i8, |a: i8, b: i8| if a < b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_min_2, i16, |a: i16, b: i16| if a < b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_min_4, i32, |a: i32, b: i32| if a < b { + a +} else { + b +}); + +atomic_rmw!(@old __sync_fetch_and_umin_1, u8, |a: u8, b: u8| if a < b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_umin_2, u16, |a: u16, b: u16| if a < b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_umin_4, u32, |a: u32, b: u32| if a < b { + a +} else { + b +}); + +atomic_rmw!(@old __sync_lock_test_and_set_1, u8, |_: u8, b: u8| b); +atomic_rmw!(@old __sync_lock_test_and_set_2, u16, |_: u16, b: u16| b); +atomic_rmw!(@old __sync_lock_test_and_set_4, u32, |_: u32, b: u32| b); + +atomic_cmpxchg!(__sync_val_compare_and_swap_1, u8); +atomic_cmpxchg!(__sync_val_compare_and_swap_2, u16); +atomic_cmpxchg!(__sync_val_compare_and_swap_4, u32); diff --git a/compiler-builtins/compiler-builtins/src/sync/mod.rs b/compiler-builtins/compiler-builtins/src/sync/mod.rs new file mode 100644 index 0000000000000..590db14bb23b3 --- /dev/null +++ b/compiler-builtins/compiler-builtins/src/sync/mod.rs @@ -0,0 +1,20 @@ +#[cfg(all( + kernel_user_helpers, + any(target_os = "linux", target_os = "android"), + target_arch = "arm" +))] +pub mod arm_linux; + +// Armv6k supports atomic instructions, but they are unavailable in Thumb mode +// unless Thumb-2 instructions available (v6t2). +// Using Thumb interworking allows us to use these instructions even from Thumb mode +// without Thumb-2 instructions, but LLVM does not implement that processing (as of LLVM 21), +// so we implement it here at this time. +// (`not(target_feature = "mclass")` is unneeded because v6k is not set on thumbv6m.) +#[cfg(all( + target_arch = "arm", + target_feature = "thumb-mode", + target_feature = "v6k", + not(target_feature = "v6t2"), +))] +pub mod thumbv6k; diff --git a/compiler-builtins/compiler-builtins/src/sync/thumbv6k.rs b/compiler-builtins/compiler-builtins/src/sync/thumbv6k.rs new file mode 100644 index 0000000000000..c47b4c2ec6b00 --- /dev/null +++ b/compiler-builtins/compiler-builtins/src/sync/thumbv6k.rs @@ -0,0 +1,213 @@ +// Armv6k supports atomic instructions, but they are unavailable in Thumb mode +// unless Thumb-2 instructions available (v6t2). +// Using Thumb interworking allows us to use these instructions even from Thumb mode +// without Thumb-2 instructions, but LLVM does not implement that processing (as of LLVM 21), +// so we implement it here at this time. + +use core::arch::asm; +use core::mem; + +// Data Memory Barrier (DMB) operation. +// +// Armv6 does not support DMB instruction, so use use special instruction equivalent to it. +// +// Refs: https://developer.arm.com/documentation/ddi0360/f/control-coprocessor-cp15/register-descriptions/c7--cache-operations-register +macro_rules! cp15_barrier { + () => { + "mcr p15, #0, {zero}, c7, c10, #5" + }; +} + +#[instruction_set(arm::a32)] +unsafe fn fence() { + unsafe { + asm!( + cp15_barrier!(), + // cp15_barrier! calls `mcr p15, 0, {zero}, c7, c10, 5`, and + // the value in the {zero} register should be zero (SBZ). + zero = inout(reg) 0_u32 => _, + options(nostack, preserves_flags), + ); + } +} + +trait Atomic: Copy + Eq { + unsafe fn load_relaxed(src: *const Self) -> Self; + unsafe fn cmpxchg(dst: *mut Self, current: Self, new: Self) -> Self; +} + +macro_rules! atomic { + ($ty:ident, $suffix:tt) => { + impl Atomic for $ty { + // #[instruction_set(arm::a32)] is unneeded for ldr. + #[inline] + unsafe fn load_relaxed( + src: *const Self, + ) -> Self { + let out: Self; + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + unsafe { + asm!( + concat!("ldr", $suffix, " {out}, [{src}]"), // atomic { out = *src } + src = in(reg) src, + out = lateout(reg) out, + options(nostack, preserves_flags), + ); + } + out + } + #[inline] + #[instruction_set(arm::a32)] + unsafe fn cmpxchg( + dst: *mut Self, + old: Self, + new: Self, + ) -> Self { + let mut out: Self; + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + // + // Instead of the common `fence; ll/sc loop; fence` form, we use the form used by + // LLVM, which omits the preceding fence if no write operation is performed. + unsafe { + asm!( + concat!("ldrex", $suffix, " {out}, [{dst}]"), // atomic { out = *dst; EXCLUSIVE = dst } + "cmp {out}, {old}", // if out == old { Z = 1 } else { Z = 0 } + "bne 3f", // if Z == 0 { jump 'cmp-fail } + cp15_barrier!(), // fence + "2:", // 'retry: + concat!("strex", $suffix, " {r}, {new}, [{dst}]"), // atomic { if EXCLUSIVE == dst { *dst = new; r = 0 } else { r = 1 }; EXCLUSIVE = None } + "cmp {r}, #0", // if r == 0 { Z = 1 } else { Z = 0 } + "beq 3f", // if Z == 1 { jump 'success } + concat!("ldrex", $suffix, " {out}, [{dst}]"), // atomic { out = *dst; EXCLUSIVE = dst } + "cmp {out}, {old}", // if out == old { Z = 1 } else { Z = 0 } + "beq 2b", // if Z == 1 { jump 'retry } + "3:", // 'cmp-fail | 'success: + cp15_barrier!(), // fence + dst = in(reg) dst, + // Note: this cast must be a zero-extend since loaded value + // which compared to it is zero-extended. + old = in(reg) u32::from(old), + new = in(reg) new, + out = out(reg) out, + r = out(reg) _, + // cp15_barrier! calls `mcr p15, 0, {zero}, c7, c10, 5`, and + // the value in the {zero} register should be zero (SBZ). + zero = inout(reg) 0_u32 => _, + // Do not use `preserves_flags` because CMP modifies the condition flags. + options(nostack), + ); + out + } + } + } + }; +} +atomic!(u8, "b"); +atomic!(u16, "h"); +atomic!(u32, ""); + +// To avoid the annoyance of sign extension, we implement signed CAS using +// unsigned CAS. (See note in cmpxchg impl in atomic! macro) +macro_rules! delegate_signed { + ($ty:ident, $base:ident) => { + const _: () = { + assert!(mem::size_of::<$ty>() == mem::size_of::<$base>()); + assert!(mem::align_of::<$ty>() == mem::align_of::<$base>()); + }; + impl Atomic for $ty { + #[inline] + unsafe fn load_relaxed(src: *const Self) -> Self { + // SAFETY: the caller must uphold the safety contract. + // casts are okay because $ty and $base implement the same layout. + unsafe { <$base as Atomic>::load_relaxed(src.cast::<$base>()).cast_signed() } + } + #[inline] + unsafe fn cmpxchg(dst: *mut Self, old: Self, new: Self) -> Self { + // SAFETY: the caller must uphold the safety contract. + // casts are okay because $ty and $base implement the same layout. + unsafe { + <$base as Atomic>::cmpxchg( + dst.cast::<$base>(), + old.cast_unsigned(), + new.cast_unsigned(), + ) + .cast_signed() + } + } + } + }; +} +delegate_signed!(i8, u8); +delegate_signed!(i16, u16); +delegate_signed!(i32, u32); + +// Generic atomic read-modify-write operation +// +// We could implement RMW more efficiently as an assembly LL/SC loop per operation, +// but we won't do that for now because it would make the implementation more complex. +// +// We also do not implement LL and SC as separate functions. This is because it +// is theoretically possible for the compiler to insert operations that might +// clear the reservation between LL and SC. See https://github.com/taiki-e/portable-atomic/blob/58ef7f27c9e20da4cc1ef0abf8b8ce9ac5219ec3/src/imp/atomic128/aarch64.rs#L44-L55 +// for more details. +unsafe fn atomic_rmw T, G: Fn(T, T) -> T>(ptr: *mut T, f: F, g: G) -> T { + loop { + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + let curval = unsafe { T::load_relaxed(ptr) }; + let newval = f(curval); + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + if unsafe { T::cmpxchg(ptr, curval, newval) } == curval { + return g(curval, newval); + } + } +} + +macro_rules! atomic_rmw { + ($name:ident, $ty:ty, $op:expr, $fetch:expr) => { + intrinsics! { + pub unsafe extern "C" fn $name(ptr: *mut $ty, val: $ty) -> $ty { + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + unsafe { + atomic_rmw( + ptr, + |x| $op(x as $ty, val), + |old, new| $fetch(old, new) + ) as $ty + } + } + } + }; + + (@old $name:ident, $ty:ty, $op:expr) => { + atomic_rmw!($name, $ty, $op, |old, _| old); + }; + + (@new $name:ident, $ty:ty, $op:expr) => { + atomic_rmw!($name, $ty, $op, |_, new| new); + }; +} +macro_rules! atomic_cmpxchg { + ($name:ident, $ty:ty) => { + intrinsics! { + pub unsafe extern "C" fn $name(ptr: *mut $ty, oldval: $ty, newval: $ty) -> $ty { + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + unsafe { <$ty as Atomic>::cmpxchg(ptr, oldval, newval) } + } + } + }; +} + +include!("arm_thumb_shared.rs"); + +intrinsics! { + pub unsafe extern "C" fn __sync_synchronize() { + // SAFETY: preconditions are the same as the calling function. + unsafe { fence() }; + } +} diff --git a/compiler-builtins/compiler-builtins/src/x86.rs b/compiler-builtins/compiler-builtins/src/x86.rs index 1a3c418609451..45f4ba207e6e0 100644 --- a/compiler-builtins/compiler-builtins/src/x86.rs +++ b/compiler-builtins/compiler-builtins/src/x86.rs @@ -1,7 +1,3 @@ -#![allow(unused_imports)] - -use core::intrinsics; - // NOTE These functions are implemented using assembly because they use a custom // calling convention which can't be implemented using a normal Rust function diff --git a/compiler-builtins/compiler-builtins/src/x86_64.rs b/compiler-builtins/compiler-builtins/src/x86_64.rs index 99a527ee9ac5e..a3a5c8f7e10f9 100644 --- a/compiler-builtins/compiler-builtins/src/x86_64.rs +++ b/compiler-builtins/compiler-builtins/src/x86_64.rs @@ -1,7 +1,3 @@ -#![allow(unused_imports)] - -use core::intrinsics; - // NOTE These functions are implemented using assembly because they use a custom // calling convention which can't be implemented using a normal Rust function diff --git a/compiler-builtins/crates/libm-macros/Cargo.toml b/compiler-builtins/crates/libm-macros/Cargo.toml index 100a8d0ec30e4..f99a92e21c709 100644 --- a/compiler-builtins/crates/libm-macros/Cargo.toml +++ b/compiler-builtins/crates/libm-macros/Cargo.toml @@ -9,10 +9,10 @@ license = "MIT OR Apache-2.0" proc-macro = true [dependencies] -heck = "0.5.0" -proc-macro2 = "1.0.95" -quote = "1.0.40" -syn = { version = "2.0.104", features = ["full", "extra-traits", "visit-mut"] } +heck.workspace = true +proc-macro2.workspace = true +quote.workspace = true +syn = { workspace = true, features = ["full", "extra-traits", "visit-mut"] } [lints.rust] # Values used during testing diff --git a/compiler-builtins/crates/libm-macros/src/shared.rs b/compiler-builtins/crates/libm-macros/src/shared.rs index 1cefe4e8c7ed4..ee1feed7c35eb 100644 --- a/compiler-builtins/crates/libm-macros/src/shared.rs +++ b/compiler-builtins/crates/libm-macros/src/shared.rs @@ -279,6 +279,17 @@ const ALL_OPERATIONS_NESTED: &[NestedOp] = &[ fn_list: &["fmaf128"], public: true, }, + NestedOp { + // `(f16) -> i32` + float_ty: FloatTy::F16, + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ilogbf16"], + public: true, + }, NestedOp { // `(f32) -> i32` float_ty: FloatTy::F32, @@ -301,6 +312,17 @@ const ALL_OPERATIONS_NESTED: &[NestedOp] = &[ fn_list: &["ilogb"], public: true, }, + NestedOp { + // `(f128) -> i32` + float_ty: FloatTy::F128, + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::I32], + }, + c_sig: None, + fn_list: &["ilogbf128"], + public: true, + }, NestedOp { // `(i32, f32) -> f32` float_ty: FloatTy::F32, @@ -395,6 +417,20 @@ const ALL_OPERATIONS_NESTED: &[NestedOp] = &[ fn_list: &["modf"], public: true, }, + NestedOp { + // `(f16, &mut c_int) -> f16` as `(f16) -> (f16, i32)` + float_ty: FloatTy::F16, + rust_sig: Signature { + args: &[Ty::F16], + returns: &[Ty::F16, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F16, Ty::MutCInt], + returns: &[Ty::F16], + }), + fn_list: &["frexpf16"], + public: true, + }, NestedOp { // `(f32, &mut c_int) -> f32` as `(f32) -> (f32, i32)` float_ty: FloatTy::F32, @@ -423,6 +459,20 @@ const ALL_OPERATIONS_NESTED: &[NestedOp] = &[ fn_list: &["frexp", "lgamma_r"], public: true, }, + NestedOp { + // `(f128, &mut c_int) -> f128` as `(f128) -> (f128, i32)` + float_ty: FloatTy::F128, + rust_sig: Signature { + args: &[Ty::F128], + returns: &[Ty::F128, Ty::I32], + }, + c_sig: Some(Signature { + args: &[Ty::F128, Ty::MutCInt], + returns: &[Ty::F128], + }), + fn_list: &["frexpf128"], + public: true, + }, NestedOp { // `(f32, f32, &mut c_int) -> f32` as `(f32, f32) -> (f32, i32)` float_ty: FloatTy::F32, diff --git a/compiler-builtins/crates/libm-macros/tests/basic.rs b/compiler-builtins/crates/libm-macros/tests/basic.rs index b4276262229fe..1876db8f5869d 100644 --- a/compiler-builtins/crates/libm-macros/tests/basic.rs +++ b/compiler-builtins/crates/libm-macros/tests/basic.rs @@ -1,3 +1,4 @@ +#![allow(unused_features)] #![feature(f16)] #![feature(f128)] // `STATUS_DLL_NOT_FOUND` on i686 MinGW, not worth looking into. diff --git a/compiler-builtins/crates/musl-math-sys/Cargo.toml b/compiler-builtins/crates/musl-math-sys/Cargo.toml index 39f6fa9065bd9..eb97ffbc86693 100644 --- a/compiler-builtins/crates/musl-math-sys/Cargo.toml +++ b/compiler-builtins/crates/musl-math-sys/Cargo.toml @@ -5,10 +5,8 @@ edition = "2024" publish = false license = "MIT OR Apache-2.0" -[dependencies] - [dev-dependencies] -libm = { path = "../../libm" } +libm.workspace = true [build-dependencies] -cc = "1.2.29" +cc.workspace = true diff --git a/compiler-builtins/crates/symbol-check/Cargo.toml b/compiler-builtins/crates/symbol-check/Cargo.toml index e2218b4917200..6d13f94888004 100644 --- a/compiler-builtins/crates/symbol-check/Cargo.toml +++ b/compiler-builtins/crates/symbol-check/Cargo.toml @@ -5,8 +5,12 @@ edition = "2024" publish = false [dependencies] -object = "0.37.1" -serde_json = "1.0.140" +getopts.workspace = true +object.workspace = true +regex.workspace = true +serde_json.workspace = true -[features] -wasm = ["object/wasm"] +[dev-dependencies] +assert_cmd.workspace = true +cc.workspace = true +tempfile.workspace = true diff --git a/compiler-builtins/crates/symbol-check/build.rs b/compiler-builtins/crates/symbol-check/build.rs new file mode 100644 index 0000000000000..b3e53c38b0bd4 --- /dev/null +++ b/compiler-builtins/crates/symbol-check/build.rs @@ -0,0 +1,6 @@ +use std::env; + +fn main() { + println!("cargo::rustc-env=HOST={}", env::var("HOST").unwrap()); + println!("cargo::rustc-env=TARGET={}", env::var("TARGET").unwrap()); +} diff --git a/compiler-builtins/crates/symbol-check/src/main.rs b/compiler-builtins/crates/symbol-check/src/main.rs index 7d0b7e90addb5..135019e5f729e 100644 --- a/compiler-builtins/crates/symbol-check/src/main.rs +++ b/compiler-builtins/crates/symbol-check/src/main.rs @@ -1,75 +1,104 @@ //! Tool used by CI to inspect compiler-builtins archives and help ensure we won't run into any //! linking errors. +//! +//! Note that symcheck is a "hostprog", i.e. is built and run on the host target even when the +//! actual target is cross compiled. -use std::collections::{BTreeMap, BTreeSet}; -use std::fs; +use std::collections::{BTreeMap, BTreeSet, HashSet}; use std::io::{BufRead, BufReader}; use std::path::{Path, PathBuf}; -use std::process::{Command, Stdio}; +use std::process::{Command, Stdio, exit}; +use std::sync::LazyLock; +use std::{env, fs}; use object::read::archive::ArchiveFile; use object::{ - File as ObjFile, Object, ObjectSection, ObjectSymbol, Result as ObjResult, Symbol, SymbolKind, - SymbolScope, + Architecture, BinaryFormat, Endianness, File as ObjFile, Object, ObjectSection, ObjectSymbol, + Result as ObjResult, SectionFlags, Symbol, SymbolKind, SymbolScope, U32, elf, }; +use regex::Regex; use serde_json::Value; const CHECK_LIBRARIES: &[&str] = &["compiler_builtins", "builtins_test_intrinsics"]; const CHECK_EXTENSIONS: &[Option<&str>] = &[Some("rlib"), Some("a"), Some("exe"), None]; +const GNU_STACK: &str = ".note.GNU-stack"; const USAGE: &str = "Usage: - symbol-check build-and-check [TARGET] -- CARGO_BUILD_ARGS ... - -Cargo will get invoked with `CARGO_ARGS` and the specified target. All output -`compiler_builtins*.rlib` files will be checked. - -If TARGET is not specified, the host target is used. - - check PATHS ... - -Run the same checks on the given set of paths, without invoking Cargo. Paths -may be either archives or object files. + symbol-check --build-and-check [--target TARGET] [--no-os] -- CARGO_BUILD_ARGS ... + symbol-check --check PATHS ...\ "; fn main() { - // Create a `&str` vec so we can match on it. - let args = std::env::args().collect::>(); - let args_ref = args.iter().map(String::as_str).collect::>(); + let mut opts = getopts::Options::new(); + + // Ideally these would be subcommands but that isn't supported. + opts.optflag("h", "help", "Print this help message"); + opts.optflag( + "", + "build-and-check", + "Cargo will get invoked with `CARGO_BUILD_ARGS` and the specified target. All output \ + `compiler_builtins*.rlib` files will be checked.", + ); + opts.optopt( + "", + "target", + "Set the target for build-and-check. Falls back to the host target otherwise.", + "TARGET", + ); + opts.optflag( + "", + "check", + "Run checks on the given set of paths, without invoking Cargo. Paths \ + may be either archives or object files.", + ); + opts.optflag( + "", + "no-os", + "The binaries will not be checked for executable stacks. Used for embedded targets which \ + don't set `.note.GNU-stack` since there is no protection.", + ); + opts.optflag("", "no-visibility", "Don't check visibility."); + + let print_usage_and_exit = |code: i32| -> ! { + eprintln!("{}", opts.usage(USAGE)); + exit(code); + }; + + let m = opts.parse(std::env::args().skip(1)).unwrap_or_else(|e| { + eprintln!("{e}"); + print_usage_and_exit(1); + }); - match &args_ref[1..] { - ["build-and-check", target, "--", args @ ..] if !args.is_empty() => { - run_build_and_check(target, args); - } - ["build-and-check", "--", args @ ..] if !args.is_empty() => { - let target = &host_target(); - run_build_and_check(target, args); - } - ["check", paths @ ..] if !paths.is_empty() => { - check_paths(paths); - } - _ => { - println!("{USAGE}"); - std::process::exit(1); - } + if m.opt_present("help") { + print_usage_and_exit(0); } -} -fn run_build_and_check(target: &str, args: &[&str]) { - // Make sure `--target` isn't passed to avoid confusion (since it should be - // proivded only once, positionally). - for arg in args { + let no_os_target = m.opt_present("no-os"); + let check_visibility = !m.opt_present("no-visibility"); + let free_args = m.free.iter().map(String::as_str).collect::>(); + for arg in &free_args { assert!( !arg.contains("--target"), - "target must be passed positionally. {USAGE}" + "target must be passed to symbol-check" ); } - let paths = exec_cargo_with_args(target, args); - check_paths(&paths); + if m.opt_present("build-and-check") { + let target = m.opt_str("target").unwrap_or(env!("HOST").to_string()); + let paths = exec_cargo_with_args(&target, &free_args); + check_paths(&paths, no_os_target, check_visibility); + } else if m.opt_present("check") { + if free_args.is_empty() { + print_usage_and_exit(1); + } + check_paths(&free_args, no_os_target, check_visibility); + } else { + print_usage_and_exit(1); + } } -fn check_paths>(paths: &[P]) { +fn check_paths>(paths: &[P], no_os_target: bool, check_visibility: bool) { for path in paths { let path = path.as_ref(); println!("Checking {}", path.display()); @@ -77,23 +106,13 @@ fn check_paths>(paths: &[P]) { verify_no_duplicates(&archive); verify_core_symbols(&archive); + verify_no_exec_stack(&archive, no_os_target); + if check_visibility { + verify_hidden_visibility(&archive); + } } } -fn host_target() -> String { - let out = Command::new("rustc") - .arg("--version") - .arg("--verbose") - .output() - .unwrap(); - assert!(out.status.success()); - let out = String::from_utf8(out.stdout).unwrap(); - out.lines() - .find_map(|s| s.strip_prefix("host: ")) - .unwrap() - .to_owned() -} - /// Run `cargo build` with the provided additional arguments, collecting the list of created /// libraries. fn exec_cargo_with_args(target: &str, args: &[&str]) -> Vec { @@ -254,11 +273,14 @@ fn verify_no_duplicates(archive: &BinFile) { found_any = true; }); - assert!(found_any, "no symbols found"); + if archive.has_symbol_tables() { + assert!(found_any, "no symbols found"); + } if !dups.is_empty() { + let count = dups.iter().map(|x| &x.name).collect::>().len(); dups.sort_unstable_by(|a, b| a.name.cmp(&b.name)); - panic!("found duplicate symbols: {dups:#?}"); + panic!("found {count} duplicate symbols: {dups:#?}"); } println!(" success: no duplicate symbols found"); @@ -266,6 +288,14 @@ fn verify_no_duplicates(archive: &BinFile) { /// Ensure that there are no references to symbols from `core` that aren't also (somehow) defined. fn verify_core_symbols(archive: &BinFile) { + // Match both mangling styles: + // + // * `_ZN4core3str8converts9from_utf817hd4454ac14cbbb790E` (old) + // * `_RNvNtNtCscK9O3IwVk7N_4core3str8converts9from_utf8` (v0) + // + // Also account for the Apple leading `_`. + static RE: LazyLock = LazyLock::new(|| Regex::new(r"^_?_[RZ].*4core").unwrap()); + let mut defined = BTreeSet::new(); let mut undefined = Vec::new(); let mut has_symbols = false; @@ -274,7 +304,7 @@ fn verify_core_symbols(archive: &BinFile) { has_symbols = true; // Find only symbols from `core` - if !symbol.name().unwrap().contains("_ZN4core") { + if !RE.is_match(symbol.name().unwrap()) { return; } @@ -286,19 +316,227 @@ fn verify_core_symbols(archive: &BinFile) { } }); - assert!(has_symbols, "no symbols found"); + if archive.has_symbol_tables() { + assert!(has_symbols, "no symbols found"); + } // Discard any symbols that are defined somewhere in the archive undefined.retain(|sym| !defined.contains(&sym.name)); if !undefined.is_empty() { undefined.sort_unstable_by(|a, b| a.name.cmp(&b.name)); - panic!("found undefined symbols from core: {undefined:#?}"); + panic!( + "found {} undefined symbols from core: {undefined:#?}", + undefined.len() + ); } println!(" success: no undefined references to core found"); } +/// Check for symbols with default visibility. +fn verify_hidden_visibility(archive: &BinFile) { + let mut visible = Vec::new(); + let mut found_any = false; + + archive.for_each_symbol(|symbol, obj, member| { + // Only check defined globals. + if !symbol.is_global() || symbol.is_undefined() { + return; + } + + let sym = SymInfo::new(&symbol, obj, member); + if sym.scope == SymbolScope::Dynamic { + visible.push(sym); + } + + found_any = true + }); + + if archive.has_symbol_tables() { + assert!(found_any, "no symbols found"); + } + + if !visible.is_empty() { + visible.sort_unstable_by(|a, b| a.name.cmp(&b.name)); + let num = visible.len(); + panic!("found {num:#?} visible symbols: {visible:#?}"); + } + + println!(" success: no visible symbols found"); +} + +/// Reasons a binary is considered to have an executable stack. +enum ExeStack { + MissingGnuStackSec, + ExeGnuStackSec, + ExePtGnuStack, +} + +/// Ensure that the object/archive will not require an executable stack. +fn verify_no_exec_stack(archive: &BinFile, no_os_target: bool) { + if no_os_target { + // We don't really have a good way of knowing whether or not an elf file is for a + // no-os environment so we rely on a CLI arg (note.GNU-stack doesn't get emitted if + // there is no OS to protect the stack). + println!(" skipping check for writeable+executable stack on no-os target"); + return; + } + + let mut problem_objfiles = Vec::new(); + + archive.for_each_object(|obj, obj_path| match check_obj_exe_stack(&obj) { + Ok(()) => (), + Err(exe) => problem_objfiles.push((obj_path.to_owned(), exe)), + }); + + if problem_objfiles.is_empty() { + println!(" success: no writeable+executable stack indicators found"); + return; + } + + eprintln!("the following object files require an executable stack:"); + + for (obj, exe) in problem_objfiles { + let reason = match exe { + ExeStack::MissingGnuStackSec => "no .note.GNU-stack section", + ExeStack::ExeGnuStackSec => ".note.GNU-stack section marked SHF_EXECINSTR", + ExeStack::ExePtGnuStack => "PT_GNU_STACK program header marked PF_X", + }; + eprintln!(" {obj} ({reason})"); + } + + exit(1); +} + +/// `Err` if the section/flag combination indicates that the object file should be linked with an +/// executable stack. +fn check_obj_exe_stack(obj: &ObjFile) -> Result<(), ExeStack> { + match obj.format() { + BinaryFormat::Elf => check_elf_exe_stack(obj), + // Technically has the `MH_ALLOW_STACK_EXECUTION` flag but I can't get the compiler to + // emit it (`-allow_stack_execute` doesn't seem to work in recent versions). + BinaryFormat::MachO => Ok(()), + // Can't find much information about Windows stack executability. + BinaryFormat::Coff | BinaryFormat::Pe => Ok(()), + // Also not sure about wasm. + BinaryFormat::Wasm => Ok(()), + BinaryFormat::Xcoff | _ => { + unimplemented!("binary format {:?} is not supported", obj.format()) + } + } +} + +/// Check for an executable stack in elf binaries. +/// +/// If the `PT_GNU_STACK` header on a binary is present and marked executable, the binary will +/// have an executable stack (RWE rather than the desired RW). If any object file has the right +/// `.note.GNU-stack` logic, the final binary will get `PT_GNU_STACK`. +/// +/// Individual object file logic is as follows, paraphrased from [1]: +/// +/// - A `.note.GNU-stack` section with the exe flag means this needs an executable stack +/// - A `.note.GNU-stack` section without the exe flag means there is no executable stack needed +/// - Without the section, behavior is target-specific. Historically it usually means an executable +/// stack is required. +/// +/// Per [2], it is now deprecated behavior for a missing `.note.GNU-stack` section to imply an +/// executable stack. However, we shouldn't assume that tooling has caught up to this. +/// +/// [1]: https://www.man7.org/linux/man-pages/man1/ld.1.html +/// [2]: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=0d38576a34ec64a1b4500c9277a8e9d0f07e6774> +fn check_elf_exe_stack(obj: &ObjFile) -> Result<(), ExeStack> { + let end = obj.endianness(); + + // Check for PT_GNU_STACK marked executable + let mut is_obj_exe = false; + let mut found_gnu_stack = false; + let mut check_ph = |p_type: U32, p_flags: U32| { + let ty = p_type.get(end); + let flags = p_flags.get(end); + + // Presence of PT_INTERP indicates that this is an executable rather than a standalone + // object file. + if ty == elf::PT_INTERP { + is_obj_exe = true; + } + + if ty == elf::PT_GNU_STACK { + assert!(!found_gnu_stack, "multiple PT_GNU_STACK sections"); + found_gnu_stack = true; + if flags & elf::PF_X != 0 { + return Err(ExeStack::ExePtGnuStack); + } + } + + Ok(()) + }; + + match obj { + ObjFile::Elf32(f) => { + for ph in f.elf_program_headers() { + check_ph(ph.p_type, ph.p_flags)?; + } + } + ObjFile::Elf64(f) => { + for ph in f.elf_program_headers() { + check_ph(ph.p_type, ph.p_flags)?; + } + } + _ => panic!("should only be called with elf objects"), + } + + if is_obj_exe { + return Ok(()); + } + + // The remaining are checks for individual object files, which wind up controlling PT_GNU_STACK + // in the final binary. + let mut gnu_stack_exe = None; + let mut has_exe_sections = false; + for sec in obj.sections() { + let SectionFlags::Elf { sh_flags } = sec.flags() else { + unreachable!("only elf files are being checked"); + }; + + let is_sec_exe = sh_flags & u64::from(elf::SHF_EXECINSTR) != 0; + + // If the magic section is present, its exe bit tells us whether or not the object + // file requires an executable stack. + if sec.name().unwrap_or_default() == GNU_STACK { + assert!(gnu_stack_exe.is_none(), "multiple {GNU_STACK} sections"); + if is_sec_exe { + gnu_stack_exe = Some(Err(ExeStack::ExeGnuStackSec)); + } else { + gnu_stack_exe = Some(Ok(())); + } + } + + // Otherwise, just keep track of whether or not we have exeuctable sections + has_exe_sections |= is_sec_exe; + } + + // GNU_STACK sets the executability if specified. + if let Some(exe) = gnu_stack_exe { + return exe; + } + + // Ignore object files that have no executable sections, like rmeta. + if !has_exe_sections { + return Ok(()); + } + + // If there is no `.note.GNU-stack` and no executable sections, behavior differs by platform. + match obj.architecture() { + // PPC64 doesn't set `.note.GNU-stack` since GNU nested functions don't need a trampoline, + // . From experimentation, it seems + // like this only applies to big endian. + Architecture::PowerPc64 if obj.endianness() == Endianness::Big => Ok(()), + + _ => Err(ExeStack::MissingGnuStackSec), + } +} + /// Thin wrapper for owning data used by `object`. struct BinFile { path: PathBuf, @@ -359,4 +597,23 @@ impl BinFile { obj.symbols().for_each(|sym| f(sym, &obj, obj_path)); }); } + + /// PE executable files don't have the same kind of symbol tables. This isn't a perfectly + /// accurate check, but at least tells us whether we can skip erroring if we don't find any + /// symbols. + fn has_symbol_tables(&self) -> bool { + let mut empty = true; + let mut ret = false; + + self.for_each_object(|obj, _obj_path| { + if !matches!(obj.format(), BinaryFormat::Pe) { + // Any non-PE objects should have symbol tables. + ret = true; + } + empty = false; + }); + + // If empty, assume there should be tables. + empty || ret + } } diff --git a/compiler-builtins/crates/symbol-check/tests/all.rs b/compiler-builtins/crates/symbol-check/tests/all.rs new file mode 100644 index 0000000000000..cfc8641aca82a --- /dev/null +++ b/compiler-builtins/crates/symbol-check/tests/all.rs @@ -0,0 +1,344 @@ +use std::env; +use std::ffi::OsString; +use std::path::{Path, PathBuf}; +use std::process::{Command, Stdio}; + +use assert_cmd::assert::Assert; +use assert_cmd::cargo::cargo_bin_cmd; +use object::BinaryFormat; +use tempfile::tempdir; + +trait AssertExt { + fn stderr_contains(self, s: &str) -> Self; +} + +impl AssertExt for Assert { + #[track_caller] + fn stderr_contains(self, s: &str) -> Self { + let out = String::from_utf8_lossy(&self.get_output().stderr); + assert!(out.contains(s), "looking for: `{s}`\nout:\n```\n{out}\n```"); + self + } +} + +#[test] +fn test_duplicates() { + let t = TestTarget::from_env(); + let dir = tempdir().unwrap(); + let dup_out = dir.path().join("dup.o"); + let lib_out = dir.path().join("libfoo.rlib"); + + // For the "bad" file, we need duplicate symbols from different object files in the archive. Do + // this reliably by building an archive and a separate object file then merging them. + t.rustc_build(&input_dir().join("duplicates.rs"), &lib_out, |cmd| cmd); + t.rustc_build(&input_dir().join("duplicates.rs"), &dup_out, |cmd| { + cmd.arg("--emit=obj") + }); + + let mut ar = t.cc_build().get_archiver(); + + if ar.get_program().to_string_lossy().contains("lib.exe") { + let mut out_arg = OsString::from("-out:"); + out_arg.push(&lib_out); + ar.arg(&out_arg); + // Repeating the same file as the first arg makes lib.exe append (taken from the + // `cc` implementation). + ar.arg(&lib_out); + } else { + ar.arg("rs") + // Eat an `libfoo.rlib(lib.rmeta) has no symbols` info message on MacOS + .stderr(Stdio::null()) + .arg(&lib_out); + } + + run(ar.arg(&dup_out)); + + let assert = t.symcheck_exe().arg(&lib_out).assert(); + assert + .failure() + .stderr_contains("duplicate symbols") + .stderr_contains("FDUP") + .stderr_contains("IDUP") + .stderr_contains("fndup"); +} + +#[test] +fn test_core_symbols() { + let t = TestTarget::from_env(); + let dir = tempdir().unwrap(); + let lib_out = dir.path().join("libfoo.rlib"); + t.rustc_build(&input_dir().join("core_symbols.rs"), &lib_out, |cmd| cmd); + let assert = t.symcheck_exe().arg(&lib_out).assert(); + assert + .failure() + .stderr_contains("found 1 undefined symbols from core") + .stderr_contains("from_utf8"); +} + +#[test] +fn test_visible_symbols() { + let t = TestTarget::from_env(); + if t.is_windows() { + eprintln!("windows does not have visibility, skipping"); + return; + } + let dir = tempdir().unwrap(); + let lib_out = dir.path().join("libfoo.rlib"); + t.rustc_build(&input_dir().join("good_lib.rs"), &lib_out, |cmd| cmd); + let assert = t.symcheck_exe().arg(&lib_out).assert(); + assert.failure().stderr_contains("found 1 visible symbols"); // good is visible. +} + +mod exe_stack { + use super::*; + + /// Check with an object that has no `.note.GNU-stack` section, indicating platform-default stack + /// writeability (usually enabled). + #[test] + fn test_missing_gnu_stack_section() { + let t = TestTarget::from_env(); + if t.is_msvc() { + // Can't easily build asm via cc with cl.exe / masm.exe + eprintln!("assembly on windows, skipping"); + return; + } + + let dir = tempdir().unwrap(); + let src = input_dir().join("missing_gnu_stack_section.S"); + + let objs = t.cc_build().file(src).out_dir(&dir).compile_intermediates(); + let [obj] = objs.as_slice() else { panic!() }; + + let assert = t.symcheck_exe().arg(obj).arg("--no-visibility").assert(); + + if t.is_ppc64be() || t.no_os() || t.binary_obj_format() != BinaryFormat::Elf { + // Ppc64be doesn't emit `.note.GNU-stack`, not relevant without an OS, and non-elf + // targets don't use `.note.GNU-stack`. + assert.success(); + return; + } + + assert + .failure() + .stderr_contains("the following object files require an executable stack") + .stderr_contains("missing_gnu_stack_section.o (no .note.GNU-stack section)"); + } + + /// Check with an object that has a `.note.GNU-stack` section with the executable flag set. + #[test] + fn test_exe_gnu_stack_section() { + let t = TestTarget::from_env(); + let mut build = t.cc_build(); + if !build.get_compiler().is_like_gnu() || t.is_windows() { + eprintln!("unsupported compiler for nested functions, skipping"); + return; + } + + let dir = tempdir().unwrap(); + let objs = build + .file(input_dir().join("has_exe_gnu_stack_section.c")) + .out_dir(&dir) + .compile_intermediates(); + let [obj] = objs.as_slice() else { panic!() }; + + let assert = t.symcheck_exe().arg(obj).arg("--no-visibility").assert(); + + if t.is_ppc64be() || t.no_os() { + // Ppc64be doesn't emit `.note.GNU-stack`, not relevant without an OS. + assert.success(); + return; + } + + assert + .failure() + .stderr_contains("the following object files require an executable stack") + .stderr_contains( + "has_exe_gnu_stack_section.o (.note.GNU-stack section marked SHF_EXECINSTR)", + ); + } + + /// Check a final binary with `PT_GNU_STACK`. + #[test] + fn test_execstack_bin() { + let t = TestTarget::from_env(); + if t.binary_obj_format() != BinaryFormat::Elf || !t.supports_executables() { + // Mac's Clang rejects `-z execstack`. `-allow_stack_execute` should work per the ld + // manpage, at least on x86, but it doesn't seem to., not relevant without an OS. + eprintln!("non-elf or no-executable target, skipping"); + return; + } + + let dir = tempdir().unwrap(); + let out = dir.path().join("execstack.out"); + + let mut cmd = t.cc_build().get_compiler().to_command(); + t.set_bin_out_path(&mut cmd, &out); + + run(cmd + .arg("-z") + .arg("execstack") + .arg(input_dir().join("good_bin.c"))); + + let assert = t.symcheck_exe().arg(&out).assert(); + assert + .failure() + .stderr_contains("the following object files require an executable stack") + .stderr_contains("execstack.out (PT_GNU_STACK program header marked PF_X)"); + } +} + +#[test] +fn test_good_lib() { + let t = TestTarget::from_env(); + let dir = tempdir().unwrap(); + let lib_out = dir.path().join("libfoo.rlib"); + t.rustc_build(&input_dir().join("good_lib.rs"), &lib_out, |cmd| cmd); + let assert = t + .symcheck_exe() + .arg(&lib_out) + .arg("--no-visibility") + .assert(); + assert.success(); +} + +#[test] +fn test_good_bin() { + let t = TestTarget::from_env(); + // Nothing to test if we can't build a binary. + if !t.supports_executables() { + eprintln!("no-exe target, skipping"); + return; + } + + let dir = tempdir().unwrap(); + let out = dir.path().join("good_bin.out"); + + let mut cmd = t.cc_build().get_compiler().to_command(); + t.set_bin_out_path(&mut cmd, &out); + run(cmd.arg(input_dir().join("good_bin.c"))); + + let assert = t.symcheck_exe().arg(&out).arg("--no-visibility").assert(); + assert.success(); +} + +/// Since symcheck is a hostprog, the target we want to build and test symcheck for may not be the +/// same as the host target. +struct TestTarget { + triple: String, +} + +impl TestTarget { + fn from_env() -> Self { + let triple = match env::var("SYMCHECK_TEST_TARGET") { + Ok(t) => t, + // Require on CI so we don't accidentally always test the native target + _ if env::var("CI").is_ok() => panic!("SYMCHECK_TEST_TARGET must be set in CI"), + // Fall back to native for local convenience. + Err(_) => env!("HOST").to_string(), + }; + + println!("using target {triple}"); + Self { triple } + } + + /// Build i -> o with optional additional configuration. + fn rustc_build(&self, i: &Path, o: &Path, mut f: impl FnMut(&mut Command) -> &mut Command) { + let mut cmd = Command::new("rustc"); + cmd.arg(i) + .arg("--target") + .arg(&self.triple) + .arg("--crate-type=lib") + .arg("-o") + .arg(o); + f(&mut cmd); + run(&mut cmd); + } + + /// Configure `cc` with the host and target. + fn cc_build(&self) -> cc::Build { + let mut b = cc::Build::new(); + b.host(env!("HOST")) + .target(&self.triple) + .opt_level(0) + .cargo_debug(true) + .cargo_metadata(false); + b + } + + fn symcheck_exe(&self) -> assert_cmd::Command { + let mut cmd = cargo_bin_cmd!(); + cmd.arg("--check"); + if self.no_os() { + cmd.arg("--no-os"); + } + cmd + } + + /// MSVC requires different flags for setting output path, account for that here. + fn set_bin_out_path<'a>(&self, cmd: &'a mut Command, out: &Path) -> &'a mut Command { + if self.cc_build().get_compiler().is_like_msvc() { + let mut exe_arg = OsString::from("/Fe"); + let mut obj_arg = OsString::from("/Fo"); + exe_arg.push(out); + obj_arg.push(out.with_extension("o")); + cmd.arg(exe_arg).arg(obj_arg) + } else { + cmd.arg("-o").arg(out) + } + } + + /// Based on `rustc_target`. + fn binary_obj_format(&self) -> BinaryFormat { + let t = &self.triple; + if t.contains("-windows-") || t.contains("-cygwin") { + // Coff for libraries, PE for executables. + BinaryFormat::Coff + } else if t.starts_with("wasm") { + BinaryFormat::Wasm + } else if t.contains("-aix") { + BinaryFormat::Xcoff + } else if t.contains("-apple-") { + BinaryFormat::MachO + } else { + BinaryFormat::Elf + } + } + + fn is_windows(&self) -> bool { + self.triple.contains("-windows-") + } + + fn is_msvc(&self) -> bool { + self.triple.contains("-windows-msvc") + } + + fn is_ppc64be(&self) -> bool { + self.triple.starts_with("powerpc64-") + } + + /// True if the target needs `--no-os` passed to symcheck. + fn no_os(&self) -> bool { + self.triple.contains("-none") + } + + /// True if the target supports (easily) building to a final executable. + fn supports_executables(&self) -> bool { + // Technically i686-pc-windows-gnu should work but it has nontrivial setup in CI. + !(self.no_os() + || self.triple == "wasm32-unknown-unknown" + || self.triple == "i686-pc-windows-gnu") + } +} + +fn input_dir() -> PathBuf { + Path::new(env!("CARGO_MANIFEST_DIR")).join("tests/input") +} + +#[track_caller] +fn run(cmd: &mut Command) { + eprintln!("+ {cmd:?}"); + let out = cmd.output().unwrap(); + println!("{}", String::from_utf8_lossy(&out.stdout)); + eprintln!("{}", String::from_utf8_lossy(&out.stderr)); + assert!(out.status.success(), "{:?}", out.status); +} diff --git a/compiler-builtins/crates/symbol-check/tests/input/core_symbols.rs b/compiler-builtins/crates/symbol-check/tests/input/core_symbols.rs new file mode 100644 index 0000000000000..cf74f97796612 --- /dev/null +++ b/compiler-builtins/crates/symbol-check/tests/input/core_symbols.rs @@ -0,0 +1,11 @@ +//! Ensure we catch calls to `core`. + +#![no_std] + +#[unsafe(no_mangle)] +pub fn call_from_core(s: &[u8]) -> &str { + match core::str::from_utf8(&s) { + Ok(s) => s, + Err(_) => "", + } +} diff --git a/compiler-builtins/crates/symbol-check/tests/input/duplicates.rs b/compiler-builtins/crates/symbol-check/tests/input/duplicates.rs new file mode 100644 index 0000000000000..92623a0b2e1a5 --- /dev/null +++ b/compiler-builtins/crates/symbol-check/tests/input/duplicates.rs @@ -0,0 +1,12 @@ +//! Ensure we catch duplicate symbols (the duplicates are in the aux file). Gets built twice +//! as separate object files. + +#![no_std] + +#[unsafe(no_mangle)] +static IDUP: i32 = 0; +#[unsafe(no_mangle)] +static FDUP: f32 = 0.0; + +#[unsafe(no_mangle)] +pub fn fndup() {} diff --git a/compiler-builtins/crates/symbol-check/tests/input/good_bin.c b/compiler-builtins/crates/symbol-check/tests/input/good_bin.c new file mode 100644 index 0000000000000..dba75b58af1a1 --- /dev/null +++ b/compiler-builtins/crates/symbol-check/tests/input/good_bin.c @@ -0,0 +1,3 @@ +/* empty main used to test binaries with compiler options */ + +int main() {} diff --git a/compiler-builtins/crates/symbol-check/tests/input/good_lib.rs b/compiler-builtins/crates/symbol-check/tests/input/good_lib.rs new file mode 100644 index 0000000000000..6679ee1dd30cf --- /dev/null +++ b/compiler-builtins/crates/symbol-check/tests/input/good_lib.rs @@ -0,0 +1,4 @@ +#![no_std] + +#[unsafe(no_mangle)] +pub fn good() {} diff --git a/compiler-builtins/crates/symbol-check/tests/input/has_exe_gnu_stack_section.c b/compiler-builtins/crates/symbol-check/tests/input/has_exe_gnu_stack_section.c new file mode 100644 index 0000000000000..d4be217b5a06c --- /dev/null +++ b/compiler-builtins/crates/symbol-check/tests/input/has_exe_gnu_stack_section.c @@ -0,0 +1,16 @@ +/* A file that requires an executable stack and thus will have a + * `.note.GNU-stack` section with the executable bit set. + * + * GNU nested functions are the only way I could find to force an explicitly + * executable stack. Supported by GCC only, not Clang. + */ + +void intermediate(void (*)(int, int), int); + +void hack(int *array, int size) { + void store (int index, int value) { + array[index] = value; + } + + intermediate(store, size); +} diff --git a/compiler-builtins/crates/symbol-check/tests/input/missing_gnu_stack_section.S b/compiler-builtins/crates/symbol-check/tests/input/missing_gnu_stack_section.S new file mode 100644 index 0000000000000..09bb761c40ba7 --- /dev/null +++ b/compiler-builtins/crates/symbol-check/tests/input/missing_gnu_stack_section.S @@ -0,0 +1,19 @@ +/* Create an object file with no `.note.GNU-stack` section. + * + * Assembly files do not get that section, meaning platform-default stack + * executability is implied (usually yes on Linux). + */ + +.global func + +#ifdef __wasm__ +.functype func () -> () +.type func, @function +#endif + +func: + nop + +#ifdef __wasm__ + end_function +#endif diff --git a/compiler-builtins/crates/util/Cargo.toml b/compiler-builtins/crates/util/Cargo.toml index 614c54bd83557..b0a365e4735b0 100644 --- a/compiler-builtins/crates/util/Cargo.toml +++ b/compiler-builtins/crates/util/Cargo.toml @@ -5,15 +5,16 @@ edition = "2024" publish = false license = "MIT OR Apache-2.0" +[dependencies] +cfg-if.workspace = true +libm.workspace = true +libm-macros.workspace = true +libm-test.workspace = true +musl-math-sys = { workspace = true, optional = true } +rug = { workspace = true, optional = true } + [features] default = ["build-musl", "build-mpfr", "unstable-float"] build-musl = ["libm-test/build-musl", "dep:musl-math-sys"] build-mpfr = ["libm-test/build-mpfr", "dep:rug"] unstable-float = ["libm/unstable-float", "libm-test/unstable-float", "rug?/nightly-float"] - -[dependencies] -libm = { path = "../../libm", default-features = false } -libm-macros = { path = "../libm-macros" } -libm-test = { path = "../../libm-test", default-features = false } -musl-math-sys = { path = "../musl-math-sys", optional = true } -rug = { version = "1.27.0", optional = true, default-features = false, features = ["float", "std"] } diff --git a/compiler-builtins/crates/util/src/main.rs b/compiler-builtins/crates/util/src/main.rs index 5972181531b26..70aa613f18d06 100644 --- a/compiler-builtins/crates/util/src/main.rs +++ b/compiler-builtins/crates/util/src/main.rs @@ -8,10 +8,11 @@ use std::env; use std::num::ParseIntError; use std::str::FromStr; -use libm::support::{Hexf, hf32, hf64}; +use cfg_if::cfg_if; +use libm::support::{Float, Hexf, hf32, hf64}; #[cfg(feature = "build-mpfr")] use libm_test::mpfloat::MpOp; -use libm_test::{MathOp, TupleCall}; +use libm_test::{Hex, MathOp, TupleCall}; #[cfg(feature = "build-mpfr")] use rug::az::{self, Az}; @@ -22,10 +23,16 @@ cargo run -p util -- SUBCOMMAND: eval inputs... + x inputs... Evaulate the expression with a given basis. This can be useful for running routines with a debugger, or quickly checking input. Examples: * eval musl sinf 1.234 # print the results of musl sinf(1.234f32) * eval mpfr pow 1.234 2.432 # print the results of mpfr pow(1.234, 2.432) + + print inputs... + p inputs... + For each input, print it in different formats with various floating + point properties (normal, infinite, etc). "; fn main() { @@ -33,7 +40,8 @@ fn main() { let str_args = args.iter().map(|s| s.as_str()).collect::>(); match &str_args.as_slice()[1..] { - ["eval", basis, op, inputs @ ..] => do_eval(basis, op, inputs), + ["eval" | "x", basis, op, inputs @ ..] => do_eval(basis, op, inputs), + ["print" | "p", inputs @ ..] => do_classify(inputs), _ => { println!("{USAGE}\nunrecognized input `{str_args:?}`"); std::process::exit(1); @@ -106,6 +114,66 @@ fn do_eval(basis: &str, op: &str, inputs: &[&str]) { panic!("no operation matching {op}"); } +/// Print basic float information to stdout. +fn do_classify(inputs: &[&str]) { + for s in inputs { + if let Some(s) = s.strip_suffix("f16") { + cfg_if! { + if #[cfg(f16_enabled)] { + let s = s.trim_end_matches("_"); + let x: f16 = parse(&[s], 0); + classify_print(x); + continue; + } else { + panic!("parsing this type requires f16 support: `{s}`"); + } + } + }; + if let Some(s) = s.strip_suffix("f32") { + let s = s.trim_end_matches("_"); + let x: f32 = parse(&[s], 0); + classify_print(x); + continue; + } else if let Some(s) = s.strip_suffix("f64") { + let s = s.trim_end_matches("_"); + let x: f64 = parse(&[s], 0); + classify_print(x); + continue; + } + if let Some(s) = s.strip_suffix("f128") { + cfg_if! { + if #[cfg(all(f128_enabled, feature = "build-mpfr"))] { + let s = s.trim_end_matches("_"); + let x: f128 = parse_rug(&[s], 0); + classify_print(x); + continue; + } else { + panic!("parsing this type requires f128 support and \ + the `build-mpfr` feature: `{s}`"); + } + } + }; + panic!("float type must be specified with a `f*` suffix: `{s}`"); + } +} + +fn classify_print(x: F) +where + F: Float, + F::Int: Hex, +{ + println!("{x:?}"); + println!(" hex: {}", Hexf(x)); + println!(" bits: {}", x.to_bits().hex()); + println!(" nan: {}", x.is_nan()); + println!(" inf: {}", x.is_infinite()); + println!(" normal: {}", !x.is_subnormal()); + println!(" pos: {}", x.is_sign_positive()); + println!(" exp: {} {}", x.ex(), x.ex().hex()); + println!(" exp unbiased: {}", x.exp_unbiased()); + println!(" frac: {} {}", x.frac(), x.frac().hex()); +} + /// Parse a tuple from a space-delimited string. trait ParseTuple { fn parse(input: &[&str]) -> Self; @@ -232,11 +300,11 @@ macro_rules! impl_parse_tuple_via_rug { }; } +#[cfg(f16_enabled)] +impl_parse_tuple!(f16); impl_parse_tuple!(f32); impl_parse_tuple!(f64); -#[cfg(f16_enabled)] -impl_parse_tuple_via_rug!(f16); #[cfg(f128_enabled)] impl_parse_tuple_via_rug!(f128); diff --git a/compiler-builtins/etc/function-definitions.json b/compiler-builtins/etc/function-definitions.json index 4f796905b7543..6bd395a84b66f 100644 --- a/compiler-builtins/etc/function-definitions.json +++ b/compiler-builtins/etc/function-definitions.json @@ -560,16 +560,32 @@ }, "frexp": { "sources": [ - "libm/src/math/frexp.rs" + "libm/src/math/frexp.rs", + "libm/src/math/generic/frexp.rs" ], "type": "f64" }, "frexpf": { "sources": [ - "libm/src/math/frexpf.rs" + "libm/src/math/frexp.rs", + "libm/src/math/generic/frexp.rs" ], "type": "f32" }, + "frexpf128": { + "sources": [ + "libm/src/math/frexp.rs", + "libm/src/math/generic/frexp.rs" + ], + "type": "f128" + }, + "frexpf16": { + "sources": [ + "libm/src/math/frexp.rs", + "libm/src/math/generic/frexp.rs" + ], + "type": "f16" + }, "hypot": { "sources": [ "libm/src/math/hypot.rs" @@ -584,16 +600,32 @@ }, "ilogb": { "sources": [ + "libm/src/math/generic/ilogb.rs", "libm/src/math/ilogb.rs" ], "type": "f64" }, "ilogbf": { "sources": [ - "libm/src/math/ilogbf.rs" + "libm/src/math/generic/ilogb.rs", + "libm/src/math/ilogb.rs" ], "type": "f32" }, + "ilogbf128": { + "sources": [ + "libm/src/math/generic/ilogb.rs", + "libm/src/math/ilogb.rs" + ], + "type": "f128" + }, + "ilogbf16": { + "sources": [ + "libm/src/math/generic/ilogb.rs", + "libm/src/math/ilogb.rs" + ], + "type": "f16" + }, "j0": { "sources": [ "libm/src/math/j0.rs" diff --git a/compiler-builtins/etc/function-list.txt b/compiler-builtins/etc/function-list.txt index 1f226c8c0ff3b..f7a694d10f95a 100644 --- a/compiler-builtins/etc/function-list.txt +++ b/compiler-builtins/etc/function-list.txt @@ -84,10 +84,14 @@ fmodf128 fmodf16 frexp frexpf +frexpf128 +frexpf16 hypot hypotf ilogb ilogbf +ilogbf128 +ilogbf16 j0 j0f j1 diff --git a/compiler-builtins/etc/thumbv6-none-eabi.json b/compiler-builtins/etc/thumbv6-none-eabi.json new file mode 100644 index 0000000000000..4c1f760ac3e03 --- /dev/null +++ b/compiler-builtins/etc/thumbv6-none-eabi.json @@ -0,0 +1,20 @@ +{ + "abi": "eabi", + "arch": "arm", + "asm-args": ["-mthumb-interwork", "-march=armv6", "-mlittle-endian"], + "c-enum-min-bits": 8, + "crt-objects-fallback": "false", + "data-layout": "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64", + "emit-debug-gdb-scripts": false, + "features": "+soft-float,+strict-align,+v6k", + "frame-pointer": "always", + "has-thumb-interworking": true, + "linker": "rust-lld", + "linker-flavor": "gnu-lld", + "llvm-floatabi": "soft", + "llvm-target": "thumbv6-none-eabi", + "max-atomic-width": 32, + "panic-strategy": "abort", + "relocation-model": "static", + "target-pointer-width": 32 +} diff --git a/compiler-builtins/libm-test/Cargo.toml b/compiler-builtins/libm-test/Cargo.toml index adecfc1af6b87..8a8c2b0a2ce01 100644 --- a/compiler-builtins/libm-test/Cargo.toml +++ b/compiler-builtins/libm-test/Cargo.toml @@ -5,6 +5,34 @@ edition = "2024" publish = false license = "MIT OR Apache-2.0" +[dependencies] +anyhow.workspace = true +# This is not directly used but is required so we can enable `gmp-mpfr-sys/force-cross`. +gmp-mpfr-sys = { workspace = true, optional = true } +indicatif.workspace = true +libm = { workspace = true, default-features = true, features = ["unstable-public-internals"] } +libm-macros.workspace = true +musl-math-sys = { workspace = true, optional = true } +paste.workspace = true +rand.workspace = true +rand_chacha.workspace = true +rayon.workspace = true +rug = { workspace = true, optional = true } + +# Really dev dependencies, but those can't be optional +criterion = { workspace = true, optional = true } +gungraun = { workspace = true, optional = true } + +[target.'cfg(target_family = "wasm")'.dependencies] +getrandom = { workspace = true, features = ["wasm_js"] } +indicatif = { workspace = true, features = ["wasmbind"] } + +[build-dependencies] +rand = { workspace = true, optional = true } + +[dev-dependencies] +libtest-mimic.workspace = true + [features] default = ["build-mpfr", "unstable-float"] @@ -18,8 +46,10 @@ build-mpfr = ["dep:rug", "dep:gmp-mpfr-sys"] # Build our own musl for testing and benchmarks build-musl = ["dep:musl-math-sys"] -# Enable report generation without bringing in more dependencies by default -benchmarking-reports = ["criterion/plotters", "criterion/html_reports"] +# Config for wall time benchmarks. Plotters and html_reports bring in extra +# deps so are off by default for CI. +benchmarking-reports = ["walltime", "criterion/plotters", "criterion/html_reports"] +walltime = ["dep:criterion"] # Enable icount benchmarks (requires gungraun-runner and valgrind locally) icount = ["dep:gungraun"] @@ -27,31 +57,6 @@ icount = ["dep:gungraun"] # Run with a reduced set of benchmarks, such as for CI short-benchmarks = [] -[dependencies] -anyhow = "1.0.98" -# This is not directly used but is required so we can enable `gmp-mpfr-sys/force-cross`. -gmp-mpfr-sys = { version = "1.6.5", optional = true, default-features = false } -gungraun = { version = "0.17.0", optional = true } -indicatif = { version = "0.18.0", default-features = false } -libm = { path = "../libm", features = ["unstable-public-internals"] } -libm-macros = { path = "../crates/libm-macros" } -musl-math-sys = { path = "../crates/musl-math-sys", optional = true } -paste = "1.0.15" -rand = "0.9.1" -rand_chacha = "0.9.0" -rayon = "1.10.0" -rug = { version = "1.27.0", optional = true, default-features = false, features = ["float", "integer", "std"] } - -[target.'cfg(target_family = "wasm")'.dependencies] -getrandom = { version = "0.3.3", features = ["wasm_js"] } - -[build-dependencies] -rand = { version = "0.9.1", optional = true } - -[dev-dependencies] -criterion = { version = "0.6.0", default-features = false, features = ["cargo_bench_support"] } -libtest-mimic = "0.8.1" - [[bench]] name = "icount" harness = false @@ -60,6 +65,7 @@ required-features = ["icount"] [[bench]] name = "random" harness = false +required-features = ["walltime"] [[test]] # No harness so that we can skip tests at runtime based on env. Prefixed with diff --git a/compiler-builtins/libm-test/benches/icount.rs b/compiler-builtins/libm-test/benches/icount.rs index fb856d9be4517..617e9fb7ad21f 100644 --- a/compiler-builtins/libm-test/benches/icount.rs +++ b/compiler-builtins/libm-test/benches/icount.rs @@ -331,10 +331,14 @@ main!( icount_bench_fmodf16_group, icount_bench_fmodf_group, icount_bench_frexp_group, + icount_bench_frexpf128_group, + icount_bench_frexpf16_group, icount_bench_frexpf_group, icount_bench_hypot_group, icount_bench_hypotf_group, icount_bench_ilogb_group, + icount_bench_ilogbf128_group, + icount_bench_ilogbf16_group, icount_bench_ilogbf_group, icount_bench_j0_group, icount_bench_j0f_group, diff --git a/compiler-builtins/libm-test/src/domain.rs b/compiler-builtins/libm-test/src/domain.rs index 94641be9b5483..eb009bfa093f4 100644 --- a/compiler-builtins/libm-test/src/domain.rs +++ b/compiler-builtins/libm-test/src/domain.rs @@ -207,7 +207,7 @@ impl EitherPrim, Domain> { .into_prim_float()]; /// Domain for `loggamma` - const LGAMMA: [Self; 1] = Self::STRICTLY_POSITIVE; + const LGAMMA: [Self; 1] = Self::UNBOUNDED1; /// Domain for `jn` and `yn`. // FIXME: the domain should provide some sort of "reasonable range" so we don't actually test diff --git a/compiler-builtins/libm-test/src/f8_impl.rs b/compiler-builtins/libm-test/src/f8_impl.rs index 905c7d7fde92a..9f19f518e2a34 100644 --- a/compiler-builtins/libm-test/src/f8_impl.rs +++ b/compiler-builtins/libm-test/src/f8_impl.rs @@ -25,12 +25,16 @@ impl Float for f8 { const NEG_ZERO: Self = Self(0b1_0000_000); const ONE: Self = Self(0b0_0111_000); const NEG_ONE: Self = Self(0b1_0111_000); - const MAX: Self = Self(0b0_1110_111); - const MIN: Self = Self(0b1_1110_111); const INFINITY: Self = Self(0b0_1111_000); const NEG_INFINITY: Self = Self(0b1_1111_000); + const MAX: Self = Self(0b0_1110_111); + const MIN: Self = Self(0b1_1110_111); + const NAN: Self = Self(0b0_1111_100); + const SNAN: Self = Self(0b0_1111_001); const NEG_NAN: Self = Self(0b1_1111_100); + const NEG_SNAN: Self = Self(0b1_1111_001); + const MIN_POSITIVE_NORMAL: Self = Self(1 << Self::SIG_BITS); // FIXME: incorrect values const EPSILON: Self = Self::ZERO; @@ -44,6 +48,7 @@ impl Float for f8 { const SIG_MASK: Self::Int = 0b0_0000_111; const EXP_MASK: Self::Int = 0b0_1111_000; const IMPLICIT_BIT: Self::Int = 0b0_0001_000; + const SIG_TOP_BIT: Self::Int = Self::IMPLICIT_BIT >> 1; fn to_bits(self) -> Self::Int { self.0 diff --git a/compiler-builtins/libm-test/src/generate/case_list.rs b/compiler-builtins/libm-test/src/generate/case_list.rs index 43b28722f2dd2..66d7f6a282f6b 100644 --- a/compiler-builtins/libm-test/src/generate/case_list.rs +++ b/compiler-builtins/libm-test/src/generate/case_list.rs @@ -460,7 +460,8 @@ fn fmodf16_cases() -> Vec> { vec![] } -fn frexp_cases() -> Vec> { +#[cfg(f16_enabled)] +fn frexpf16_cases() -> Vec> { vec![] } @@ -468,6 +469,15 @@ fn frexpf_cases() -> Vec> { vec![] } +fn frexp_cases() -> Vec> { + vec![] +} + +#[cfg(f128_enabled)] +fn frexpf128_cases() -> Vec> { + vec![] +} + fn hypot_cases() -> Vec> { vec![] } @@ -476,7 +486,8 @@ fn hypotf_cases() -> Vec> { vec![] } -fn ilogb_cases() -> Vec> { +#[cfg(f16_enabled)] +fn ilogbf16_cases() -> Vec> { vec![] } @@ -484,6 +495,15 @@ fn ilogbf_cases() -> Vec> { vec![] } +fn ilogb_cases() -> Vec> { + vec![] +} + +#[cfg(f128_enabled)] +fn ilogbf128_cases() -> Vec> { + vec![] +} + fn j0_cases() -> Vec> { vec![] } diff --git a/compiler-builtins/libm-test/src/generate/random.rs b/compiler-builtins/libm-test/src/generate/random.rs index 4ee88946d8eaf..09a3766c66780 100644 --- a/compiler-builtins/libm-test/src/generate/random.rs +++ b/compiler-builtins/libm-test/src/generate/random.rs @@ -5,7 +5,7 @@ use std::sync::LazyLock; use libm::support::Float; use rand::distr::{Alphanumeric, StandardUniform}; use rand::prelude::Distribution; -use rand::{Rng, SeedableRng}; +use rand::{RngExt, SeedableRng}; use rand_chacha::ChaCha8Rng; use super::KnownSize; diff --git a/compiler-builtins/libm-test/src/lib.rs b/compiler-builtins/libm-test/src/lib.rs index accb39654d15a..60d96ae9bceee 100644 --- a/compiler-builtins/libm-test/src/lib.rs +++ b/compiler-builtins/libm-test/src/lib.rs @@ -1,6 +1,7 @@ #![cfg_attr(f16_enabled, feature(f16))] #![cfg_attr(f128_enabled, feature(f128))] #![allow(clippy::unusual_byte_groupings)] // sometimes we group by sign_exp_sig +#![allow(unstable_name_collisions)] // FIXME(float_bits_const): remove when stable pub mod domain; mod f8_impl; diff --git a/compiler-builtins/libm-test/src/mpfloat.rs b/compiler-builtins/libm-test/src/mpfloat.rs index 9b51dc6051d03..91130f892b8ab 100644 --- a/compiler-builtins/libm-test/src/mpfloat.rs +++ b/compiler-builtins/libm-test/src/mpfloat.rs @@ -162,15 +162,21 @@ libm_macros::for_each_function! { fmodf16, frexp, frexpf, + frexpf128, + frexpf16, ilogb, ilogbf, + ilogbf128, + ilogbf16, jn, jnf, ldexp, ldexpf, ldexpf128, ldexpf16, + lgamma, lgamma_r, + lgammaf, lgammaf_r, modf, modff, @@ -213,7 +219,6 @@ libm_macros::for_each_function! { fmaximum_num | fmaximum_numf | fmaximum_numf16 | fmaximum_numf128 => max, fmin | fminf | fminf16 | fminf128 | fminimum_num | fminimum_numf | fminimum_numf16 | fminimum_numf128 => min, - lgamma | lgammaf => ln_gamma, log | logf => ln, log1p | log1pf => ln_1p, tgamma | tgammaf => gamma, @@ -323,43 +328,6 @@ macro_rules! impl_op_for_ty { } } - impl MpOp for crate::op::[]::Routine { - type MpTy = MpFloat; - - fn new_mp() -> Self::MpTy { - new_mpfloat::() - } - - fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { - this.assign(input.0); - let exp = this.frexp_mut(); - (prep_retval::(this, Ordering::Equal), exp) - } - } - - impl MpOp for crate::op::[]::Routine { - type MpTy = MpFloat; - - fn new_mp() -> Self::MpTy { - new_mpfloat::() - } - - fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { - this.assign(input.0); - - // `get_exp` follows `frexp` for `0.5 <= |m| < 1.0`. Adjust the exponent by - // one to scale the significand to `1.0 <= |m| < 2.0`. - this.get_exp().map(|v| v - 1).unwrap_or_else(|| { - if this.is_infinite() { - i32::MAX - } else { - // Zero or NaN - i32::MIN - } - }) - } - } - impl MpOp for crate::op::[]::Routine { type MpTy = MpFloat; @@ -504,6 +472,43 @@ macro_rules! impl_op_for_ty_all { } } + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + let exp = this.frexp_mut(); + (prep_retval::(this, Ordering::Equal), exp) + } + } + + impl MpOp for crate::op::[]::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + this.assign(input.0); + + // `get_exp` follows `frexp` for `0.5 <= |m| < 1.0`. Adjust the exponent by + // one to scale the significand to `1.0 <= |m| < 2.0`. + this.get_exp().map(|v| v - 1).unwrap_or_else(|| { + if this.is_infinite() { + i32::MAX + } else { + // Zero or NaN + i32::MIN + } + }) + } + } + // `ldexp` and `scalbn` are the same for binary floating point, so just forward all // methods. impl MpOp for crate::op::[]::Routine { @@ -576,6 +581,30 @@ impl MpOp for crate::op::lgammaf_r::Routine { } } +impl MpOp for crate::op::lgamma::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + ::run(this, input).0 + } +} + +impl MpOp for crate::op::lgammaf::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + ::run(this, input).0 + } +} + /* stub implementations so we don't need to special case them */ impl MpOp for crate::op::nextafter::Routine { diff --git a/compiler-builtins/libm-test/src/precision.rs b/compiler-builtins/libm-test/src/precision.rs index 7887c032394b8..e994244142749 100644 --- a/compiler-builtins/libm-test/src/precision.rs +++ b/compiler-builtins/libm-test/src/precision.rs @@ -1,9 +1,10 @@ //! Configuration for skipping or changing the result for individual test cases (inputs) rather //! than ignoring entire tests. +use BaseName as Bn; use CheckBasis::{Mpfr, Musl}; +use Identifier as Id; use libm::support::CastFrom; -use {BaseName as Bn, Identifier as Id}; use crate::{BaseName, CheckBasis, CheckCtx, Float, Identifier, Int, TestResult}; @@ -67,7 +68,7 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { Bn::Exp2 => 1, Bn::Expm1 => 1, Bn::Hypot => 1, - Bn::Lgamma | Bn::LgammaR => 16, + Bn::Lgamma | Bn::LgammaR => 4, Bn::Log => 1, Bn::Log10 => 1, Bn::Log1p => 1, @@ -102,7 +103,6 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { match ctx.base_name { Bn::Cosh => ulp = 2, Bn::Exp10 if usize::BITS < 64 => ulp = 4, - Bn::Lgamma | Bn::LgammaR => ulp = 400, Bn::Tanh => ulp = 4, _ => (), } @@ -218,17 +218,26 @@ impl MaybeOverride<(f16,)> for SpecialCase {} impl MaybeOverride<(f32,)> for SpecialCase { fn check_float(input: (f32,), actual: F, expected: F, ctx: &CheckCtx) -> CheckAction { - if (ctx.base_name == BaseName::Lgamma || ctx.base_name == BaseName::LgammaR) - && input.0 > 4e36 + if ctx.base_name == BaseName::J0 && input.0 < -1e34 { + // Errors get huge close to -inf + return XFAIL_NOCHECK; + } + + // the testing infrastructure doesn't account for allowed ulp in the case of overflow + if matches!(ctx.base_name, BaseName::Lgamma | BaseName::LgammaR) + && input.0 == 4.0850034e36 && expected.is_infinite() - && !actual.is_infinite() + && actual == F::MAX { - // This result should saturate but we return a finite value. return XFAIL_NOCHECK; } - if ctx.base_name == BaseName::J0 && input.0 < -1e34 { - // Errors get huge close to -inf + // FIXME(correctness): lgammaf has high relative inaccuracy near its zeroes + if matches!(ctx.base_name, BaseName::Lgamma | BaseName::LgammaR) + && input.0 > -13.0625 + && input.0 < -2.0 + && (expected.abs() < F::ONE || (input.0 - input.0.round()).abs() < 0.02) + { return XFAIL_NOCHECK; } @@ -266,6 +275,24 @@ impl MaybeOverride<(f64,)> for SpecialCase { return XFAIL_NOCHECK; } + if ctx.base_name == BaseName::Acosh + && input.0 < 1.0 + && actual.is_nan() + && ctx.basis == CheckBasis::Musl + { + // Musl sometimes evaluates acosh(negative) to a numeric value + return XFAIL_NOCHECK; + } + + // FIXME(correctness): lgamma has high relative inaccuracy near its zeroes + if matches!(ctx.base_name, BaseName::Lgamma | BaseName::LgammaR) + && input.0 > -32.0 + && input.0 < -2.0 + && (expected.abs() < F::ONE || (input.0 - input.0.round()).abs() < 0.02) + { + return XFAIL_NOCHECK; + } + // maybe_check_nan_bits(actual, expected, ctx) unop_common(input, actual, expected, ctx) } @@ -295,27 +322,6 @@ fn unop_common( expected: F2, ctx: &CheckCtx, ) -> CheckAction { - if ctx.base_name == BaseName::Acosh - && input.0 < F1::NEG_ONE - && !(expected.is_nan() && actual.is_nan()) - { - // acoshf is undefined for x <= 1.0, but we return a random result at lower values. - - if ctx.basis == CheckBasis::Musl { - return XFAIL_NOCHECK; - } - - return XFAIL("acoshf undefined"); - } - - if (ctx.base_name == BaseName::Lgamma || ctx.base_name == BaseName::LgammaR) - && input.0 < F1::ZERO - && !input.0.is_infinite() - { - // loggamma should not be defined for x < 0, yet we both return results - return XFAIL_NOCHECK; - } - // fabs and copysign must leave NaNs untouched. if ctx.base_name == BaseName::Fabs && input.0.is_nan() { // LLVM currently uses x87 instructions which quieten signalling NaNs to handle the i686 @@ -401,14 +407,6 @@ fn binop_common( return SKIP; } - // FIXME(#939): this should not be skipped, there is a bug in our implementationi. - if ctx.base_name == BaseName::FmaximumNum - && ctx.basis == CheckBasis::Mpfr - && ((input.0.is_nan() && actual.is_nan() && expected.is_nan()) || input.1.is_nan()) - { - return XFAIL_NOCHECK; - } - /* FIXME(#439): our fmin and fmax do not compare signed zeros */ if ctx.base_name == BaseName::Fmin @@ -510,7 +508,7 @@ fn int_float_common( if input.0 > 4000 { return XFAIL_NOCHECK; } else if input.0 > 100 { - return CheckAction::AssertWithUlp(1_000_000); + return CheckAction::AssertWithUlp(2_000_000); } } DEFAULT diff --git a/compiler-builtins/libm-test/src/test_traits.rs b/compiler-builtins/libm-test/src/test_traits.rs index 278274d917b35..f8621a3734a4c 100644 --- a/compiler-builtins/libm-test/src/test_traits.rs +++ b/compiler-builtins/libm-test/src/test_traits.rs @@ -260,7 +260,7 @@ where Ok(()) } -impl_int!(u32, i32, u64, i64); +impl_int!(u16, i16, u32, i32, u64, i64, u128, i128); /* trait implementations for floats */ @@ -456,3 +456,15 @@ impl_tuples!( (f32, f32); (f64, f64); ); + +#[cfg(f16_enabled)] +impl_tuples!( + (f16, i32); + (f16, f16); +); + +#[cfg(f128_enabled)] +impl_tuples!( + (f128, i32); + (f128, f128); +); diff --git a/compiler-builtins/libm-test/tests/u256.rs b/compiler-builtins/libm-test/tests/u256.rs index d1c5cfbcc586d..e697945f47971 100644 --- a/compiler-builtins/libm-test/tests/u256.rs +++ b/compiler-builtins/libm-test/tests/u256.rs @@ -10,7 +10,7 @@ type BigInt = rug::Integer; use libm_test::bigint_fuzz_iteration_count; use libm_test::generate::random::SEED; -use rand::{Rng, SeedableRng}; +use rand::{RngExt, SeedableRng}; use rand_chacha::ChaCha8Rng; use rug::Assign; use rug::integer::Order; diff --git a/compiler-builtins/libm/CHANGELOG.md b/compiler-builtins/libm/CHANGELOG.md index 33fec06aa2379..037f79ef3ef1c 100644 --- a/compiler-builtins/libm/CHANGELOG.md +++ b/compiler-builtins/libm/CHANGELOG.md @@ -8,6 +8,22 @@ and this project adheres to ## [Unreleased] +## [0.2.16](https://github.com/rust-lang/compiler-builtins/compare/libm-v0.2.15...libm-v0.2.16) - 2025-12-07 + +### Fixed + +- Fix an incorrect result for `fminimum` and `fmaximum` with the input (-0, NaN) +- Fix a typo in `libm::Libm::roundeven` +- Fix the `expm1f` overflow threshold +- Change `CmpResult` to use a pointer-sized return type +- Compare against `CARGO_CFG_TARGET_FAMILY` in a multi-valued fashion +- Implement `exp` and its variants for i586 with inline assembly +- Implement `floor` and `ceil` in assembly on `i586` + +### Other + +- Significantly optimize `fmod` worst case performance ([#1002](https://github.com/rust-lang/compiler-builtins/pull/1002)) + ## [0.2.15](https://github.com/rust-lang/compiler-builtins/compare/libm-v0.2.14...libm-v0.2.15) - 2025-05-06 ### Other diff --git a/compiler-builtins/libm/Cargo.toml b/compiler-builtins/libm/Cargo.toml index 5b5ca34fd2c9e..28e594dca1f91 100644 --- a/compiler-builtins/libm/Cargo.toml +++ b/compiler-builtins/libm/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "libm" -version = "0.2.15" +version = "0.2.16" authors = [ "Alex Crichton ", "Amanieu d'Antras ", @@ -13,7 +13,11 @@ keywords = ["libm", "math"] repository = "https://github.com/rust-lang/compiler-builtins" license = "MIT" edition = "2021" -rust-version = "1.63" +rust-version = "1.67" + +[dev-dependencies] +# FIXME(msrv): switch to `no-panic.workspace` when possible +no-panic = "0.1.36" [features] default = ["arch"] @@ -42,9 +46,6 @@ unstable-float = [] # hard float operations. force-soft-floats = [] -[dev-dependencies] -no-panic = "0.1.35" - [lints.rust] unexpected_cfgs = { level = "warn", check-cfg = [ # compiler-builtins sets this feature, but we use it in `libm` diff --git a/compiler-builtins/libm/src/lib.rs b/compiler-builtins/libm/src/lib.rs index 31b12235314cd..85ed5e2c9fc63 100644 --- a/compiler-builtins/libm/src/lib.rs +++ b/compiler-builtins/libm/src/lib.rs @@ -8,6 +8,7 @@ )] #![cfg_attr(f128_enabled, feature(f128))] #![cfg_attr(f16_enabled, feature(f16))] +#![allow(unstable_name_collisions)] // FIXME(float_bits_const): remove when stable #![allow(clippy::assign_op_pattern)] #![allow(clippy::deprecated_cfg_attr)] #![allow(clippy::eq_op)] diff --git a/compiler-builtins/libm/src/libm_helper.rs b/compiler-builtins/libm/src/libm_helper.rs index 0bb669398657e..1e6e0beb3e3e0 100644 --- a/compiler-builtins/libm/src/libm_helper.rs +++ b/compiler-builtins/libm/src/libm_helper.rs @@ -202,6 +202,8 @@ libm_helper! { (fn fminimum(x: f16, y: f16) -> (f16); => fminimumf16); (fn fminimum_num(x: f16, y: f16) -> (f16); => fminimum_numf16); (fn fmod(x: f16, y: f16) -> (f16); => fmodf16); + (fn frexp(x: f16) -> (f16, i32); => frexpf16); + (fn ilogb(x: f16) -> (i32); => ilogbf16); (fn ldexp(x: f16, n: i32) -> (f16); => ldexpf16); (fn rint(x: f16) -> (f16); => rintf16); (fn round(x: f16) -> (f16); => roundf16); @@ -231,6 +233,8 @@ libm_helper! { (fn fminimum(x: f128, y: f128) -> (f128); => fminimumf128); (fn fminimum_num(x: f128, y: f128) -> (f128); => fminimum_numf128); (fn fmod(x: f128, y: f128) -> (f128); => fmodf128); + (fn frexp(x: f128) -> (f128, i32); => frexpf128); + (fn ilogb(x: f128) -> (i32); => ilogbf128); (fn ldexp(x: f128, n: i32) -> (f128); => ldexpf128); (fn rint(x: f128) -> (f128); => rintf128); (fn round(x: f128) -> (f128); => roundf128); diff --git a/compiler-builtins/libm/src/math/acosh.rs b/compiler-builtins/libm/src/math/acosh.rs index 8737bad012c84..2904fc0ed5201 100644 --- a/compiler-builtins/libm/src/math/acosh.rs +++ b/compiler-builtins/libm/src/math/acosh.rs @@ -1,4 +1,4 @@ -use super::{log, log1p, sqrt}; +use super::{Float, log, log1p, sqrt}; const LN2: f64 = 0.693147180559945309417232121458176568; /* 0x3fe62e42, 0xfefa39ef*/ @@ -9,19 +9,19 @@ const LN2: f64 = 0.693147180559945309417232121458176568; /* 0x3fe62e42, 0xfefa3 /// `x` must be a number greater than or equal to 1. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn acosh(x: f64) -> f64 { - let u = x.to_bits(); - let e = ((u >> 52) as usize) & 0x7ff; + let ux = x.to_bits(); /* x < 1 domain error is handled in the called functions */ - - if e < 0x3ff + 1 { - /* |x| < 2, up to 2ulp error in [1,1.125] */ - return log1p(x - 1.0 + sqrt((x - 1.0) * (x - 1.0) + 2.0 * (x - 1.0))); - } - if e < 0x3ff + 26 { - /* |x| < 0x1p26 */ - return log(2.0 * x - 1.0 / (x + sqrt(x * x - 1.0))); + if (ux & !f64::SIGN_MASK) < 2_f64.to_bits() { + /* |x| < 2, invalid if x < 1 */ + /* up to 2ulp error in [1,1.125] */ + let x_1 = x - 1.0; + log1p(x_1 + sqrt(x_1 * x_1 + 2.0 * x_1)) + } else if ux < ((1 << 26) as f64).to_bits() { + /* 2 <= x < 0x1p26 */ + log(2.0 * x - 1.0 / (x + sqrt(x * x - 1.0))) + } else { + /* x >= 0x1p26 or x <= -2 or nan */ + log(x) + LN2 } - /* |x| >= 0x1p26 or nan */ - return log(x) + LN2; } diff --git a/compiler-builtins/libm/src/math/acoshf.rs b/compiler-builtins/libm/src/math/acoshf.rs index 432fa03f11635..d9aafaabdef43 100644 --- a/compiler-builtins/libm/src/math/acoshf.rs +++ b/compiler-builtins/libm/src/math/acoshf.rs @@ -1,4 +1,4 @@ -use super::{log1pf, logf, sqrtf}; +use super::{Float, log1pf, logf, sqrtf}; const LN2: f32 = 0.693147180559945309417232121458176568; @@ -9,18 +9,19 @@ const LN2: f32 = 0.693147180559945309417232121458176568; /// `x` must be a number greater than or equal to 1. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn acoshf(x: f32) -> f32 { - let u = x.to_bits(); - let a = u & 0x7fffffff; + let ux = x.to_bits(); - if a < 0x3f800000 + (1 << 23) { - /* |x| < 2, invalid if x < 1 or nan */ + /* x < 1 domain error is handled in the called functions */ + if (ux & !f32::SIGN_MASK) < 2_f32.to_bits() { + /* |x| < 2, invalid if x < 1 */ /* up to 2ulp error in [1,1.125] */ - return log1pf(x - 1.0 + sqrtf((x - 1.0) * (x - 1.0) + 2.0 * (x - 1.0))); + let x_1 = x - 1.0; + log1pf(x_1 + sqrtf(x_1 * x_1 + 2.0 * x_1)) + } else if ux < ((1 << 12) as f32).to_bits() { + /* 2 <= x < 0x1p12 */ + logf(2.0 * x - 1.0 / (x + sqrtf(x * x - 1.0))) + } else { + /* x >= 0x1p12 or x <= -2 or nan */ + logf(x) + LN2 } - if a < 0x3f800000 + (12 << 23) { - /* |x| < 0x1p12 */ - return logf(2.0 * x - 1.0 / (x + sqrtf(x * x - 1.0))); - } - /* x >= 0x1p12 */ - return logf(x) + LN2; } diff --git a/compiler-builtins/libm/src/math/exp2.rs b/compiler-builtins/libm/src/math/exp2.rs index 08b71587f6de5..d4c9e96652000 100644 --- a/compiler-builtins/libm/src/math/exp2.rs +++ b/compiler-builtins/libm/src/math/exp2.rs @@ -380,7 +380,7 @@ pub fn exp2(mut x: f64) -> f64 { let mut i0 = ui as u32; i0 = i0.wrapping_add(TBLSIZE as u32 / 2); let ku = i0 / TBLSIZE as u32 * TBLSIZE as u32; - let ki = div!(ku as i32, TBLSIZE as i32); + let ki = (ku as i32) / TBLSIZE as i32; i0 %= TBLSIZE as u32; let uf = f64::from_bits(ui) - redux; let mut z = x - uf; diff --git a/compiler-builtins/libm/src/math/fmin_fmax.rs b/compiler-builtins/libm/src/math/fmin_fmax.rs index c4c1b0435dd29..ead9e6599f1be 100644 --- a/compiler-builtins/libm/src/math/fmin_fmax.rs +++ b/compiler-builtins/libm/src/math/fmin_fmax.rs @@ -77,9 +77,12 @@ pub fn fmaxf128(x: f128, y: f128) -> f128 { #[cfg(test)] mod tests { use super::*; + use crate::support::hex_float::Hexi; use crate::support::{Float, Hexf}; fn fmin_spec_test(f: impl Fn(F, F) -> F) { + // Note that (YaN, sNaN) and (sNaN, YaN) results differ from 754-2008. This is intentional, + // see comments in the generic implementations. let cases = [ (F::ZERO, F::ZERO, F::ZERO), (F::ZERO, F::ONE, F::ZERO), @@ -88,6 +91,8 @@ mod tests { (F::ZERO, F::NEG_INFINITY, F::NEG_INFINITY), (F::ZERO, F::NAN, F::ZERO), (F::ZERO, F::NEG_NAN, F::ZERO), + (F::ZERO, F::SNAN, F::ZERO), + (F::ZERO, F::NEG_SNAN, F::ZERO), (F::NEG_ZERO, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_ZERO, F::ONE, F::NEG_ZERO), (F::NEG_ZERO, F::NEG_ONE, F::NEG_ONE), @@ -95,6 +100,8 @@ mod tests { (F::NEG_ZERO, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_ZERO, F::NAN, F::NEG_ZERO), (F::NEG_ZERO, F::NEG_NAN, F::NEG_ZERO), + (F::NEG_ZERO, F::SNAN, F::NEG_ZERO), + (F::NEG_ZERO, F::NEG_SNAN, F::NEG_ZERO), (F::ONE, F::ZERO, F::ZERO), (F::ONE, F::NEG_ZERO, F::NEG_ZERO), (F::ONE, F::ONE, F::ONE), @@ -103,6 +110,8 @@ mod tests { (F::ONE, F::NEG_INFINITY, F::NEG_INFINITY), (F::ONE, F::NAN, F::ONE), (F::ONE, F::NEG_NAN, F::ONE), + (F::ONE, F::SNAN, F::ONE), + (F::ONE, F::NEG_SNAN, F::ONE), (F::NEG_ONE, F::ZERO, F::NEG_ONE), (F::NEG_ONE, F::NEG_ZERO, F::NEG_ONE), (F::NEG_ONE, F::ONE, F::NEG_ONE), @@ -111,6 +120,8 @@ mod tests { (F::NEG_ONE, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_ONE, F::NAN, F::NEG_ONE), (F::NEG_ONE, F::NEG_NAN, F::NEG_ONE), + (F::NEG_ONE, F::SNAN, F::NEG_ONE), + (F::NEG_ONE, F::NEG_SNAN, F::NEG_ONE), (F::INFINITY, F::ZERO, F::ZERO), (F::INFINITY, F::NEG_ZERO, F::NEG_ZERO), (F::INFINITY, F::ONE, F::ONE), @@ -119,6 +130,8 @@ mod tests { (F::INFINITY, F::NEG_INFINITY, F::NEG_INFINITY), (F::INFINITY, F::NAN, F::INFINITY), (F::INFINITY, F::NEG_NAN, F::INFINITY), + (F::INFINITY, F::SNAN, F::INFINITY), + (F::INFINITY, F::NEG_SNAN, F::INFINITY), (F::NEG_INFINITY, F::ZERO, F::NEG_INFINITY), (F::NEG_INFINITY, F::NEG_ZERO, F::NEG_INFINITY), (F::NEG_INFINITY, F::ONE, F::NEG_INFINITY), @@ -127,6 +140,8 @@ mod tests { (F::NEG_INFINITY, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_INFINITY, F::NAN, F::NEG_INFINITY), (F::NEG_INFINITY, F::NEG_NAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::SNAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::NEG_SNAN, F::NEG_INFINITY), (F::NAN, F::ZERO, F::ZERO), (F::NAN, F::NEG_ZERO, F::NEG_ZERO), (F::NAN, F::ONE, F::ONE), @@ -140,6 +155,18 @@ mod tests { (F::NEG_NAN, F::NEG_ONE, F::NEG_ONE), (F::NEG_NAN, F::INFINITY, F::INFINITY), (F::NEG_NAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::SNAN, F::ZERO, F::ZERO), + (F::SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::SNAN, F::ONE, F::ONE), + (F::SNAN, F::NEG_ONE, F::NEG_ONE), + (F::SNAN, F::INFINITY, F::INFINITY), + (F::SNAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::NEG_SNAN, F::ZERO, F::ZERO), + (F::NEG_SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::NEG_SNAN, F::ONE, F::ONE), + (F::NEG_SNAN, F::NEG_ONE, F::NEG_ONE), + (F::NEG_SNAN, F::INFINITY, F::INFINITY), + (F::NEG_SNAN, F::NEG_INFINITY, F::NEG_INFINITY), ]; for (x, y, res) in cases { @@ -147,12 +174,29 @@ mod tests { assert_biteq!(val, res, "fmin({}, {})", Hexf(x), Hexf(y)); } - // Ordering between zeros and NaNs does not matter + // Ordering between zeros does not matter assert_eq!(f(F::ZERO, F::NEG_ZERO), F::ZERO); assert_eq!(f(F::NEG_ZERO, F::ZERO), F::ZERO); - assert!(f(F::NAN, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_NAN).is_nan()); + + // Selection between NaNs does not matter, it just must be quiet + assert!(f(F::NAN, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_NAN).is_qnan()); + + // These operations should technically return a qnan, but LLVM optimizes out our + // `* 1.0` canonicalization. + assert!(f(F::NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::SNAN).is_nan()); + assert!(f(F::SNAN, F::NAN).is_nan()); + assert!(f(F::SNAN, F::NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_SNAN).is_nan()); } #[test] @@ -186,6 +230,8 @@ mod tests { (F::ZERO, F::NEG_INFINITY, F::ZERO), (F::ZERO, F::NAN, F::ZERO), (F::ZERO, F::NEG_NAN, F::ZERO), + (F::ZERO, F::SNAN, F::ZERO), + (F::ZERO, F::NEG_SNAN, F::ZERO), (F::NEG_ZERO, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_ZERO, F::ONE, F::ONE), (F::NEG_ZERO, F::NEG_ONE, F::NEG_ZERO), @@ -193,6 +239,8 @@ mod tests { (F::NEG_ZERO, F::NEG_INFINITY, F::NEG_ZERO), (F::NEG_ZERO, F::NAN, F::NEG_ZERO), (F::NEG_ZERO, F::NEG_NAN, F::NEG_ZERO), + (F::NEG_ZERO, F::SNAN, F::NEG_ZERO), + (F::NEG_ZERO, F::NEG_SNAN, F::NEG_ZERO), (F::ONE, F::ZERO, F::ONE), (F::ONE, F::NEG_ZERO, F::ONE), (F::ONE, F::ONE, F::ONE), @@ -201,6 +249,8 @@ mod tests { (F::ONE, F::NEG_INFINITY, F::ONE), (F::ONE, F::NAN, F::ONE), (F::ONE, F::NEG_NAN, F::ONE), + (F::ONE, F::SNAN, F::ONE), + (F::ONE, F::NEG_SNAN, F::ONE), (F::NEG_ONE, F::ZERO, F::ZERO), (F::NEG_ONE, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_ONE, F::ONE, F::ONE), @@ -209,6 +259,8 @@ mod tests { (F::NEG_ONE, F::NEG_INFINITY, F::NEG_ONE), (F::NEG_ONE, F::NAN, F::NEG_ONE), (F::NEG_ONE, F::NEG_NAN, F::NEG_ONE), + (F::NEG_ONE, F::SNAN, F::NEG_ONE), + (F::NEG_ONE, F::NEG_SNAN, F::NEG_ONE), (F::INFINITY, F::ZERO, F::INFINITY), (F::INFINITY, F::NEG_ZERO, F::INFINITY), (F::INFINITY, F::ONE, F::INFINITY), @@ -217,6 +269,8 @@ mod tests { (F::INFINITY, F::NEG_INFINITY, F::INFINITY), (F::INFINITY, F::NAN, F::INFINITY), (F::INFINITY, F::NEG_NAN, F::INFINITY), + (F::INFINITY, F::SNAN, F::INFINITY), + (F::INFINITY, F::NEG_SNAN, F::INFINITY), (F::NEG_INFINITY, F::ZERO, F::ZERO), (F::NEG_INFINITY, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_INFINITY, F::ONE, F::ONE), @@ -225,6 +279,8 @@ mod tests { (F::NEG_INFINITY, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_INFINITY, F::NAN, F::NEG_INFINITY), (F::NEG_INFINITY, F::NEG_NAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::SNAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::NEG_SNAN, F::NEG_INFINITY), (F::NAN, F::ZERO, F::ZERO), (F::NAN, F::NEG_ZERO, F::NEG_ZERO), (F::NAN, F::ONE, F::ONE), @@ -238,19 +294,54 @@ mod tests { (F::NEG_NAN, F::NEG_ONE, F::NEG_ONE), (F::NEG_NAN, F::INFINITY, F::INFINITY), (F::NEG_NAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::SNAN, F::ZERO, F::ZERO), + (F::SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::SNAN, F::ONE, F::ONE), + (F::SNAN, F::NEG_ONE, F::NEG_ONE), + (F::SNAN, F::INFINITY, F::INFINITY), + (F::SNAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::NEG_SNAN, F::ZERO, F::ZERO), + (F::NEG_SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::NEG_SNAN, F::ONE, F::ONE), + (F::NEG_SNAN, F::NEG_ONE, F::NEG_ONE), + (F::NEG_SNAN, F::INFINITY, F::INFINITY), + (F::NEG_SNAN, F::NEG_INFINITY, F::NEG_INFINITY), ]; for (x, y, res) in cases { let val = f(x, y); - assert_biteq!(val, res, "fmax({}, {})", Hexf(x), Hexf(y)); + assert_biteq!( + val, + res, + "fmax({}, {}) ({}, {})", + Hexf(x), + Hexf(y), + Hexi(x.to_bits()), + Hexi(y.to_bits()), + ); } - // Ordering between zeros and NaNs does not matter + // Ordering between zeros assert_eq!(f(F::ZERO, F::NEG_ZERO), F::ZERO); assert_eq!(f(F::NEG_ZERO, F::ZERO), F::ZERO); - assert!(f(F::NAN, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_NAN).is_nan()); + + // Selection between NaNs does not matter, it just must be quiet + assert!(f(F::NAN, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_NAN).is_qnan()); + + assert!(f(F::NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::SNAN).is_nan()); + assert!(f(F::SNAN, F::NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::SNAN, F::SNAN).is_nan()); } #[test] diff --git a/compiler-builtins/libm/src/math/fminimum_fmaximum.rs b/compiler-builtins/libm/src/math/fminimum_fmaximum.rs index a3c9c9c3991b7..ffc724e3a8d74 100644 --- a/compiler-builtins/libm/src/math/fminimum_fmaximum.rs +++ b/compiler-builtins/libm/src/math/fminimum_fmaximum.rs @@ -69,6 +69,7 @@ pub fn fmaximumf128(x: f128, y: f128) -> f128 { #[cfg(test)] mod tests { use super::*; + use crate::support::hex_float::Hexi; use crate::support::{Float, Hexf}; fn fminimum_spec_test(f: impl Fn(F, F) -> F) { @@ -122,29 +123,63 @@ mod tests { (F::NAN, F::INFINITY, F::NAN), (F::NAN, F::NEG_INFINITY, F::NAN), (F::NAN, F::NAN, F::NAN), + (F::NAN, F::SNAN, F::NAN), ]; for (x, y, res) in cases { let val = f(x, y); - assert_biteq!(val, res, "fminimum({}, {})", Hexf(x), Hexf(y)); + assert_biteq!( + val, + res, + "fminimum({}, {}) ({}, {})", + Hexf(x), + Hexf(y), + Hexi(x.to_bits()), + Hexi(y.to_bits()), + ); } - // Ordering between NaNs does not matter - assert!(f(F::NAN, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NAN).is_nan()); - assert!(f(F::ZERO, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_ZERO, F::NEG_NAN).is_nan()); - assert!(f(F::ONE, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_ONE, F::NEG_NAN).is_nan()); - assert!(f(F::INFINITY, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_INFINITY, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::ZERO).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_ZERO).is_nan()); - assert!(f(F::NEG_NAN, F::ONE).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_ONE).is_nan()); - assert!(f(F::NEG_NAN, F::INFINITY).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_INFINITY).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_NAN).is_nan()); + // On platforms where operations only return a single canonical NaN (e.g. RISC-V), the + // result may not exactly match one of the inputs which is fine. + assert!(f(F::NAN, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NAN).is_qnan()); + assert!(f(F::ZERO, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_ZERO, F::NEG_NAN).is_qnan()); + assert!(f(F::ONE, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_ONE, F::NEG_NAN).is_qnan()); + assert!(f(F::INFINITY, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_INFINITY, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::ZERO).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_ZERO).is_qnan()); + assert!(f(F::NEG_NAN, F::ONE).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_ONE).is_qnan()); + assert!(f(F::NEG_NAN, F::INFINITY).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_INFINITY).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_NAN).is_qnan()); + + // These operations should technically return a qnan, but LLVM optimizes out our + // `* 1.0` canonicalization. + assert!(f(F::INFINITY, F::SNAN,).is_nan()); + assert!(f(F::NEG_INFINITY, F::SNAN,).is_nan()); + assert!(f(F::NEG_ONE, F::SNAN,).is_nan()); + assert!(f(F::NEG_SNAN, F::INFINITY).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_INFINITY).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_ONE).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_ZERO).is_nan()); + assert!(f(F::NEG_SNAN, F::ONE).is_nan()); + assert!(f(F::NEG_SNAN, F::ZERO).is_nan()); + assert!(f(F::NEG_ZERO, F::SNAN,).is_nan()); + assert!(f(F::ONE, F::SNAN,).is_nan()); + assert!(f(F::SNAN, F::INFINITY,).is_nan()); + assert!(f(F::SNAN, F::NEG_INFINITY,).is_nan()); + assert!(f(F::SNAN, F::NEG_ONE,).is_nan()); + assert!(f(F::SNAN, F::NEG_SNAN,).is_nan()); + assert!(f(F::SNAN, F::NEG_ZERO,).is_nan()); + assert!(f(F::SNAN, F::ONE,).is_nan()); + assert!(f(F::SNAN, F::SNAN,).is_nan()); + assert!(f(F::SNAN, F::ZERO,).is_nan()); + assert!(f(F::ZERO, F::SNAN,).is_nan()); } #[test] @@ -220,29 +255,63 @@ mod tests { (F::NAN, F::INFINITY, F::NAN), (F::NAN, F::NEG_INFINITY, F::NAN), (F::NAN, F::NAN, F::NAN), + (F::NAN, F::SNAN, F::NAN), ]; for (x, y, res) in cases { let val = f(x, y); - assert_biteq!(val, res, "fmaximum({}, {})", Hexf(x), Hexf(y)); + assert_biteq!( + val, + res, + "fmaximum({}, {}) ({}, {})", + Hexf(x), + Hexf(y), + Hexi(x.to_bits()), + Hexi(y.to_bits()), + ); } - // Ordering between NaNs does not matter - assert!(f(F::NAN, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NAN).is_nan()); - assert!(f(F::ZERO, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_ZERO, F::NEG_NAN).is_nan()); - assert!(f(F::ONE, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_ONE, F::NEG_NAN).is_nan()); - assert!(f(F::INFINITY, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_INFINITY, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::ZERO).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_ZERO).is_nan()); - assert!(f(F::NEG_NAN, F::ONE).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_ONE).is_nan()); - assert!(f(F::NEG_NAN, F::INFINITY).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_INFINITY).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_NAN).is_nan()); + // On platforms where operations only return a single canonical NaN (e.g. RISC-V), the + // result may not exactly match one of the inputs which is fine. + assert!(f(F::NAN, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NAN).is_qnan()); + assert!(f(F::ZERO, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_ZERO, F::NEG_NAN).is_qnan()); + assert!(f(F::ONE, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_ONE, F::NEG_NAN).is_qnan()); + assert!(f(F::INFINITY, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_INFINITY, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::ZERO).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_ZERO).is_qnan()); + assert!(f(F::NEG_NAN, F::ONE).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_ONE).is_qnan()); + assert!(f(F::NEG_NAN, F::INFINITY).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_INFINITY).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_NAN).is_qnan()); + + // These operations should technically return a qnan, but LLVM optimizes out our + // `* 1.0` canonicalization. + assert!(f(F::INFINITY, F::SNAN,).is_nan()); + assert!(f(F::NEG_INFINITY, F::SNAN,).is_nan()); + assert!(f(F::NEG_ONE, F::SNAN,).is_nan()); + assert!(f(F::NEG_SNAN, F::INFINITY).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_INFINITY).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_ONE).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_ZERO).is_nan()); + assert!(f(F::NEG_SNAN, F::ONE).is_nan()); + assert!(f(F::NEG_SNAN, F::ZERO).is_nan()); + assert!(f(F::NEG_ZERO, F::SNAN,).is_nan()); + assert!(f(F::ONE, F::SNAN,).is_nan()); + assert!(f(F::SNAN, F::INFINITY,).is_nan()); + assert!(f(F::SNAN, F::NEG_INFINITY,).is_nan()); + assert!(f(F::SNAN, F::NEG_ONE,).is_nan()); + assert!(f(F::SNAN, F::NEG_SNAN,).is_nan()); + assert!(f(F::SNAN, F::NEG_ZERO,).is_nan()); + assert!(f(F::SNAN, F::ONE,).is_nan()); + assert!(f(F::SNAN, F::SNAN,).is_nan()); + assert!(f(F::SNAN, F::ZERO,).is_nan()); + assert!(f(F::ZERO, F::SNAN,).is_nan()); } #[test] diff --git a/compiler-builtins/libm/src/math/fminimum_fmaximum_num.rs b/compiler-builtins/libm/src/math/fminimum_fmaximum_num.rs index 612cefe756e30..3157f8a3fee8c 100644 --- a/compiler-builtins/libm/src/math/fminimum_fmaximum_num.rs +++ b/compiler-builtins/libm/src/math/fminimum_fmaximum_num.rs @@ -69,6 +69,7 @@ pub fn fmaximum_numf128(x: f128, y: f128) -> f128 { #[cfg(test)] mod tests { use super::*; + use crate::support::hex_float::Hexi; use crate::support::{Float, Hexf}; fn fminimum_num_spec_test(f: impl Fn(F, F) -> F) { @@ -81,6 +82,8 @@ mod tests { (F::ZERO, F::NEG_INFINITY, F::NEG_INFINITY), (F::ZERO, F::NAN, F::ZERO), (F::ZERO, F::NEG_NAN, F::ZERO), + (F::ZERO, F::SNAN, F::ZERO), + (F::ZERO, F::NEG_SNAN, F::ZERO), (F::NEG_ZERO, F::ZERO, F::NEG_ZERO), (F::NEG_ZERO, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_ZERO, F::ONE, F::NEG_ZERO), @@ -89,6 +92,8 @@ mod tests { (F::NEG_ZERO, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_ZERO, F::NAN, F::NEG_ZERO), (F::NEG_ZERO, F::NEG_NAN, F::NEG_ZERO), + (F::NEG_ZERO, F::SNAN, F::NEG_ZERO), + (F::NEG_ZERO, F::NEG_SNAN, F::NEG_ZERO), (F::ONE, F::ZERO, F::ZERO), (F::ONE, F::NEG_ZERO, F::NEG_ZERO), (F::ONE, F::ONE, F::ONE), @@ -97,6 +102,8 @@ mod tests { (F::ONE, F::NEG_INFINITY, F::NEG_INFINITY), (F::ONE, F::NAN, F::ONE), (F::ONE, F::NEG_NAN, F::ONE), + (F::ONE, F::SNAN, F::ONE), + (F::ONE, F::NEG_SNAN, F::ONE), (F::NEG_ONE, F::ZERO, F::NEG_ONE), (F::NEG_ONE, F::NEG_ZERO, F::NEG_ONE), (F::NEG_ONE, F::ONE, F::NEG_ONE), @@ -105,6 +112,8 @@ mod tests { (F::NEG_ONE, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_ONE, F::NAN, F::NEG_ONE), (F::NEG_ONE, F::NEG_NAN, F::NEG_ONE), + (F::NEG_ONE, F::SNAN, F::NEG_ONE), + (F::NEG_ONE, F::NEG_SNAN, F::NEG_ONE), (F::INFINITY, F::ZERO, F::ZERO), (F::INFINITY, F::NEG_ZERO, F::NEG_ZERO), (F::INFINITY, F::ONE, F::ONE), @@ -113,6 +122,8 @@ mod tests { (F::INFINITY, F::NEG_INFINITY, F::NEG_INFINITY), (F::INFINITY, F::NAN, F::INFINITY), (F::INFINITY, F::NEG_NAN, F::INFINITY), + (F::INFINITY, F::SNAN, F::INFINITY), + (F::INFINITY, F::NEG_SNAN, F::INFINITY), (F::NEG_INFINITY, F::ZERO, F::NEG_INFINITY), (F::NEG_INFINITY, F::NEG_ZERO, F::NEG_INFINITY), (F::NEG_INFINITY, F::ONE, F::NEG_INFINITY), @@ -121,6 +132,8 @@ mod tests { (F::NEG_INFINITY, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_INFINITY, F::NAN, F::NEG_INFINITY), (F::NEG_INFINITY, F::NEG_NAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::SNAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::NEG_SNAN, F::NEG_INFINITY), (F::NAN, F::ZERO, F::ZERO), (F::NAN, F::NEG_ZERO, F::NEG_ZERO), (F::NAN, F::ONE, F::ONE), @@ -134,17 +147,52 @@ mod tests { (F::NEG_NAN, F::NEG_ONE, F::NEG_ONE), (F::NEG_NAN, F::INFINITY, F::INFINITY), (F::NEG_NAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::SNAN, F::ZERO, F::ZERO), + (F::SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::SNAN, F::ONE, F::ONE), + (F::SNAN, F::NEG_ONE, F::NEG_ONE), + (F::SNAN, F::INFINITY, F::INFINITY), + (F::SNAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::NEG_SNAN, F::ZERO, F::ZERO), + (F::NEG_SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::NEG_SNAN, F::ONE, F::ONE), + (F::NEG_SNAN, F::NEG_ONE, F::NEG_ONE), + (F::NEG_SNAN, F::INFINITY, F::INFINITY), + (F::NEG_SNAN, F::NEG_INFINITY, F::NEG_INFINITY), ]; for (x, y, expected) in cases { let actual = f(x, y); - assert_biteq!(actual, expected, "fminimum_num({}, {})", Hexf(x), Hexf(y)); + assert_biteq!( + actual, + expected, + "fminimum_num({}, {}) ({}, {})", + Hexf(x), + Hexf(y), + Hexi(x.to_bits()), + Hexi(y.to_bits()), + ); } - // Ordering between NaNs does not matter - assert!(f(F::NAN, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_NAN).is_nan()); + // Selection between NaNs does not matter, it just must be quiet + assert!(f(F::NAN, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_NAN).is_qnan()); + + // These operations should technically return a qnan, but LLVM optimizes out our + // `* 1.0` canonicalization. + assert!(f(F::NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::SNAN).is_nan()); + assert!(f(F::SNAN, F::NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::SNAN, F::SNAN).is_nan()); } #[test] @@ -179,6 +227,8 @@ mod tests { (F::ZERO, F::NEG_INFINITY, F::ZERO), (F::ZERO, F::NAN, F::ZERO), (F::ZERO, F::NEG_NAN, F::ZERO), + (F::ZERO, F::SNAN, F::ZERO), + (F::ZERO, F::NEG_SNAN, F::ZERO), (F::NEG_ZERO, F::ZERO, F::ZERO), (F::NEG_ZERO, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_ZERO, F::ONE, F::ONE), @@ -187,6 +237,8 @@ mod tests { (F::NEG_ZERO, F::NEG_INFINITY, F::NEG_ZERO), (F::NEG_ZERO, F::NAN, F::NEG_ZERO), (F::NEG_ZERO, F::NEG_NAN, F::NEG_ZERO), + (F::NEG_ZERO, F::SNAN, F::NEG_ZERO), + (F::NEG_ZERO, F::NEG_SNAN, F::NEG_ZERO), (F::ONE, F::ZERO, F::ONE), (F::ONE, F::NEG_ZERO, F::ONE), (F::ONE, F::ONE, F::ONE), @@ -195,6 +247,8 @@ mod tests { (F::ONE, F::NEG_INFINITY, F::ONE), (F::ONE, F::NAN, F::ONE), (F::ONE, F::NEG_NAN, F::ONE), + (F::ONE, F::SNAN, F::ONE), + (F::ONE, F::NEG_SNAN, F::ONE), (F::NEG_ONE, F::ZERO, F::ZERO), (F::NEG_ONE, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_ONE, F::ONE, F::ONE), @@ -203,6 +257,8 @@ mod tests { (F::NEG_ONE, F::NEG_INFINITY, F::NEG_ONE), (F::NEG_ONE, F::NAN, F::NEG_ONE), (F::NEG_ONE, F::NEG_NAN, F::NEG_ONE), + (F::NEG_ONE, F::SNAN, F::NEG_ONE), + (F::NEG_ONE, F::NEG_SNAN, F::NEG_ONE), (F::INFINITY, F::ZERO, F::INFINITY), (F::INFINITY, F::NEG_ZERO, F::INFINITY), (F::INFINITY, F::ONE, F::INFINITY), @@ -211,6 +267,8 @@ mod tests { (F::INFINITY, F::NEG_INFINITY, F::INFINITY), (F::INFINITY, F::NAN, F::INFINITY), (F::INFINITY, F::NEG_NAN, F::INFINITY), + (F::INFINITY, F::SNAN, F::INFINITY), + (F::INFINITY, F::NEG_SNAN, F::INFINITY), (F::NEG_INFINITY, F::ZERO, F::ZERO), (F::NEG_INFINITY, F::NEG_ZERO, F::NEG_ZERO), (F::NEG_INFINITY, F::ONE, F::ONE), @@ -219,6 +277,8 @@ mod tests { (F::NEG_INFINITY, F::NEG_INFINITY, F::NEG_INFINITY), (F::NEG_INFINITY, F::NAN, F::NEG_INFINITY), (F::NEG_INFINITY, F::NEG_NAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::SNAN, F::NEG_INFINITY), + (F::NEG_INFINITY, F::NEG_SNAN, F::NEG_INFINITY), (F::NAN, F::ZERO, F::ZERO), (F::NAN, F::NEG_ZERO, F::NEG_ZERO), (F::NAN, F::ONE, F::ONE), @@ -232,17 +292,52 @@ mod tests { (F::NEG_NAN, F::NEG_ONE, F::NEG_ONE), (F::NEG_NAN, F::INFINITY, F::INFINITY), (F::NEG_NAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::SNAN, F::ZERO, F::ZERO), + (F::SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::SNAN, F::ONE, F::ONE), + (F::SNAN, F::NEG_ONE, F::NEG_ONE), + (F::SNAN, F::INFINITY, F::INFINITY), + (F::SNAN, F::NEG_INFINITY, F::NEG_INFINITY), + (F::NEG_SNAN, F::ZERO, F::ZERO), + (F::NEG_SNAN, F::NEG_ZERO, F::NEG_ZERO), + (F::NEG_SNAN, F::ONE, F::ONE), + (F::NEG_SNAN, F::NEG_ONE, F::NEG_ONE), + (F::NEG_SNAN, F::INFINITY, F::INFINITY), + (F::NEG_SNAN, F::NEG_INFINITY, F::NEG_INFINITY), ]; for (x, y, expected) in cases { let actual = f(x, y); - assert_biteq!(actual, expected, "fmaximum_num({}, {})", Hexf(x), Hexf(y)); + assert_biteq!( + actual, + expected, + "fmaximum_num({}, {}) ({}, {})", + Hexf(x), + Hexf(y), + Hexi(x.to_bits()), + Hexi(y.to_bits()), + ); } - // Ordering between NaNs does not matter - assert!(f(F::NAN, F::NEG_NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NAN).is_nan()); - assert!(f(F::NEG_NAN, F::NEG_NAN).is_nan()); + // Selection between NaNs does not matter, it just must be quiet + assert!(f(F::NAN, F::NEG_NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NAN).is_qnan()); + assert!(f(F::NEG_NAN, F::NEG_NAN).is_qnan()); + + // These operations should technically return a qnan, but LLVM optimizes out our + // `* 1.0` canonicalization. + assert!(f(F::NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_NAN, F::SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::NEG_SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::NEG_SNAN, F::SNAN).is_nan()); + assert!(f(F::SNAN, F::NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_NAN).is_nan()); + assert!(f(F::SNAN, F::NEG_SNAN).is_nan()); + assert!(f(F::SNAN, F::SNAN).is_nan()); } #[test] diff --git a/compiler-builtins/libm/src/math/frexp.rs b/compiler-builtins/libm/src/math/frexp.rs index 932111eebc955..af38915a3ac69 100644 --- a/compiler-builtins/libm/src/math/frexp.rs +++ b/compiler-builtins/libm/src/math/frexp.rs @@ -1,21 +1,34 @@ +/// Decompose a float into a normalized value within the range `[0.5, 1)`, and a power of 2. +/// +/// That is, `x * 2^p` will represent the input value. +// Placeholder so we can have `frexpf16` in the `Float` trait. +#[cfg(f16_enabled)] #[cfg_attr(assert_no_panic, no_panic::no_panic)] -pub fn frexp(x: f64) -> (f64, i32) { - let mut y = x.to_bits(); - let ee = ((y >> 52) & 0x7ff) as i32; +pub fn frexpf16(x: f16) -> (f16, i32) { + super::generic::frexp(x) +} - if ee == 0 { - if x != 0.0 { - let x1p64 = f64::from_bits(0x43f0000000000000); - let (x, e) = frexp(x * x1p64); - return (x, e - 64); - } - return (x, 0); - } else if ee == 0x7ff { - return (x, 0); - } +/// Decompose a float into a normalized value within the range `[0.5, 1)`, and a power of 2. +/// +/// That is, `x * 2^p` will represent the input value. +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn frexpf(x: f32) -> (f32, i32) { + super::generic::frexp(x) +} - let e = ee - 0x3fe; - y &= 0x800fffffffffffff; - y |= 0x3fe0000000000000; - return (f64::from_bits(y), e); +/// Decompose a float into a normalized value within the range `[0.5, 1)`, and a power of 2. +/// +/// That is, `x * 2^p` will represent the input value. +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn frexp(x: f64) -> (f64, i32) { + super::generic::frexp(x) +} + +/// Decompose a float into a normalized value within the range `[0.5, 1)`, and a power of 2. +/// +/// That is, `x * 2^p` will represent the input value. +#[cfg(f128_enabled)] +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn frexpf128(x: f128) -> (f128, i32) { + super::generic::frexp(x) } diff --git a/compiler-builtins/libm/src/math/frexpf.rs b/compiler-builtins/libm/src/math/frexpf.rs deleted file mode 100644 index 904bf14f7b8ea..0000000000000 --- a/compiler-builtins/libm/src/math/frexpf.rs +++ /dev/null @@ -1,22 +0,0 @@ -#[cfg_attr(assert_no_panic, no_panic::no_panic)] -pub fn frexpf(x: f32) -> (f32, i32) { - let mut y = x.to_bits(); - let ee: i32 = ((y >> 23) & 0xff) as i32; - - if ee == 0 { - if x != 0.0 { - let x1p64 = f32::from_bits(0x5f800000); - let (x, e) = frexpf(x * x1p64); - return (x, e - 64); - } else { - return (x, 0); - } - } else if ee == 0xff { - return (x, 0); - } - - let e = ee - 0x7e; - y &= 0x807fffff; - y |= 0x3f000000; - (f32::from_bits(y), e) -} diff --git a/compiler-builtins/libm/src/math/generic/ceil.rs b/compiler-builtins/libm/src/math/generic/ceil.rs index 1072ba7c29b63..5584f6503ef58 100644 --- a/compiler-builtins/libm/src/math/generic/ceil.rs +++ b/compiler-builtins/libm/src/math/generic/ceil.rs @@ -46,7 +46,7 @@ pub fn ceil_status(x: F) -> FpResult { F::from_bits(ix) } else { // |x| < 1.0, raise an inexact exception since truncation will happen (unless x == 0). - if ix & F::SIG_MASK == F::Int::ZERO { + if ix & !F::SIGN_MASK == F::Int::ZERO { status = Status::OK; } else { status = Status::INEXACT; @@ -72,103 +72,83 @@ mod tests { use super::*; use crate::support::Hexf; - /// Test against https://en.cppreference.com/w/cpp/numeric/math/ceil - fn spec_test(cases: &[(F, F, Status)]) { - let roundtrip = [ - F::ZERO, - F::ONE, - F::NEG_ONE, - F::NEG_ZERO, - F::INFINITY, - F::NEG_INFINITY, - ]; - - for x in roundtrip { - let FpResult { val, status } = ceil_status(x); - assert_biteq!(val, x, "{}", Hexf(x)); - assert_eq!(status, Status::OK, "{}", Hexf(x)); - } + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0, Status::OK), + (-0.0, -0.0, Status::OK), + (1.0, 1.0, Status::OK), + (-1.0, -1.0, Status::OK), + (<$f>::INFINITY, <$f>::INFINITY, Status::OK), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), + // with rounding + (0.1, 1.0, Status::INEXACT), + (-0.1, -0.0, Status::INEXACT), + (0.5, 1.0, Status::INEXACT), + (-0.5, -0.0, Status::INEXACT), + (0.9, 1.0, Status::INEXACT), + (-0.9, -0.0, Status::INEXACT), + (1.1, 2.0, Status::INEXACT), + (-1.1, -1.0, Status::INEXACT), + (1.5, 2.0, Status::INEXACT), + (-1.5, -1.0, Status::INEXACT), + (1.9, 2.0, Status::INEXACT), + (-1.9, -1.0, Status::INEXACT), + ] + }; + } - for &(x, res, res_stat) in cases { + #[track_caller] + fn check(cases: &[(F, F, Status)]) { + for &(x, exp_res, exp_stat) in cases { let FpResult { val, status } = ceil_status(x); - assert_biteq!(val, res, "{}", Hexf(x)); - assert_eq!(status, res_stat, "{}", Hexf(x)); + assert_biteq!(val, exp_res, "{x:?} {}", Hexf(x)); + assert_eq!( + status, + exp_stat, + "{x:?} {} -> {exp_res:?} {}", + Hexf(x), + Hexf(exp_res) + ); } } - /* Skipping f16 / f128 "sanity_check"s due to rejected literal lexing at MSRV */ - #[test] #[cfg(f16_enabled)] - fn spec_tests_f16() { - let cases = [ - (0.1, 1.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.9, 1.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 2.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.9, 2.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ]; - spec_test::(&cases); - } - - #[test] - fn sanity_check_f32() { - assert_eq!(ceil(1.1f32), 2.0); - assert_eq!(ceil(2.9f32), 3.0); - } - - #[test] - fn spec_tests_f32() { - let cases = [ - (0.1, 1.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.9, 1.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 2.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.9, 2.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ]; - spec_test::(&cases); + fn check_f16() { + check::(&cases!(f16)); + check::(&[ + (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), + (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), + ]); } #[test] - fn sanity_check_f64() { - assert_eq!(ceil(1.1f64), 2.0); - assert_eq!(ceil(2.9f64), 3.0); + fn check_f32() { + check::(&cases!(f32)); + check::(&[ + (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), + (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), + ]); } #[test] - fn spec_tests_f64() { - let cases = [ - (0.1, 1.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.9, 1.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 2.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.9, 2.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ]; - spec_test::(&cases); + fn check_f64() { + check::(&cases!(f64)); + check::(&[ + (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), + (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), + ]); } #[test] #[cfg(f128_enabled)] fn spec_tests_f128() { - let cases = [ - (0.1, 1.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.9, 1.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 2.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.9, 2.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ]; - spec_test::(&cases); + check::(&cases!(f128)); + check::(&[ + (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), + (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), + ]); } } diff --git a/compiler-builtins/libm/src/math/generic/floor.rs b/compiler-builtins/libm/src/math/generic/floor.rs index e6dfd8866a425..7045229c0c75a 100644 --- a/compiler-builtins/libm/src/math/generic/floor.rs +++ b/compiler-builtins/libm/src/math/generic/floor.rs @@ -26,7 +26,6 @@ pub fn floor_status(x: F) -> FpResult { return FpResult::ok(x); } - let status; let res = if e >= 0 { // |x| >= 1.0 let m = F::SIG_MASK >> e.unsigned(); @@ -35,9 +34,6 @@ pub fn floor_status(x: F) -> FpResult { return FpResult::ok(x); } - // Otherwise, raise an inexact exception. - status = Status::INEXACT; - if x.is_sign_negative() { ix += m; } @@ -45,26 +41,22 @@ pub fn floor_status(x: F) -> FpResult { ix &= !m; F::from_bits(ix) } else { - // |x| < 1.0, raise an inexact exception since truncation will happen. - if ix & F::SIG_MASK == F::Int::ZERO { - status = Status::OK; - } else { - status = Status::INEXACT; + // |x| < 1.0, zero or inexact with truncation + + if (ix & !F::SIGN_MASK) == F::Int::ZERO { + return FpResult::ok(x); } if x.is_sign_positive() { // 0.0 <= x < 1.0; rounding down goes toward +0.0. F::ZERO - } else if ix << 1 != zero { + } else { // -1.0 < x < 0.0; rounding down goes toward -1.0. F::NEG_ONE - } else { - // -0.0 remains unchanged - x } }; - FpResult::new(res, status) + FpResult::new(res, Status::INEXACT) } #[cfg(test)] @@ -72,86 +64,83 @@ mod tests { use super::*; use crate::support::Hexf; - /// Test against https://en.cppreference.com/w/cpp/numeric/math/floor - fn spec_test(cases: &[(F, F, Status)]) { - let roundtrip = [ - F::ZERO, - F::ONE, - F::NEG_ONE, - F::NEG_ZERO, - F::INFINITY, - F::NEG_INFINITY, - ]; - - for x in roundtrip { - let FpResult { val, status } = floor_status(x); - assert_biteq!(val, x, "{}", Hexf(x)); - assert_eq!(status, Status::OK, "{}", Hexf(x)); - } + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0, Status::OK), + (-0.0, -0.0, Status::OK), + (1.0, 1.0, Status::OK), + (-1.0, -1.0, Status::OK), + (<$f>::INFINITY, <$f>::INFINITY, Status::OK), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), + // with rounding + (0.1, 0.0, Status::INEXACT), + (-0.1, -1.0, Status::INEXACT), + (0.5, 0.0, Status::INEXACT), + (-0.5, -1.0, Status::INEXACT), + (0.9, 0.0, Status::INEXACT), + (-0.9, -1.0, Status::INEXACT), + (1.1, 1.0, Status::INEXACT), + (-1.1, -2.0, Status::INEXACT), + (1.5, 1.0, Status::INEXACT), + (-1.5, -2.0, Status::INEXACT), + (1.9, 1.0, Status::INEXACT), + (-1.9, -2.0, Status::INEXACT), + ] + }; + } - for &(x, res, res_stat) in cases { + #[track_caller] + fn check(cases: &[(F, F, Status)]) { + for &(x, exp_res, exp_stat) in cases { let FpResult { val, status } = floor_status(x); - assert_biteq!(val, res, "{}", Hexf(x)); - assert_eq!(status, res_stat, "{}", Hexf(x)); + assert_biteq!(val, exp_res, "{x:?} {}", Hexf(x)); + assert_eq!( + status, + exp_stat, + "{x:?} {} -> {exp_res:?} {}", + Hexf(x), + Hexf(exp_res) + ); } } - /* Skipping f16 / f128 "sanity_check"s and spec cases due to rejected literal lexing at MSRV */ - #[test] #[cfg(f16_enabled)] - fn spec_tests_f16() { - let cases = []; - spec_test::(&cases); - } - - #[test] - fn sanity_check_f32() { - assert_eq!(floor(0.5f32), 0.0); - assert_eq!(floor(1.1f32), 1.0); - assert_eq!(floor(2.9f32), 2.0); - } - - #[test] - fn spec_tests_f32() { - let cases = [ - (0.1, 0.0, Status::INEXACT), - (-0.1, -1.0, Status::INEXACT), - (0.9, 0.0, Status::INEXACT), - (-0.9, -1.0, Status::INEXACT), - (1.1, 1.0, Status::INEXACT), - (-1.1, -2.0, Status::INEXACT), - (1.9, 1.0, Status::INEXACT), - (-1.9, -2.0, Status::INEXACT), - ]; - spec_test::(&cases); + fn check_f16() { + check::(&cases!(f16)); + check::(&[ + (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), + (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), + ]); } #[test] - fn sanity_check_f64() { - assert_eq!(floor(1.1f64), 1.0); - assert_eq!(floor(2.9f64), 2.0); + fn check_f32() { + check::(&cases!(f32)); + check::(&[ + (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), + (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), + ]); } #[test] - fn spec_tests_f64() { - let cases = [ - (0.1, 0.0, Status::INEXACT), - (-0.1, -1.0, Status::INEXACT), - (0.9, 0.0, Status::INEXACT), - (-0.9, -1.0, Status::INEXACT), - (1.1, 1.0, Status::INEXACT), - (-1.1, -2.0, Status::INEXACT), - (1.9, 1.0, Status::INEXACT), - (-1.9, -2.0, Status::INEXACT), - ]; - spec_test::(&cases); + fn check_f64() { + check::(&cases!(f64)); + check::(&[ + (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), + (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), + ]); } #[test] #[cfg(f128_enabled)] fn spec_tests_f128() { - let cases = []; - spec_test::(&cases); + check::(&cases!(f128)); + check::(&[ + (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), + (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), + ]); } } diff --git a/compiler-builtins/libm/src/math/generic/fmax.rs b/compiler-builtins/libm/src/math/generic/fmax.rs index b05804704d03e..bdd46cc38a818 100644 --- a/compiler-builtins/libm/src/math/generic/fmax.rs +++ b/compiler-builtins/libm/src/math/generic/fmax.rs @@ -8,11 +8,15 @@ //! - Otherwise, either `x` or `y`, canonicalized //! - -0.0 and +0.0 may be disregarded (unlike newer operations) //! -//! Excluded from our implementation is sNaN handling. +//! We do not treat sNaN and qNaN differently; even though IEEE technically requires this, (a call +//! with sNaN should return qNaN rather than the other result), it breaks associativity so isn't +//! desired behavior. C23 does not differentiate between sNaN and qNaN, so we do not either. More +//! on the problems with `minNum` [here][minnum-removal]. //! -//! More on the differences: [link]. +//! IEEE also specifies that a sNaN in either argument should signal invalid, but we do not +//! implement this. //! -//! [link]: https://grouper.ieee.org/groups/msc/ANSI_IEEE-Std-754-2019/background/minNum_maxNum_Removal_Demotion_v3.pdf +//! [minnum-removal]: https://grouper.ieee.org/groups/msc/ANSI_IEEE-Std-754-2019/background/minNum_maxNum_Removal_Demotion_v3.pdf use crate::support::Float; diff --git a/compiler-builtins/libm/src/math/generic/fmaximum.rs b/compiler-builtins/libm/src/math/generic/fmaximum.rs index 55a031e18ee8d..1fa48f964804e 100644 --- a/compiler-builtins/libm/src/math/generic/fmaximum.rs +++ b/compiler-builtins/libm/src/math/generic/fmaximum.rs @@ -7,7 +7,8 @@ //! - +0.0 if x and y are zero with opposite signs //! - qNaN if either operation is NaN //! -//! Excluded from our implementation is sNaN handling. +//! Note that the IEEE 754-2019 specifies that a sNaN in either argument should signal invalid, +//! but we do not implement this. use crate::support::Float; diff --git a/compiler-builtins/libm/src/math/generic/fmaximum_num.rs b/compiler-builtins/libm/src/math/generic/fmaximum_num.rs index 2dc60b2d237f5..c7ca50a89dc8d 100644 --- a/compiler-builtins/libm/src/math/generic/fmaximum_num.rs +++ b/compiler-builtins/libm/src/math/generic/fmaximum_num.rs @@ -9,7 +9,8 @@ //! - Non-NaN if one operand is NaN //! - qNaN if both operands are NaNx //! -//! Excluded from our implementation is sNaN handling. +//! Note that the IEEE 754-2019 specifies that a sNaN in either argument should signal invalid, +//! but we do not implement this. use crate::support::Float; diff --git a/compiler-builtins/libm/src/math/generic/fmin.rs b/compiler-builtins/libm/src/math/generic/fmin.rs index e2245bf9e137b..e7755e82345c6 100644 --- a/compiler-builtins/libm/src/math/generic/fmin.rs +++ b/compiler-builtins/libm/src/math/generic/fmin.rs @@ -8,11 +8,15 @@ //! - Otherwise, either `x` or `y`, canonicalized //! - -0.0 and +0.0 may be disregarded (unlike newer operations) //! -//! Excluded from our implementation is sNaN handling. +//! We do not treat sNaN and qNaN differently; even though IEEE technically requires this, (a call +//! with sNaN should return qNaN rather than the other result), it breaks associativity so isn't +//! desired behavior. C23 does not differentiate between sNaN and qNaN, so we do not either. More +//! on the problems with `minNum` [here][minnum-removal]. //! -//! More on the differences: [link]. +//! IEEE also specifies that a sNaN in either argument should signal invalid, but we do not +//! implement this. //! -//! [link]: https://grouper.ieee.org/groups/msc/ANSI_IEEE-Std-754-2019/background/minNum_maxNum_Removal_Demotion_v3.pdf +//! [minnum-removal]: https://grouper.ieee.org/groups/msc/ANSI_IEEE-Std-754-2019/background/minNum_maxNum_Removal_Demotion_v3.pdf use crate::support::Float; diff --git a/compiler-builtins/libm/src/math/generic/fminimum.rs b/compiler-builtins/libm/src/math/generic/fminimum.rs index aa68b1291d42b..82e72d6440649 100644 --- a/compiler-builtins/libm/src/math/generic/fminimum.rs +++ b/compiler-builtins/libm/src/math/generic/fminimum.rs @@ -7,7 +7,8 @@ //! - -0.0 if x and y are zero with opposite signs //! - qNaN if either operation is NaN //! -//! Excluded from our implementation is sNaN handling. +//! Note that the IEEE 754-2019 specifies that a sNaN in either argument should signal invalid, +//! but we do not implement this. use crate::support::Float; diff --git a/compiler-builtins/libm/src/math/generic/fminimum_num.rs b/compiler-builtins/libm/src/math/generic/fminimum_num.rs index 265bd4605ce39..5b5271b123bad 100644 --- a/compiler-builtins/libm/src/math/generic/fminimum_num.rs +++ b/compiler-builtins/libm/src/math/generic/fminimum_num.rs @@ -9,7 +9,8 @@ //! - Non-NaN if one operand is NaN //! - qNaN if both operands are NaNx //! -//! Excluded from our implementation is sNaN handling. +//! Note that the IEEE 754-2019 specifies that a sNaN in either argument should signal invalid, +//! but we do not implement this. use crate::support::Float; diff --git a/compiler-builtins/libm/src/math/generic/frexp.rs b/compiler-builtins/libm/src/math/generic/frexp.rs new file mode 100644 index 0000000000000..cbf5b100ba0f8 --- /dev/null +++ b/compiler-builtins/libm/src/math/generic/frexp.rs @@ -0,0 +1,26 @@ +use super::super::{CastFrom, Float}; + +#[inline] +pub fn frexp(x: F) -> (F, i32) { + let mut ix = x.to_bits(); + let mut ee = x.ex() as i32; + + if ee == 0 { + if x == F::ZERO { + return (x, 0); + } + + // Subnormals, needs to be normalized first + ix &= F::SIG_MASK; + (ee, ix) = F::normalize(ix); + ix |= x.to_bits() & F::SIGN_MASK; + } else if ee == F::EXP_SAT as i32 { + // inf or NaN + return (x, 0); + } + + let e = ee - (F::EXP_BIAS as i32 - 1); + ix &= F::SIGN_MASK | F::SIG_MASK; + ix |= F::Int::cast_from(F::EXP_BIAS - 1) << F::SIG_BITS; + (F::from_bits(ix), e) +} diff --git a/compiler-builtins/libm/src/math/generic/ilogb.rs b/compiler-builtins/libm/src/math/generic/ilogb.rs new file mode 100644 index 0000000000000..02a7d6b30b103 --- /dev/null +++ b/compiler-builtins/libm/src/math/generic/ilogb.rs @@ -0,0 +1,35 @@ +use super::super::{Float, MinInt}; + +const FP_ILOGBNAN: i32 = i32::MIN; +const FP_ILOGB0: i32 = FP_ILOGBNAN; + +#[inline] +pub fn ilogb(x: F) -> i32 { + let zero = F::Int::ZERO; + let mut i = x.to_bits(); + let e = x.ex() as i32; + + if e == 0 { + i <<= F::EXP_BITS + 1; + if i == F::Int::ZERO { + force_eval!(0.0 / 0.0); + return FP_ILOGB0; + } + /* subnormal x */ + let mut e = -(F::EXP_BIAS as i32); + while i >> (F::BITS - 1) == zero { + e -= 1; + i <<= 1; + } + e + } else if e == F::EXP_SAT as i32 { + force_eval!(0.0 / 0.0); + if i << (F::EXP_BITS + 1) != zero { + FP_ILOGBNAN + } else { + i32::MAX + } + } else { + e - F::EXP_BIAS as i32 + } +} diff --git a/compiler-builtins/libm/src/math/generic/mod.rs b/compiler-builtins/libm/src/math/generic/mod.rs index 9d497a03f5447..114fcddf516e5 100644 --- a/compiler-builtins/libm/src/math/generic/mod.rs +++ b/compiler-builtins/libm/src/math/generic/mod.rs @@ -15,6 +15,8 @@ mod fmin; mod fminimum; mod fminimum_num; mod fmod; +mod frexp; +mod ilogb; mod rint; mod round; mod scalbn; @@ -35,6 +37,8 @@ pub use fmin::fmin; pub use fminimum::fminimum; pub use fminimum_num::fminimum_num; pub use fmod::fmod; +pub use frexp::frexp; +pub use ilogb::ilogb; pub use rint::rint_round; pub use round::round; pub use scalbn::scalbn; diff --git a/compiler-builtins/libm/src/math/generic/sqrt.rs b/compiler-builtins/libm/src/math/generic/sqrt.rs index 9481c4cdb7bbe..e97a43d349569 100644 --- a/compiler-builtins/libm/src/math/generic/sqrt.rs +++ b/compiler-builtins/libm/src/math/generic/sqrt.rs @@ -419,9 +419,7 @@ mod tests { fn conformance_tests_f16() { let cases = [ (f16::PI, 0x3f17_u16), - // 10_000.0, using a hex literal for MSRV hack (Rust < 1.67 checks literal widths as - // part of the AST, so the `cfg` is irrelevant here). - (f16::from_bits(0x70e2), 0x5640_u16), + (10000.0_f16, 0x5640_u16), (f16::from_bits(0x0000000f), 0x13bf_u16), (f16::INFINITY, f16::INFINITY.to_bits()), ]; diff --git a/compiler-builtins/libm/src/math/generic/trunc.rs b/compiler-builtins/libm/src/math/generic/trunc.rs index d5b444d15dfc0..7f18eb42e884a 100644 --- a/compiler-builtins/libm/src/math/generic/trunc.rs +++ b/compiler-builtins/libm/src/math/generic/trunc.rs @@ -10,38 +10,34 @@ pub fn trunc(x: F) -> F { #[inline] pub fn trunc_status(x: F) -> FpResult { - let mut xi: F::Int = x.to_bits(); + let xi: F::Int = x.to_bits(); let e: i32 = x.exp_unbiased(); - // C1: The represented value has no fractional part, so no truncation is needed + // The represented value has no fractional part, so no truncation is needed if e >= F::SIG_BITS as i32 { return FpResult::ok(x); } - let mask = if e < 0 { - // C2: If the exponent is negative, the result will be zero so we mask out everything + let clear_mask = if e < 0 { + // If the exponent is negative, the result will be zero so we clear everything // except the sign. - F::SIGN_MASK + !F::SIGN_MASK } else { - // C3: Otherwise, we mask out the last `e` bits of the significand. - !(F::SIG_MASK >> e.unsigned()) + // Otherwise, we keep `e` fractional bits and clear the rest. + F::SIG_MASK >> e.unsigned() }; - // C4: If the to-be-masked-out portion is already zero, we have an exact result - if (xi & !mask) == IntTy::::ZERO { - return FpResult::ok(x); - } - - // C5: Otherwise the result is inexact and we will truncate. Raise `FE_INEXACT`, mask the - // result, and return. - - let status = if xi & F::SIG_MASK == F::Int::ZERO { + let cleared = xi & clear_mask; + let status = if cleared == IntTy::::ZERO { + // If the to-be-zeroed portion is already zero, we have an exact result. Status::OK } else { + // Otherwise the result is inexact and we will truncate, so indicate `FE_INEXACT`. Status::INEXACT }; - xi &= mask; - FpResult::new(F::from_bits(xi), status) + + // Now zero the bits we need to truncate and return. + FpResult::new(F::from_bits(xi ^ cleared), status) } #[cfg(test)] @@ -49,100 +45,83 @@ mod tests { use super::*; use crate::support::Hexf; - fn spec_test(cases: &[(F, F, Status)]) { - let roundtrip = [ - F::ZERO, - F::ONE, - F::NEG_ONE, - F::NEG_ZERO, - F::INFINITY, - F::NEG_INFINITY, - ]; - - for x in roundtrip { - let FpResult { val, status } = trunc_status(x); - assert_biteq!(val, x, "{}", Hexf(x)); - assert_eq!(status, Status::OK, "{}", Hexf(x)); - } + macro_rules! cases { + ($f:ty) => { + [ + // roundtrip + (0.0, 0.0, Status::OK), + (-0.0, -0.0, Status::OK), + (1.0, 1.0, Status::OK), + (-1.0, -1.0, Status::OK), + (<$f>::INFINITY, <$f>::INFINITY, Status::OK), + (<$f>::NEG_INFINITY, <$f>::NEG_INFINITY, Status::OK), + // with rounding + (0.1, 0.0, Status::INEXACT), + (-0.1, -0.0, Status::INEXACT), + (0.5, 0.0, Status::INEXACT), + (-0.5, -0.0, Status::INEXACT), + (0.9, 0.0, Status::INEXACT), + (-0.9, -0.0, Status::INEXACT), + (1.1, 1.0, Status::INEXACT), + (-1.1, -1.0, Status::INEXACT), + (1.5, 1.0, Status::INEXACT), + (-1.5, -1.0, Status::INEXACT), + (1.9, 1.0, Status::INEXACT), + (-1.9, -1.0, Status::INEXACT), + ] + }; + } - for &(x, res, res_stat) in cases { + #[track_caller] + fn check(cases: &[(F, F, Status)]) { + for &(x, exp_res, exp_stat) in cases { let FpResult { val, status } = trunc_status(x); - assert_biteq!(val, res, "{}", Hexf(x)); - assert_eq!(status, res_stat, "{}", Hexf(x)); + assert_biteq!(val, exp_res, "{x:?} {}", Hexf(x)); + assert_eq!( + status, + exp_stat, + "{x:?} {} -> {exp_res:?} {}", + Hexf(x), + Hexf(exp_res) + ); } } - /* Skipping f16 / f128 "sanity_check"s and spec cases due to rejected literal lexing at MSRV */ - #[test] #[cfg(f16_enabled)] - fn spec_tests_f16() { - let cases = []; - spec_test::(&cases); - } - - #[test] - fn sanity_check_f32() { - assert_eq!(trunc(0.5f32), 0.0); - assert_eq!(trunc(1.1f32), 1.0); - assert_eq!(trunc(2.9f32), 2.0); - } - - #[test] - fn spec_tests_f32() { - let cases = [ - (0.1, 0.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.9, 0.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 1.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.9, 1.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ]; - spec_test::(&cases); - - assert_biteq!(trunc(1.1f32), 1.0); - assert_biteq!(trunc(1.1f64), 1.0); - - // C1 - assert_biteq!(trunc(hf32!("0x1p23")), hf32!("0x1p23")); - assert_biteq!(trunc(hf64!("0x1p52")), hf64!("0x1p52")); - assert_biteq!(trunc(hf32!("-0x1p23")), hf32!("-0x1p23")); - assert_biteq!(trunc(hf64!("-0x1p52")), hf64!("-0x1p52")); - - // C2 - assert_biteq!(trunc(hf32!("0x1p-1")), 0.0); - assert_biteq!(trunc(hf64!("0x1p-1")), 0.0); - assert_biteq!(trunc(hf32!("-0x1p-1")), -0.0); - assert_biteq!(trunc(hf64!("-0x1p-1")), -0.0); + fn check_f16() { + check::(&cases!(f16)); + check::(&[ + (hf16!("0x1p10"), hf16!("0x1p10"), Status::OK), + (hf16!("-0x1p10"), hf16!("-0x1p10"), Status::OK), + ]); } #[test] - fn sanity_check_f64() { - assert_eq!(trunc(1.1f64), 1.0); - assert_eq!(trunc(2.9f64), 2.0); + fn check_f32() { + check::(&cases!(f32)); + check::(&[ + (hf32!("0x1p23"), hf32!("0x1p23"), Status::OK), + (hf32!("-0x1p23"), hf32!("-0x1p23"), Status::OK), + ]); } #[test] - fn spec_tests_f64() { - let cases = [ - (0.1, 0.0, Status::INEXACT), - (-0.1, -0.0, Status::INEXACT), - (0.9, 0.0, Status::INEXACT), - (-0.9, -0.0, Status::INEXACT), - (1.1, 1.0, Status::INEXACT), - (-1.1, -1.0, Status::INEXACT), - (1.9, 1.0, Status::INEXACT), - (-1.9, -1.0, Status::INEXACT), - ]; - spec_test::(&cases); + fn check_f64() { + check::(&cases!(f64)); + check::(&[ + (hf64!("0x1p52"), hf64!("0x1p52"), Status::OK), + (hf64!("-0x1p52"), hf64!("-0x1p52"), Status::OK), + ]); } #[test] #[cfg(f128_enabled)] fn spec_tests_f128() { - let cases = []; - spec_test::(&cases); + check::(&cases!(f128)); + check::(&[ + (hf128!("0x1p112"), hf128!("0x1p112"), Status::OK), + (hf128!("-0x1p112"), hf128!("-0x1p112"), Status::OK), + ]); } } diff --git a/compiler-builtins/libm/src/math/ilogb.rs b/compiler-builtins/libm/src/math/ilogb.rs index ef774f6ad3a65..4c3f0a6aa0452 100644 --- a/compiler-builtins/libm/src/math/ilogb.rs +++ b/compiler-builtins/libm/src/math/ilogb.rs @@ -1,32 +1,25 @@ -const FP_ILOGBNAN: i32 = -1 - 0x7fffffff; -const FP_ILOGB0: i32 = FP_ILOGBNAN; +/// Extract the binary exponent of `x`. +#[cfg(f16_enabled)] +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn ilogbf16(x: f16) -> i32 { + super::generic::ilogb(x) +} +/// Extract the binary exponent of `x`. +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn ilogbf(x: f32) -> i32 { + super::generic::ilogb(x) +} + +/// Extract the binary exponent of `x`. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn ilogb(x: f64) -> i32 { - let mut i: u64 = x.to_bits(); - let e = ((i >> 52) & 0x7ff) as i32; + super::generic::ilogb(x) +} - if e == 0 { - i <<= 12; - if i == 0 { - force_eval!(0.0 / 0.0); - return FP_ILOGB0; - } - /* subnormal x */ - let mut e = -0x3ff; - while (i >> 63) == 0 { - e -= 1; - i <<= 1; - } - e - } else if e == 0x7ff { - force_eval!(0.0 / 0.0); - if (i << 12) != 0 { - FP_ILOGBNAN - } else { - i32::MAX - } - } else { - e - 0x3ff - } +/// Extract the binary exponent of `x`. +#[cfg(f128_enabled)] +#[cfg_attr(assert_no_panic, no_panic::no_panic)] +pub fn ilogbf128(x: f128) -> i32 { + super::generic::ilogb(x) } diff --git a/compiler-builtins/libm/src/math/ilogbf.rs b/compiler-builtins/libm/src/math/ilogbf.rs deleted file mode 100644 index 5b0cb46ec558b..0000000000000 --- a/compiler-builtins/libm/src/math/ilogbf.rs +++ /dev/null @@ -1,28 +0,0 @@ -const FP_ILOGBNAN: i32 = -1 - 0x7fffffff; -const FP_ILOGB0: i32 = FP_ILOGBNAN; - -#[cfg_attr(assert_no_panic, no_panic::no_panic)] -pub fn ilogbf(x: f32) -> i32 { - let mut i = x.to_bits(); - let e = ((i >> 23) & 0xff) as i32; - - if e == 0 { - i <<= 9; - if i == 0 { - force_eval!(0.0 / 0.0); - return FP_ILOGB0; - } - /* subnormal x */ - let mut e = -0x7f; - while (i >> 31) == 0 { - e -= 1; - i <<= 1; - } - e - } else if e == 0xff { - force_eval!(0.0 / 0.0); - if (i << 9) != 0 { FP_ILOGBNAN } else { i32::MAX } - } else { - e - 0x7f - } -} diff --git a/compiler-builtins/libm/src/math/lgamma_r.rs b/compiler-builtins/libm/src/math/lgamma_r.rs index 38eb270f68390..f3c6fef1464d8 100644 --- a/compiler-builtins/libm/src/math/lgamma_r.rs +++ b/compiler-builtins/libm/src/math/lgamma_r.rs @@ -79,6 +79,7 @@ */ use super::{floor, k_cos, k_sin, log}; +use crate::support::unchecked_div_i32; const PI: f64 = 3.14159265358979311600e+00; /* 0x400921FB, 0x54442D18 */ const A0: f64 = 7.72156649015328655494e-02; /* 0x3FB3C467, 0xE37DB0C8 */ @@ -152,7 +153,8 @@ fn sin_pi(mut x: f64) -> f64 { x = 2.0 * (x * 0.5 - floor(x * 0.5)); /* x mod 2.0 */ n = (x * 4.0) as i32; - n = div!(n + 1, 2); + // SAFETY: nonzero divisor, nonnegative dividend (`n < 8`). + n = unsafe { unchecked_div_i32(n + 1, 2) }; x -= (n as f64) * 0.5; x *= PI; diff --git a/compiler-builtins/libm/src/math/lgammaf_r.rs b/compiler-builtins/libm/src/math/lgammaf_r.rs index a0b6a678a6709..5c087f14d7df2 100644 --- a/compiler-builtins/libm/src/math/lgammaf_r.rs +++ b/compiler-builtins/libm/src/math/lgammaf_r.rs @@ -14,6 +14,7 @@ */ use super::{floorf, k_cosf, k_sinf, logf}; +use crate::support::unchecked_div_isize; const PI: f32 = 3.1415927410e+00; /* 0x40490fdb */ const A0: f32 = 7.7215664089e-02; /* 0x3d9e233f */ @@ -88,7 +89,8 @@ fn sin_pi(mut x: f32) -> f32 { x = 2.0 * (x * 0.5 - floorf(x * 0.5)); /* x mod 2.0 */ n = (x * 4.0) as isize; - n = div!(n + 1, 2); + // SAFETY: nonzero divisor, nonnegative dividend (`n < 8`). + n = unsafe { unchecked_div_isize(n + 1, 2) }; y = (x as f64) - (n as f64) * 0.5; y *= 3.14159265358979323846; match n { diff --git a/compiler-builtins/libm/src/math/mod.rs b/compiler-builtins/libm/src/math/mod.rs index 8eecfe5667d1f..4bee4478164a0 100644 --- a/compiler-builtins/libm/src/math/mod.rs +++ b/compiler-builtins/libm/src/math/mod.rs @@ -58,24 +58,6 @@ macro_rules! i { }; } -// Temporary macro to avoid panic codegen for division (in debug mode too). At -// the time of this writing this is only used in a few places, and once -// rust-lang/rust#72751 is fixed then this macro will no longer be necessary and -// the native `/` operator can be used and panics won't be codegen'd. -#[cfg(any(debug_assertions, not(intrinsics_enabled)))] -macro_rules! div { - ($a:expr, $b:expr) => { - $a / $b - }; -} - -#[cfg(all(not(debug_assertions), intrinsics_enabled))] -macro_rules! div { - ($a:expr, $b:expr) => { - unsafe { core::intrinsics::unchecked_div($a, $b) } - }; -} - // `support` may be public for testing #[macro_use] #[cfg(feature = "unstable-public-internals")] @@ -166,11 +148,9 @@ mod fminimum_fmaximum; mod fminimum_fmaximum_num; mod fmod; mod frexp; -mod frexpf; mod hypot; mod hypotf; mod ilogb; -mod ilogbf; mod j0; mod j0f; mod j1; @@ -260,12 +240,10 @@ pub use self::fmin_fmax::{fmax, fmaxf, fmin, fminf}; pub use self::fminimum_fmaximum::{fmaximum, fmaximumf, fminimum, fminimumf}; pub use self::fminimum_fmaximum_num::{fmaximum_num, fmaximum_numf, fminimum_num, fminimum_numf}; pub use self::fmod::{fmod, fmodf}; -pub use self::frexp::frexp; -pub use self::frexpf::frexpf; +pub use self::frexp::{frexp, frexpf}; pub use self::hypot::hypot; pub use self::hypotf::hypotf; -pub use self::ilogb::ilogb; -pub use self::ilogbf::ilogbf; +pub use self::ilogb::{ilogb, ilogbf}; pub use self::j0::{j0, y0}; pub use self::j0f::{j0f, y0f}; pub use self::j1::{j1, y1}; @@ -326,6 +304,8 @@ cfg_if! { pub use self::fminimum_fmaximum::{fmaximumf16, fminimumf16}; pub use self::fminimum_fmaximum_num::{fmaximum_numf16, fminimum_numf16}; pub use self::fmod::fmodf16; + pub use self::frexp::frexpf16; + pub use self::ilogb::ilogbf16; pub use self::ldexp::ldexpf16; pub use self::rint::rintf16; pub use self::round::roundf16; @@ -353,6 +333,8 @@ cfg_if! { pub use self::fminimum_fmaximum::{fmaximumf128, fminimumf128}; pub use self::fminimum_fmaximum_num::{fmaximum_numf128, fminimum_numf128}; pub use self::fmod::fmodf128; + pub use self::frexp::frexpf128; + pub use self::ilogb::ilogbf128; pub use self::ldexp::ldexpf128; pub use self::rint::rintf128; pub use self::round::roundf128; diff --git a/compiler-builtins/libm/src/math/rem_pio2_large.rs b/compiler-builtins/libm/src/math/rem_pio2_large.rs index bb2c532916b2a..841a51b84c278 100644 --- a/compiler-builtins/libm/src/math/rem_pio2_large.rs +++ b/compiler-builtins/libm/src/math/rem_pio2_large.rs @@ -1,4 +1,6 @@ #![allow(unused_unsafe)] +// FIXME(clippy): the suggested fix is bad but the code as-written could be better +#![allow(clippy::explicit_counter_loop)] /* origin: FreeBSD /usr/src/lib/msun/src/k_rem_pio2.c */ /* * ==================================================== @@ -255,7 +257,7 @@ pub(crate) fn rem_pio2_large(x: &[f64], y: &mut [f64], e0: i32, prec: usize) -> /* determine jx,jv,q0, note that 3>q0 */ let jx = nx - 1; - let mut jv = div!(e0 - 3, 24); + let mut jv = (e0 - 3) / 24; if jv < 0 { jv = 0; } diff --git a/compiler-builtins/libm/src/math/sincosf.rs b/compiler-builtins/libm/src/math/sincosf.rs index c4beb5267f280..1d15abe543067 100644 --- a/compiler-builtins/libm/src/math/sincosf.rs +++ b/compiler-builtins/libm/src/math/sincosf.rs @@ -122,8 +122,6 @@ pub fn sincosf(x: f32) -> (f32, f32) { } } -// PowerPC tests are failing on LLVM 13: https://github.com/rust-lang/rust/issues/88520 -#[cfg(not(target_arch = "powerpc64"))] #[cfg(test)] mod tests { use super::sincosf; diff --git a/compiler-builtins/libm/src/math/support/big/tests.rs b/compiler-builtins/libm/src/math/support/big/tests.rs index 0c32f445c1368..2eafed50a2757 100644 --- a/compiler-builtins/libm/src/math/support/big/tests.rs +++ b/compiler-builtins/libm/src/math/support/big/tests.rs @@ -261,8 +261,6 @@ fn shr_u256() { #[test] #[should_panic] #[cfg(debug_assertions)] -// FIXME(ppc): ppc64le seems to have issues with `should_panic` tests. -#[cfg(not(all(target_arch = "powerpc64", target_endian = "little")))] fn shr_u256_overflow() { // Like regular shr, panic on overflow with debug assertions let _ = u256::MAX >> 256; diff --git a/compiler-builtins/libm/src/math/support/env.rs b/compiler-builtins/libm/src/math/support/env.rs index 53ae32f658dbe..0f89799ed9189 100644 --- a/compiler-builtins/libm/src/math/support/env.rs +++ b/compiler-builtins/libm/src/math/support/env.rs @@ -49,10 +49,14 @@ pub enum Round { } /// IEEE 754 exception status flags. -#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[derive(Clone, Copy, PartialEq, Eq)] pub struct Status(u8); impl Status { + /* Note that if we ever store/load this to/from floating point control status registers, it + * may be worth making these values platform-dependent to line up with register layout + * to avoid bit swapping. For the time being, this isn't a concern. */ + /// Default status indicating no errors. pub const OK: Self = Self(0); @@ -74,7 +78,7 @@ impl Status { /// result is -inf. /// `x / y` when `x != 0.0` and `y == 0.0`, #[cfg_attr(not(feature = "unstable-public-internals"), allow(dead_code))] - pub const DIVIDE_BY_ZERO: Self = Self(1 << 2); + pub const DIVIDE_BY_ZERO: Self = Self(1 << 1); /// The result exceeds the maximum finite value. /// @@ -82,14 +86,14 @@ impl Status { /// on the intermediate result. `Zero` rounds to the signed maximum finite. `Positive` and /// `Negative` round to signed maximum finite in one direction, signed infinity in the other. #[cfg_attr(not(feature = "unstable-public-internals"), allow(dead_code))] - pub const OVERFLOW: Self = Self(1 << 3); + pub const OVERFLOW: Self = Self(1 << 2); /// The result is subnormal and lost precision. - pub const UNDERFLOW: Self = Self(1 << 4); + pub const UNDERFLOW: Self = Self(1 << 3); /// The finite-precision result does not match that of infinite precision, and the reason /// is not represented by one of the other flags. - pub const INEXACT: Self = Self(1 << 5); + pub const INEXACT: Self = Self(1 << 4); /// True if `UNDERFLOW` is set. #[cfg_attr(not(feature = "unstable-public-internals"), allow(dead_code))] @@ -128,3 +132,38 @@ impl Status { Self(self.0 | rhs.0) } } + +#[cfg(any(test, feature = "unstable-public-internals"))] +impl core::fmt::Debug for Status { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + // shift -> flag map + let names = &[ + "INVALID", + "DIVIDE_BY_ZERO", + "OVERFLOW", + "UNDERFLOW", + "INEXACT", + ]; + + write!(f, "Status(")?; + let mut any = false; + for shift in 0..u8::BITS { + if self.0 & (1 << shift) != 0 { + if any { + write!(f, " | ")?; + } + match names.get(shift as usize) { + Some(name) => write!(f, "{name}")?, + None => write!(f, "UNKNOWN(1 << {shift})")?, + } + any = true; + } + } + + if !any { + write!(f, "OK")?; + } + write!(f, ")")?; + Ok(()) + } +} diff --git a/compiler-builtins/libm/src/math/support/float_traits.rs b/compiler-builtins/libm/src/math/support/float_traits.rs index 4e5011f62e0f6..944546601c9ca 100644 --- a/compiler-builtins/libm/src/math/support/float_traits.rs +++ b/compiler-builtins/libm/src/math/support/float_traits.rs @@ -1,9 +1,13 @@ -#![allow(unknown_lints)] // FIXME(msrv) we shouldn't need this - use core::{fmt, mem, ops}; use super::int_traits::{CastFrom, Int, MinInt}; +/// Whether MIPS sNaN/qNaNs should be used. +/// +/// Note that MIPS is doing some general migration here, though this is only available on (rare) +/// modern MIPS hardware per discussion at . +const MIPS_NAN: bool = cfg!(target_arch = "mips") || cfg!(target_arch = "mips64"); + /// Trait for some basic operations on floats // #[allow(dead_code)] #[allow(dead_code)] // Some constants are only used with tests @@ -36,10 +40,16 @@ pub trait Float: const NEG_ONE: Self; const INFINITY: Self; const NEG_INFINITY: Self; - const NAN: Self; - const NEG_NAN: Self; const MAX: Self; const MIN: Self; + + /// Quiet NaN. + const NAN: Self; + /// Signaling NaN. + const SNAN: Self; + const NEG_NAN: Self; + const NEG_SNAN: Self; + const EPSILON: Self; const PI: Self; const NEG_PI: Self; @@ -86,6 +96,9 @@ pub trait Float: /// The implicit bit of the float format const IMPLICIT_BIT: Self::Int; + /// A mask for the top bit of the significand, useful for NaN ops. + const SIG_TOP_BIT: Self::Int; + /// Returns `self` transmuted to `Self::Int` fn to_bits(self) -> Self::Int; @@ -118,6 +131,24 @@ pub trait Float: /// Returns true if the value is NaN. fn is_nan(self) -> bool; + fn is_qnan(self) -> bool { + if !self.is_nan() { + return false; + } + + let top = self.to_bits() & Self::SIG_TOP_BIT; + + if MIPS_NAN { + top == Self::Int::ZERO + } else { + top != Self::Int::ZERO + } + } + + fn is_snan(self) -> bool { + self.is_nan() && !self.is_qnan() + } + /// Returns true if the value is +inf or -inf. fn is_infinite(self) -> bool; @@ -178,7 +209,6 @@ pub trait Float: fn fma(self, y: Self, z: Self) -> Self; /// Returns (normalized exponent, normalized significand) - #[allow(dead_code)] fn normalize(significand: Self::Int) -> (i32, Self::Int); /// Returns a number that represents the sign of self. @@ -226,13 +256,28 @@ macro_rules! float_impl { const NEG_ONE: Self = -1.0; const INFINITY: Self = Self::INFINITY; const NEG_INFINITY: Self = Self::NEG_INFINITY; - const NAN: Self = Self::NAN; - // NAN isn't guaranteed to be positive but it usually is. We only use this for - // tests. - const NEG_NAN: Self = $from_bits($to_bits(Self::NAN) | Self::SIGN_MASK); const MAX: Self = -Self::MIN; // Sign bit set, saturated mantissa, saturated exponent with last bit zeroed const MIN: Self = $from_bits(Self::Int::MAX & !(1 << Self::SIG_BITS)); + + // The default NaN seems to set one of the top two significand bits on most + // platforms (sNaN vs. qNaN). For mips, the significand is all 1s (with the + // exception of the signaling bit). + const NAN: Self = $from_bits(if MIPS_NAN { + Self::EXP_MASK | (Self::SIG_TOP_BIT - 1) + } else { + Self::EXP_MASK | Self::SIG_TOP_BIT + }); + const SNAN: Self = $from_bits(if MIPS_NAN { + Self::EXP_MASK | Self::SIG_MASK + } else { + Self::EXP_MASK | (Self::SIG_TOP_BIT >> 1) + }); + // NAN isn't guaranteed to be positive but it usually is. We only use these for + // tests. + const NEG_NAN: Self = $from_bits($to_bits(Self::NAN) | Self::SIGN_MASK); + const NEG_SNAN: Self = $from_bits($to_bits(Self::SNAN) | Self::SIGN_MASK); + const EPSILON: Self = <$ty>::EPSILON; // Exponent is a 1 in the LSB @@ -249,6 +294,7 @@ macro_rules! float_impl { const SIG_MASK: Self::Int = (1 << Self::SIG_BITS) - 1; const EXP_MASK: Self::Int = !(Self::SIGN_MASK | Self::SIG_MASK); const IMPLICIT_BIT: Self::Int = 1 << Self::SIG_BITS; + const SIG_TOP_BIT: Self::Int = Self::IMPLICIT_BIT >> 1; fn to_bits(self) -> Self::Int { self.to_bits() @@ -289,10 +335,7 @@ macro_rules! float_impl { cfg_if! { // fma is not yet available in `core` if #[cfg(intrinsics_enabled)] { - // FIXME(msrv,bench): once our benchmark rustc version is above the - // 2022-09-23 nightly, this can be removed. - #[allow(unused_unsafe)] - unsafe { core::intrinsics::$fma_intrinsic(self, y, z) } + core::intrinsics::$fma_intrinsic(self, y, z) } else { super::super::$fma_fn(self, y, z) } @@ -300,10 +343,7 @@ macro_rules! float_impl { } fn normalize(significand: Self::Int) -> (i32, Self::Int) { let shift = significand.leading_zeros().wrapping_sub(Self::EXP_BITS); - ( - 1i32.wrapping_sub(shift as i32), - significand << shift as Self::Int, - ) + (1i32.wrapping_sub(shift as i32), significand << shift) } } }; @@ -459,6 +499,17 @@ mod tests { assert_eq!(f16::EXP_MAX, 15); assert_eq!(f16::EXP_MIN, -14); assert_eq!(f16::EXP_MIN_SUBNORM, -24); + assert_biteq!(f16::NAN, ::NAN); + // Value of NAN and FLT16_SNAN in C. We don't strictly need to match up, but it is good to + // be aware if there are platforms where we don't. + if MIPS_NAN { + assert_biteq!(f16::NAN, f16::from_bits(0x7fbf)); + assert_biteq!(f16::SNAN, f16::from_bits(0x7fff)); + } else { + assert_biteq!(f16::NAN, f16::from_bits(0x7e00)); + assert_biteq!(f16::SNAN, f16::from_bits(0x7d00)); + } + assert!(f16::NAN.is_qnan()); // `exp_unbiased` assert_eq!(f16::FRAC_PI_2.exp_unbiased(), 0); @@ -485,6 +536,21 @@ mod tests { assert_eq!(f32::EXP_MAX, 127); assert_eq!(f32::EXP_MIN, -126); assert_eq!(f32::EXP_MIN_SUBNORM, -149); + assert_biteq!(f32::NAN, ::NAN); + // Value of NAN and FLT_SNAN in C. We don't strictly need to match up, but it is good to + // be aware if there are platforms where we don't. + if MIPS_NAN { + assert_biteq!(f32::NAN, f32::from_bits(0x7fbfffff)); + assert_biteq!(f32::SNAN, f32::from_bits(0x7fffffff)); + } else { + assert_biteq!(f32::NAN, f32::from_bits(0x7fc00000)); + assert_biteq!(f32::SNAN, f32::from_bits(0x7fa00000)); + } + assert!(f32::NAN.is_qnan()); + // FIXME(rust-lang/rust#115567): x87 use in `is_snan` quiets the sNaN + if !cfg!(x86_no_sse) { + assert!(f32::SNAN.is_snan()); + } // `exp_unbiased` assert_eq!(f32::FRAC_PI_2.exp_unbiased(), 0); @@ -515,6 +581,21 @@ mod tests { assert_eq!(f64::EXP_MAX, 1023); assert_eq!(f64::EXP_MIN, -1022); assert_eq!(f64::EXP_MIN_SUBNORM, -1074); + assert_biteq!(f64::NAN, ::NAN); + // Value of NAN and DBL_SNAN in C. We don't strictly need to match up, but it is good to + // be aware if there are platforms where we don't. + if MIPS_NAN { + assert_biteq!(f64::NAN, f64::from_bits(0x7ff7ffffffffffff)); + assert_biteq!(f64::SNAN, f64::from_bits(0x7fffffffffffffff)); + } else { + assert_biteq!(f64::NAN, f64::from_bits(0x7ff8000000000000)); + assert_biteq!(f64::SNAN, f64::from_bits(0x7ff4000000000000)); + } + assert!(f64::NAN.is_qnan()); + // FIXME(rust-lang/rust#115567): x87 use in `is_snan` quiets the sNaN + if !cfg!(x86_no_sse) { + assert!(f64::SNAN.is_snan()); + } // `exp_unbiased` assert_eq!(f64::FRAC_PI_2.exp_unbiased(), 0); @@ -546,6 +627,30 @@ mod tests { assert_eq!(f128::EXP_MAX, 16383); assert_eq!(f128::EXP_MIN, -16382); assert_eq!(f128::EXP_MIN_SUBNORM, -16494); + assert_biteq!(f128::NAN, ::NAN); + // Value of NAN and FLT128_SNAN in C. We don't strictly need to match up, but it is good to + // be aware if there are platforms where we don't. + if MIPS_NAN { + assert_biteq!( + f128::NAN, + f128::from_bits(0x7fff7fffffffffffffffffffffffffff) + ); + assert_biteq!( + f128::SNAN, + f128::from_bits(0x7fffffffffffffffffffffffffffffff) + ); + } else { + assert_biteq!( + f128::NAN, + f128::from_bits(0x7fff8000000000000000000000000000) + ); + assert_biteq!( + f128::SNAN, + f128::from_bits(0x7fff4000000000000000000000000000) + ); + } + assert!(f128::NAN.is_qnan()); + assert!(f128::SNAN.is_snan()); // `exp_unbiased` assert_eq!(f128::FRAC_PI_2.exp_unbiased(), 0); diff --git a/compiler-builtins/libm/src/math/support/hex_float.rs b/compiler-builtins/libm/src/math/support/hex_float.rs index c8558b90053d1..5be0d3159de3b 100644 --- a/compiler-builtins/libm/src/math/support/hex_float.rs +++ b/compiler-builtins/libm/src/math/support/hex_float.rs @@ -121,7 +121,7 @@ const fn parse_finite( Ok(Parsed { sig, exp }) => (sig, exp), }; - let mut round_bits = u128_ilog2(sig) as i32 - sig_bits as i32; + let mut round_bits = sig.ilog2() as i32 - sig_bits as i32; // Round at least up to min_lsb if exp < min_lsb - round_bits { @@ -299,29 +299,11 @@ const fn parse_hex(mut b: &[u8]) -> Result { )); }; - { - let e; - if negate_exp { - e = (exp as i64) - (pexp as i64); - } else { - e = (exp as i64) + (pexp as i64); - }; - - exp = if e < i32::MIN as i64 { - i32::MIN - } else if e > i32::MAX as i64 { - i32::MAX - } else { - e as i32 - }; - } - /* FIXME(msrv): once MSRV >= 1.66, replace the above workaround block with: if negate_exp { exp = exp.saturating_sub_unsigned(pexp); } else { exp = exp.saturating_add_unsigned(pexp); }; - */ Ok(Parsed { sig, exp }) } @@ -342,19 +324,11 @@ const fn hex_digit(c: u8) -> Option { } } -/* FIXME(msrv): vendor some things that are not const stable at our MSRV */ - -/// `u128::ilog2` -const fn u128_ilog2(v: u128) -> u32 { - assert!(v != 0); - u128::BITS - 1 - v.leading_zeros() -} - #[cfg(any(test, feature = "unstable-public-internals"))] mod hex_fmt { use core::fmt; - use crate::support::Float; + use crate::support::{Float, Int}; /// Format a floating point number as its IEEE hex (`%a`) representation. pub struct Hexf(pub F); @@ -366,8 +340,10 @@ mod hex_fmt { write!(f, "-")?; } - if x.is_nan() { - return write!(f, "NaN"); + if x.is_snan() { + return write!(f, "sNaN"); + } else if x.is_nan() { + return write!(f, "qNaN"); } else if x.is_infinite() { return write!(f, "inf"); } else if *x == F::ZERO { @@ -445,7 +421,7 @@ mod hex_fmt { let _ = f; unimplemented!() } else { - fmt::LowerHex::fmt(&self.0, f) + write!(f, "{:#010x}", self.0) } } } @@ -482,6 +458,53 @@ mod hex_fmt { } } } + + pub struct Hexi(pub F); + + impl fmt::LowerHex for Hexi { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + cfg_if! { + if #[cfg(feature = "compiler-builtins")] { + let _ = f; + unimplemented!() + } else { + write!(f, "{:#0width$x}", self.0, width = ((I::BITS / 4) + 2) as usize) + } + } + } + } + + impl fmt::Debug for Hexi + where + Hexi: fmt::LowerHex, + { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + cfg_if! { + if #[cfg(feature = "compiler-builtins")] { + let _ = f; + unimplemented!() + } else { + fmt::LowerHex::fmt(self, f) + } + } + } + } + + impl fmt::Display for Hexi + where + Hexi: fmt::LowerHex, + { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + cfg_if! { + if #[cfg(feature = "compiler-builtins")] { + let _ = f; + unimplemented!() + } else { + fmt::LowerHex::fmt(self, f) + } + } + } + } } #[cfg(any(test, feature = "unstable-public-internals"))] @@ -490,6 +513,7 @@ pub use hex_fmt::*; #[cfg(test)] mod parse_tests { extern crate std; + use std::string::String; use std::{format, println}; use super::*; @@ -538,6 +562,16 @@ mod parse_tests { } Ok(()) } + + #[cfg_attr(not(f16_enabled), expect(unused))] + pub fn canonicalize_snan_str(s: String) -> String { + if s.contains("sNaN") || s.contains("qNaN") { + s.replace("sNaN", "NaN").replace("qNaN", "NaN") + } else { + s + } + } + #[test] #[cfg(f16_enabled)] fn test_rounding() { @@ -545,7 +579,11 @@ mod parse_tests { for i in -n..n { let u = i.rotate_right(11) as u32; let s = format!("{}", Hexf(f32::from_bits(u))); - assert!(rounding_properties(&s).is_ok()); + let s = canonicalize_snan_str(s); + match rounding_properties(&s) { + Ok(()) => (), + Err(e) => panic!("failed rounding properties for `{s}`: {e:?}"), + } } } @@ -872,8 +910,6 @@ mod parse_tests { } #[cfg(test)] -// FIXME(ppc): something with `should_panic` tests cause a SIGILL with ppc64le -#[cfg(not(all(target_arch = "powerpc64", target_endian = "little")))] mod tests_panicking { extern crate std; use super::*; @@ -1080,8 +1116,11 @@ mod print_tests { use std::format; // Exhaustively check that `f16` roundtrips. for x in 0..=u16::MAX { + use super::parse_tests::canonicalize_snan_str; + let f = f16::from_bits(x); let s = format!("{}", Hexf(f)); + let s = canonicalize_snan_str(s); let from_s = hf16(&s); if f.is_nan() && from_s.is_nan() { @@ -1100,6 +1139,8 @@ mod print_tests { #[cfg(f16_enabled)] fn test_f16_to_f32() { use std::format; + + use super::parse_tests::canonicalize_snan_str; // Exhaustively check that these are equivalent for all `f16`: // - `f16 -> f32` // - `f16 -> str -> f32` @@ -1108,8 +1149,10 @@ mod print_tests { for x in 0..=u16::MAX { let f16 = f16::from_bits(x); let s16 = format!("{}", Hexf(f16)); + let s16 = canonicalize_snan_str(s16); let f32 = f16 as f32; let s32 = format!("{}", Hexf(f32)); + let s32 = canonicalize_snan_str(s32); let a = hf32(&s16); let b = hf32(&s32); @@ -1150,8 +1193,17 @@ mod print_tests { assert_eq!(Hexf(f32::NEG_ZERO).to_string(), "-0x0p+0"); assert_eq!(Hexf(f64::NEG_ZERO).to_string(), "-0x0p+0"); - assert_eq!(Hexf(f32::NAN).to_string(), "NaN"); - assert_eq!(Hexf(f64::NAN).to_string(), "NaN"); + assert_eq!(Hexf(f32::NAN).to_string(), "qNaN"); + assert_eq!(Hexf(f64::NAN).to_string(), "qNaN"); + assert_eq!(Hexf(f32::NEG_NAN).to_string(), "-qNaN"); + assert_eq!(Hexf(f64::NEG_NAN).to_string(), "-qNaN"); + if !cfg!(x86_no_sse) { + // FIXME(rust-lang/rust#115567): calls quiet the sNaN + assert_eq!(Hexf(f32::SNAN).to_string(), "sNaN"); + assert_eq!(Hexf(f64::SNAN).to_string(), "sNaN"); + assert_eq!(Hexf(f32::NEG_SNAN).to_string(), "-sNaN"); + assert_eq!(Hexf(f64::NEG_SNAN).to_string(), "-sNaN"); + } assert_eq!(Hexf(f32::INFINITY).to_string(), "inf"); assert_eq!(Hexf(f64::INFINITY).to_string(), "inf"); @@ -1165,7 +1217,9 @@ mod print_tests { assert_eq!(Hexf(f16::MIN).to_string(), "-0x1.ffcp+15"); assert_eq!(Hexf(f16::ZERO).to_string(), "0x0p+0"); assert_eq!(Hexf(f16::NEG_ZERO).to_string(), "-0x0p+0"); - assert_eq!(Hexf(f16::NAN).to_string(), "NaN"); + assert_eq!(Hexf(f16::NAN).to_string(), "qNaN"); + assert_eq!(Hexf(f16::SNAN).to_string(), "sNaN"); + assert_eq!(Hexf(f16::NEG_NAN).to_string(), "-qNaN"); assert_eq!(Hexf(f16::INFINITY).to_string(), "inf"); assert_eq!(Hexf(f16::NEG_INFINITY).to_string(), "-inf"); } @@ -1182,7 +1236,9 @@ mod print_tests { ); assert_eq!(Hexf(f128::ZERO).to_string(), "0x0p+0"); assert_eq!(Hexf(f128::NEG_ZERO).to_string(), "-0x0p+0"); - assert_eq!(Hexf(f128::NAN).to_string(), "NaN"); + assert_eq!(Hexf(f128::NAN).to_string(), "qNaN"); + assert_eq!(Hexf(f128::SNAN).to_string(), "sNaN"); + assert_eq!(Hexf(f128::NEG_NAN).to_string(), "-qNaN"); assert_eq!(Hexf(f128::INFINITY).to_string(), "inf"); assert_eq!(Hexf(f128::NEG_INFINITY).to_string(), "-inf"); } diff --git a/compiler-builtins/libm/src/math/support/mod.rs b/compiler-builtins/libm/src/math/support/mod.rs index 15ab010dc8d5f..9dc872cdc1506 100644 --- a/compiler-builtins/libm/src/math/support/mod.rs +++ b/compiler-builtins/libm/src/math/support/mod.rs @@ -35,5 +35,38 @@ pub use modular::linear_mul_reduction; /// Hint to the compiler that the current path is cold. pub fn cold_path() { #[cfg(intrinsics_enabled)] - core::intrinsics::cold_path(); + core::hint::cold_path(); +} + +/// # Safety +/// +/// `y` must not be zero and the result must not overflow (`x > i32::MIN`). +pub unsafe fn unchecked_div_i32(x: i32, y: i32) -> i32 { + cfg_if! { + if #[cfg(all(not(debug_assertions), intrinsics_enabled))] { + // Temporary macro to avoid panic codegen for division (in debug mode too). At + // the time of this writing this is only used in a few places, and once + // rust-lang/rust#72751 is fixed then this macro will no longer be necessary and + // the native `/` operator can be used and panics won't be codegen'd. + // + // Note: I am not sure whether the above comment is still up to date, we need + // to double check whether panics are elided where we use this. + unsafe { core::intrinsics::unchecked_div(x, y) } + } else { + x / y + } + } +} + +/// # Safety +/// +/// `y` must not be zero and the result must not overflow (`x > isize::MIN`). +pub unsafe fn unchecked_div_isize(x: isize, y: isize) -> isize { + cfg_if! { + if #[cfg(all(not(debug_assertions), intrinsics_enabled))] { + unsafe { core::intrinsics::unchecked_div(x, y) } + } else { + x / y + } + } } diff --git a/compiler-builtins/libm/src/math/tgamma.rs b/compiler-builtins/libm/src/math/tgamma.rs index 41415d9d12589..c526842470c85 100644 --- a/compiler-builtins/libm/src/math/tgamma.rs +++ b/compiler-builtins/libm/src/math/tgamma.rs @@ -23,6 +23,7 @@ Gamma(x)*Gamma(-x) = -pi/(x sin(pi x)) most ideas and constants are from boost and python */ use super::{exp, floor, k_cos, k_sin, pow}; +use crate::support::unchecked_div_isize; const PI: f64 = 3.141592653589793238462643383279502884; @@ -37,7 +38,8 @@ fn sinpi(mut x: f64) -> f64 { /* reduce x into [-.25,.25] */ n = (4.0 * x) as isize; - n = div!(n + 1, 2); + // SAFETY: nonzero divisor, nonnegative dividend (`n < 8`). + n = unsafe { unchecked_div_isize(n + 1, 2) }; x -= (n as f64) * 0.5; x *= PI; diff --git a/compiler-builtins/rust-version b/compiler-builtins/rust-version index 6a2835bc2d9eb..aa3876b14a221 100644 --- a/compiler-builtins/rust-version +++ b/compiler-builtins/rust-version @@ -1 +1 @@ -23d01cd2412583491621ab1ca4f1b01e37d11e39 +db3e99bbab28c6ca778b13222becdea54533d908 diff --git a/compiler-builtins/triagebot.toml b/compiler-builtins/triagebot.toml index b210a5fb52563..d0cdb497edbad 100644 --- a/compiler-builtins/triagebot.toml +++ b/compiler-builtins/triagebot.toml @@ -10,7 +10,7 @@ exclude_titles = ["Rustc pull update"] # when commits are included in subtrees, as well as warning links in commits. # Documentation at: https://forge.rust-lang.org/triagebot/issue-links.html [issue-links] -check-commits = false +check-commits = "uncanonicalized" # Enable issue transfers within the org # Documentation at: https://forge.rust-lang.org/triagebot/transfer.html diff --git a/core/src/alloc/global.rs b/core/src/alloc/global.rs index 9b80e3b70fa2f..e97398aa5dc4a 100644 --- a/core/src/alloc/global.rs +++ b/core/src/alloc/global.rs @@ -19,7 +19,7 @@ use crate::{cmp, ptr}; /// /// # Example /// -/// ``` +/// ```standalone_crate /// use std::alloc::{GlobalAlloc, Layout}; /// use std::cell::UnsafeCell; /// use std::ptr::null_mut; @@ -57,7 +57,7 @@ use crate::{cmp, ptr}; /// let mut allocated = 0; /// if self /// .remaining -/// .fetch_update(Relaxed, Relaxed, |mut remaining| { +/// .try_update(Relaxed, Relaxed, |mut remaining| { /// if size > remaining { /// return None; /// } @@ -284,9 +284,10 @@ pub unsafe trait GlobalAlloc { /// [`handle_alloc_error`]: ../../alloc/alloc/fn.handle_alloc_error.html #[stable(feature = "global_alloc", since = "1.28.0")] unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - // SAFETY: the caller must ensure that the `new_size` does not overflow. - // `layout.align()` comes from a `Layout` and is thus guaranteed to be valid. - let new_layout = unsafe { Layout::from_size_align_unchecked(new_size, layout.align()) }; + let alignment = layout.alignment(); + // SAFETY: the caller must ensure that the `new_size` does not overflow + // when rounded up to the next multiple of `alignment`. + let new_layout = unsafe { Layout::from_size_alignment_unchecked(new_size, alignment) }; // SAFETY: the caller must ensure that `new_layout` is greater than zero. let new_ptr = unsafe { self.alloc(new_layout) }; if !new_ptr.is_null() { diff --git a/core/src/alloc/layout.rs b/core/src/alloc/layout.rs index 4bffdd17696fb..66f5310db8310 100644 --- a/core/src/alloc/layout.rs +++ b/core/src/alloc/layout.rs @@ -6,8 +6,8 @@ use crate::error::Error; use crate::intrinsics::{unchecked_add, unchecked_mul, unchecked_sub}; -use crate::mem::SizedTypeProperties; -use crate::ptr::{Alignment, NonNull}; +use crate::mem::{Alignment, SizedTypeProperties}; +use crate::ptr::NonNull; use crate::{assert_unsafe_precondition, fmt, mem}; /// Layout of a block of memory. @@ -263,12 +263,12 @@ impl Layout { /// be that of a valid pointer, which means this must not be used /// as a "not yet initialized" sentinel value. /// Types that lazily allocate must track initialization by some other means. - #[stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "alloc_layout_extra", since = "1.95.0")] + #[rustc_const_stable(feature = "alloc_layout_extra", since = "1.95.0")] #[must_use] #[inline] pub const fn dangling_ptr(&self) -> NonNull { - NonNull::without_provenance(self.align.as_nonzero()) + NonNull::without_provenance(self.align.as_nonzero_usize()) } /// Creates a layout describing the record that can hold a value @@ -423,8 +423,8 @@ impl Layout { /// let repeated = padding_needed.repeat(0).unwrap(); /// assert_eq!(repeated, (Layout::from_size_align(0, 4).unwrap(), 8)); /// ``` - #[stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "alloc_layout_extra", since = "1.95.0")] + #[rustc_const_stable(feature = "alloc_layout_extra", since = "1.95.0")] #[inline] pub const fn repeat(&self, n: usize) -> Result<(Self, usize), LayoutError> { // FIXME(const-hack): the following could be way shorter with `?` @@ -520,8 +520,8 @@ impl Layout { /// aligned. /// /// On arithmetic overflow, returns `LayoutError`. - #[stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "alloc_layout_extra", since = "1.95.0")] + #[rustc_const_stable(feature = "alloc_layout_extra", since = "1.95.0")] #[inline] pub const fn repeat_packed(&self, n: usize) -> Result { if let Some(size) = self.size.checked_mul(n) { @@ -538,8 +538,8 @@ impl Layout { /// and is not incorporated *at all* into the resulting layout. /// /// On arithmetic overflow, returns `LayoutError`. - #[stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "alloc_layout_extra", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "alloc_layout_extra", since = "1.95.0")] + #[rustc_const_stable(feature = "alloc_layout_extra", since = "1.95.0")] #[inline] pub const fn extend_packed(&self, next: Self) -> Result { // SAFETY: each `size` is at most `isize::MAX == usize::MAX/2`, so the diff --git a/core/src/alloc/mod.rs b/core/src/alloc/mod.rs index 959407b753487..18310cf98918d 100644 --- a/core/src/alloc/mod.rs +++ b/core/src/alloc/mod.rs @@ -100,6 +100,13 @@ impl fmt::Display for AllocError { /// A memory block which is [*currently allocated*] may be passed to /// any method of the allocator that accepts such an argument. /// +/// Additionally, any memory block returned by the allocator must +/// satisfy the allocation invariants described in `core::ptr`. +/// In particular, if a block has base address `p` and size `n`, +/// then `p as usize + n <= usize::MAX` must hold. +/// +/// This ensures that pointer arithmetic within the allocation +/// (for example, `ptr.add(len)`) cannot overflow the address space. /// [*currently allocated*]: #currently-allocated-memory #[unstable(feature = "allocator_api", issue = "32838")] #[rustc_const_unstable(feature = "const_heap", issue = "79597")] diff --git a/core/src/any.rs b/core/src/any.rs index 42f332f7d8ba8..71a529400511c 100644 --- a/core/src/any.rs +++ b/core/src/any.rs @@ -86,7 +86,10 @@ #![stable(feature = "rust1", since = "1.0.0")] -use crate::{fmt, hash, intrinsics, ptr}; +use crate::intrinsics::{self, type_id_vtable}; +use crate::mem::transmute; +use crate::mem::type_info::{TraitImpl, TypeKind}; +use crate::{fmt, hash, ptr}; /////////////////////////////////////////////////////////////////////////////// // Any trait @@ -788,6 +791,67 @@ impl TypeId { const { intrinsics::type_id::() } } + /// Checks if the [TypeId] implements the trait. If it does it returns [TraitImpl] which can be used to build a fat pointer. + /// It can only be called at compile time. `self` must be the [TypeId] of a sized type or None will be returned. + /// + /// # Examples + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::{TypeId}; + /// + /// pub trait Blah {} + /// impl Blah for u8 {} + /// + /// assert!(const { TypeId::of::().trait_info_of::() }.is_some()); + /// assert!(const { TypeId::of::().trait_info_of::() }.is_none()); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + pub const fn trait_info_of< + T: ptr::Pointee> + ?Sized + 'static, + >( + self, + ) -> Option> { + // SAFETY: The vtable was obtained for `T`, so it is guaranteed to be `DynMetadata`. + // The intrinsic can't infer this because it is designed to work with arbitrary TypeIds. + unsafe { transmute(self.trait_info_of_trait_type_id(const { TypeId::of::() })) } + } + + /// Checks if the [TypeId] implements the trait of `trait_represented_by_type_id`. If it does it returns [TraitImpl] which can be used to build a fat pointer. + /// It can only be called at compile time. `self` must be the [TypeId] of a sized type or None will be returned. + /// + /// # Examples + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::{TypeId}; + /// + /// pub trait Blah {} + /// impl Blah for u8 {} + /// + /// assert!(const { TypeId::of::().trait_info_of_trait_type_id(TypeId::of::()) }.is_some()); + /// assert!(const { TypeId::of::().trait_info_of_trait_type_id(TypeId::of::()) }.is_none()); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + pub const fn trait_info_of_trait_type_id( + self, + trait_represented_by_type_id: TypeId, + ) -> Option> { + if self.info().size.is_none() { + return None; + } + + if matches!(trait_represented_by_type_id.info().kind, TypeKind::DynTrait(_)) + && let Some(vtable) = type_id_vtable(self, trait_represented_by_type_id) + { + Some(TraitImpl { vtable }) + } else { + None + } + } + fn as_u128(self) -> u128 { let mut bytes = [0; 16]; @@ -948,7 +1012,8 @@ pub const fn try_as_dyn< >( t: &T, ) -> Option<&U> { - let vtable: Option> = const { intrinsics::vtable_for::() }; + let vtable: Option> = + const { TypeId::of::().trait_info_of::().as_ref().map(TraitImpl::get_vtable) }; match vtable { Some(dyn_metadata) => { let pointer = ptr::from_raw_parts(t, dyn_metadata); @@ -1001,7 +1066,8 @@ pub const fn try_as_dyn_mut< >( t: &mut T, ) -> Option<&mut U> { - let vtable: Option> = const { intrinsics::vtable_for::() }; + let vtable: Option> = + const { TypeId::of::().trait_info_of::().as_ref().map(TraitImpl::get_vtable) }; match vtable { Some(dyn_metadata) => { let pointer = ptr::from_raw_parts_mut(t, dyn_metadata); diff --git a/core/src/array/drain.rs b/core/src/array/drain.rs index 1c6137191324c..17792dca583d2 100644 --- a/core/src/array/drain.rs +++ b/core/src/array/drain.rs @@ -31,7 +31,6 @@ impl<'l, 'f, T, U, const N: usize, F: FnMut(T) -> U> Drain<'l, 'f, T, N, F> { } /// See [`Drain::new`]; this is our fake iterator. -#[rustc_const_unstable(feature = "array_try_map", issue = "79711")] #[unstable(feature = "array_try_map", issue = "79711")] pub(super) struct Drain<'l, 'f, T, const N: usize, F> { // FIXME(const-hack): This is essentially a slice::IterMut<'static>, replace when possible. diff --git a/core/src/array/mod.rs b/core/src/array/mod.rs index 6cca2e6358b63..b116841578902 100644 --- a/core/src/array/mod.rs +++ b/core/src/array/mod.rs @@ -405,7 +405,8 @@ where /// Implements comparison of arrays [lexicographically](Ord#lexicographical-comparison). #[stable(feature = "rust1", since = "1.0.0")] -impl PartialOrd for [T; N] { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const PartialOrd for [T; N] { #[inline] fn partial_cmp(&self, other: &[T; N]) -> Option { PartialOrd::partial_cmp(&&self[..], &&other[..]) @@ -430,7 +431,8 @@ impl PartialOrd for [T; N] { /// Implements comparison of arrays [lexicographically](Ord#lexicographical-comparison). #[stable(feature = "rust1", since = "1.0.0")] -impl Ord for [T; N] { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const Ord for [T; N] { #[inline] fn cmp(&self, other: &[T; N]) -> Ordering { Ord::cmp(&&self[..], &&other[..]) @@ -516,20 +518,47 @@ impl [T; N] { /// /// # Note on performance and stack usage /// - /// Unfortunately, usages of this method are currently not always optimized - /// as well as they could be. This mainly concerns large arrays, as mapping - /// over small arrays seem to be optimized just fine. Also note that in - /// debug mode (i.e. without any optimizations), this method can use a lot - /// of stack space (a few times the size of the array or more). + /// Note that this method is *eager*. It evaluates `f` all `N` times before + /// returning the new array. /// - /// Therefore, in performance-critical code, try to avoid using this method - /// on large arrays or check the emitted code. Also try to avoid chained - /// maps (e.g. `arr.map(...).map(...)`). + /// That means that `arr.map(f).map(g)` is, in general, *not* equivalent to + /// `array.map(|x| g(f(x)))`, as the former calls `f` 4 times then `g` 4 times, + /// whereas the latter interleaves the calls (`fgfgfgfg`). /// - /// In many cases, you can instead use [`Iterator::map`] by calling `.iter()` - /// or `.into_iter()` on your array. `[T; N]::map` is only necessary if you - /// really need a new array of the same size as the result. Rust's lazy - /// iterators tend to get optimized very well. + /// A consequence of this is that it can have fairly-high stack usage, especially + /// in debug mode or for long arrays. The backend may be able to optimize it + /// away, but especially for complicated mappings it might not be able to. + /// + /// If you're doing a one-step `map` and really want an array as the result, + /// then absolutely use this method. Its implementation uses a bunch of tricks + /// to help the optimizer handle it well. Particularly for simple arrays, + /// like `[u8; 3]` or `[f32; 4]`, there's nothing to be concerned about. + /// + /// However, if you don't actually need an *array* of the results specifically, + /// just to process them, then you likely want [`Iterator::map`] instead. + /// + /// For example, rather than doing an array-to-array map of all the elements + /// in the array up-front and only iterating after that completes, + /// + /// ``` + /// # let my_array = [1, 2, 3]; + /// # let f = |x: i32| x + 1; + /// for x in my_array.map(f) { + /// // ... + /// } + /// ``` + /// + /// It's often better to use an iterator along the lines of + /// + /// ``` + /// # let my_array = [1, 2, 3]; + /// # let f = |x: i32| x + 1; + /// for x in my_array.into_iter().map(f) { + /// // ... + /// } + /// ``` + /// + /// as that's more likely to avoid large temporaries. /// /// /// # Examples diff --git a/core/src/ascii/ascii_char.rs b/core/src/ascii/ascii_char.rs index d77fafed2039b..ec3e551056fee 100644 --- a/core/src/ascii/ascii_char.rs +++ b/core/src/ascii/ascii_char.rs @@ -878,7 +878,7 @@ impl AsciiChar { /// # Examples /// /// ``` - /// #![feature(ascii_char, ascii_char_variants, is_ascii_octdigit)] + /// #![feature(ascii_char, ascii_char_variants)] /// /// use std::ascii; /// diff --git a/core/src/bstr/mod.rs b/core/src/bstr/mod.rs index 34e1ea66c99ad..9d623d3af8b5d 100644 --- a/core/src/bstr/mod.rs +++ b/core/src/bstr/mod.rs @@ -6,7 +6,7 @@ mod traits; pub use traits::{impl_partial_eq, impl_partial_eq_n, impl_partial_eq_ord}; use crate::borrow::{Borrow, BorrowMut}; -use crate::fmt; +use crate::fmt::{self, Alignment}; use crate::ops::{Deref, DerefMut, DerefPure}; /// A wrapper for `&[u8]` representing a human-readable string that's conventionally, but not @@ -174,44 +174,85 @@ impl fmt::Debug for ByteStr { #[unstable(feature = "bstr", issue = "134915")] impl fmt::Display for ByteStr { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fn fmt_nopad(this: &ByteStr, f: &mut fmt::Formatter<'_>) -> fmt::Result { - for chunk in this.utf8_chunks() { + fn emit(byte_str: &ByteStr, f: &mut fmt::Formatter<'_>) -> fmt::Result { + for chunk in byte_str.utf8_chunks() { f.write_str(chunk.valid())?; if !chunk.invalid().is_empty() { f.write_str("\u{FFFD}")?; } } + Ok(()) } - let Some(align) = f.align() else { - return fmt_nopad(self, f); - }; - let nchars: usize = self - .utf8_chunks() - .map(|chunk| { - chunk.valid().chars().count() + if chunk.invalid().is_empty() { 0 } else { 1 } - }) - .sum(); - let padding = f.width().unwrap_or(0).saturating_sub(nchars); - let fill = f.fill(); - let (lpad, rpad) = match align { - fmt::Alignment::Left => (0, padding), - fmt::Alignment::Right => (padding, 0), - fmt::Alignment::Center => { - let half = padding / 2; - (half, half + padding % 2) + let requested_width = f.width().unwrap_or(0); + if requested_width == 0 && f.precision().is_none() { + // Avoid counting the characters if no truncation or padding was + // requested. + return emit(self, f); + } + + let (truncated, actual_width) = match f.precision() { + // The entire string is truncated away. Weird, but ok. + Some(0) => (ByteStr::new(&[]), 0), + // Advance through string until we run out of space. + Some(precision) => { + let mut remaining_width = precision; + let mut chunks = self.utf8_chunks(); + let mut current_width = 0; + let mut offset = 0; + loop { + let Some(chunk) = chunks.next() else { + // We reached the end of the string without running out + // of space, so print the entire string. + break (self, current_width); + }; + + let mut chars = chunk.valid().char_indices(); + let Err(remaining) = chars.advance_by(remaining_width) else { + // We've counted off `precision` characters, so truncate + // the string at the current offset. + break (&self[..offset + chars.offset()], precision); + }; + + offset += chunk.valid().len(); + current_width += remaining_width - remaining.get(); + remaining_width = remaining.get(); + + // `remaining_width` cannot be zero, there is still space + // remaining. So next, count the � character emitted for + // the invalid chunk (if it exists). + if !chunk.invalid().is_empty() { + offset += chunk.invalid().len(); + current_width += 1; + remaining_width -= 1; + + if remaining_width == 0 { + break (&self[..offset], precision); + } + } + } + } + // The string shouldn't be truncated at all, so just count the number + // of characters to calculate the padding. + None => { + let actual_width = self + .utf8_chunks() + .map(|chunk| { + chunk.valid().chars().count() + + if chunk.invalid().is_empty() { 0 } else { 1 } + }) + .sum(); + (self, actual_width) } }; - for _ in 0..lpad { - write!(f, "{fill}")?; - } - fmt_nopad(self, f)?; - for _ in 0..rpad { - write!(f, "{fill}")?; - } - Ok(()) + // The width is originally stored as a 16-bit number, so this cannot fail. + let padding = u16::try_from(requested_width.saturating_sub(actual_width)).unwrap(); + + let post_padding = f.padding(padding, Alignment::Left)?; + emit(truncated, f)?; + post_padding.write(f) } } diff --git a/core/src/bstr/traits.rs b/core/src/bstr/traits.rs index ff46bb13ba4eb..bcfffd52d7419 100644 --- a/core/src/bstr/traits.rs +++ b/core/src/bstr/traits.rs @@ -45,8 +45,7 @@ impl hash::Hash for ByteStr { #[unstable(feature = "bstr_internals", issue = "none")] macro_rules! impl_partial_eq { ($lhs:ty, $rhs:ty) => { - #[allow(unused_lifetimes)] - impl<'a> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { let other: &[u8] = other.as_ref(); @@ -54,8 +53,7 @@ macro_rules! impl_partial_eq { } } - #[allow(unused_lifetimes)] - impl<'a> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { let this: &[u8] = self.as_ref(); @@ -76,9 +74,8 @@ macro_rules! impl_partial_eq_ord { ($lhs:ty, $rhs:ty) => { $crate::bstr::impl_partial_eq!($lhs, $rhs); - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { let other: &[u8] = other.as_ref(); @@ -86,9 +83,8 @@ macro_rules! impl_partial_eq_ord { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { let this: &[u8] = self.as_ref(); @@ -107,7 +103,6 @@ pub use impl_partial_eq_ord; #[unstable(feature = "bstr_internals", issue = "none")] macro_rules! impl_partial_eq_n { ($lhs:ty, $rhs:ty) => { - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] impl PartialEq<$rhs> for $lhs { #[inline] @@ -117,7 +112,6 @@ macro_rules! impl_partial_eq_n { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] impl PartialEq<$lhs> for $rhs { #[inline] @@ -274,4 +268,5 @@ impl_slice_index!(range::RangeFrom); impl_slice_index!(ops::RangeInclusive); impl_slice_index!(range::RangeInclusive); impl_slice_index!(ops::RangeToInclusive); +impl_slice_index!(range::RangeToInclusive); impl_slice_index!((ops::Bound, ops::Bound)); diff --git a/core/src/cell.rs b/core/src/cell.rs index 661ea4ab6a27f..d67693f9d0fc3 100644 --- a/core/src/cell.rs +++ b/core/src/cell.rs @@ -689,6 +689,30 @@ impl, U> CoerceUnsized> for Cell {} #[unstable(feature = "dispatch_from_dyn", issue = "none")] impl, U> DispatchFromDyn> for Cell {} +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsRef<[Cell; N]> for Cell<[T; N]> { + #[inline] + fn as_ref(&self) -> &[Cell; N] { + self.as_array_of_cells() + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsRef<[Cell]> for Cell<[T; N]> { + #[inline] + fn as_ref(&self) -> &[Cell] { + &*self.as_array_of_cells() + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsRef<[Cell]> for Cell<[T]> { + #[inline] + fn as_ref(&self) -> &[Cell] { + self.as_slice_of_cells() + } +} + impl Cell<[T]> { /// Returns a `&[Cell]` from a `&Cell<[T]>` /// @@ -750,7 +774,6 @@ impl Cell<[T; N]> { /// following is unsound: /// /// ```rust -/// #![feature(cell_get_cloned)] /// # use std::cell::Cell; /// /// #[derive(Copy, Debug)] @@ -2695,18 +2718,6 @@ fn assert_coerce_unsized( let _: RefCell<&dyn Send> = d; } -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for UnsafeCell {} - -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for SyncUnsafeCell {} - -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for Cell {} - -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for RefCell {} - #[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] unsafe impl<'b, T: ?Sized> PinCoerceUnsized for Ref<'b, T> {} diff --git a/core/src/cell/lazy.rs b/core/src/cell/lazy.rs index 28a76569c1d03..ae559e599f481 100644 --- a/core/src/cell/lazy.rs +++ b/core/src/cell/lazy.rs @@ -366,6 +366,16 @@ impl fmt::Debug for LazyCell { } } +#[stable(feature = "from_wrapper_impls", since = "CURRENT_RUSTC_VERSION")] +impl From for LazyCell { + /// Constructs a `LazyCell` that starts already initialized + /// with the provided value. + #[inline] + fn from(value: T) -> Self { + Self { state: UnsafeCell::new(State::Init(value)) } + } +} + #[cold] #[inline(never)] const fn panic_poisoned() -> ! { diff --git a/core/src/char/methods.rs b/core/src/char/methods.rs index 87b328c912878..46d48afbf5a14 100644 --- a/core/src/char/methods.rs +++ b/core/src/char/methods.rs @@ -778,7 +778,72 @@ impl char { pub fn is_alphabetic(self) -> bool { match self { 'a'..='z' | 'A'..='Z' => true, - c => c > '\x7f' && unicode::Alphabetic(c), + '\0'..='\u{A9}' => false, + _ => unicode::Alphabetic(self), + } + } + + /// Returns `true` if this `char` has the `Cased` property. + /// A character is cased if and only if it is uppercase, lowercase, or titlecase. + /// + /// `Cased` is described in Chapter 4 (Character Properties) of the [Unicode Standard] and + /// specified in the [Unicode Character Database][ucd] [`DerivedCoreProperties.txt`]. + /// + /// [Unicode Standard]: https://www.unicode.org/versions/latest/ + /// [ucd]: https://www.unicode.org/reports/tr44/ + /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(titlecase)] + /// assert!('A'.is_cased()); + /// assert!('a'.is_cased()); + /// assert!(!'京'.is_cased()); + /// ``` + #[must_use] + #[unstable(feature = "titlecase", issue = "153892")] + #[inline] + pub fn is_cased(self) -> bool { + match self { + 'a'..='z' | 'A'..='Z' => true, + '\0'..='\u{A9}' => false, + _ => unicode::Cased(self), + } + } + + /// Returns the case of this character: + /// [`Some(CharCase::Upper)`][`CharCase::Upper`] if [`self.is_uppercase()`][`char::is_uppercase`], + /// [`Some(CharCase::Lower)`][`CharCase::Lower`] if [`self.is_lowercase()`][`char::is_lowercase`], + /// [`Some(CharCase::Title)`][`CharCase::Title`] if [`self.is_titlecase()`][`char::is_titlecase`], and + /// `None` if [`!self.is_cased()`][`char::is_cased`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(titlecase)] + /// use core::char::CharCase; + /// assert_eq!('a'.case(), Some(CharCase::Lower)); + /// assert_eq!('δ'.case(), Some(CharCase::Lower)); + /// assert_eq!('A'.case(), Some(CharCase::Upper)); + /// assert_eq!('Δ'.case(), Some(CharCase::Upper)); + /// assert_eq!('Dž'.case(), Some(CharCase::Title)); + /// assert_eq!('中'.case(), None); + /// ``` + #[must_use] + #[unstable(feature = "titlecase", issue = "153892")] + #[inline] + pub fn case(self) -> Option { + match self { + 'a'..='z' => Some(CharCase::Lower), + 'A'..='Z' => Some(CharCase::Upper), + '\0'..='\u{A9}' => None, + _ if !unicode::Cased(self) => None, + _ if unicode::Lowercase(self) => Some(CharCase::Lower), + _ if unicode::Uppercase(self) => Some(CharCase::Upper), + _ => Some(CharCase::Title), } } @@ -819,7 +884,42 @@ impl char { pub const fn is_lowercase(self) -> bool { match self { 'a'..='z' => true, - c => c > '\x7f' && unicode::Lowercase(c), + '\0'..='\u{A9}' => false, + _ => unicode::Lowercase(self), + } + } + + /// Returns `true` if this `char` has the general category for titlecase letters. + /// Conceptually, these characters consist of an uppercase portion followed by a lowercase portion. + /// + /// Titlecase letters (code points with the general category of `Lt`) are described in Chapter 4 + /// (Character Properties) of the [Unicode Standard] and specified in the [Unicode Character + /// Database][ucd] [`UnicodeData.txt`]. + /// + /// [Unicode Standard]: https://www.unicode.org/versions/latest/ + /// [ucd]: https://www.unicode.org/reports/tr44/ + /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(titlecase)] + /// assert!('Dž'.is_titlecase()); + /// assert!('ῼ'.is_titlecase()); + /// assert!(!'D'.is_titlecase()); + /// assert!(!'z'.is_titlecase()); + /// assert!(!'中'.is_titlecase()); + /// assert!(!' '.is_titlecase()); + /// ``` + #[must_use] + #[unstable(feature = "titlecase", issue = "153892")] + #[inline] + pub fn is_titlecase(self) -> bool { + match self { + '\0'..='\u{01C4}' => false, + _ => self.is_cased() && !self.is_lowercase() && !self.is_uppercase(), } } @@ -860,7 +960,8 @@ impl char { pub const fn is_uppercase(self) -> bool { match self { 'A'..='Z' => true, - c => c > '\x7f' && unicode::Uppercase(c), + '\0'..='\u{BF}' => false, + _ => unicode::Uppercase(self), } } @@ -893,7 +994,8 @@ impl char { pub const fn is_whitespace(self) -> bool { match self { ' ' | '\x09'..='\x0d' => true, - c => c > '\x7f' && unicode::White_Space(c), + '\0'..='\u{84}' => false, + _ => unicode::White_Space(self), } } @@ -920,10 +1022,10 @@ impl char { #[stable(feature = "rust1", since = "1.0.0")] #[inline] pub fn is_alphanumeric(self) -> bool { - if self.is_ascii() { - self.is_ascii_alphanumeric() - } else { - unicode::Alphabetic(self) || unicode::N(self) + match self { + 'a'..='z' | 'A'..='Z' | '0'..='9' => true, + '\0'..='\u{A9}' => false, + _ => unicode::Alphabetic(self) || unicode::N(self), } } @@ -969,23 +1071,7 @@ impl char { #[must_use] #[inline] pub(crate) fn is_grapheme_extended(self) -> bool { - !self.is_ascii() && unicode::Grapheme_Extend(self) - } - - /// Returns `true` if this `char` has the `Cased` property. - /// - /// `Cased` is described in Chapter 4 (Character Properties) of the [Unicode Standard] and - /// specified in the [Unicode Character Database][ucd] [`DerivedCoreProperties.txt`]. - /// - /// [Unicode Standard]: https://www.unicode.org/versions/latest/ - /// [ucd]: https://www.unicode.org/reports/tr44/ - /// [`DerivedCoreProperties.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt - #[must_use] - #[inline] - #[doc(hidden)] - #[unstable(feature = "char_internals", reason = "exposed only for libstd", issue = "none")] - pub fn is_cased(self) -> bool { - if self.is_ascii() { self.is_ascii_alphabetic() } else { unicode::Cased(self) } + self > '\u{02FF}' && unicode::Grapheme_Extend(self) } /// Returns `true` if this `char` has the `Case_Ignorable` property. @@ -1047,7 +1133,8 @@ impl char { pub fn is_numeric(self) -> bool { match self { '0'..='9' => true, - c => c > '\x7f' && unicode::N(c), + '\0'..='\u{B1}' => false, + _ => unicode::N(self), } } @@ -1110,7 +1197,7 @@ impl char { /// // convert into themselves. /// assert_eq!('山'.to_lowercase().to_string(), "山"); /// ``` - #[must_use = "this returns the lowercase character as a new iterator, \ + #[must_use = "this returns the lowercased character as a new iterator, \ without modifying the original"] #[stable(feature = "rust1", since = "1.0.0")] #[inline] @@ -1118,9 +1205,115 @@ impl char { ToLowercase(CaseMappingIter::new(conversions::to_lower(self))) } + /// Returns an iterator that yields the titlecase mapping of this `char` as one or more + /// `char`s. + /// + /// This is usually, but not always, equivalent to the uppercase mapping + /// returned by [`Self::to_uppercase`]. Prefer this method when seeking to capitalize + /// Only The First Letter of a word, but use [`Self::to_uppercase`] for ALL CAPS. + /// + /// If this `char` does not have a titlecase mapping, the iterator yields the same `char`. + /// + /// If this `char` has a one-to-one titlecase mapping given by the [Unicode Character + /// Database][ucd] [`UnicodeData.txt`], the iterator yields that `char`. + /// + /// [ucd]: https://www.unicode.org/reports/tr44/ + /// [`UnicodeData.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/UnicodeData.txt + /// + /// If this `char` requires special considerations (e.g. multiple `char`s) the iterator yields + /// the `char`(s) given by [`SpecialCasing.txt`]. + /// + /// [`SpecialCasing.txt`]: https://www.unicode.org/Public/UCD/latest/ucd/SpecialCasing.txt + /// + /// This operation performs an unconditional mapping without tailoring. That is, the conversion + /// is independent of context and language. + /// + /// In the [Unicode Standard], Chapter 4 (Character Properties) discusses case mapping in + /// general and Chapter 3 (Conformance) discusses the default algorithm for case conversion. + /// + /// [Unicode Standard]: https://www.unicode.org/versions/latest/ + /// + /// # Examples + /// + /// As an iterator: + /// + /// ``` + /// #![feature(titlecase)] + /// for c in 'ß'.to_titlecase() { + /// print!("{c}"); + /// } + /// println!(); + /// ``` + /// + /// Using `println!` directly: + /// + /// ``` + /// #![feature(titlecase)] + /// println!("{}", 'ß'.to_titlecase()); + /// ``` + /// + /// Both are equivalent to: + /// + /// ``` + /// println!("Ss"); + /// ``` + /// + /// Using [`to_string`](../std/string/trait.ToString.html#tymethod.to_string): + /// + /// ``` + /// #![feature(titlecase)] + /// assert_eq!('c'.to_titlecase().to_string(), "C"); + /// assert_eq!('dž'.to_titlecase().to_string(), "Dž"); + /// assert_eq!('ῼ'.to_titlecase().to_string(), "ῼ"); + /// + /// // Sometimes the result is more than one character: + /// assert_eq!('ß'.to_titlecase().to_string(), "Ss"); + /// + /// // Characters that do not have separate cased forms + /// // convert into themselves. + /// assert_eq!('山'.to_titlecase().to_string(), "山"); + /// ``` + /// + /// # Note on locale + /// + /// In Turkish and Azeri, the equivalent of 'i' in Latin has five forms instead of two: + /// + /// * 'Dotless': I / ı, sometimes written ï + /// * 'Dotted': İ / i + /// + /// Note that the lowercase dotted 'i' is the same as the Latin. Therefore: + /// + /// ``` + /// #![feature(titlecase)] + /// let upper_i = 'i'.to_titlecase().to_string(); + /// ``` + /// + /// The value of `upper_i` here relies on the language of the text: if we're + /// in `en-US`, it should be `"I"`, but if we're in `tr-TR` or `az-AZ`, it should + /// be `"İ"`. `to_titlecase()` does not take this into account, and so: + /// + /// ``` + /// #![feature(titlecase)] + /// let upper_i = 'i'.to_titlecase().to_string(); + /// + /// assert_eq!(upper_i, "I"); + /// ``` + /// + /// holds across languages. + #[must_use = "this returns the titlecased character as a new iterator, \ + without modifying the original"] + #[unstable(feature = "titlecase", issue = "153892")] + #[inline] + pub fn to_titlecase(self) -> ToTitlecase { + ToTitlecase(CaseMappingIter::new(conversions::to_title(self))) + } + /// Returns an iterator that yields the uppercase mapping of this `char` as one or more /// `char`s. /// + /// Prefer this method when converting a word into ALL CAPS, but consider [`Self::to_titlecase`] + /// instead if you seek to capitalize Only The First Letter. + /// /// If this `char` does not have an uppercase mapping, the iterator yields the same `char`. /// /// If this `char` has a one-to-one uppercase mapping given by the [Unicode Character @@ -1170,9 +1363,11 @@ impl char { /// /// ``` /// assert_eq!('c'.to_uppercase().to_string(), "C"); + /// assert_eq!('dž'.to_uppercase().to_string(), "DŽ"); /// /// // Sometimes the result is more than one character: /// assert_eq!('ſt'.to_uppercase().to_string(), "ST"); + /// assert_eq!('ῼ'.to_uppercase().to_string(), "ΩΙ"); /// /// // Characters that do not have both uppercase and lowercase /// // convert into themselves. @@ -1181,7 +1376,7 @@ impl char { /// /// # Note on locale /// - /// In Turkish, the equivalent of 'i' in Latin has five forms instead of two: + /// In Turkish and Azeri, the equivalent of 'i' in Latin has five forms instead of two: /// /// * 'Dotless': I / ı, sometimes written ï /// * 'Dotted': İ / i @@ -1193,7 +1388,7 @@ impl char { /// ``` /// /// The value of `upper_i` here relies on the language of the text: if we're - /// in `en-US`, it should be `"I"`, but if we're in `tr_TR`, it should + /// in `en-US`, it should be `"I"`, but if we're in `tr-TR` or `az-AZ`, it should /// be `"İ"`. `to_uppercase()` does not take this into account, and so: /// /// ``` @@ -1203,7 +1398,7 @@ impl char { /// ``` /// /// holds across languages. - #[must_use = "this returns the uppercase character as a new iterator, \ + #[must_use = "this returns the uppercased character as a new iterator, \ without modifying the original"] #[stable(feature = "rust1", since = "1.0.0")] #[inline] @@ -1446,7 +1641,7 @@ impl char { #[rustc_const_stable(feature = "const_ascii_ctype_on_intrinsics", since = "1.47.0")] #[inline] pub const fn is_ascii_alphabetic(&self) -> bool { - matches!(*self, 'A'..='Z' | 'a'..='z') + matches!(*self, 'a'..='z' | 'A'..='Z') } /// Checks if the value is an ASCII uppercase character: diff --git a/core/src/char/mod.rs b/core/src/char/mod.rs index 82a3f6f916be3..3231c4193064c 100644 --- a/core/src/char/mod.rs +++ b/core/src/char/mod.rs @@ -363,13 +363,21 @@ impl fmt::Display for EscapeDebug { } macro_rules! casemappingiter_impls { - ($(#[$attr:meta])* $ITER_NAME:ident) => { + ( + #[$stab:meta] + #[$dendstab:meta] + #[$fusedstab:meta] + #[$exactstab:meta] + #[$displaystab:meta] + $(#[$attr:meta])* + $ITER_NAME:ident + ) => { $(#[$attr])* - #[stable(feature = "rust1", since = "1.0.0")] + #[$stab] #[derive(Debug, Clone)] pub struct $ITER_NAME(CaseMappingIter); - #[stable(feature = "rust1", since = "1.0.0")] + #[$stab] impl Iterator for $ITER_NAME { type Item = char; fn next(&mut self) -> Option { @@ -405,7 +413,7 @@ macro_rules! casemappingiter_impls { } } - #[stable(feature = "case_mapping_double_ended", since = "1.59.0")] + #[$dendstab] impl DoubleEndedIterator for $ITER_NAME { fn next_back(&mut self) -> Option { self.0.next_back() @@ -423,10 +431,10 @@ macro_rules! casemappingiter_impls { } } - #[stable(feature = "fused", since = "1.26.0")] + #[$fusedstab] impl FusedIterator for $ITER_NAME {} - #[stable(feature = "exact_size_case_mapping_iter", since = "1.35.0")] + #[$exactstab] impl ExactSizeIterator for $ITER_NAME { fn len(&self) -> usize { self.0.len() @@ -453,7 +461,7 @@ macro_rules! casemappingiter_impls { #[unstable(feature = "std_internals", issue = "none")] unsafe impl TrustedRandomAccess for $ITER_NAME {} - #[stable(feature = "char_struct_display", since = "1.16.0")] + #[$displaystab] impl fmt::Display for $ITER_NAME { #[inline] fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -464,23 +472,48 @@ macro_rules! casemappingiter_impls { } casemappingiter_impls! { - /// Returns an iterator that yields the lowercase equivalent of a `char`. + #[stable(feature = "rust1", since = "1.0.0")] + #[stable(feature = "case_mapping_double_ended", since = "1.59.0")] + #[stable(feature = "fused", since = "1.26.0")] + #[stable(feature = "exact_size_case_mapping_iter", since = "1.35.0")] + #[stable(feature = "char_struct_display", since = "1.16.0")] + /// Returns an iterator that yields the uppercase equivalent of a `char`. /// - /// This `struct` is created by the [`to_lowercase`] method on [`char`]. See + /// This `struct` is created by the [`to_uppercase`] method on [`char`]. See /// its documentation for more. /// - /// [`to_lowercase`]: char::to_lowercase - ToLowercase + /// [`to_uppercase`]: char::to_uppercase + ToUppercase } casemappingiter_impls! { - /// Returns an iterator that yields the uppercase equivalent of a `char`. + #[unstable(feature = "titlecase", issue = "153892")] + #[unstable(feature = "titlecase", issue = "153892")] + #[unstable(feature = "titlecase", issue = "153892")] + #[unstable(feature = "titlecase", issue = "153892")] + #[unstable(feature = "titlecase", issue = "153892")] + /// Returns an iterator that yields the titlecase equivalent of a `char`. /// - /// This `struct` is created by the [`to_uppercase`] method on [`char`]. See + /// This `struct` is created by the [`to_titlecase`] method on [`char`]. See /// its documentation for more. /// - /// [`to_uppercase`]: char::to_uppercase - ToUppercase + /// [`to_titlecase`]: char::to_titlecase + ToTitlecase +} + +casemappingiter_impls! { + #[stable(feature = "rust1", since = "1.0.0")] + #[stable(feature = "case_mapping_double_ended", since = "1.59.0")] + #[stable(feature = "fused", since = "1.26.0")] + #[stable(feature = "exact_size_case_mapping_iter", since = "1.35.0")] + #[stable(feature = "char_struct_display", since = "1.16.0")] + /// Returns an iterator that yields the lowercase equivalent of a `char`. + /// + /// This `struct` is created by the [`to_lowercase`] method on [`char`]. See + /// its documentation for more. + /// + /// [`to_lowercase`]: char::to_lowercase + ToLowercase } #[derive(Debug, Clone)] @@ -603,3 +636,23 @@ impl fmt::Display for TryFromCharError { #[stable(feature = "u8_from_char", since = "1.59.0")] impl Error for TryFromCharError {} + +/// The case of a cased character, +/// as returned by [`char::case`]. +/// +/// Titlecase characters conceptually are composed of an uppercase portion +/// followed by a lowercase portion. +/// The variant discriminants represent this: +/// the most significant bit represents whether the case +/// conceptually starts as uppercase, while the least significant bit +/// represents whether it conceptually ends as uppercase. +#[unstable(feature = "titlecase", issue = "153892")] +#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash, PartialOrd, Ord)] +pub enum CharCase { + /// Lowercase. Corresponds to the `Lowercase` Unicode property. + Lower = 0b00, + /// Titlecase. Corresponds to the `Titlecase_Letter` Unicode general category. + Title = 0b10, + /// Uppercase. Corresponds to the `Uppercase` Unicode property. + Upper = 0b11, +} diff --git a/core/src/cmp.rs b/core/src/cmp.rs index 78ea1f1113258..49d7487c2803b 100644 --- a/core/src/cmp.rs +++ b/core/src/cmp.rs @@ -336,19 +336,28 @@ pub macro PartialEq($item:item) { #[rustc_diagnostic_item = "Eq"] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] pub const trait Eq: [const] PartialEq + PointeeSized { - // this method is used solely by `impl Eq or #[derive(Eq)]` to assert that every component of a - // type implements `Eq` itself. The current deriving infrastructure means doing this assertion - // without using a method on this trait is nearly impossible. + // This method was used solely by `#[derive(Eq)]` to assert that every component of a + // type implements `Eq` itself. // // This should never be implemented by hand. #[doc(hidden)] #[coverage(off)] #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_diagnostic_item = "assert_receiver_is_total_eq"] + #[deprecated(since = "1.95.0", note = "implementation detail of `#[derive(Eq)]`")] fn assert_receiver_is_total_eq(&self) {} + + // FIXME (#152504): this method is used solely by `#[derive(Eq)]` to assert that + // every component of a type implements `Eq` itself. It will be removed again soon. + #[doc(hidden)] + #[coverage(off)] + #[unstable(feature = "derive_eq_internals", issue = "none")] + fn assert_fields_are_eq(&self) {} } /// Derive macro generating an impl of the trait [`Eq`]. +/// The behavior of this macro is described in detail [here](Eq#derivable). #[rustc_builtin_macro] #[stable(feature = "builtin_macro_prelude", since = "1.38.0")] #[allow_internal_unstable(core_intrinsics, derive_eq_internals, structural_match)] diff --git a/core/src/convert/num.rs b/core/src/convert/num.rs index 6e82e3356410c..b80980219b1e2 100644 --- a/core/src/convert/num.rs +++ b/core/src/convert/num.rs @@ -70,8 +70,8 @@ impl_from_bool!(i8 i16 i32 i64 i128 isize); /// Implement `From<$small>` for `$large` macro_rules! impl_from { - ($small:ty => $large:ty, #[$attr:meta]) => { - #[$attr] + ($small:ty => $large:ty, $(#[$attrs:meta]),+) => { + $(#[$attrs])+ #[rustc_const_unstable(feature = "const_convert", issue = "143773")] impl const From<$small> for $large { #[doc = concat!("Converts from [`", stringify!($small), "`] to [`", stringify!($large), "`] losslessly.")] @@ -157,8 +157,7 @@ impl_from!(i16 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0" impl_from!(i16 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); impl_from!(i32 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); impl_from!(i32 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -// FIXME(f128): This impl would allow using `f128` on stable before it is stabilised. -// impl_from!(i64 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); +impl_from!(i64 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); // unsigned integer -> float impl_from!(u8 => f16, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); @@ -170,8 +169,7 @@ impl_from!(u16 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0" impl_from!(u16 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); impl_from!(u32 => f64, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); impl_from!(u32 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); -// FIXME(f128): This impl would allow using `f128` on stable before it is stabilised. -// impl_from!(u64 => f128, #[stable(feature = "lossless_float_conv", since = "1.6.0")]); +impl_from!(u64 => f128, #[unstable(feature = "f128", issue = "116909")], #[unstable_feature_bound(f128)]); // float -> float // FIXME(f16,f128): adding additional `From<{float}>` impls to `f32` breaks inference. See @@ -198,11 +196,11 @@ macro_rules! impl_float_from_bool { /// # Examples /// ``` $($(#[doc = $doctest_prefix])*)? - #[doc = concat!("let x: ", stringify!($float)," = false.into();")] + #[doc = concat!("let x = ", stringify!($float), "::from(false);")] /// assert_eq!(x, 0.0); /// assert!(x.is_sign_positive()); /// - #[doc = concat!("let y: ", stringify!($float)," = true.into();")] + #[doc = concat!("let y = ", stringify!($float), "::from(true);")] /// assert_eq!(y, 1.0); $($(#[doc = $doctest_suffix])*)? /// ``` @@ -219,6 +217,7 @@ impl_float_from_bool!( f16; doctest_prefix: // rustdoc doesn't remove the conventional space after the `///` + ///# #![allow(unused_features)] ///#![feature(f16)] ///# #[cfg(all(target_arch = "x86_64", target_os = "linux"))] { /// @@ -230,6 +229,7 @@ impl_float_from_bool!(f64); impl_float_from_bool!( f128; doctest_prefix: + ///# #![allow(unused_features)] ///#![feature(f128)] ///# #[cfg(all(target_arch = "x86_64", target_os = "linux"))] { /// @@ -341,11 +341,11 @@ macro_rules! impl_try_from_integer_for_bool { /// # Examples /// /// ``` - #[doc = concat!("assert_eq!(0_", stringify!($int), ".try_into(), Ok(false));")] + #[doc = concat!("assert_eq!(bool::try_from(0_", stringify!($int), "), Ok(false));")] /// - #[doc = concat!("assert_eq!(1_", stringify!($int), ".try_into(), Ok(true));")] + #[doc = concat!("assert_eq!(bool::try_from(1_", stringify!($int), "), Ok(true));")] /// - #[doc = concat!("assert!(<", stringify!($int), " as TryInto>::try_into(2).is_err());")] + #[doc = concat!("assert!(bool::try_from(2_", stringify!($int), ").is_err());")] /// ``` #[inline] fn try_from(i: $int) -> Result { diff --git a/core/src/ffi/c_str.rs b/core/src/ffi/c_str.rs index 621277179bb38..62b3d75d7a779 100644 --- a/core/src/ffi/c_str.rs +++ b/core/src/ffi/c_str.rs @@ -8,7 +8,7 @@ use crate::iter::FusedIterator; use crate::marker::PhantomData; use crate::ptr::NonNull; use crate::slice::memchr; -use crate::{fmt, ops, slice, str}; +use crate::{fmt, ops, range, slice, str}; // FIXME: because this is doc(inline)d, we *have* to use intra-doc links because the actual link // depends on where the item is being documented. however, since this is libcore, we can't @@ -716,6 +716,16 @@ impl ops::Index> for CStr { } } +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +impl ops::Index> for CStr { + type Output = CStr; + + #[inline] + fn index(&self, index: range::RangeFrom) -> &CStr { + ops::Index::index(self, ops::RangeFrom::from(index)) + } +} + #[stable(feature = "cstring_asref", since = "1.7.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] impl const AsRef for CStr { diff --git a/core/src/ffi/va_list.rs b/core/src/ffi/va_list.rs index d0f155316a109..f0f58a0f83430 100644 --- a/core/src/ffi/va_list.rs +++ b/core/src/ffi/va_list.rs @@ -183,7 +183,44 @@ crate::cfg_select! { } } -/// A variable argument list, equivalent to `va_list` in C. +/// A variable argument list, ABI-compatible with `va_list` in C. +/// +/// This type is created in c-variadic functions when `...` is desugared. A `VaList` +/// is automatically initialized (equivalent to calling `va_start` in C). +/// +/// ``` +/// #![feature(c_variadic)] +/// +/// use std::ffi::VaList; +/// +/// /// # Safety +/// /// Must be passed at least `count` arguments of type `i32`. +/// unsafe extern "C" fn my_func(count: u32, ap: ...) -> i32 { +/// unsafe { vmy_func(count, ap) } +/// } +/// +/// /// # Safety +/// /// Must be passed at least `count` arguments of type `i32`. +/// unsafe fn vmy_func(count: u32, mut ap: VaList<'_>) -> i32 { +/// let mut sum = 0; +/// for _ in 0..count { +/// sum += unsafe { ap.arg::() }; +/// } +/// sum +/// } +/// +/// assert_eq!(unsafe { my_func(1, 42i32) }, 42); +/// assert_eq!(unsafe { my_func(3, 42i32, -7i32, 20i32) }, 55); +/// ``` +/// +/// The [`VaList::arg`] method can be used to read an argument from the list. This method +/// automatically advances the `VaList` to the next argument. The C equivalent is `va_arg`. +/// +/// Cloning a `VaList` performs the equivalent of C `va_copy`, producing an independent cursor +/// that arguments can be read from without affecting the original. Dropping a `VaList` performs +/// the equivalent of C `va_end`. +/// +/// This can be used across an FFI boundary, and fully matches the platform's `va_list`. #[repr(transparent)] #[lang = "va_list"] pub struct VaList<'a> { @@ -200,13 +237,14 @@ impl fmt::Debug for VaList<'_> { impl VaList<'_> { // Helper used in the implementation of the `va_copy` intrinsic. - pub(crate) fn duplicate(&self) -> Self { - Self { inner: self.inner.clone(), _marker: self._marker } + pub(crate) const fn duplicate(&self) -> Self { + Self { inner: self.inner, _marker: self._marker } } } -impl Clone for VaList<'_> { - #[inline] +#[rustc_const_unstable(feature = "const_c_variadic", issue = "151787")] +impl<'f> const Clone for VaList<'f> { + #[inline] // Avoid codegen when not used to help backends that don't support VaList. fn clone(&self) -> Self { // We only implement Clone and not Copy because some future target might not be able to // implement Copy (e.g. because it allocates). For the same reason we use an intrinsic @@ -216,7 +254,9 @@ impl Clone for VaList<'_> { } } -impl<'f> Drop for VaList<'f> { +#[rustc_const_unstable(feature = "const_c_variadic", issue = "151787")] +impl<'f> const Drop for VaList<'f> { + #[inline] // Avoid codegen when not used to help backends that don't support VaList. fn drop(&mut self) { // SAFETY: this variable argument list is being dropped, so won't be read from again. unsafe { va_end(self) } @@ -276,22 +316,20 @@ unsafe impl VaArgSafe for *mut T {} unsafe impl VaArgSafe for *const T {} impl<'f> VaList<'f> { - /// Advance to and read the next variable argument. + /// Read an argument from the variable argument list, and advance to the next argument. /// - /// # Safety + /// Only types that implement [`VaArgSafe`] can be read from a variable argument list. /// - /// This function is only sound to call when: + /// # Safety /// - /// - there is a next variable argument available. - /// - the next argument's type must be ABI-compatible with the type `T`. - /// - the next argument must have a properly initialized value of type `T`. + /// This function is only sound to call when there is another argument to read, and that + /// argument is a properly initialized value of the type `T`. /// /// Calling this function with an incompatible type, an invalid value, or when there /// are no more variable arguments, is unsound. - /// - /// [valid]: https://doc.rust-lang.org/nightly/nomicon/what-unsafe-does.html - #[inline] - pub unsafe fn arg(&mut self) -> T { + #[inline] // Avoid codegen when not used to help backends that don't support VaList. + #[rustc_const_unstable(feature = "const_c_variadic", issue = "151787")] + pub const unsafe fn arg(&mut self) -> T { // SAFETY: the caller must uphold the safety contract for `va_arg`. unsafe { va_arg(self) } } diff --git a/core/src/field.rs b/core/src/field.rs new file mode 100644 index 0000000000000..e8ef309b9c84f --- /dev/null +++ b/core/src/field.rs @@ -0,0 +1,83 @@ +//! Field Reflection + +use crate::marker::PhantomData; + +/// Field Representing Type +#[unstable(feature = "field_representing_type_raw", issue = "none")] +#[lang = "field_representing_type"] +#[expect(missing_debug_implementations)] +#[fundamental] +pub struct FieldRepresentingType { + _phantom: PhantomData, +} + +// SAFETY: `FieldRepresentingType` doesn't contain any `T` +unsafe impl Send + for FieldRepresentingType +{ +} + +// SAFETY: `FieldRepresentingType` doesn't contain any `T` +unsafe impl Sync + for FieldRepresentingType +{ +} + +impl Copy + for FieldRepresentingType +{ +} + +impl Clone + for FieldRepresentingType +{ + fn clone(&self) -> Self { + *self + } +} + +/// Expands to the field representing type of the given field. +/// +/// The container type may be a tuple, `struct`, `union` or `enum`. In the case of an enum, the +/// variant must also be specified. Only a single field is supported. +#[unstable(feature = "field_projections", issue = "145383")] +#[allow_internal_unstable(field_representing_type_raw, builtin_syntax)] +// NOTE: when stabilizing this macro, we can never add new trait impls for `FieldRepresentingType`, +// since it is `#[fundamental]` and thus could break users of this macro, since the compiler expands +// it to `FieldRepresentingType<...>`. Thus stabilizing this requires careful thought about the +// completeness of the trait impls for `FieldRepresentingType`. +pub macro field_of($Container:ty, $($fields:expr)+ $(,)?) { + builtin # field_of($Container, $($fields)+) +} + +/// Type representing a field of a `struct`, `union`, `enum` variant or tuple. +/// +/// # Safety +/// +/// Given a valid value of type `Self::Base`, there exists a valid value of type `Self::Type` at +/// byte offset `OFFSET` +#[lang = "field"] +#[unstable(feature = "field_projections", issue = "145383")] +#[rustc_deny_explicit_impl] +#[rustc_dyn_incompatible_trait] +// NOTE: the compiler provides the impl of `Field` for `FieldRepresentingType` when it can guarantee +// the safety requirements of this trait. It also has to manually add the correct trait bounds on +// associated types (and the `Self` type). Thus any changes to the bounds here must be reflected in +// the old and new trait solver: +// - `fn assemble_candidates_for_field_trait` in +// `compiler/rustc_trait_selection/src/traits/select/candidate_assembly.rs`, and +// - `fn consider_builtin_field_candidate` in +// `compiler/rustc_next_trait_solver/src/solve/trait_goals.rs`. +pub unsafe trait Field: Send + Sync + Copy { + /// The type of the base where this field exists in. + #[lang = "field_base"] + type Base; + + /// The type of the field. + #[lang = "field_type"] + type Type; + + /// The offset of the field in bytes. + #[lang = "field_offset"] + const OFFSET: usize = crate::intrinsics::field_offset::(); +} diff --git a/core/src/fmt/builders.rs b/core/src/fmt/builders.rs index 7550dac45cd02..19dd13967fdd6 100644 --- a/core/src/fmt/builders.rs +++ b/core/src/fmt/builders.rs @@ -1227,7 +1227,7 @@ impl<'a, 'b: 'a> DebugMap<'a, 'b> { /// assert_eq!(format!("{:?}", wrapped), "'a'"); /// ``` #[stable(feature = "fmt_from_fn", since = "1.93.0")] -#[rustc_const_stable(feature = "const_fmt_from_fn", since = "CURRENT_RUSTC_VERSION")] +#[rustc_const_stable(feature = "const_fmt_from_fn", since = "1.95.0")] #[must_use = "returns a type implementing Debug and Display, which do not have any effects unless they are used"] pub const fn from_fn) -> fmt::Result>(f: F) -> FromFn { FromFn(f) diff --git a/core/src/fmt/float.rs b/core/src/fmt/float.rs index 6a458436726cf..87ce27b0d86de 100644 --- a/core/src/fmt/float.rs +++ b/core/src/fmt/float.rs @@ -1,6 +1,6 @@ use crate::fmt::{Debug, Display, Formatter, LowerExp, Result, UpperExp}; use crate::mem::MaybeUninit; -use crate::num::{flt2dec, fmt as numfmt}; +use crate::num::imp::{flt2dec, fmt as numfmt}; #[doc(hidden)] trait GeneralFormat: PartialOrd { diff --git a/core/src/fmt/mod.rs b/core/src/fmt/mod.rs index e20109c3cc9a8..ecd1e34078e29 100644 --- a/core/src/fmt/mod.rs +++ b/core/src/fmt/mod.rs @@ -6,7 +6,7 @@ use crate::cell::{Cell, Ref, RefCell, RefMut, SyncUnsafeCell, UnsafeCell}; use crate::char::EscapeDebugExtArgs; use crate::hint::assert_unchecked; use crate::marker::{PhantomData, PointeeSized}; -use crate::num::fmt as numfmt; +use crate::num::imp::fmt as numfmt; use crate::ops::Deref; use crate::ptr::NonNull; use crate::{iter, mem, result, str}; @@ -1037,9 +1037,10 @@ impl Display for Arguments<'_> { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_on_unimplemented( on( - crate_local, + all(crate_local, not(Self = "{union}")), note = "add `#[derive(Debug)]` to `{Self}` or manually `impl {This} for {Self}`" ), + on(all(crate_local, Self = "{union}"), note = "manually `impl {This} for {Self}`"), on( from_desugaring = "FormatLiteral", label = "`{Self}` cannot be formatted using `{{:?}}` because it doesn't implement `{This}`" diff --git a/core/src/fmt/num.rs b/core/src/fmt/num.rs index 253a7b7587e49..e9302a6127f5c 100644 --- a/core/src/fmt/num.rs +++ b/core/src/fmt/num.rs @@ -2,7 +2,7 @@ use crate::fmt::NumBuffer; use crate::mem::MaybeUninit; -use crate::num::fmt as numfmt; +use crate::num::imp::fmt as numfmt; use crate::{fmt, str}; /// Formatting of integers with a non-decimal radix. @@ -594,6 +594,7 @@ impl_Debug! { // Include wasm32 in here since it doesn't reflect the native pointer size, and // often cares strongly about getting a smaller code size. #[cfg(any(target_pointer_width = "64", target_arch = "wasm32"))] +#[doc(auto_cfg = false)] mod imp { use super::*; impl_Display!(i8, u8, i16, u16, i32, u32, i64, u64, isize, usize; as u64 into display_u64); @@ -601,6 +602,7 @@ mod imp { } #[cfg(not(any(target_pointer_width = "64", target_arch = "wasm32")))] +#[doc(auto_cfg = false)] mod imp { use super::*; impl_Display!(i8, u8, i16, u16, i32, u32, isize, usize; as u32 into display_u32); @@ -823,7 +825,7 @@ fn enc_16lsd(buf: &mut [MaybeUninit], n: u64) { let mut remain = n; // Format per four digits from the lookup table. - for quad_index in (0..4).rev() { + for quad_index in (1..4).rev() { // pull two pairs let quad = remain % 1_00_00; remain /= 1_00_00; @@ -834,6 +836,14 @@ fn enc_16lsd(buf: &mut [MaybeUninit], n: u64) { buf[quad_index * 4 + OFFSET + 2].write(DECIMAL_PAIRS[pair2 * 2 + 0]); buf[quad_index * 4 + OFFSET + 3].write(DECIMAL_PAIRS[pair2 * 2 + 1]); } + + // final two pairs + let pair1 = (remain / 100) as usize; + let pair2 = (remain % 100) as usize; + buf[OFFSET + 0].write(DECIMAL_PAIRS[pair1 * 2 + 0]); + buf[OFFSET + 1].write(DECIMAL_PAIRS[pair1 * 2 + 1]); + buf[OFFSET + 2].write(DECIMAL_PAIRS[pair2 * 2 + 0]); + buf[OFFSET + 3].write(DECIMAL_PAIRS[pair2 * 2 + 1]); } /// Euclidean division plus remainder with constant 1E16 basically consumes 16 diff --git a/core/src/future/async_drop.rs b/core/src/future/async_drop.rs index c48c3f2ba281e..106493fd3e815 100644 --- a/core/src/future/async_drop.rs +++ b/core/src/future/async_drop.rs @@ -41,6 +41,15 @@ pub trait AsyncDrop { } /// Async drop. +/// +/// # Safety +/// +/// The pointer `_to_drop` must be valid for both reads and writes, +/// not only for the duration of this function call, +/// but also until the returned future has completed. +/// See [ptr::drop_in_place] for additional safety concerns. +/// +/// [ptr::drop_in_place]: crate::ptr::drop_in_place() #[unstable(feature = "async_drop", issue = "126482")] #[lang = "async_drop_in_place"] pub async unsafe fn async_drop_in_place(_to_drop: *mut T) { diff --git a/core/src/hint.rs b/core/src/hint.rs index dccac26e07e69..a8e01e6e78b4b 100644 --- a/core/src/hint.rs +++ b/core/src/hint.rs @@ -514,7 +514,7 @@ pub const fn black_box(dummy: T) -> T { /// macro_rules! make_error { /// ($($args:expr),*) => { /// core::hint::must_use({ -/// let error = $crate::make_error(core::format_args!($($args),*)); +/// let error = make_error(core::format_args!($($args),*)); /// error /// }) /// }; @@ -724,7 +724,6 @@ pub const fn unlikely(b: bool) -> bool { /// # Examples /// /// ``` -/// #![feature(cold_path)] /// use core::hint::cold_path; /// /// fn foo(x: &[i32]) { @@ -750,7 +749,6 @@ pub const fn unlikely(b: bool) -> bool { /// than the branch: /// /// ``` -/// #![feature(cold_path)] /// use core::hint::cold_path; /// /// #[inline(always)] @@ -777,7 +775,8 @@ pub const fn unlikely(b: bool) -> bool { /// } /// } /// ``` -#[unstable(feature = "cold_path", issue = "136873")] +#[stable(feature = "cold_path", since = "1.95.0")] +#[rustc_const_stable(feature = "cold_path", since = "1.95.0")] #[inline(always)] pub const fn cold_path() { crate::intrinsics::cold_path() diff --git a/core/src/index.rs b/core/src/index.rs index 3baefdf10cecb..70372163c6e17 100644 --- a/core/src/index.rs +++ b/core/src/index.rs @@ -315,7 +315,7 @@ unsafe impl SliceIndex<[T]> for Clamp> { } #[unstable(feature = "sliceindex_wrappers", issue = "146179")] -unsafe impl SliceIndex<[T]> for Clamp> { +unsafe impl SliceIndex<[T]> for Clamp> { type Output = [T]; fn get(self, slice: &[T]) -> Option<&Self::Output> { @@ -408,7 +408,7 @@ unsafe impl SliceIndex<[T]> for Clamp> { } #[unstable(feature = "sliceindex_wrappers", issue = "146179")] -unsafe impl SliceIndex<[T]> for Clamp { +unsafe impl SliceIndex<[T]> for Clamp { type Output = [T]; fn get(self, slice: &[T]) -> Option<&Self::Output> { diff --git a/core/src/intrinsics/bounds.rs b/core/src/intrinsics/bounds.rs index 353908598d40b..21705005ed0ae 100644 --- a/core/src/intrinsics/bounds.rs +++ b/core/src/intrinsics/bounds.rs @@ -39,3 +39,14 @@ impl ChangePointee for *mut T { impl ChangePointee for *const T { type Output = *const U; } + +/// Built-in float types (f16, f32, f64 and f128). +/// +/// # Safety +/// Must actually *be* such a type. +pub unsafe trait FloatPrimitive: Sized + Copy {} + +unsafe impl FloatPrimitive for f16 {} +unsafe impl FloatPrimitive for f32 {} +unsafe impl FloatPrimitive for f64 {} +unsafe impl FloatPrimitive for f128 {} diff --git a/core/src/intrinsics/fallback.rs b/core/src/intrinsics/fallback.rs index 932537f2581f8..aa9033ee3d260 100644 --- a/core/src/intrinsics/fallback.rs +++ b/core/src/intrinsics/fallback.rs @@ -218,3 +218,38 @@ macro_rules! impl_funnel_shifts { impl_funnel_shifts! { u8, u16, u32, u64, u128, usize } + +#[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] +pub const trait CarrylessMul: Copy + 'static { + /// See [`super::carryless_mul`]; we just need the trait indirection to handle + /// different types since calling intrinsics with generics doesn't work. + fn carryless_mul(self, rhs: Self) -> Self; +} + +macro_rules! impl_carryless_mul{ + ($($type:ident),*) => {$( + #[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] + impl const CarrylessMul for $type { + #[inline] + fn carryless_mul(self, rhs: Self) -> Self { + let mut result = 0; + let mut i = 0; + + while i < $type::BITS { + // If the i-th bit in rhs is set. + if (rhs >> i) & 1 != 0 { + // Then xor the result with `self` shifted to the left by i positions. + result ^= self << i; + } + i += 1; + } + + result + } + } + )*}; +} + +impl_carryless_mul! { + u8, u16, u32, u64, u128, usize +} diff --git a/core/src/intrinsics/mir.rs b/core/src/intrinsics/mir.rs index 939298268c934..7659e0042b379 100644 --- a/core/src/intrinsics/mir.rs +++ b/core/src/intrinsics/mir.rs @@ -62,7 +62,9 @@ //! //! # Examples //! -//! ```rust +#![cfg_attr(panic = "unwind", doc = "```rust")] +// This test can't support panic=abort because it generates an UnwindContinue MIR terminator. +#![cfg_attr(panic = "abort", doc = "```ignore")] //! #![feature(core_intrinsics, custom_mir)] //! #![allow(internal_features)] //! #![allow(unused_assignments)] diff --git a/core/src/intrinsics/mod.rs b/core/src/intrinsics/mod.rs index 051dda731881f..6f9d351300168 100644 --- a/core/src/intrinsics/mod.rs +++ b/core/src/intrinsics/mod.rs @@ -409,8 +409,7 @@ pub const unsafe fn assume(b: bool) { /// Therefore, implementations must not require the user to uphold /// any safety invariants. /// -/// This intrinsic does not have a stable counterpart. -#[unstable(feature = "core_intrinsics", issue = "none")] +/// The stabilized version of this intrinsic is [`core::hint::cold_path`]. #[rustc_intrinsic] #[rustc_nounwind] #[miri::intrinsic_fallback_is_spec] @@ -1574,7 +1573,7 @@ pub const fn roundf128(x: f128) -> f128; /// This intrinsic does not have a stable counterpart. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn fadd_fast(a: T, b: T) -> T; +pub unsafe fn fadd_fast(a: T, b: T) -> T; /// Float subtraction that allows optimizations based on algebraic rules. /// Requires that inputs and output of the operation are finite, causing UB otherwise. @@ -1582,7 +1581,7 @@ pub unsafe fn fadd_fast(a: T, b: T) -> T; /// This intrinsic does not have a stable counterpart. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn fsub_fast(a: T, b: T) -> T; +pub unsafe fn fsub_fast(a: T, b: T) -> T; /// Float multiplication that allows optimizations based on algebraic rules. /// Requires that inputs and output of the operation are finite, causing UB otherwise. @@ -1590,7 +1589,7 @@ pub unsafe fn fsub_fast(a: T, b: T) -> T; /// This intrinsic does not have a stable counterpart. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn fmul_fast(a: T, b: T) -> T; +pub unsafe fn fmul_fast(a: T, b: T) -> T; /// Float division that allows optimizations based on algebraic rules. /// Requires that inputs and output of the operation are finite, causing UB otherwise. @@ -1598,7 +1597,7 @@ pub unsafe fn fmul_fast(a: T, b: T) -> T; /// This intrinsic does not have a stable counterpart. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn fdiv_fast(a: T, b: T) -> T; +pub unsafe fn fdiv_fast(a: T, b: T) -> T; /// Float remainder that allows optimizations based on algebraic rules. /// Requires that inputs and output of the operation are finite, causing UB otherwise. @@ -1606,7 +1605,7 @@ pub unsafe fn fdiv_fast(a: T, b: T) -> T; /// This intrinsic does not have a stable counterpart. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn frem_fast(a: T, b: T) -> T; +pub unsafe fn frem_fast(a: T, b: T) -> T; /// Converts with LLVM’s fptoui/fptosi, which may return undef for values out of range /// () @@ -1614,42 +1613,43 @@ pub unsafe fn frem_fast(a: T, b: T) -> T; /// Stabilized as [`f32::to_int_unchecked`] and [`f64::to_int_unchecked`]. #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn float_to_int_unchecked(value: Float) -> Int; +pub unsafe fn float_to_int_unchecked(value: Float) +-> Int; /// Float addition that allows optimizations based on algebraic rules. /// /// Stabilized as [`f16::algebraic_add`], [`f32::algebraic_add`], [`f64::algebraic_add`] and [`f128::algebraic_add`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn fadd_algebraic(a: T, b: T) -> T; +pub const fn fadd_algebraic(a: T, b: T) -> T; /// Float subtraction that allows optimizations based on algebraic rules. /// /// Stabilized as [`f16::algebraic_sub`], [`f32::algebraic_sub`], [`f64::algebraic_sub`] and [`f128::algebraic_sub`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn fsub_algebraic(a: T, b: T) -> T; +pub const fn fsub_algebraic(a: T, b: T) -> T; /// Float multiplication that allows optimizations based on algebraic rules. /// /// Stabilized as [`f16::algebraic_mul`], [`f32::algebraic_mul`], [`f64::algebraic_mul`] and [`f128::algebraic_mul`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn fmul_algebraic(a: T, b: T) -> T; +pub const fn fmul_algebraic(a: T, b: T) -> T; /// Float division that allows optimizations based on algebraic rules. /// /// Stabilized as [`f16::algebraic_div`], [`f32::algebraic_div`], [`f64::algebraic_div`] and [`f128::algebraic_div`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn fdiv_algebraic(a: T, b: T) -> T; +pub const fn fdiv_algebraic(a: T, b: T) -> T; /// Float remainder that allows optimizations based on algebraic rules. /// /// Stabilized as [`f16::algebraic_rem`], [`f32::algebraic_rem`], [`f64::algebraic_rem`] and [`f128::algebraic_rem`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn frem_algebraic(a: T, b: T) -> T; +pub const fn frem_algebraic(a: T, b: T) -> T; /// Returns the number of bits set in an integer type `T` /// @@ -2179,6 +2179,19 @@ pub const unsafe fn unchecked_funnel_shr( unsafe { a.unchecked_funnel_shr(b, shift) } } +/// Carryless multiply. +/// +/// Safe versions of this intrinsic are available on the integer primitives +/// via the `carryless_mul` method. For example, [`u32::carryless_mul`]. +#[rustc_intrinsic] +#[rustc_nounwind] +#[rustc_const_unstable(feature = "uint_carryless_mul", issue = "152080")] +#[unstable(feature = "uint_carryless_mul", issue = "152080")] +#[miri::intrinsic_fallback_is_spec] +pub const fn carryless_mul(a: T, b: T) -> T { + a.carryless_mul(b) +} + /// This is an implementation detail of [`crate::ptr::read`] and should /// not be used anywhere else. See its comments for why this exists. /// @@ -2490,14 +2503,6 @@ pub(crate) macro const_eval_select { /// particular value, ever. However, the compiler will generally make it /// return `true` only if the value of the argument is actually known. /// -/// # Stability concerns -/// -/// While it is safe to call, this intrinsic may behave differently in -/// a `const` context than otherwise. See the [`const_eval_select()`] -/// documentation for an explanation of the issues this can cause. Unlike -/// `const_eval_select`, this intrinsic isn't guaranteed to behave -/// deterministically even in a `const` context. -/// /// # Type Requirements /// /// `T` must be either a `bool`, a `char`, a primitive numeric type (e.g. `f32`, @@ -2578,6 +2583,12 @@ pub const unsafe fn typed_swap_nonoverlapping(x: *mut T, y: *mut T) { /// assertions are enabled whenever the *user crate* has UB checks enabled. However, if the /// user has UB checks disabled, the checks will still get optimized out. This intrinsic is /// primarily used by [`crate::ub_checks::assert_unsafe_precondition`]. +/// +/// # Consteval +/// +/// In consteval, this function currently returns `true`. This is because the value of the `ub_checks` +/// configuration can differ across crates, but we need this function to always return the same +/// value in consteval in order to avoid unsoundness. #[rustc_intrinsic_const_stable_indirect] // just for UB checks #[inline(always)] #[rustc_intrinsic] @@ -2597,6 +2608,12 @@ pub const fn ub_checks() -> bool { /// `#[inline]`), gating assertions on `overflow_checks()` rather than `cfg!(overflow_checks)` means that /// assertions are enabled whenever the *user crate* has overflow checks enabled. However if the /// user has overflow checks disabled, the checks will still get optimized out. +/// +/// # Consteval +/// +/// In consteval, this function currently returns `true`. This is because the value of the `overflow_checks` +/// configuration can differ across crates, but we need this function to always return the same +/// value in consteval in order to avoid unsoundness. #[inline(always)] #[rustc_intrinsic] pub const fn overflow_checks() -> bool { @@ -2739,18 +2756,6 @@ pub unsafe fn vtable_size(ptr: *const ()) -> usize; #[rustc_intrinsic] pub unsafe fn vtable_align(ptr: *const ()) -> usize; -/// The intrinsic returns the `U` vtable for `T` if `T` can be coerced to the trait object type `U`. -/// -/// # Compile-time failures -/// Determining whether `T` can be coerced to the trait object type `U` requires trait resolution by the compiler. -/// In some cases, that resolution can exceed the recursion limit, -/// and compilation will fail instead of this function returning `None`. -#[rustc_nounwind] -#[unstable(feature = "core_intrinsics", issue = "none")] -#[rustc_intrinsic] -pub const fn vtable_for> + ?Sized>() --> Option>; - /// The size of a type in bytes. /// /// Note that, unlike most intrinsics, this is safe to call; @@ -2812,6 +2817,20 @@ pub const fn align_of() -> usize; #[lang = "offset_of"] pub const fn offset_of(variant: u32, field: u32) -> usize; +/// The offset of a field queried by its field representing type. +/// +/// Returns the offset of the field represented by `F`. This function essentially does the same as +/// the [`offset_of`] intrinsic, but expects the field to be represented by a generic rather than +/// the variant and field indices. This also is a safe intrinsic and can only be evaluated at +/// compile-time, so it should only appear in constants or inline const blocks. +/// +/// There should be no need to call this intrinsic manually, as its value is used to define +/// [`Field::OFFSET`](crate::field::Field::OFFSET), which is publicly accessible. +#[rustc_intrinsic] +#[unstable(feature = "field_projections", issue = "145383")] +#[rustc_const_unstable(feature = "field_projections", issue = "145383")] +pub const fn field_offset() -> usize; + /// Returns the number of variants of the type `T` cast to a `usize`; /// if `T` has no variants, returns `0`. Uninhabited variants will be counted. /// @@ -2852,6 +2871,20 @@ pub const unsafe fn size_of_val(ptr: *const T) -> usize; #[rustc_intrinsic_const_stable_indirect] pub const unsafe fn align_of_val(ptr: *const T) -> usize; +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +/// Check if a type represented by a `TypeId` implements a trait represented by a `TypeId`. +/// It can only be called at compile time, the backends do +/// not implement it. If it implements the trait the dyn metadata gets returned for vtable access. +pub const fn type_id_vtable( + _id: crate::any::TypeId, + _trait: crate::any::TypeId, +) -> Option> { + panic!( + "`TypeId::trait_info_of` and `trait_info_of_trait_type_id` can only be called at compile-time" + ) +} + /// Compute the type information of a concrete type. /// It can only be called at compile time, the backends do /// not implement it. @@ -2887,7 +2920,7 @@ pub const fn type_name() -> &'static str; #[rustc_nounwind] #[unstable(feature = "core_intrinsics", issue = "none")] #[rustc_intrinsic] -pub const fn type_id() -> crate::any::TypeId; +pub const fn type_id() -> crate::any::TypeId; /// Tests (at compile-time) if two [`crate::any::TypeId`] instances identify the /// same type. This is necessary because at const-eval time the actual discriminating @@ -2959,6 +2992,8 @@ pub const unsafe fn write_bytes(dst: *mut T, val: u8, count: usize); /// Returns the minimum of two `f16` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 minimumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -2971,10 +3006,19 @@ pub const unsafe fn write_bytes(dst: *mut T, val: u8, count: usize); /// The stabilized version of this intrinsic is [`f16::min`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn minnumf16(x: f16, y: f16) -> f16; +pub const fn minimum_number_nsz_f16(x: f16, y: f16) -> f16 { + if x.is_nan() || y <= x { + y + } else { + // Either y > x or y is a NaN. + x + } +} /// Returns the minimum of two `f32` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 minimumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -2988,10 +3032,19 @@ pub const fn minnumf16(x: f16, y: f16) -> f16; #[rustc_nounwind] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn minnumf32(x: f32, y: f32) -> f32; +pub const fn minimum_number_nsz_f32(x: f32, y: f32) -> f32 { + if x.is_nan() || y <= x { + y + } else { + // Either y > x or y is a NaN. + x + } +} /// Returns the minimum of two `f64` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 minimumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3005,10 +3058,19 @@ pub const fn minnumf32(x: f32, y: f32) -> f32; #[rustc_nounwind] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn minnumf64(x: f64, y: f64) -> f64; +pub const fn minimum_number_nsz_f64(x: f64, y: f64) -> f64 { + if x.is_nan() || y <= x { + y + } else { + // Either y > x or y is a NaN. + x + } +} /// Returns the minimum of two `f128` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 minimumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3021,7 +3083,14 @@ pub const fn minnumf64(x: f64, y: f64) -> f64; /// The stabilized version of this intrinsic is [`f128::min`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn minnumf128(x: f128, y: f128) -> f128; +pub const fn minimum_number_nsz_f128(x: f128, y: f128) -> f128 { + if x.is_nan() || y <= x { + y + } else { + // Either y > x or y is a NaN. + x + } +} /// Returns the minimum of two `f16` values, propagating NaN. /// @@ -3125,6 +3194,8 @@ pub const fn minimumf128(x: f128, y: f128) -> f128 { /// Returns the maximum of two `f16` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 maximumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3137,10 +3208,19 @@ pub const fn minimumf128(x: f128, y: f128) -> f128 { /// The stabilized version of this intrinsic is [`f16::max`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn maxnumf16(x: f16, y: f16) -> f16; +pub const fn maximum_number_nsz_f16(x: f16, y: f16) -> f16 { + if x.is_nan() || y >= x { + y + } else { + // Either y < x or y is a NaN. + x + } +} /// Returns the maximum of two `f32` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 maximumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3154,10 +3234,19 @@ pub const fn maxnumf16(x: f16, y: f16) -> f16; #[rustc_nounwind] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn maxnumf32(x: f32, y: f32) -> f32; +pub const fn maximum_number_nsz_f32(x: f32, y: f32) -> f32 { + if x.is_nan() || y >= x { + y + } else { + // Either y < x or y is a NaN. + x + } +} /// Returns the maximum of two `f64` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 maximumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3171,10 +3260,19 @@ pub const fn maxnumf32(x: f32, y: f32) -> f32; #[rustc_nounwind] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn maxnumf64(x: f64, y: f64) -> f64; +pub const fn maximum_number_nsz_f64(x: f64, y: f64) -> f64 { + if x.is_nan() || y >= x { + y + } else { + // Either y < x or y is a NaN. + x + } +} /// Returns the maximum of two `f128` values, ignoring NaN. /// +/// This behaves like IEEE 754-2019 maximumNumber, *except* that it does not order signed +/// zeros deterministically. In particular: /// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If /// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` /// and `-0.0`), either input may be returned non-deterministically. @@ -3187,7 +3285,14 @@ pub const fn maxnumf64(x: f64, y: f64) -> f64; /// The stabilized version of this intrinsic is [`f128::max`]. #[rustc_nounwind] #[rustc_intrinsic] -pub const fn maxnumf128(x: f128, y: f128) -> f128; +pub const fn maximum_number_nsz_f128(x: f128, y: f128) -> f128 { + if x.is_nan() || y >= x { + y + } else { + // Either y < x or y is a NaN. + x + } +} /// Returns the maximum of two `f16` values, propagating NaN. /// @@ -3285,39 +3390,14 @@ pub const fn maximumf128(x: f128, y: f128) -> f128 { } } -/// Returns the absolute value of an `f16`. -/// -/// The stabilized version of this intrinsic is -/// [`f16::abs`](../../std/primitive.f16.html#method.abs) -#[rustc_nounwind] -#[rustc_intrinsic] -pub const fn fabsf16(x: f16) -> f16; - -/// Returns the absolute value of an `f32`. -/// -/// The stabilized version of this intrinsic is -/// [`f32::abs`](../../std/primitive.f32.html#method.abs) -#[rustc_nounwind] -#[rustc_intrinsic_const_stable_indirect] -#[rustc_intrinsic] -pub const fn fabsf32(x: f32) -> f32; - -/// Returns the absolute value of an `f64`. +/// Returns the absolute value of a floating-point value. /// -/// The stabilized version of this intrinsic is -/// [`f64::abs`](../../std/primitive.f64.html#method.abs) +/// The stabilized versions of this intrinsic are available on the float +/// primitives via the `abs` method. For example, [`f32::abs`]. #[rustc_nounwind] #[rustc_intrinsic_const_stable_indirect] #[rustc_intrinsic] -pub const fn fabsf64(x: f64) -> f64; - -/// Returns the absolute value of an `f128`. -/// -/// The stabilized version of this intrinsic is -/// [`f128::abs`](../../std/primitive.f128.html#method.abs) -#[rustc_nounwind] -#[rustc_intrinsic] -pub const fn fabsf128(x: f128) -> f128; +pub const fn fabs(x: T) -> T; /// Copies the sign from `y` to `x` for `f16` values. /// @@ -3473,7 +3553,7 @@ pub(crate) const fn miri_promise_symbolic_alignment(ptr: *const (), align: usize /// #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn va_arg(ap: &mut VaList<'_>) -> T; +pub const unsafe fn va_arg(ap: &mut VaList<'_>) -> T; /// Duplicates a variable argument list. The returned list is initially at the same position as /// the one in `src`, but can be advanced independently. @@ -3485,7 +3565,7 @@ pub unsafe fn va_arg(ap: &mut VaList<'_>) -> T; /// when a variable argument list is used incorrectly. #[rustc_intrinsic] #[rustc_nounwind] -pub fn va_copy<'f>(src: &VaList<'f>) -> VaList<'f> { +pub const fn va_copy<'f>(src: &VaList<'f>) -> VaList<'f> { src.duplicate() } @@ -3504,6 +3584,6 @@ pub fn va_copy<'f>(src: &VaList<'f>) -> VaList<'f> { /// #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn va_end(ap: &mut VaList<'_>) { +pub const unsafe fn va_end(ap: &mut VaList<'_>) { /* deliberately does nothing */ } diff --git a/core/src/intrinsics/simd.rs b/core/src/intrinsics/simd.rs index f70262c38ae50..ae86690dc418d 100644 --- a/core/src/intrinsics/simd.rs +++ b/core/src/intrinsics/simd.rs @@ -62,6 +62,7 @@ pub const unsafe fn simd_splat(value: U) -> T; /// Adds two simd vectors elementwise. /// /// `T` must be a vector of integers or floats. +/// For integers, wrapping arithmetic is used. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_add(x: T, y: T) -> T; @@ -69,6 +70,7 @@ pub const unsafe fn simd_add(x: T, y: T) -> T; /// Subtracts `rhs` from `lhs` elementwise. /// /// `T` must be a vector of integers or floats. +/// For integers, wrapping arithmetic is used. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_sub(lhs: T, rhs: T) -> T; @@ -76,6 +78,7 @@ pub const unsafe fn simd_sub(lhs: T, rhs: T) -> T; /// Multiplies two simd vectors elementwise. /// /// `T` must be a vector of integers or floats. +/// For integers, wrapping arithmetic is used. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_mul(x: T, y: T) -> T; @@ -162,6 +165,18 @@ pub const unsafe fn simd_funnel_shl(a: T, b: T, shift: T) -> T; #[rustc_nounwind] pub const unsafe fn simd_funnel_shr(a: T, b: T, shift: T) -> T; +/// Compute the carry-less product. +/// +/// This is similar to long multiplication except that the carry is discarded. +/// +/// This operation can be used to model multiplication in `GF(2)[X]`, the polynomial +/// ring over `GF(2)`. +/// +/// `T` must be a vector of integers. +#[rustc_intrinsic] +#[rustc_nounwind] +pub unsafe fn simd_carryless_mul(a: T, b: T) -> T; + /// "And"s vectors elementwise. /// /// `T` must be a vector of integers. @@ -221,8 +236,7 @@ pub const unsafe fn simd_as(x: T) -> U; /// Negates a vector elementwise. /// /// `T` must be a vector of integers or floats. -/// -/// Rust panics for `-::Min` due to overflow, but it is not UB with this intrinsic. +/// For integers, wrapping arithmetic is used. #[rustc_intrinsic] #[rustc_nounwind] pub const unsafe fn simd_neg(x: T) -> T; @@ -238,19 +252,27 @@ pub const unsafe fn simd_fabs(x: T) -> T; /// /// `T` must be a vector of floating-point primitive types. /// -/// Follows IEEE-754 `minNum` semantics. +/// This behaves like IEEE 754-2019 minimumNumber, *except* that it does not order signed +/// zeros deterministically. In particular, for each vector lane: +/// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If +/// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` +/// and `-0.0`), either input may be returned non-deterministically. #[rustc_intrinsic] #[rustc_nounwind] -pub const unsafe fn simd_fmin(x: T, y: T) -> T; +pub const unsafe fn simd_minimum_number_nsz(x: T, y: T) -> T; /// Returns the maximum of two vectors, elementwise. /// /// `T` must be a vector of floating-point primitive types. /// -/// Follows IEEE-754 `maxNum` semantics. +/// This behaves like IEEE 754-2019 maximumNumber, *except* that it does not order signed +/// zeros deterministically. In particular, for each vector lane: +/// If one of the arguments is NaN (quiet or signaling), then the other argument is returned. If +/// both arguments are NaN, returns NaN. If the inputs compare equal (such as for the case of `+0.0` +/// and `-0.0`), either input may be returned non-deterministically. #[rustc_intrinsic] #[rustc_nounwind] -pub const unsafe fn simd_fmax(x: T, y: T) -> T; +pub const unsafe fn simd_maximum_number_nsz(x: T, y: T) -> T; /// Tests elementwise equality of two vectors. /// diff --git a/core/src/iter/adapters/intersperse.rs b/core/src/iter/adapters/intersperse.rs index bb94ed0a0a170..f64dea2df862c 100644 --- a/core/src/iter/adapters/intersperse.rs +++ b/core/src/iter/adapters/intersperse.rs @@ -1,5 +1,4 @@ use crate::fmt; -use crate::iter::{Fuse, FusedIterator}; /// An iterator adapter that places a separator between all elements. /// @@ -14,15 +13,7 @@ where started: bool, separator: I::Item, next_item: Option, - iter: Fuse, -} - -#[unstable(feature = "iter_intersperse", issue = "79524")] -impl FusedIterator for Intersperse -where - I: FusedIterator, - I::Item: Clone, -{ + iter: I, } impl Intersperse @@ -30,7 +21,7 @@ where I::Item: Clone, { pub(in crate::iter) fn new(iter: I, separator: I::Item) -> Self { - Self { started: false, separator, next_item: None, iter: iter.fuse() } + Self { started: false, separator, next_item: None, iter } } } @@ -57,8 +48,9 @@ where } } } else { - self.started = true; - self.iter.next() + let item = self.iter.next(); + self.started = item.is_some(); + item } } @@ -95,15 +87,7 @@ where started: bool, separator: G, next_item: Option, - iter: Fuse, -} - -#[unstable(feature = "iter_intersperse", issue = "79524")] -impl FusedIterator for IntersperseWith -where - I: FusedIterator, - G: FnMut() -> I::Item, -{ + iter: I, } #[unstable(feature = "iter_intersperse", issue = "79524")] @@ -146,7 +130,7 @@ where G: FnMut() -> I::Item, { pub(in crate::iter) fn new(iter: I, separator: G) -> Self { - Self { started: false, separator, next_item: None, iter: iter.fuse() } + Self { started: false, separator, next_item: None, iter } } } @@ -173,8 +157,9 @@ where } } } else { - self.started = true; - self.iter.next() + let item = self.iter.next(); + self.started = item.is_some(); + item } } diff --git a/core/src/iter/adapters/map_windows.rs b/core/src/iter/adapters/map_windows.rs index cef556319143e..9398fbbe8a1cd 100644 --- a/core/src/iter/adapters/map_windows.rs +++ b/core/src/iter/adapters/map_windows.rs @@ -14,10 +14,7 @@ pub struct MapWindows { } struct MapWindowsInner { - // We fuse the inner iterator because there shouldn't be "holes" in - // the sliding window. Once the iterator returns a `None`, we make - // our `MapWindows` iterator return `None` forever. - iter: Option, + iter: I, // Since iterators are assumed lazy, i.e. it only yields an item when // `Iterator::next()` is called, and `MapWindows` is not an exception. // @@ -26,7 +23,7 @@ struct MapWindowsInner { // we collect the first `N` items yielded from the inner iterator and // put it into the buffer. // - // When the inner iterator has returned a `None` (i.e. fused), we take + // When the inner iterator has returned a `None`, we take // away this `buffer` and leave it `None` to reclaim its resources. // // FIXME: should we shrink the size of `buffer` using niche optimization? @@ -64,19 +61,16 @@ impl MapWindows { impl MapWindowsInner { #[inline] fn new(iter: I) -> Self { - Self { iter: Some(iter), buffer: None } + Self { iter, buffer: None } } fn next_window(&mut self) -> Option<&[I::Item; N]> { - let iter = self.iter.as_mut()?; match self.buffer { // It is the first time to advance. We collect // the first `N` items from `self.iter` to initialize `self.buffer`. - None => self.buffer = Buffer::try_from_iter(iter), - Some(ref mut buffer) => match iter.next() { + None => self.buffer = Buffer::try_from_iter(&mut self.iter), + Some(ref mut buffer) => match self.iter.next() { None => { - // Fuse the inner iterator since it yields a `None`. - self.iter.take(); self.buffer.take(); } // Advance the iterator. We first call `next` before changing our buffer @@ -89,8 +83,7 @@ impl MapWindowsInner { } fn size_hint(&self) -> (usize, Option) { - let Some(ref iter) = self.iter else { return (0, Some(0)) }; - let (lo, hi) = iter.size_hint(); + let (lo, hi) = self.iter.size_hint(); if self.buffer.is_some() { // If the first `N` items are already yielded by the inner iterator, // the size hint is then equal to the that of the inner iterator's. @@ -253,12 +246,10 @@ where } } -// Note that even if the inner iterator not fused, the `MapWindows` is still fused, -// because we don't allow "holes" in the mapping window. #[unstable(feature = "iter_map_windows", issue = "87155")] impl FusedIterator for MapWindows where - I: Iterator, + I: FusedIterator, F: FnMut(&[I::Item; N]) -> R, { } diff --git a/core/src/iter/adapters/mod.rs b/core/src/iter/adapters/mod.rs index d0b89fdbb5843..ca950a138f31c 100644 --- a/core/src/iter/adapters/mod.rs +++ b/core/src/iter/adapters/mod.rs @@ -155,6 +155,9 @@ where for<'a> F: FnMut(GenericShunt<'a, I, R>) -> U, R: Residual, { + // FIXME(#11084): we might be able to get rid of GenericShunt in favor of + // Iterator::scan, as performance should be comparable + let mut residual = None; let shunt = GenericShunt { iter, residual: &mut residual }; let value = f(shunt); diff --git a/core/src/iter/range.rs b/core/src/iter/range.rs index 350b5d31e8940..951bb5d0029f6 100644 --- a/core/src/iter/range.rs +++ b/core/src/iter/range.rs @@ -29,7 +29,8 @@ unsafe_impl_trusted_step![AsciiChar char i8 i16 i32 i64 i128 isize u8 u16 u32 u6 unstable `Step` trait" )] #[unstable(feature = "step_trait", issue = "42168")] -pub trait Step: Clone + PartialOrd + Sized { +#[rustc_const_unstable(feature = "step_trait", issue = "42168")] +pub const trait Step: [const] Clone + [const] PartialOrd + Sized { /// Returns the bounds on the number of *successor* steps required to get from `start` to `end` /// like [`Iterator::size_hint()`][Iterator::size_hint()]. /// @@ -262,7 +263,8 @@ macro_rules! step_integer_impls { $( #[allow(unreachable_patterns)] #[unstable(feature = "step_trait", issue = "42168")] - impl Step for $u_narrower { + #[rustc_const_unstable(feature = "step_trait", issue = "42168")] + impl const Step for $u_narrower { step_identical_methods!(); step_unsigned_methods!(); @@ -296,7 +298,8 @@ macro_rules! step_integer_impls { #[allow(unreachable_patterns)] #[unstable(feature = "step_trait", issue = "42168")] - impl Step for $i_narrower { + #[rustc_const_unstable(feature = "step_trait", issue = "42168")] + impl const Step for $i_narrower { step_identical_methods!(); step_signed_methods!($u_narrower); @@ -362,7 +365,8 @@ macro_rules! step_integer_impls { $( #[allow(unreachable_patterns)] #[unstable(feature = "step_trait", issue = "42168")] - impl Step for $u_wider { + #[rustc_const_unstable(feature = "step_trait", issue = "42168")] + impl const Step for $u_wider { step_identical_methods!(); step_unsigned_methods!(); @@ -392,7 +396,8 @@ macro_rules! step_integer_impls { #[allow(unreachable_patterns)] #[unstable(feature = "step_trait", issue = "42168")] - impl Step for $i_wider { + #[rustc_const_unstable(feature = "step_trait", issue = "42168")] + impl const Step for $i_wider { step_identical_methods!(); step_signed_methods!($u_wider); @@ -449,7 +454,8 @@ step_integer_impls! { } #[unstable(feature = "step_trait", issue = "42168")] -impl Step for char { +#[rustc_const_unstable(feature = "step_trait", issue = "42168")] +impl const Step for char { #[inline] fn steps_between(&start: &char, &end: &char) -> (usize, Option) { let start = start as u32; @@ -536,7 +542,8 @@ impl Step for char { } #[unstable(feature = "step_trait", issue = "42168")] -impl Step for AsciiChar { +#[rustc_const_unstable(feature = "step_trait", issue = "42168")] +impl const Step for AsciiChar { #[inline] fn steps_between(&start: &AsciiChar, &end: &AsciiChar) -> (usize, Option) { Step::steps_between(&start.to_u8(), &end.to_u8()) @@ -578,7 +585,8 @@ impl Step for AsciiChar { } #[unstable(feature = "step_trait", issue = "42168")] -impl Step for Ipv4Addr { +#[rustc_const_unstable(feature = "step_trait", issue = "42168")] +impl const Step for Ipv4Addr { #[inline] fn steps_between(&start: &Ipv4Addr, &end: &Ipv4Addr) -> (usize, Option) { u32::steps_between(&start.to_bits(), &end.to_bits()) @@ -610,7 +618,8 @@ impl Step for Ipv4Addr { } #[unstable(feature = "step_trait", issue = "42168")] -impl Step for Ipv6Addr { +#[rustc_const_unstable(feature = "step_trait", issue = "42168")] +impl const Step for Ipv6Addr { #[inline] fn steps_between(&start: &Ipv6Addr, &end: &Ipv6Addr) -> (usize, Option) { u128::steps_between(&start.to_bits(), &end.to_bits()) diff --git a/core/src/iter/traits/iterator.rs b/core/src/iter/traits/iterator.rs index d919230d094d8..943e869d74380 100644 --- a/core/src/iter/traits/iterator.rs +++ b/core/src/iter/traits/iterator.rs @@ -631,8 +631,28 @@ pub const trait Iterator { Zip::new(self, other.into_iter()) } - /// Creates a new iterator which places a copy of `separator` between adjacent - /// items of the original iterator. + /// Creates a new iterator which places a copy of `separator` between items + /// of the original iterator. + /// + /// Specifically on fused iterators, it is guaranteed that the new iterator + /// places a copy of `separator` between *adjacent* `Some(_)` items. For non-fused iterators, + /// it is guaranteed that [`intersperse`] will create a new iterator that places a copy + /// of `separator` between `Some(_)` items, particularly just right before the subsequent + /// `Some(_)` item. + /// + /// For example, consider the following non-fused iterator: + /// + /// ```text + /// Some(1) -> Some(2) -> None -> Some(3) -> Some(4) -> ... + /// ``` + /// + /// If this non-fused iterator were to be interspersed with `0`, + /// then the interspersed iterator will produce: + /// + /// ```text + /// Some(1) -> Some(0) -> Some(2) -> None -> Some(0) -> Some(3) -> Some(0) -> + /// Some(4) -> ... + /// ``` /// /// In case `separator` does not implement [`Clone`] or needs to be /// computed every time, use [`intersperse_with`]. @@ -663,6 +683,7 @@ pub const trait Iterator { /// ``` /// /// [`Clone`]: crate::clone::Clone + /// [`intersperse`]: Iterator::intersperse /// [`intersperse_with`]: Iterator::intersperse_with #[inline] #[unstable(feature = "iter_intersperse", issue = "79524")] @@ -676,12 +697,32 @@ pub const trait Iterator { } /// Creates a new iterator which places an item generated by `separator` - /// between adjacent items of the original iterator. + /// between items of the original iterator. + /// + /// Specifically on fused iterators, it is guaranteed that the new iterator + /// places an item generated by `separator` between adjacent `Some(_)` items. + /// For non-fused iterators, it is guaranteed that [`intersperse_with`] will + /// create a new iterator that places an item generated by `separator` between `Some(_)` + /// items, particularly just right before the subsequent `Some(_)` item. + /// + /// For example, consider the following non-fused iterator: /// - /// The closure will be called exactly once each time an item is placed - /// between two adjacent items from the underlying iterator; specifically, - /// the closure is not called if the underlying iterator yields less than - /// two items and after the last item is yielded. + /// ```text + /// Some(1) -> Some(2) -> None -> Some(3) -> Some(4) -> ... + /// ``` + /// + /// If this non-fused iterator were to be interspersed with a `separator` closure + /// that returns `0` repeatedly, the interspersed iterator will produce: + /// + /// ```text + /// Some(1) -> Some(0) -> Some(2) -> None -> Some(0) -> Some(3) -> Some(0) -> + /// Some(4) -> ... + /// ``` + /// + /// The `separator` closure will be called exactly once each time an item + /// is placed between two adjacent items from the underlying iterator; + /// specifically, the closure is not called if the underlying iterator yields + /// less than two items and after the last item is yielded. /// /// If the iterator's item implements [`Clone`], it may be easier to use /// [`intersperse`]. @@ -723,6 +764,7 @@ pub const trait Iterator { /// ``` /// [`Clone`]: crate::clone::Clone /// [`intersperse`]: Iterator::intersperse + /// [`intersperse_with`]: Iterator::intersperse_with #[inline] #[unstable(feature = "iter_intersperse", issue = "79524")] #[rustc_non_const_trait_method] @@ -1615,11 +1657,6 @@ pub const trait Iterator { /// items yielded by `self`). If 𝑘 is less than `N`, this method yields an /// empty iterator. /// - /// The returned iterator implements [`FusedIterator`], because once `self` - /// returns `None`, even if it returns a `Some(T)` again in the next iterations, - /// we cannot put it into a contiguous array buffer, and thus the returned iterator - /// should be fused. - /// /// [`slice::windows()`]: slice::windows /// [`FusedIterator`]: crate::iter::FusedIterator /// @@ -1680,7 +1717,7 @@ pub const trait Iterator { /// assert_eq!(it.next(), None); /// ``` /// - /// For non-fused iterators, they are fused after `map_windows`. + /// For non-fused iterators, the window is reset after `None` is yielded. /// /// ``` /// #![feature(iter_map_windows)] @@ -1697,11 +1734,11 @@ pub const trait Iterator { /// let val = self.state; /// self.state = self.state + 1; /// - /// // yields `0..5` first, then only even numbers since `6..`. - /// if val < 5 || val % 2 == 0 { - /// Some(val) - /// } else { + /// // Skip every 5th number + /// if (val + 1) % 5 == 0 { /// None + /// } else { + /// Some(val) /// } /// } /// } @@ -1709,32 +1746,35 @@ pub const trait Iterator { /// /// let mut iter = NonFusedIterator::default(); /// - /// // yields 0..5 first. /// assert_eq!(iter.next(), Some(0)); /// assert_eq!(iter.next(), Some(1)); /// assert_eq!(iter.next(), Some(2)); /// assert_eq!(iter.next(), Some(3)); - /// assert_eq!(iter.next(), Some(4)); - /// // then we can see our iterator going back and forth /// assert_eq!(iter.next(), None); + /// assert_eq!(iter.next(), Some(5)); /// assert_eq!(iter.next(), Some(6)); - /// assert_eq!(iter.next(), None); + /// assert_eq!(iter.next(), Some(7)); /// assert_eq!(iter.next(), Some(8)); /// assert_eq!(iter.next(), None); + /// assert_eq!(iter.next(), Some(10)); + /// assert_eq!(iter.next(), Some(11)); /// - /// // however, with `.map_windows()`, it is fused. /// let mut iter = NonFusedIterator::default() /// .map_windows(|arr: &[_; 2]| *arr); /// /// assert_eq!(iter.next(), Some([0, 1])); /// assert_eq!(iter.next(), Some([1, 2])); /// assert_eq!(iter.next(), Some([2, 3])); - /// assert_eq!(iter.next(), Some([3, 4])); /// assert_eq!(iter.next(), None); /// - /// // it will always return `None` after the first time. - /// assert_eq!(iter.next(), None); + /// assert_eq!(iter.next(), Some([5, 6])); + /// assert_eq!(iter.next(), Some([6, 7])); + /// assert_eq!(iter.next(), Some([7, 8])); /// assert_eq!(iter.next(), None); + /// + /// assert_eq!(iter.next(), Some([10, 11])); + /// assert_eq!(iter.next(), Some([11, 12])); + /// assert_eq!(iter.next(), Some([12, 13])); /// assert_eq!(iter.next(), None); /// ``` #[inline] @@ -1908,7 +1948,7 @@ pub const trait Iterator { /// without giving up ownership of the original iterator, /// so you can use the original iterator afterwards. /// - /// Uses [`impl Iterator for &mut I { type Item = I::Item; ...}`](https://doc.rust-lang.org/nightly/std/iter/trait.Iterator.html#impl-Iterator-for-%26mut+I). + /// Uses [`impl Iterator for &mut I { type Item = I::Item; ...}`](Iterator#impl-Iterator-for-%26mut+I). /// /// # Examples /// diff --git a/core/src/lib.rs b/core/src/lib.rs index 432ca50b33613..35f93d8fb33b2 100644 --- a/core/src/lib.rs +++ b/core/src/lib.rs @@ -48,7 +48,7 @@ html_playground_url = "https://play.rust-lang.org/", issue_tracker_base_url = "https://github.com/rust-lang/rust/issues/", test(no_crate_inject, attr(deny(warnings))), - test(attr(allow(dead_code, deprecated, unused_variables, unused_mut))) + test(attr(allow(dead_code, deprecated, unused_variables, unused_mut, duplicate_features))) )] #![doc(rust_logo)] #![doc(auto_cfg(hide( @@ -87,6 +87,7 @@ #![allow(incomplete_features)] #![warn(multiple_supertrait_upcastable)] #![allow(internal_features)] +#![allow(unused_features)] #![deny(ffi_unwind_calls)] #![warn(unreachable_pub)] // Do not check link redundancy on bootstrapping phase @@ -95,42 +96,21 @@ // // Library features: // tidy-alphabetical-start -#![feature(array_ptr_get)] #![feature(asm_experimental_arch)] -#![feature(bstr)] #![feature(bstr_internals)] -#![feature(cfg_select)] #![feature(cfg_target_has_reliable_f16_f128)] #![feature(const_carrying_mul_add)] #![feature(const_cmp)] #![feature(const_destruct)] #![feature(const_eval_select)] #![feature(const_select_unpredictable)] -#![feature(const_unsigned_bigint_helpers)] #![feature(core_intrinsics)] #![feature(coverage_attribute)] #![feature(disjoint_bitor)] -#![feature(internal_impls_macro)] -#![feature(ip)] -#![feature(is_ascii_octdigit)] -#![feature(link_cfg)] #![feature(offset_of_enum)] #![feature(panic_internals)] #![feature(pattern_type_macro)] -#![feature(ptr_alignment_type)] -#![feature(ptr_metadata)] -#![feature(set_ptr_value)] -#![feature(signed_bigint_helpers)] -#![feature(slice_ptr_get)] -#![feature(str_internals)] -#![feature(str_split_inclusive_remainder)] -#![feature(str_split_remainder)] -#![feature(type_info)] #![feature(ub_checks)] -#![feature(unsafe_pinned)] -#![feature(utf16_extra)] -#![feature(variant_count)] -#![feature(widening_mul)] // tidy-alphabetical-end // // Language features: @@ -155,13 +135,14 @@ #![feature(extern_types)] #![feature(f16)] #![feature(f128)] +#![feature(field_projections)] #![feature(freeze_impls)] #![feature(fundamental)] #![feature(funnel_shifts)] -#![feature(if_let_guard)] #![feature(intra_doc_pointers)] #![feature(intrinsics)] #![feature(lang_items)] +#![feature(link_cfg)] #![feature(link_llvm_intrinsics)] #![feature(macro_metavar_expr)] #![feature(macro_metavar_expr_concat)] @@ -175,9 +156,7 @@ #![feature(optimize_attribute)] #![feature(pattern_types)] #![feature(prelude_import)] -#![feature(reborrow)] #![feature(repr_simd)] -#![feature(rustc_allow_const_fn_unstable)] #![feature(rustc_attrs)] #![feature(rustdoc_internals)] #![feature(simd_ffi)] @@ -188,6 +167,7 @@ #![feature(trait_alias)] #![feature(transparent_unions)] #![feature(try_blocks)] +#![feature(uint_carryless_mul)] #![feature(unboxed_closures)] #![feature(unsized_fn_params)] #![feature(with_negative_coherence)] @@ -201,6 +181,7 @@ #![feature(hexagon_target_feature)] #![feature(loongarch_target_feature)] #![feature(mips_target_feature)] +#![feature(movrs_target_feature)] #![feature(nvptx_target_feature)] #![feature(powerpc_target_feature)] #![feature(riscv_target_feature)] @@ -225,7 +206,7 @@ use prelude::rust_2024::*; #[macro_use] mod macros; -#[unstable(feature = "assert_matches", issue = "82775")] +#[stable(feature = "assert_matches", since = "1.95.0")] pub use crate::macros::{assert_matches, debug_assert_matches}; #[unstable(feature = "derive_from", issue = "144889")] @@ -246,7 +227,7 @@ pub mod autodiff { #[unstable(feature = "contracts", issue = "128044")] pub mod contracts; -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "1.95.0")] pub use crate::macros::cfg_select; #[macro_use] @@ -294,6 +275,8 @@ pub mod cmp; pub mod convert; pub mod default; pub mod error; +#[unstable(feature = "field_projections", issue = "145383")] +pub mod field; pub mod index; pub mod marker; pub mod ops; @@ -324,7 +307,7 @@ pub mod pat; pub mod pin; #[unstable(feature = "random", issue = "130703")] pub mod random; -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] pub mod range; pub mod result; pub mod sync; diff --git a/core/src/macros/mod.rs b/core/src/macros/mod.rs index 3176f3c067092..7f35e94d3df30 100644 --- a/core/src/macros/mod.rs +++ b/core/src/macros/mod.rs @@ -124,8 +124,6 @@ macro_rules! assert_ne { }; } -// FIXME add back debug_assert_matches doc link after bootstrap. - /// Asserts that an expression matches the provided pattern. /// /// This macro is generally preferable to `assert!(matches!(value, pattern))`, because it can print @@ -137,9 +135,11 @@ macro_rules! assert_ne { /// otherwise this macro will panic. /// /// Assertions are always checked in both debug and release builds, and cannot -/// be disabled. See `debug_assert_matches!` for assertions that are disabled in +/// be disabled. See [`debug_assert_matches!`] for assertions that are disabled in /// release builds by default. /// +/// [`debug_assert_matches!`]: crate::debug_assert_matches +/// /// On panic, this macro will print the value of the expression with its debug representation. /// /// Like [`assert!`], this macro has a second form, where a custom panic message can be provided. @@ -147,8 +147,6 @@ macro_rules! assert_ne { /// # Examples /// /// ``` -/// #![feature(assert_matches)] -/// /// use std::assert_matches; /// /// let a = Some(345); @@ -166,7 +164,7 @@ macro_rules! assert_ne { /// assert_matches!(a, Some(x) if x > 100); /// // assert_matches!(a, Some(x) if x < 100); // panics /// ``` -#[unstable(feature = "assert_matches", issue = "82775")] +#[stable(feature = "assert_matches", since = "1.95.0")] #[allow_internal_unstable(panic_internals)] #[rustc_macro_transparency = "semiopaque"] pub macro assert_matches { @@ -208,8 +206,6 @@ pub macro assert_matches { /// # Example /// /// ``` -/// #![feature(cfg_select)] -/// /// cfg_select! { /// unix => { /// fn foo() { /* unix specific functionality */ } @@ -227,14 +223,12 @@ pub macro assert_matches { /// right-hand side: /// /// ``` -/// #![feature(cfg_select)] -/// /// let _some_string = cfg_select! { /// unix => "With great power comes great electricity bills", /// _ => { "Behind every successful diet is an unwatched pizza" } /// }; /// ``` -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "1.95.0")] #[rustc_diagnostic_item = "cfg_select"] #[rustc_builtin_macro] pub macro cfg_select($($tt:tt)*) { @@ -380,8 +374,6 @@ macro_rules! debug_assert_ne { /// # Examples /// /// ``` -/// #![feature(assert_matches)] -/// /// use std::debug_assert_matches; /// /// let a = Some(345); @@ -399,7 +391,7 @@ macro_rules! debug_assert_ne { /// debug_assert_matches!(a, Some(x) if x > 100); /// // debug_assert_matches!(a, Some(x) if x < 100); // panics /// ``` -#[unstable(feature = "assert_matches", issue = "82775")] +#[stable(feature = "assert_matches", since = "1.95.0")] #[allow_internal_unstable(assert_matches)] #[rustc_macro_transparency = "semiopaque"] pub macro debug_assert_matches($($arg:tt)*) { @@ -449,7 +441,7 @@ macro_rules! matches { /// [raw-identifier syntax][ris]: `r#try`. /// /// [propagating-errors]: https://doc.rust-lang.org/book/ch09-02-recoverable-errors-with-result.html#a-shortcut-for-propagating-errors-the--operator -/// [ris]: https://doc.rust-lang.org/nightly/rust-by-example/compatibility/raw_identifiers.html +/// [ris]: ../rust-by-example/compatibility/raw_identifiers.html /// /// `try!` matches the given [`Result`]. In case of the `Ok` variant, the /// expression has the value of the wrapped value. @@ -611,6 +603,9 @@ macro_rules! write { ($dst:expr, $($arg:tt)*) => { $dst.write_fmt($crate::format_args!($($arg)*)) }; + ($($arg:tt)*) => { + compile_error!("requires a destination and format arguments, like `write!(dest, \"format string\", args...)`") + }; } /// Writes formatted data into a buffer, with a newline appended. @@ -649,6 +644,9 @@ macro_rules! writeln { ($dst:expr, $($arg:tt)*) => { $dst.write_fmt($crate::format_args_nl!($($arg)*)) }; + ($($arg:tt)*) => { + compile_error!("requires a destination and format arguments, like `writeln!(dest, \"format string\", args...)`") + }; } /// Indicates unreachable code. @@ -1781,7 +1779,7 @@ pub(crate) mod builtin { /// /// See also [`std::alloc::GlobalAlloc`](../../../std/alloc/trait.GlobalAlloc.html). #[stable(feature = "global_allocator", since = "1.28.0")] - #[allow_internal_unstable(rustc_attrs)] + #[allow_internal_unstable(rustc_attrs, ptr_alignment_type)] #[rustc_builtin_macro] pub macro global_allocator($item:item) { /* compiler built-in */ diff --git a/core/src/marker.rs b/core/src/marker.rs index 57416455e9de8..c79e8fc4060c1 100644 --- a/core/src/marker.rs +++ b/core/src/marker.rs @@ -46,15 +46,12 @@ use crate::pin::UnsafePinned; /// marker_impls! { /// MarkerTrait for /// u8, i8, -/// {T: ?Sized} *const T, -/// {T: ?Sized} *mut T, +/// {T: PointeeSized} *const T, +/// {T: PointeeSized} *mut T, /// {T: MarkerTrait} PhantomData, /// u32, /// } /// ``` -#[unstable(feature = "internal_impls_macro", issue = "none")] -// Allow implementations of `UnsizedConstParamTy` even though std cannot use that feature. -#[allow_internal_unstable(unsized_const_params)] macro marker_impls { ( $(#[$($meta:tt)*])* $Trait:ident for $({$($bounds:tt)*})? $T:ty $(, $($rest:tt)*)? ) => { $(#[$($meta)*])* impl< $($($bounds)*)? > $Trait for $T {} @@ -927,14 +924,20 @@ marker_impls! { /// This is part of [RFC 3467](https://rust-lang.github.io/rfcs/3467-unsafe-pinned.html), and is /// tracked by [#125735](https://github.com/rust-lang/rust/issues/125735). #[lang = "unsafe_unpin"] -pub(crate) unsafe auto trait UnsafeUnpin {} +#[unstable(feature = "unsafe_unpin", issue = "125735")] +pub unsafe auto trait UnsafeUnpin {} -impl !UnsafeUnpin for UnsafePinned {} -unsafe impl UnsafeUnpin for PhantomData {} -unsafe impl UnsafeUnpin for *const T {} -unsafe impl UnsafeUnpin for *mut T {} -unsafe impl UnsafeUnpin for &T {} -unsafe impl UnsafeUnpin for &mut T {} +#[unstable(feature = "unsafe_unpin", issue = "125735")] +impl !UnsafeUnpin for UnsafePinned {} +marker_impls! { +#[unstable(feature = "unsafe_unpin", issue = "125735")] + unsafe UnsafeUnpin for + {T: PointeeSized} PhantomData, + {T: PointeeSized} *const T, + {T: PointeeSized} *mut T, + {T: PointeeSized} &T, + {T: PointeeSized} &mut T, +} /// Types that do not require any pinning guarantees. /// @@ -1027,6 +1030,7 @@ impl !Unpin for PhantomPinned {} // continue working. Ideally PhantomPinned could just wrap an `UnsafePinned<()>` to get the same // effect, but we can't add a new field to an already stable unit struct -- that would be a breaking // change. +#[unstable(feature = "unsafe_unpin", issue = "125735")] impl !UnsafeUnpin for PhantomPinned {} marker_impls! { @@ -1073,7 +1077,7 @@ pub trait Tuple {} /// that all fields are also `ConstParamTy`, which implies that recursively, all fields /// are `StructuralPartialEq`. #[lang = "const_param_ty"] -#[unstable(feature = "unsized_const_params", issue = "95174")] +#[unstable(feature = "const_param_ty_trait", issue = "95174", implied_by = "unsized_const_params")] #[diagnostic::on_unimplemented(message = "`{Self}` can't be used as a const parameter type")] #[allow(multiple_supertrait_upcastable)] // We name this differently than the derive macro so that the `adt_const_params` can @@ -1083,7 +1087,7 @@ pub trait ConstParamTy_: StructuralPartialEq + Eq {} /// Derive macro generating an impl of the trait `ConstParamTy`. #[rustc_builtin_macro] -#[allow_internal_unstable(unsized_const_params)] +#[allow_internal_unstable(const_param_ty_trait)] #[unstable(feature = "adt_const_params", issue = "95174")] pub macro ConstParamTy($item:item) { /* compiler built-in */ diff --git a/core/src/ptr/alignment.rs b/core/src/mem/alignment.rs similarity index 90% rename from core/src/ptr/alignment.rs rename to core/src/mem/alignment.rs index 7c34b026e14be..a8c4c8ea78ff7 100644 --- a/core/src/ptr/alignment.rs +++ b/core/src/mem/alignment.rs @@ -11,7 +11,8 @@ use crate::{cmp, fmt, hash, mem, num}; /// Note that particularly large alignments, while representable in this type, /// are likely not to be supported by actual allocators and linkers. #[unstable(feature = "ptr_alignment_type", issue = "102070")] -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Copy)] +#[derive_const(Clone, PartialEq, Eq)] #[repr(transparent)] pub struct Alignment { // This field is never used directly (nor is the enum), @@ -37,7 +38,7 @@ impl Alignment { /// /// ``` /// #![feature(ptr_alignment_type)] - /// use std::ptr::Alignment; + /// use std::mem::Alignment; /// /// assert_eq!(Alignment::MIN.as_usize(), 1); /// ``` @@ -52,8 +53,7 @@ impl Alignment { #[inline] #[must_use] pub const fn of() -> Self { - // This can't actually panic since type alignment is always a power of two. - const { Alignment::new(align_of::()).unwrap() } + ::ALIGNMENT } /// Returns the [ABI]-required minimum alignment of the type of the value that `val` points to. @@ -66,7 +66,7 @@ impl Alignment { /// /// ``` /// #![feature(ptr_alignment_type)] - /// use std::ptr::Alignment; + /// use std::mem::Alignment; /// /// assert_eq!(Alignment::of_val(&5i32).as_usize(), 4); /// ``` @@ -113,15 +113,13 @@ impl Alignment { /// /// ``` /// #![feature(ptr_alignment_type)] - /// #![feature(layout_for_ptr)] - /// use std::ptr::Alignment; + /// use std::mem::Alignment; /// /// assert_eq!(unsafe { Alignment::of_val_raw(&5i32) }.as_usize(), 4); /// ``` #[inline] #[must_use] #[unstable(feature = "ptr_alignment_type", issue = "102070")] - // #[unstable(feature = "layout_for_ptr", issue = "69835")] pub const unsafe fn of_val_raw(val: *const T) -> Self { // SAFETY: precondition propagated to the caller let align = unsafe { mem::align_of_val_raw(val) }; @@ -171,16 +169,28 @@ impl Alignment { #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[inline] pub const fn as_usize(self) -> usize { - // Going through `as_nonzero` helps this be more clearly the inverse of + // Going through `as_nonzero_usize` helps this be more clearly the inverse of // `new_unchecked`, letting MIR optimizations fold it away. - self.as_nonzero().get() + self.as_nonzero_usize().get() } /// Returns the alignment as a [NonZero]<[usize]>. #[unstable(feature = "ptr_alignment_type", issue = "102070")] + #[deprecated( + since = "CURRENT_RUSTC_VERSION", + note = "renamed to `as_nonzero_usize`", + suggestion = "as_nonzero_usize" + )] #[inline] pub const fn as_nonzero(self) -> NonZero { + self.as_nonzero_usize() + } + + /// Returns the alignment as a [NonZero]<[usize]>. + #[unstable(feature = "ptr_alignment_type", issue = "102070")] + #[inline] + pub const fn as_nonzero_usize(self) -> NonZero { // This transmutes directly to avoid the UbCheck in `NonZero::new_unchecked` // since there's no way for the user to trip that check anyway -- the // validity invariant of the type would have to have been broken earlier -- @@ -206,7 +216,7 @@ impl Alignment { #[unstable(feature = "ptr_alignment_type", issue = "102070")] #[inline] pub const fn log2(self) -> u32 { - self.as_nonzero().trailing_zeros() + self.as_nonzero_usize().trailing_zeros() } /// Returns a bit mask that can be used to match this alignment. @@ -216,9 +226,10 @@ impl Alignment { /// # Examples /// /// ``` - /// #![feature(ptr_alignment_type)] /// #![feature(ptr_mask)] - /// use std::ptr::{Alignment, NonNull}; + /// #![feature(ptr_alignment_type)] + /// use std::mem::Alignment; + /// use std::ptr::NonNull; /// /// #[repr(align(1))] struct Align1(u8); /// #[repr(align(2))] struct Align2(u16); @@ -248,7 +259,7 @@ impl Alignment { #[unstable(feature = "ptr_alignment_type", issue = "102070")] impl fmt::Debug for Alignment { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - write!(f, "{:?} (1 << {:?})", self.as_nonzero(), self.log2()) + write!(f, "{:?} (1 << {:?})", self.as_nonzero_usize(), self.log2()) } } @@ -279,7 +290,7 @@ impl const TryFrom for Alignment { impl const From for NonZero { #[inline] fn from(align: Alignment) -> NonZero { - align.as_nonzero() + align.as_nonzero_usize() } } @@ -293,15 +304,17 @@ impl const From for usize { } #[unstable(feature = "ptr_alignment_type", issue = "102070")] -impl cmp::Ord for Alignment { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const cmp::Ord for Alignment { #[inline] fn cmp(&self, other: &Self) -> cmp::Ordering { - self.as_nonzero().get().cmp(&other.as_nonzero().get()) + self.as_nonzero_usize().cmp(&other.as_nonzero_usize()) } } #[unstable(feature = "ptr_alignment_type", issue = "102070")] -impl cmp::PartialOrd for Alignment { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const cmp::PartialOrd for Alignment { #[inline] fn partial_cmp(&self, other: &Self) -> Option { Some(self.cmp(other)) @@ -312,7 +325,7 @@ impl cmp::PartialOrd for Alignment { impl hash::Hash for Alignment { #[inline] fn hash(&self, state: &mut H) { - self.as_nonzero().hash(state) + self.as_nonzero_usize().hash(state) } } @@ -326,7 +339,8 @@ impl const Default for Alignment { } #[cfg(target_pointer_width = "16")] -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Copy)] +#[derive_const(Clone, PartialEq, Eq)] #[repr(usize)] enum AlignmentEnum { _Align1Shl0 = 1 << 0, @@ -348,7 +362,8 @@ enum AlignmentEnum { } #[cfg(target_pointer_width = "32")] -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Copy)] +#[derive_const(Clone, PartialEq, Eq)] #[repr(usize)] enum AlignmentEnum { _Align1Shl0 = 1 << 0, @@ -386,7 +401,8 @@ enum AlignmentEnum { } #[cfg(target_pointer_width = "64")] -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Copy)] +#[derive_const(Clone, PartialEq, Eq)] #[repr(usize)] enum AlignmentEnum { _Align1Shl0 = 1 << 0, diff --git a/core/src/mem/maybe_dangling.rs b/core/src/mem/maybe_dangling.rs index a5f77e667f975..c85576b5778cc 100644 --- a/core/src/mem/maybe_dangling.rs +++ b/core/src/mem/maybe_dangling.rs @@ -4,10 +4,6 @@ use crate::{mem, ptr}; /// Allows wrapped [references] and [boxes] to dangle. /// -///
-/// This type is not properly implemented yet, and the documentation below is thus not accurate. -///
-/// /// That is, if a reference (or a `Box`) is wrapped in `MaybeDangling` (including when in a /// (nested) field of a compound type wrapped in `MaybeDangling`), it does not have to follow /// pointer aliasing rules or be dereferenceable. @@ -73,6 +69,7 @@ use crate::{mem, ptr}; #[repr(transparent)] #[rustc_pub_transparent] #[derive(Debug, Copy, Clone, Default)] +#[lang = "maybe_dangling"] pub struct MaybeDangling(P); impl MaybeDangling

{ - cross_thread: bool, - marker: PhantomData

, +pub struct MaybeCrossThread { + pub cross_thread: bool, } -impl

MaybeCrossThread

{ - pub const fn new(cross_thread: bool) -> Self { - MaybeCrossThread { cross_thread, marker: PhantomData } - } -} +pub const SAME_THREAD: MaybeCrossThread = MaybeCrossThread { cross_thread: false }; +pub const CROSS_THREAD: MaybeCrossThread = MaybeCrossThread { cross_thread: true }; -impl

ExecutionStrategy for MaybeCrossThread

-where - P: MessagePipe + Send + 'static, -{ +impl ExecutionStrategy for MaybeCrossThread { fn run_bridge_and_client( &self, - dispatcher: &mut impl DispatcherTrait, + dispatcher: &mut Dispatcher, input: Buffer, run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, force_show_panics: bool, ) -> Buffer { if self.cross_thread || ALREADY_RUNNING_SAME_THREAD.get() { - >::new().run_bridge_and_client( - dispatcher, - input, - run_client, - force_show_panics, - ) - } else { - SameThread.run_bridge_and_client(dispatcher, input, run_client, force_show_panics) - } - } -} - -pub struct SameThread; - -impl ExecutionStrategy for SameThread { - fn run_bridge_and_client( - &self, - dispatcher: &mut impl DispatcherTrait, - input: Buffer, - run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, - force_show_panics: bool, - ) -> Buffer { - let _guard = RunningSameThreadGuard::new(); - - let mut dispatch = |buf| dispatcher.dispatch(buf); - - run_client(BridgeConfig { input, dispatch: (&mut dispatch).into(), force_show_panics }) - } -} - -pub struct CrossThread

(PhantomData

); - -impl

CrossThread

{ - pub const fn new() -> Self { - CrossThread(PhantomData) - } -} + let (mut server, mut client) = MessagePipe::new(); + + let join_handle = thread::spawn(move || { + let mut dispatch = |b: Buffer| -> Buffer { + client.send(b); + client.recv().expect("server died while client waiting for reply") + }; + + run_client(BridgeConfig { + input, + dispatch: (&mut dispatch).into(), + force_show_panics, + }) + }); + + while let Some(b) = server.recv() { + server.send(dispatcher.dispatch(b)); + } -impl

ExecutionStrategy for CrossThread

-where - P: MessagePipe + Send + 'static, -{ - fn run_bridge_and_client( - &self, - dispatcher: &mut impl DispatcherTrait, - input: Buffer, - run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, - force_show_panics: bool, - ) -> Buffer { - let (mut server, mut client) = P::new(); + join_handle.join().unwrap() + } else { + let _guard = RunningSameThreadGuard::new(); - let join_handle = thread::spawn(move || { - let mut dispatch = |b: Buffer| -> Buffer { - client.send(b); - client.recv().expect("server died while client waiting for reply") - }; + let mut dispatch = |buf| dispatcher.dispatch(buf); run_client(BridgeConfig { input, dispatch: (&mut dispatch).into(), force_show_panics }) - }); - - while let Some(b) = server.recv() { - server.send(dispatcher.dispatch(b)); } - - join_handle.join().unwrap() } } /// A message pipe used for communicating between server and client threads. -pub trait MessagePipe: Sized { +struct MessagePipe { + tx: mpsc::SyncSender, + rx: mpsc::Receiver, +} + +impl MessagePipe { /// Creates a new pair of endpoints for the message pipe. - fn new() -> (Self, Self); + fn new() -> (Self, Self) { + let (tx1, rx1) = mpsc::sync_channel(1); + let (tx2, rx2) = mpsc::sync_channel(1); + (MessagePipe { tx: tx1, rx: rx2 }, MessagePipe { tx: tx2, rx: rx1 }) + } /// Send a message to the other endpoint of this pipe. - fn send(&mut self, value: T); + fn send(&mut self, value: T) { + self.tx.send(value).unwrap(); + } /// Receive a message from the other endpoint of this pipe. /// /// Returns `None` if the other end of the pipe has been destroyed, and no /// message was received. - fn recv(&mut self) -> Option; + fn recv(&mut self) -> Option { + self.rx.recv().ok() + } } fn run_server< @@ -312,7 +275,6 @@ impl client::Client { ) -> Result where S: Server, - S::TokenStream: Default, { let client::Client { handle_counters, run, _marker } = *self; run_server( @@ -338,7 +300,6 @@ impl client::Client<(crate::TokenStream, crate::TokenStream), crate::TokenStream ) -> Result where S: Server, - S::TokenStream: Default, { let client::Client { handle_counters, run, _marker } = *self; run_server( diff --git a/proc_macro/src/lib.rs b/proc_macro/src/lib.rs index 49b6f2ae41f89..a01bf38a62dbf 100644 --- a/proc_macro/src/lib.rs +++ b/proc_macro/src/lib.rs @@ -27,6 +27,7 @@ #![feature(restricted_std)] #![feature(rustc_attrs)] #![feature(extend_one)] +#![feature(mem_conjure_zst)] #![recursion_limit = "256"] #![allow(internal_features)] #![deny(ffi_unwind_calls)] @@ -109,15 +110,18 @@ impl !Send for TokenStream {} impl !Sync for TokenStream {} /// Error returned from `TokenStream::from_str`. +/// +/// The contained error message is explicitly not guaranteed to be stable in any way, +/// and may change between Rust versions or across compilations. #[stable(feature = "proc_macro_lib", since = "1.15.0")] #[non_exhaustive] #[derive(Debug)] -pub struct LexError; +pub struct LexError(String); #[stable(feature = "proc_macro_lexerror_impls", since = "1.44.0")] impl fmt::Display for LexError { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.write_str("cannot parse string into token stream") + f.write_str(&self.0) } } @@ -196,7 +200,7 @@ impl FromStr for TokenStream { type Err = LexError; fn from_str(src: &str) -> Result { - Ok(TokenStream(Some(BridgeMethods::ts_from_str(src)))) + Ok(TokenStream(Some(BridgeMethods::ts_from_str(src).map_err(LexError)?))) } } @@ -1593,7 +1597,7 @@ impl FromStr for Literal { fn from_str(src: &str) -> Result { match BridgeMethods::literal_from_str(src) { Ok(literal) => Ok(Literal(literal)), - Err(()) => Err(LexError), + Err(msg) => Err(LexError(msg)), } } } diff --git a/rtstartup/rsbegin.rs b/rtstartup/rsbegin.rs index 62d247fafb7ad..6ee06cce5c630 100644 --- a/rtstartup/rsbegin.rs +++ b/rtstartup/rsbegin.rs @@ -90,12 +90,12 @@ pub mod eh_frames { unsafe extern "C" fn init() { // register unwind info on module startup - __register_frame_info(&__EH_FRAME_BEGIN__ as *const u8, &mut OBJ as *mut _ as *mut u8); + __register_frame_info(&__EH_FRAME_BEGIN__ as *const u8, &raw mut OBJ as *mut u8); } unsafe extern "C" fn uninit() { // unregister on shutdown - __deregister_frame_info(&__EH_FRAME_BEGIN__ as *const u8, &mut OBJ as *mut _ as *mut u8); + __deregister_frame_info(&__EH_FRAME_BEGIN__ as *const u8, &raw mut OBJ as *mut u8); } // MinGW-specific init/uninit routine registration diff --git a/std/Cargo.toml b/std/Cargo.toml index f4cc8edc0c1da..f7bc729598cd3 100644 --- a/std/Cargo.toml +++ b/std/Cargo.toml @@ -33,7 +33,7 @@ miniz_oxide = { version = "0.8.0", optional = true, default-features = false } addr2line = { version = "0.25.0", optional = true, default-features = false } [target.'cfg(not(all(windows, target_env = "msvc")))'.dependencies] -libc = { version = "0.2.178", default-features = false, features = [ +libc = { version = "0.2.183", default-features = false, features = [ 'rustc-dep-of-std', ], public = true } @@ -62,7 +62,7 @@ path = "../windows_link" rand = { version = "0.9.0", default-features = false, features = ["alloc"] } rand_xorshift = "0.4.0" -[target.'cfg(any(all(target_family = "wasm", target_os = "unknown"), target_os = "xous", target_os = "vexos", all(target_vendor = "fortanix", target_env = "sgx")))'.dependencies] +[target.'cfg(any(all(target_family = "wasm", not(any(unix, target_os = "wasi"))), target_os = "xous", target_os = "vexos", all(target_vendor = "fortanix", target_env = "sgx")))'.dependencies] dlmalloc = { version = "0.2.10", features = ['rustc-dep-of-std'] } [target.x86_64-fortanix-unknown-sgx.dependencies] @@ -146,10 +146,6 @@ harness = false name = "sync" path = "tests/sync/lib.rs" -[[test]] -name = "floats" -path = "tests/floats/lib.rs" - [[test]] name = "thread_local" path = "tests/thread_local/lib.rs" diff --git a/std/benches/lib.rs b/std/benches/lib.rs index e749d9c0f7998..2707b414f578b 100644 --- a/std/benches/lib.rs +++ b/std/benches/lib.rs @@ -1,4 +1,4 @@ -// Disabling in Miri as these would take too long. +// This is marked as `test = true` and hence picked up by `./x miri`, but that would be too slow. #![cfg(not(miri))] #![feature(test)] diff --git a/std/benches/path.rs b/std/benches/path.rs index 912c783b31e4c..b6d5a8672aa6c 100644 --- a/std/benches/path.rs +++ b/std/benches/path.rs @@ -4,7 +4,6 @@ use std::hash::{DefaultHasher, Hash, Hasher}; use std::path::*; #[bench] -#[cfg_attr(miri, ignore)] // Miri isn't fast... fn bench_path_cmp_fast_path_buf_sort(b: &mut test::Bencher) { let prefix = "my/home"; let mut paths: Vec<_> = @@ -18,7 +17,6 @@ fn bench_path_cmp_fast_path_buf_sort(b: &mut test::Bencher) { } #[bench] -#[cfg_attr(miri, ignore)] // Miri isn't fast... fn bench_path_cmp_fast_path_long(b: &mut test::Bencher) { let prefix = "/my/home/is/my/castle/and/my/castle/has/a/rusty/workbench/"; let paths: Vec<_> = @@ -37,7 +35,6 @@ fn bench_path_cmp_fast_path_long(b: &mut test::Bencher) { } #[bench] -#[cfg_attr(miri, ignore)] // Miri isn't fast... fn bench_path_cmp_fast_path_short(b: &mut test::Bencher) { let prefix = "my/home"; let paths: Vec<_> = @@ -80,7 +77,6 @@ fn bench_path_file_name(b: &mut test::Bencher) { } #[bench] -#[cfg_attr(miri, ignore)] // Miri isn't fast... fn bench_path_hashset(b: &mut test::Bencher) { let prefix = "/my/home/is/my/castle/and/my/castle/has/a/rusty/workbench/"; let paths: Vec<_> = @@ -99,7 +95,6 @@ fn bench_path_hashset(b: &mut test::Bencher) { } #[bench] -#[cfg_attr(miri, ignore)] // Miri isn't fast... fn bench_path_hashset_miss(b: &mut test::Bencher) { let prefix = "/my/home/is/my/castle/and/my/castle/has/a/rusty/workbench/"; let paths: Vec<_> = diff --git a/std/build.rs b/std/build.rs index c0a6e30b38082..5f2e441bf7d83 100644 --- a/std/build.rs +++ b/std/build.rs @@ -79,4 +79,28 @@ fn main() { println!("cargo:rustc-cfg=backtrace_in_libstd"); println!("cargo:rustc-env=STD_ENV_ARCH={}", env::var("CARGO_CFG_TARGET_ARCH").unwrap()); + + println!("cargo:rustc-check-cfg=cfg(vxworks_lt_25_09)"); + + if target_os == "vxworks" { + match vxworks_version_code() { + Some((major, minor)) if (major, minor) < (25, 9) => { + println!("cargo:rustc-cfg=vxworks_lt_25_09"); + } + _ => {} + } + } +} + +/// Retrieve the VxWorks release version from the environment variable set by the VxWorks build +/// environment, in `(minor, patch)` form. +fn vxworks_version_code() -> Option<(u32, u32)> { + let version = env::var("WIND_RELEASE_ID").ok()?; + + let mut pieces = version.trim().split(['.']); + + let major: u32 = pieces.next().and_then(|x| x.parse().ok()).unwrap_or(0); + let minor: u32 = pieces.next().and_then(|x| x.parse().ok()).unwrap_or(0); + + Some((major, minor)) } diff --git a/std/src/backtrace/tests.rs b/std/src/backtrace/tests.rs index 174d62813bd58..b68b528c18668 100644 --- a/std/src/backtrace/tests.rs +++ b/std/src/backtrace/tests.rs @@ -44,10 +44,9 @@ fn generate_fake_frames() -> Vec { #[test] fn test_debug() { let backtrace = Backtrace { - inner: Inner::Captured(LazyLock::preinit(Capture { - actual_start: 1, - frames: generate_fake_frames(), - })), + inner: Inner::Captured( + (Capture { actual_start: 1, frames: generate_fake_frames() }).into(), + ), }; #[rustfmt::skip] @@ -66,10 +65,9 @@ fn test_debug() { #[test] fn test_frames() { let backtrace = Backtrace { - inner: Inner::Captured(LazyLock::preinit(Capture { - actual_start: 1, - frames: generate_fake_frames(), - })), + inner: Inner::Captured( + (Capture { actual_start: 1, frames: generate_fake_frames() }).into(), + ), }; let frames = backtrace.frames(); diff --git a/std/src/collections/hash/map.rs b/std/src/collections/hash/map.rs index b82beb3b8b2ef..fe49660325e65 100644 --- a/std/src/collections/hash/map.rs +++ b/std/src/collections/hash/map.rs @@ -357,6 +357,7 @@ impl HashMap { /// map.insert(1, 2); /// ``` #[inline] + #[must_use] #[stable(feature = "hashmap_build_hasher", since = "1.7.0")] #[rustc_const_stable(feature = "const_collections_with_hasher", since = "1.85.0")] pub const fn with_hasher(hash_builder: S) -> HashMap { @@ -389,6 +390,7 @@ impl HashMap { /// map.insert(1, 2); /// ``` #[inline] + #[must_use] #[stable(feature = "hashmap_build_hasher", since = "1.7.0")] pub fn with_capacity_and_hasher(capacity: usize, hasher: S) -> HashMap { HashMap { base: base::HashMap::with_capacity_and_hasher(capacity, hasher) } @@ -409,6 +411,7 @@ impl HashMap { /// The `hash_builder` passed should implement the [`BuildHasher`] trait for /// the `HashMap` to be useful, see its documentation for details. #[inline] + #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] pub fn with_hasher_in(hash_builder: S, alloc: A) -> Self { HashMap { base: base::HashMap::with_hasher_in(hash_builder, alloc) } @@ -430,6 +433,7 @@ impl HashMap { /// the `HashMap` to be useful, see its documentation for details. /// #[inline] + #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] pub fn with_capacity_and_hasher_in(capacity: usize, hash_builder: S, alloc: A) -> Self { HashMap { base: base::HashMap::with_capacity_and_hasher_in(capacity, hash_builder, alloc) } diff --git a/std/src/collections/hash/set.rs b/std/src/collections/hash/set.rs index 3f3d601e4d30c..0fe26848fe7bb 100644 --- a/std/src/collections/hash/set.rs +++ b/std/src/collections/hash/set.rs @@ -229,6 +229,7 @@ impl HashSet { /// set.insert(2); /// ``` #[inline] + #[must_use] #[stable(feature = "hashmap_build_hasher", since = "1.7.0")] #[rustc_const_stable(feature = "const_collections_with_hasher", since = "1.85.0")] pub const fn with_hasher(hasher: S) -> HashSet { @@ -261,6 +262,7 @@ impl HashSet { /// set.insert(1); /// ``` #[inline] + #[must_use] #[stable(feature = "hashmap_build_hasher", since = "1.7.0")] pub fn with_capacity_and_hasher(capacity: usize, hasher: S) -> HashSet { HashSet { base: base::HashSet::with_capacity_and_hasher(capacity, hasher) } @@ -281,6 +283,7 @@ impl HashSet { /// The `hash_builder` passed should implement the [`BuildHasher`] trait for /// the `HashSet` to be useful, see its documentation for details. #[inline] + #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] pub fn with_hasher_in(hasher: S, alloc: A) -> HashSet { HashSet { base: base::HashSet::with_hasher_in(hasher, alloc) } @@ -301,6 +304,7 @@ impl HashSet { /// The `hash_builder` passed should implement the [`BuildHasher`] trait for /// the `HashSet` to be useful, see its documentation for details. #[inline] + #[must_use] #[unstable(feature = "allocator_api", issue = "32838")] pub fn with_capacity_and_hasher_in(capacity: usize, hasher: S, alloc: A) -> HashSet { HashSet { base: base::HashSet::with_capacity_and_hasher_in(capacity, hasher, alloc) } diff --git a/std/src/env.rs b/std/src/env.rs index 1f0ced5d0fd0d..d3e4417656e9a 100644 --- a/std/src/env.rs +++ b/std/src/env.rs @@ -15,7 +15,7 @@ use crate::ffi::{OsStr, OsString}; use crate::num::NonZero; use crate::ops::Try; use crate::path::{Path, PathBuf}; -use crate::sys::{env as env_imp, os as os_imp}; +use crate::sys::{env as env_imp, paths as paths_imp}; use crate::{array, fmt, io, sys}; /// Returns the current working directory as a [`PathBuf`]. @@ -51,7 +51,7 @@ use crate::{array, fmt, io, sys}; #[doc(alias = "GetCurrentDirectory")] #[stable(feature = "env", since = "1.0.0")] pub fn current_dir() -> io::Result { - os_imp::getcwd() + paths_imp::getcwd() } /// Changes the current working directory to the specified path. @@ -78,7 +78,7 @@ pub fn current_dir() -> io::Result { #[doc(alias = "chdir", alias = "SetCurrentDirectory", alias = "SetCurrentDirectoryW")] #[stable(feature = "env", since = "1.0.0")] pub fn set_current_dir>(path: P) -> io::Result<()> { - os_imp::chdir(path.as_ref()) + paths_imp::chdir(path.as_ref()) } /// An iterator over a snapshot of the environment variables of this process. @@ -444,7 +444,7 @@ pub unsafe fn remove_var>(key: K) { #[must_use = "iterators are lazy and do nothing unless consumed"] #[stable(feature = "env", since = "1.0.0")] pub struct SplitPaths<'a> { - inner: os_imp::SplitPaths<'a>, + inner: paths_imp::SplitPaths<'a>, } /// Parses input according to platform conventions for the `PATH` @@ -480,7 +480,7 @@ pub struct SplitPaths<'a> { /// ``` #[stable(feature = "env", since = "1.0.0")] pub fn split_paths + ?Sized>(unparsed: &T) -> SplitPaths<'_> { - SplitPaths { inner: os_imp::split_paths(unparsed.as_ref()) } + SplitPaths { inner: paths_imp::split_paths(unparsed.as_ref()) } } #[stable(feature = "env", since = "1.0.0")] @@ -508,7 +508,7 @@ impl fmt::Debug for SplitPaths<'_> { #[derive(Debug)] #[stable(feature = "env", since = "1.0.0")] pub struct JoinPathsError { - inner: os_imp::JoinPathsError, + inner: paths_imp::JoinPathsError, } /// Joins a collection of [`Path`]s appropriately for the `PATH` @@ -579,7 +579,7 @@ where I: IntoIterator, T: AsRef, { - os_imp::join_paths(paths.into_iter()).map_err(|e| JoinPathsError { inner: e }) + paths_imp::join_paths(paths.into_iter()).map_err(|e| JoinPathsError { inner: e }) } #[stable(feature = "env", since = "1.0.0")] @@ -641,7 +641,7 @@ impl Error for JoinPathsError { #[must_use] #[stable(feature = "env", since = "1.0.0")] pub fn home_dir() -> Option { - os_imp::home_dir() + paths_imp::home_dir() } /// Returns the path of a temporary directory. @@ -670,6 +670,17 @@ pub fn home_dir() -> Option { /// /// On Windows, the behavior is equivalent to that of [`GetTempPath2`][GetTempPath2] / /// [`GetTempPath`][GetTempPath], which this function uses internally. +/// Specifically, for non-SYSTEM processes, the function checks for the +/// following environment variables in order and returns the first path found: +/// +/// 1. The path specified by the `TMP` environment variable. +/// 2. The path specified by the `TEMP` environment variable. +/// 3. The path specified by the `USERPROFILE` environment variable. +/// 4. The Windows directory. +/// +/// When called from a process running as SYSTEM, +/// [`GetTempPath2`][GetTempPath2] returns `C:\Windows\SystemTemp` +/// regardless of environment variables. /// /// Note that, this [may change in the future][changes]. /// @@ -690,7 +701,7 @@ pub fn home_dir() -> Option { #[doc(alias = "GetTempPath", alias = "GetTempPath2")] #[stable(feature = "env", since = "1.0.0")] pub fn temp_dir() -> PathBuf { - os_imp::temp_dir() + paths_imp::temp_dir() } /// Returns the full filesystem path of the current running executable. @@ -712,28 +723,21 @@ pub fn temp_dir() -> PathBuf { /// /// # Security /// -/// The output of this function should not be trusted for anything -/// that might have security implications. Basically, if users can run -/// the executable, they can change the output arbitrarily. -/// -/// As an example, you can easily introduce a race condition. It goes -/// like this: -/// -/// 1. You get the path to the current executable using `current_exe()`, and -/// store it in a variable. -/// 2. Time passes. A malicious actor removes the current executable, and -/// replaces it with a malicious one. -/// 3. You then use the stored path to re-execute the current -/// executable. +/// The output of this function must be treated with care to avoid security +/// vulnerabilities, particularly in processes that run with privileges higher +/// than the user, such as setuid or setgid programs. /// -/// You expected to safely execute the current executable, but you're -/// instead executing something completely different. The code you -/// just executed runs with your privileges. +/// For example, on some Unix platforms, the result is calculated by +/// searching `$PATH` for an executable matching `argv[0]`, but both the +/// environment and arguments can be be set arbitrarily by the user who +/// invokes the program. /// -/// This sort of behavior has been known to [lead to privilege escalation] when -/// used incorrectly. +/// On Linux, if `fs.secure_hardlinks` is not set, an attacker who can +/// create hardlinks to the executable may be able to cause this function +/// to return an attacker-controlled path, which they later replace with +/// a different program. /// -/// [lead to privilege escalation]: https://securityvulns.com/Wdocument183.html +/// This list of illustrative example attacks is not exhaustive. /// /// # Examples /// @@ -748,7 +752,7 @@ pub fn temp_dir() -> PathBuf { /// ``` #[stable(feature = "env", since = "1.0.0")] pub fn current_exe() -> io::Result { - os_imp::current_exe() + paths_imp::current_exe() } /// An iterator over the arguments of a process, yielding a [`String`] value for diff --git a/std/src/ffi/os_str.rs b/std/src/ffi/os_str.rs index 4e4d377ae2708..f0cebb05c76a5 100644 --- a/std/src/ffi/os_str.rs +++ b/std/src/ffi/os_str.rs @@ -576,15 +576,21 @@ impl OsString { /// Truncate the `OsString` to the specified length. /// + /// If `new_len` is greater than the string's current length, this has no + /// effect. + /// /// # Panics + /// /// Panics if `len` does not lie on a valid `OsStr` boundary /// (as described in [`OsStr::slice_encoded_bytes`]). #[inline] #[unstable(feature = "os_string_truncate", issue = "133262")] pub fn truncate(&mut self, len: usize) { - self.as_os_str().inner.check_public_boundary(len); - // SAFETY: The length was just checked to be at a valid boundary. - unsafe { self.inner.truncate_unchecked(len) }; + if len <= self.len() { + self.as_os_str().inner.check_public_boundary(len); + // SAFETY: The length was just checked to be at a valid boundary. + unsafe { self.inner.truncate_unchecked(len) }; + } } /// Provides plumbing to `Vec::extend_from_slice` without giving full @@ -1565,7 +1571,7 @@ impl Ord for OsStr { macro_rules! impl_cmp { ($lhs:ty, $rhs: ty) => { #[stable(feature = "cmp_os_str", since = "1.8.0")] - impl<'a, 'b> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { ::eq(self, other) @@ -1573,7 +1579,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_os_str", since = "1.8.0")] - impl<'a, 'b> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { ::eq(self, other) @@ -1581,7 +1587,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_os_str", since = "1.8.0")] - impl<'a, 'b> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { ::partial_cmp(self, other) @@ -1589,7 +1595,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_os_str", since = "1.8.0")] - impl<'a, 'b> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { ::partial_cmp(self, other) @@ -1599,10 +1605,10 @@ macro_rules! impl_cmp { } impl_cmp!(OsString, OsStr); -impl_cmp!(OsString, &'a OsStr); -impl_cmp!(Cow<'a, OsStr>, OsStr); -impl_cmp!(Cow<'a, OsStr>, &'b OsStr); -impl_cmp!(Cow<'a, OsStr>, OsString); +impl_cmp!(OsString, &OsStr); +impl_cmp!(Cow<'_, OsStr>, OsStr); +impl_cmp!(Cow<'_, OsStr>, &OsStr); +impl_cmp!(Cow<'_, OsStr>, OsString); #[stable(feature = "rust1", since = "1.0.0")] impl Hash for OsStr { diff --git a/std/src/fs.rs b/std/src/fs.rs index a24baad615012..9643d3fcae662 100644 --- a/std/src/fs.rs +++ b/std/src/fs.rs @@ -277,6 +277,7 @@ pub struct OpenOptions(fs_imp::OpenOptions); /// Representation of the various timestamps on a file. #[derive(Copy, Clone, Debug, Default)] #[stable(feature = "file_set_times", since = "1.75.0")] +#[must_use = "must be applied to a file via `File::set_times` to have any effect"] pub struct FileTimes(fs_imp::FileTimes); /// Representation of the various permissions on a file. @@ -814,7 +815,8 @@ impl File { /// Acquire an exclusive lock on the file. Blocks until the lock can be acquired. /// - /// This acquires an exclusive lock; no other file handle to this file may acquire another lock. + /// This acquires an exclusive lock; no other file handle to this file, in this or any other + /// process, may acquire another lock. /// /// This lock may be advisory or mandatory. This lock is meant to interact with [`lock`], /// [`try_lock`], [`lock_shared`], [`try_lock_shared`], and [`unlock`]. Its interactions with @@ -867,8 +869,8 @@ impl File { /// Acquire a shared (non-exclusive) lock on the file. Blocks until the lock can be acquired. /// - /// This acquires a shared lock; more than one file handle may hold a shared lock, but none may - /// hold an exclusive lock at the same time. + /// This acquires a shared lock; more than one file handle, in this or any other process, may + /// hold a shared lock, but none may hold an exclusive lock at the same time. /// /// This lock may be advisory or mandatory. This lock is meant to interact with [`lock`], /// [`try_lock`], [`lock_shared`], [`try_lock_shared`], and [`unlock`]. Its interactions with @@ -922,7 +924,8 @@ impl File { /// Returns `Err(TryLockError::WouldBlock)` if a different lock is already held on this file /// (via another handle/descriptor). /// - /// This acquires an exclusive lock; no other file handle to this file may acquire another lock. + /// This acquires an exclusive lock; no other file handle to this file, in this or any other + /// process, may acquire another lock. /// /// This lock may be advisory or mandatory. This lock is meant to interact with [`lock`], /// [`try_lock`], [`lock_shared`], [`try_lock_shared`], and [`unlock`]. Its interactions with @@ -986,8 +989,8 @@ impl File { /// Returns `Err(TryLockError::WouldBlock)` if a different lock is already held on this file /// (via another handle/descriptor). /// - /// This acquires a shared lock; more than one file handle may hold a shared lock, but none may - /// hold an exclusive lock at the same time. + /// This acquires a shared lock; more than one file handle, in this or any other process, may + /// hold a shared lock, but none may hold an exclusive lock at the same time. /// /// This lock may be advisory or mandatory. This lock is meant to interact with [`lock`], /// [`try_lock`], [`lock_shared`], [`try_lock_shared`], and [`unlock`]. Its interactions with @@ -2679,7 +2682,7 @@ impl AsInner for DirEntry { /// /// This function will only ever return an error of kind `NotFound` if the given /// path does not exist. Note that the inverse is not true, -/// ie. if a path does not exist, its removal may fail for a number of reasons, +/// i.e. if a path does not exist, its removal may fail for a number of reasons, /// such as insufficient permissions. /// /// # Examples @@ -3149,7 +3152,7 @@ pub fn create_dir_all>(path: P) -> io::Result<()> { /// /// This function will only ever return an error of kind `NotFound` if the given /// path does not exist. Note that the inverse is not true, -/// ie. if a path does not exist, its removal may fail for a number of reasons, +/// i.e. if a path does not exist, its removal may fail for a number of reasons, /// such as insufficient permissions. /// /// # Examples diff --git a/std/src/io/buffered/tests.rs b/std/src/io/buffered/tests.rs index 6ad4158b92904..e335d8afdc483 100644 --- a/std/src/io/buffered/tests.rs +++ b/std/src/io/buffered/tests.rs @@ -391,16 +391,16 @@ fn test_read_until() { let mut v = Vec::new(); reader.read_until(0, &mut v).unwrap(); assert_eq!(v, [0]); - v.truncate(0); + v.clear(); reader.read_until(2, &mut v).unwrap(); assert_eq!(v, [1, 2]); - v.truncate(0); + v.clear(); reader.read_until(1, &mut v).unwrap(); assert_eq!(v, [1]); - v.truncate(0); + v.clear(); reader.read_until(8, &mut v).unwrap(); assert_eq!(v, [0]); - v.truncate(0); + v.clear(); reader.read_until(9, &mut v).unwrap(); assert_eq!(v, []); } @@ -429,13 +429,13 @@ fn test_read_line() { let mut s = String::new(); reader.read_line(&mut s).unwrap(); assert_eq!(s, "a\n"); - s.truncate(0); + s.clear(); reader.read_line(&mut s).unwrap(); assert_eq!(s, "b\n"); - s.truncate(0); + s.clear(); reader.read_line(&mut s).unwrap(); assert_eq!(s, "c"); - s.truncate(0); + s.clear(); reader.read_line(&mut s).unwrap(); assert_eq!(s, ""); } diff --git a/std/src/io/copy/tests.rs b/std/src/io/copy/tests.rs index 25b1ece2745b9..7bdba3a04416e 100644 --- a/std/src/io/copy/tests.rs +++ b/std/src/io/copy/tests.rs @@ -97,16 +97,17 @@ fn copy_specializes_to_vec() { #[test] fn copy_specializes_from_vecdeque() { - let mut source = VecDeque::with_capacity(100 * 1024); - for _ in 0..20 * 1024 { + let num: usize = if cfg!(miri) { 512 } else { 20 * 1024 }; + let mut source = VecDeque::with_capacity(4 * num); + for _ in 0..num { source.push_front(0); } - for _ in 0..20 * 1024 { + for _ in 0..num { source.push_back(0); } let mut sink = WriteObserver { observed_buffer: 0 }; - assert_eq!(40 * 1024u64, io::copy(&mut source, &mut sink).unwrap()); - assert_eq!(20 * 1024, sink.observed_buffer); + assert_eq!(2 * num as u64, io::copy(&mut source, &mut sink).unwrap()); + assert_eq!(num, sink.observed_buffer); } #[test] diff --git a/std/src/io/mod.rs b/std/src/io/mod.rs index 623c34c6d2910..cba578cd3a6fa 100644 --- a/std/src/io/mod.rs +++ b/std/src/io/mod.rs @@ -3348,6 +3348,7 @@ impl SizeHint for &[u8] { /// [`split`]: BufRead::split #[stable(feature = "rust1", since = "1.0.0")] #[derive(Debug)] +#[cfg_attr(not(test), rustc_diagnostic_item = "IoSplit")] pub struct Split { buf: B, delim: u8, diff --git a/std/src/io/tests.rs b/std/src/io/tests.rs index b22988d4a8a9d..a56359dae765b 100644 --- a/std/src/io/tests.rs +++ b/std/src/io/tests.rs @@ -17,10 +17,10 @@ fn read_until() { let mut v = Vec::new(); assert_eq!(buf.read_until(b'3', &mut v).unwrap(), 3); assert_eq!(v, b"123"); - v.truncate(0); + v.clear(); assert_eq!(buf.read_until(b'3', &mut v).unwrap(), 1); assert_eq!(v, b"3"); - v.truncate(0); + v.clear(); assert_eq!(buf.read_until(b'3', &mut v).unwrap(), 0); assert_eq!(v, []); } @@ -80,10 +80,10 @@ fn read_line() { let mut v = String::new(); assert_eq!(buf.read_line(&mut v).unwrap(), 3); assert_eq!(v, "12\n"); - v.truncate(0); + v.clear(); assert_eq!(buf.read_line(&mut v).unwrap(), 1); assert_eq!(v, "\n"); - v.truncate(0); + v.clear(); assert_eq!(buf.read_line(&mut v).unwrap(), 0); assert_eq!(v, ""); } diff --git a/std/src/lib.rs b/std/src/lib.rs index dcde208fac77b..1730742dffe93 100644 --- a/std/src/lib.rs +++ b/std/src/lib.rs @@ -94,8 +94,8 @@ //! pull-requests for your suggested changes. //! //! Contributions are appreciated! If you see a part of the docs that can be -//! improved, submit a PR, or chat with us first on [Zulip][rust-zulip] -//! #docs. +//! improved, submit a PR, or chat with us first on [Zulip][t-libs-zulip] +//! #t-libs. //! //! # A Tour of The Rust Standard Library //! @@ -209,7 +209,7 @@ //! [multithreading]: thread //! [other]: #what-is-in-the-standard-library-documentation //! [primitive types]: ../book/ch03-02-data-types.html -//! [rust-zulip]: https://rust-lang.zulipchat.com/ +//! [t-libs-zulip]: https://rust-lang.zulipchat.com/#narrow/channel/219381-t-libs/ //! [array]: prim@array //! [slice]: prim@slice @@ -275,9 +275,7 @@ #![feature(cfg_sanitizer_cfi)] #![feature(cfg_target_thread_local)] #![feature(cfi_encoding)] -#![feature(const_default)] #![feature(const_trait_impl)] -#![feature(core_float_math)] #![feature(decl_macro)] #![feature(deprecated_suggestion)] #![feature(doc_cfg)] @@ -287,17 +285,11 @@ #![feature(f16)] #![feature(f128)] #![feature(ffi_const)] -#![feature(formatting_options)] -#![feature(funnel_shifts)] -#![feature(if_let_guard)] #![feature(intra_doc_pointers)] -#![feature(iter_advance_by)] -#![feature(iter_next_chunk)] #![feature(lang_items)] #![feature(link_cfg)] #![feature(linkage)] #![feature(macro_metavar_expr_concat)] -#![feature(maybe_uninit_fill)] #![feature(min_specialization)] #![feature(must_not_suspend)] #![feature(needs_panic_runtime)] @@ -322,10 +314,11 @@ #![feature(bstr)] #![feature(bstr_internals)] #![feature(cast_maybe_uninit)] -#![feature(cfg_select)] #![feature(char_internals)] #![feature(clone_to_uninit)] #![feature(const_convert)] +#![feature(const_default)] +#![feature(core_float_math)] #![feature(core_intrinsics)] #![feature(core_io_borrowed_buf)] #![feature(cstr_display)] @@ -341,13 +334,20 @@ #![feature(float_minimum_maximum)] #![feature(fmt_internals)] #![feature(fn_ptr_trait)] +#![feature(formatting_options)] +#![feature(funnel_shifts)] #![feature(generic_atomic)] +#![feature(hash_map_internals)] +#![feature(hash_map_macro)] #![feature(hasher_prefixfree_extras)] #![feature(hashmap_internals)] #![feature(hint_must_use)] #![feature(int_from_ascii)] #![feature(ip)] +#![feature(iter_advance_by)] +#![feature(iter_next_chunk)] #![feature(maybe_uninit_array_assume_init)] +#![feature(maybe_uninit_fill)] #![feature(panic_can_unwind)] #![feature(panic_internals)] #![feature(pin_coerce_unsized_trait)] @@ -365,6 +365,7 @@ #![feature(sync_unsafe_cell)] #![feature(temporary_niche_types)] #![feature(ub_checks)] +#![feature(uint_carryless_mul)] #![feature(used_with_arg)] // tidy-alphabetical-end // @@ -394,7 +395,6 @@ // // Only for re-exporting: // tidy-alphabetical-start -#![feature(assert_matches)] #![feature(async_iterator)] #![feature(c_variadic)] #![feature(cfg_accessible)] @@ -497,6 +497,8 @@ pub use core::cmp; pub use core::convert; #[stable(feature = "rust1", since = "1.0.0")] pub use core::default; +#[unstable(feature = "field_projections", issue = "145383")] +pub use core::field; #[stable(feature = "futures_api", since = "1.36.0")] pub use core::future; #[stable(feature = "core_hint", since = "1.27.0")] @@ -535,7 +537,7 @@ pub use core::option; pub use core::pin; #[stable(feature = "rust1", since = "1.0.0")] pub use core::ptr; -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] pub use core::range; #[stable(feature = "rust1", since = "1.0.0")] pub use core::result; @@ -696,7 +698,7 @@ mod panicking; #[allow(dead_code, unused_attributes, fuzzy_provenance_casts, unsafe_op_in_unsafe_fn)] mod backtrace_rs; -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "1.95.0")] pub use core::cfg_select; #[unstable( feature = "concat_bytes", @@ -726,7 +728,7 @@ pub use core::{ assert_eq, assert_ne, debug_assert, debug_assert_eq, debug_assert_ne, r#try, unimplemented, unreachable, write, writeln, }; -#[unstable(feature = "assert_matches", issue = "82775")] +#[stable(feature = "assert_matches", since = "1.95.0")] pub use core::{assert_matches, debug_assert_matches}; // Re-export unstable derive macro defined through core. diff --git a/std/src/macros.rs b/std/src/macros.rs index 0bb14552432d5..108cd3cd98eb5 100644 --- a/std/src/macros.rs +++ b/std/src/macros.rs @@ -5,6 +5,9 @@ //! library. // ignore-tidy-dbg +#[cfg(test)] +mod tests; + #[doc = include_str!("../../core/src/macros/panic.md")] #[macro_export] #[rustc_builtin_macro(std_panic)] @@ -359,19 +362,16 @@ macro_rules! dbg { }; } -/// Internal macro that processes a list of expressions and produces a chain of -/// nested `match`es, one for each expression, before finally calling `eprint!` -/// with the collected information and returning all the evaluated expressions -/// in a tuple. +/// Internal macro that processes a list of expressions, binds their results +/// with `match`, calls `eprint!` with the collected information, and returns +/// all the evaluated expressions in a tuple. /// /// E.g. `dbg_internal!(() () (1, 2))` expands into /// ```rust, ignore -/// match 1 { -/// tmp_1 => match 2 { -/// tmp_2 => { -/// eprint!("...", &tmp_1, &tmp_2, /* some other arguments */); -/// (tmp_1, tmp_2) -/// } +/// match (1, 2) { +/// (tmp_1, tmp_2) => { +/// eprint!("...", &tmp_1, &tmp_2, /* some other arguments */); +/// (tmp_1, tmp_2) /// } /// } /// ``` @@ -380,37 +380,117 @@ macro_rules! dbg { #[doc(hidden)] #[rustc_macro_transparency = "semiopaque"] pub macro dbg_internal { - (($($piece:literal),+) ($($processed:expr => $bound:expr),+) ()) => {{ - $crate::eprint!( - $crate::concat!($($piece),+), - $( - $crate::stringify!($processed), - // The `&T: Debug` check happens here (not in the format literal desugaring) - // to avoid format literal related messages and suggestions. - &&$bound as &dyn $crate::fmt::Debug - ),+, - // The location returned here is that of the macro invocation, so - // it will be the same for all expressions. Thus, label these - // arguments so that they can be reused in every piece of the - // formatting template. - file=$crate::file!(), - line=$crate::line!(), - column=$crate::column!() - ); - // Comma separate the variables only when necessary so that this will - // not yield a tuple for a single expression, but rather just parenthesize - // the expression. - ($($bound),+) - }}, - (($($piece:literal),*) ($($processed:expr => $bound:expr),*) ($val:expr $(,$rest:expr)*)) => { + (($($piece:literal),+) ($($processed:expr => $bound:ident),+) ()) => { // Use of `match` here is intentional because it affects the lifetimes // of temporaries - https://stackoverflow.com/a/48732525/1063961 - match $val { - tmp => $crate::macros::dbg_internal!( - ($($piece,)* "[{file}:{line}:{column}] {} = {:#?}\n") - ($($processed => $bound,)* $val => tmp) - ($($rest),*) - ), + // Always put the arguments in a tuple to avoid an unused parens lint on the pattern. + match ($($processed,)+) { + ($($bound,)+) => { + $crate::eprint!( + $crate::concat!($($piece),+), + $( + $crate::stringify!($processed), + // The `&T: Debug` check happens here (not in the format literal desugaring) + // to avoid format literal related messages and suggestions. + &&$bound as &dyn $crate::fmt::Debug + ),+, + // The location returned here is that of the macro invocation, so + // it will be the same for all expressions. Thus, label these + // arguments so that they can be reused in every piece of the + // formatting template. + file=$crate::file!(), + line=$crate::line!(), + column=$crate::column!() + ); + // Comma separate the variables only when necessary so that this will + // not yield a tuple for a single expression, but rather just parenthesize + // the expression. + ($($bound),+) + + } } }, + (($($piece:literal),*) ($($processed:expr => $bound:ident),*) ($val:expr $(,$rest:expr)*)) => { + $crate::macros::dbg_internal!( + ($($piece,)* "[{file}:{line}:{column}] {} = {:#?}\n") + ($($processed => $bound,)* $val => tmp) + ($($rest),*) + ) + }, +} + +#[doc(hidden)] +#[macro_export] +#[allow_internal_unstable(hash_map_internals)] +#[unstable(feature = "hash_map_internals", issue = "none")] +macro_rules! repetition_utils { + (@count $($tokens:tt),*) => {{ + [$($crate::repetition_utils!(@replace $tokens => ())),*].len() + }}; + + (@replace $x:tt => $y:tt) => { $y } +} + +/// Creates a [`HashMap`] containing the arguments. +/// +/// `hash_map!` allows specifying the entries that make +/// up the [`HashMap`] where the key and value are separated by a `=>`. +/// +/// The entries are separated by commas with a trailing comma being allowed. +/// +/// It is semantically equivalent to using repeated [`HashMap::insert`] +/// on a newly created hashmap. +/// +/// `hash_map!` will attempt to avoid repeated reallocations by +/// using [`HashMap::with_capacity`]. +/// +/// # Examples +/// +/// ```rust +/// #![feature(hash_map_macro)] +/// use std::hash_map; +/// +/// let map = hash_map! { +/// "key" => "value", +/// "key1" => "value1" +/// }; +/// +/// assert_eq!(map.get("key"), Some(&"value")); +/// assert_eq!(map.get("key1"), Some(&"value1")); +/// assert!(map.get("brrrrrrooooommm").is_none()); +/// ``` +/// +/// And with a trailing comma +/// +///```rust +/// #![feature(hash_map_macro)] +/// use std::hash_map; +/// +/// let map = hash_map! { +/// "key" => "value", // notice the , +/// }; +/// +/// assert_eq!(map.get("key"), Some(&"value")); +/// ``` +/// +/// The key and value are moved into the HashMap. +/// +/// [`HashMap`]: crate::collections::HashMap +/// [`HashMap::insert`]: crate::collections::HashMap::insert +/// [`HashMap::with_capacity`]: crate::collections::HashMap::with_capacity +#[macro_export] +#[allow_internal_unstable(hash_map_internals)] +#[unstable(feature = "hash_map_macro", issue = "144032")] +macro_rules! hash_map { + () => {{ + $crate::collections::HashMap::new() + }}; + + ( $( $key:expr => $value:expr ),* $(,)? ) => {{ + let mut map = $crate::collections::HashMap::with_capacity( + const { $crate::repetition_utils!(@count $($key),*) } + ); + $( map.insert($key, $value); )* + map + }} } diff --git a/std/src/macros/tests.rs b/std/src/macros/tests.rs new file mode 100644 index 0000000000000..db2be925ff30a --- /dev/null +++ b/std/src/macros/tests.rs @@ -0,0 +1,13 @@ +// ignore-tidy-dbg + +/// Test for : +/// `dbg!` shouldn't drop arguments' temporaries. +#[test] +fn no_dropping_temps() { + fn temp() {} + + *dbg!(&temp()); + *dbg!(&temp(), 1).0; + *dbg!(0, &temp()).1; + *dbg!(0, &temp(), 2).1; +} diff --git a/std/src/num/f128.rs b/std/src/num/f128.rs index 6f1fd2975b714..2c8898a6aa86a 100644 --- a/std/src/num/f128.rs +++ b/std/src/num/f128.rs @@ -16,6 +16,7 @@ use crate::intrinsics; use crate::sys::cmath; #[cfg(not(test))] +#[doc(test(attr(allow(unused_features))))] impl f128 { /// Raises a number to a floating point power. /// diff --git a/std/src/num/f16.rs b/std/src/num/f16.rs index 20d0b4e1e552b..7ca266c8a5f60 100644 --- a/std/src/num/f16.rs +++ b/std/src/num/f16.rs @@ -16,6 +16,7 @@ use crate::intrinsics; use crate::sys::cmath; #[cfg(not(test))] +#[doc(test(attr(allow(unused_features))))] impl f16 { /// Raises a number to a floating point power. /// @@ -916,7 +917,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// #![feature(float_gamma)] /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// @@ -952,7 +952,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// #![feature(float_gamma)] /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// @@ -988,7 +987,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// #![feature(float_erf)] /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// The error function relates what percent of a normal distribution lies @@ -1028,7 +1026,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// #![feature(float_erf)] /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// let x: f16 = 0.123; diff --git a/std/src/os/fd/mod.rs b/std/src/os/fd/mod.rs index 95cf4932e6e2c..473d7ae3e2ae6 100644 --- a/std/src/os/fd/mod.rs +++ b/std/src/os/fd/mod.rs @@ -16,6 +16,9 @@ mod owned; #[cfg(not(target_os = "trusty"))] mod net; +// Implementation of stdio file descriptor constants. +mod stdio; + #[cfg(test)] mod tests; @@ -24,3 +27,5 @@ mod tests; pub use owned::*; #[stable(feature = "os_fd", since = "1.66.0")] pub use raw::*; +#[unstable(feature = "stdio_fd_consts", issue = "150836")] +pub use stdio::*; diff --git a/std/src/os/fd/raw.rs b/std/src/os/fd/raw.rs index 39e374174646c..0d96958b6cca1 100644 --- a/std/src/os/fd/raw.rs +++ b/std/src/os/fd/raw.rs @@ -16,7 +16,7 @@ use crate::io; use crate::os::hermit::io::OwnedFd; #[cfg(all(not(target_os = "hermit"), not(target_os = "motor")))] use crate::os::raw; -#[cfg(all(doc, not(target_arch = "wasm32")))] +#[cfg(all(doc, not(any(target_arch = "wasm32", target_env = "sgx"))))] use crate::os::unix::io::AsFd; #[cfg(unix)] use crate::os::unix::io::OwnedFd; diff --git a/std/src/os/fd/stdio.rs b/std/src/os/fd/stdio.rs new file mode 100644 index 0000000000000..c50cbd39849b7 --- /dev/null +++ b/std/src/os/fd/stdio.rs @@ -0,0 +1,53 @@ +use super::BorrowedFd; + +/// The file descriptor for the standard input stream of the current process. +/// +/// See [`io::stdin()`][`crate::io::stdin`] for the higher level handle, which should be preferred +/// whenever possible. See [`STDERR`] for why the file descriptor might be required and caveats. +#[unstable(feature = "stdio_fd_consts", issue = "150836")] +pub const STDIN: BorrowedFd<'static> = unsafe { BorrowedFd::borrow_raw(0) }; + +/// The file descriptor for the standard output stream of the current process. +/// +/// See [`io::stdout()`][`crate::io::stdout`] for the higher level handle, which should be preferred +/// whenever possible. See [`STDERR`] for why the file descriptor might be required and caveats. In +/// addition to the issues discussed there, note that [`Stdout`][`crate::io::Stdout`] is buffered by +/// default, and writing to the file descriptor will bypass this buffer. +#[unstable(feature = "stdio_fd_consts", issue = "150836")] +pub const STDOUT: BorrowedFd<'static> = unsafe { BorrowedFd::borrow_raw(1) }; + +/// The file descriptor for the standard error stream of the current process. +/// +/// See [`io::stderr()`][`crate::io::stderr`] for the higher level handle, which should be preferred +/// whenever possible. However, there are situations where touching the `std::io` handles (or most +/// other parts of the standard library) risks deadlocks or other subtle bugs. For example: +/// +/// - Global allocators must be careful to [avoid reentrancy][global-alloc-reentrancy], and the +/// `std::io` handles may allocate memory on (some) accesses. +/// - Signal handlers must be *async-signal-safe*, which rules out panicking, taking locks (may +/// deadlock if the signal handler interrupted a thread holding that lock), allocating memory, or +/// anything else that is not explicitly declared async-signal-safe. +/// - `CommandExt::pre_exec` callbacks can safely panic (with some limitations), but otherwise must +/// abide by similar limitations as signal handlers. In particular, at the time these callbacks +/// run, the stdio file descriptors have already been replaced, but the locks protecting the +/// `std::io` handles may be permanently locked if another thread held the lock at `fork()` time. +/// +/// In these and similar cases, direct access to the file descriptor may be required. However, in +/// most cases, using the `std::io` handles and accessing the file descriptor via the `AsFd` +/// implementations is preferable, as it enables cooperation with the standard library's locking and +/// buffering. +/// +/// # I/O safety +/// +/// This is a `BorrowedFd<'static>` because the standard input/output/error streams are shared +/// resources that must remain available for the lifetime of the process. This is only true when +/// linking `std`, and may not always hold for [code running before `main()`][before-after-main] or +/// in `no_std` environments. It is [unsound][io-safety] to close these file descriptors. Safe +/// patterns for changing these file descriptors are available on Unix via the `StdioExt` extension +/// trait. +/// +/// [before-after-main]: ../../../std/index.html#use-before-and-after-main +/// [io-safety]: ../../../std/io/index.html#io-safety +/// [global-alloc-reentrancy]: ../../../std/alloc/trait.GlobalAlloc.html#re-entrance +#[unstable(feature = "stdio_fd_consts", issue = "150836")] +pub const STDERR: BorrowedFd<'static> = unsafe { BorrowedFd::borrow_raw(2) }; diff --git a/std/src/os/hermit/ffi.rs b/std/src/os/hermit/ffi.rs index 19761fd99b400..01a54e1ac8df8 100644 --- a/std/src/os/hermit/ffi.rs +++ b/std/src/os/hermit/ffi.rs @@ -1,4 +1,4 @@ -//! HermitCore-specific extension to the primitives in the `std::ffi` module +//! Hermit-specific extension to the primitives in the `std::ffi` module //! //! # Examples //! diff --git a/std/src/os/unix/process.rs b/std/src/os/unix/process.rs index fab1b20b8c0e9..a739d6ad2a90d 100644 --- a/std/src/os/unix/process.rs +++ b/std/src/os/unix/process.rs @@ -593,5 +593,5 @@ impl From for process::ChildStderr { #[must_use] #[stable(feature = "unix_ppid", since = "1.27.0")] pub fn parent_id() -> u32 { - crate::sys::os::getppid() + crate::sys::process::getppid() } diff --git a/std/src/os/vxworks/fs.rs b/std/src/os/vxworks/fs.rs index b88ed19b067a5..a21748ce9fe00 100644 --- a/std/src/os/vxworks/fs.rs +++ b/std/src/os/vxworks/fs.rs @@ -69,24 +69,54 @@ impl MetadataExt for Metadata { fn st_size(&self) -> u64 { self.as_inner().as_inner().st_size as u64 } + #[cfg(vxworks_lt_25_09)] fn st_atime(&self) -> i64 { self.as_inner().as_inner().st_atime as i64 } + #[cfg(not(vxworks_lt_25_09))] + fn st_atime(&self) -> i64 { + self.as_inner().as_inner().st_atim.tv_sec as i64 + } + #[cfg(vxworks_lt_25_09)] fn st_atime_nsec(&self) -> i64 { 0 } + #[cfg(not(vxworks_lt_25_09))] + fn st_atime_nsec(&self) -> i64 { + self.as_inner().as_inner().st_atim.tv_nsec as i64 + } + #[cfg(vxworks_lt_25_09)] fn st_mtime(&self) -> i64 { self.as_inner().as_inner().st_mtime as i64 } + #[cfg(not(vxworks_lt_25_09))] + fn st_mtime(&self) -> i64 { + self.as_inner().as_inner().st_mtim.tv_sec as i64 + } + #[cfg(vxworks_lt_25_09)] fn st_mtime_nsec(&self) -> i64 { 0 } + #[cfg(not(vxworks_lt_25_09))] + fn st_mtime_nsec(&self) -> i64 { + self.as_inner().as_inner().st_mtim.tv_nsec as i64 + } + #[cfg(vxworks_lt_25_09)] fn st_ctime(&self) -> i64 { self.as_inner().as_inner().st_ctime as i64 } + #[cfg(not(vxworks_lt_25_09))] + fn st_ctime(&self) -> i64 { + self.as_inner().as_inner().st_ctim.tv_sec as i64 + } + #[cfg(vxworks_lt_25_09)] fn st_ctime_nsec(&self) -> i64 { 0 } + #[cfg(not(vxworks_lt_25_09))] + fn st_ctime_nsec(&self) -> i64 { + self.as_inner().as_inner().st_ctim.tv_nsec as i64 + } fn st_blksize(&self) -> u64 { self.as_inner().as_inner().st_blksize as u64 } diff --git a/std/src/os/windows/fs.rs b/std/src/os/windows/fs.rs index 73f3e589e2432..7fd46b31f7d83 100644 --- a/std/src/os/windows/fs.rs +++ b/std/src/os/windows/fs.rs @@ -138,6 +138,8 @@ impl FileExt for fs::File { } /// Windows-specific extensions to [`fs::OpenOptions`]. +// WARNING: This trait is not sealed. DON'T add any new methods! +// Add them to OpenOptionsExt2 instead. #[stable(feature = "open_options_ext", since = "1.10.0")] pub trait OpenOptionsExt { /// Overrides the `dwDesiredAccess` argument to the call to [`CreateFile`] @@ -305,18 +307,6 @@ pub trait OpenOptionsExt { /// https://docs.microsoft.com/en-us/windows/win32/api/winnt/ne-winnt-security_impersonation_level #[stable(feature = "open_options_ext", since = "1.10.0")] fn security_qos_flags(&mut self, flags: u32) -> &mut Self; - - /// If set to `true`, prevent the "last access time" of the file from being changed. - /// - /// Default to `false`. - #[unstable(feature = "windows_freeze_file_times", issue = "149715")] - fn freeze_last_access_time(&mut self, freeze: bool) -> &mut Self; - - /// If set to `true`, prevent the "last write time" of the file from being changed. - /// - /// Default to `false`. - #[unstable(feature = "windows_freeze_file_times", issue = "149715")] - fn freeze_last_write_time(&mut self, freeze: bool) -> &mut Self; } #[stable(feature = "open_options_ext", since = "1.10.0")] @@ -345,7 +335,28 @@ impl OpenOptionsExt for OpenOptions { self.as_inner_mut().security_qos_flags(flags); self } +} + +#[unstable(feature = "windows_freeze_file_times", issue = "149715")] +pub trait OpenOptionsExt2: Sealed { + /// If set to `true`, prevent the "last access time" of the file from being changed. + /// + /// Default to `false`. + #[unstable(feature = "windows_freeze_file_times", issue = "149715")] + fn freeze_last_access_time(&mut self, freeze: bool) -> &mut Self; + + /// If set to `true`, prevent the "last write time" of the file from being changed. + /// + /// Default to `false`. + #[unstable(feature = "windows_freeze_file_times", issue = "149715")] + fn freeze_last_write_time(&mut self, freeze: bool) -> &mut Self; +} + +#[unstable(feature = "sealed", issue = "none")] +impl Sealed for OpenOptions {} +#[unstable(feature = "windows_freeze_file_times", issue = "149715")] +impl OpenOptionsExt2 for OpenOptions { fn freeze_last_access_time(&mut self, freeze: bool) -> &mut Self { self.as_inner_mut().freeze_last_access_time(freeze); self diff --git a/std/src/os/windows/net/listener.rs b/std/src/os/windows/net/listener.rs index 332b116ee1a39..345cfe8d22ba9 100644 --- a/std/src/os/windows/net/listener.rs +++ b/std/src/os/windows/net/listener.rs @@ -12,6 +12,8 @@ use crate::{fmt, io}; /// A structure representing a Unix domain socket server. /// +/// Under Windows, it will only work starting from Windows 10 17063. +/// /// # Examples /// /// ```no_run diff --git a/std/src/os/windows/net/stream.rs b/std/src/os/windows/net/stream.rs index c31f03fdf53f8..f2d0f7c09e9f1 100644 --- a/std/src/os/windows/net/stream.rs +++ b/std/src/os/windows/net/stream.rs @@ -17,6 +17,8 @@ use crate::time::Duration; use crate::{fmt, io}; /// A Unix stream socket. /// +/// Under Windows, it will only work starting from Windows 10 17063. +/// /// # Examples /// /// ```no_run diff --git a/std/src/os/windows/process.rs b/std/src/os/windows/process.rs index b32c6cd442ffa..ff3ae8145e0f6 100644 --- a/std/src/os/windows/process.rs +++ b/std/src/os/windows/process.rs @@ -573,7 +573,8 @@ impl<'a> ProcThreadAttributeListBuilder<'a> { /// /// # Example /// - /// ``` + #[cfg_attr(target_vendor = "win7", doc = "```no_run")] + #[cfg_attr(not(target_vendor = "win7"), doc = "```")] /// #![feature(windows_process_extensions_raw_attribute)] /// use std::ffi::c_void; /// use std::os::windows::process::{CommandExt, ProcThreadAttributeList}; diff --git a/std/src/path.rs b/std/src/path.rs index 25bd7005b9942..6b894f6bf4243 100644 --- a/std/src/path.rs +++ b/std/src/path.rs @@ -19,6 +19,20 @@ //! matter the platform or filesystem. An exception to this is made for Windows //! drive letters. //! +//! ## Path normalization +//! +//! Several methods in this module perform basic path normalization by disregarding +//! repeated separators, non-leading `.` components, and trailing separators. These include: +//! - Methods for iteration, such as [`Path::components`] and [`Path::iter`] +//! - Methods for inspection, such as [`Path::has_root`] +//! - Comparisons using [`PartialEq`], [`PartialOrd`], and [`Ord`] +//! +//! [`Path::join`] and [`PathBuf::push`] also disregard trailing slashes. +//! +// FIXME(normalize_lexically): mention normalize_lexically once stable +//! These methods **do not** resolve `..` components or symlinks. For full normalization +//! including `..` resolution, use [`Path::canonicalize`] (which does access the filesystem). +//! //! ## Simple usage //! //! Path manipulation includes both parsing components from slices and building @@ -79,7 +93,7 @@ use crate::ops::{self, Deref}; use crate::rc::Rc; use crate::str::FromStr; use crate::sync::Arc; -use crate::sys::path::{HAS_PREFIXES, MAIN_SEP_STR, is_sep_byte, is_verbatim_sep, parse_prefix}; +use crate::sys::path::{HAS_PREFIXES, is_sep_byte, is_verbatim_sep, parse_prefix}; use crate::{cmp, fmt, fs, io, sys}; //////////////////////////////////////////////////////////////////////////////// @@ -252,22 +266,33 @@ impl<'a> Prefix<'a> { /// ``` #[must_use] #[stable(feature = "rust1", since = "1.0.0")] -pub fn is_separator(c: char) -> bool { +#[rustc_const_unstable(feature = "const_path_separators", issue = "153106")] +pub const fn is_separator(c: char) -> bool { c.is_ascii() && is_sep_byte(c as u8) } -/// The primary separator of path components for the current platform. -/// -/// For example, `/` on Unix and `\` on Windows. +/// All path separators recognized on the current platform, represented as [`char`]s; for example, +/// this is `&['/'][..]` on Unix and `&['\\', '/'][..]` on Windows. The [primary +/// separator](MAIN_SEPARATOR) is always element 0 of the slice. +#[unstable(feature = "const_path_separators", issue = "153106")] +pub const SEPARATORS: &[char] = crate::sys::path::SEPARATORS; + +/// All path separators recognized on the current platform, represented as [`&str`]s; for example, +/// this is `&["/"][..]` on Unix and `&["\\", "/"][..]` on Windows. The [primary +/// separator](MAIN_SEPARATOR_STR) is always element 0 of the slice. +#[unstable(feature = "const_path_separators", issue = "153106")] +pub const SEPARATORS_STR: &[&str] = crate::sys::path::SEPARATORS_STR; + +/// The primary separator of path components for the current platform, represented as a [`char`]; +/// for example, this is `'/'` on Unix and `'\\'` on Windows. #[stable(feature = "rust1", since = "1.0.0")] #[cfg_attr(not(test), rustc_diagnostic_item = "path_main_separator")] -pub const MAIN_SEPARATOR: char = crate::sys::path::MAIN_SEP; +pub const MAIN_SEPARATOR: char = SEPARATORS[0]; -/// The primary separator of path components for the current platform. -/// -/// For example, `/` on Unix and `\` on Windows. +/// The primary separator of path components for the current platform, represented as a [`&str`]; +/// for example, this is `"/"` on Unix and `"\\"` on Windows. #[stable(feature = "main_separator_str", since = "1.68.0")] -pub const MAIN_SEPARATOR_STR: &str = crate::sys::path::MAIN_SEP_STR; +pub const MAIN_SEPARATOR_STR: &str = SEPARATORS_STR[0]; //////////////////////////////////////////////////////////////////////////////// // Misc helpers @@ -548,7 +573,7 @@ impl<'a> Component<'a> { pub fn as_os_str(self) -> &'a OsStr { match self { Component::Prefix(p) => p.as_os_str(), - Component::RootDir => OsStr::new(MAIN_SEP_STR), + Component::RootDir => OsStr::new(MAIN_SEPARATOR_STR), Component::CurDir => OsStr::new("."), Component::ParentDir => OsStr::new(".."), Component::Normal(path) => path, @@ -1339,7 +1364,7 @@ impl PathBuf { // absolute `path` replaces `self` if need_clear { - self.inner.truncate(0); + self.inner.clear(); // verbatim paths need . and .. removed } else if comps.prefix_verbatim() && !path.inner.is_empty() { @@ -1365,7 +1390,7 @@ impl PathBuf { for c in buf { if need_sep && c != Component::RootDir { - res.push(MAIN_SEP_STR); + res.push(MAIN_SEPARATOR_STR); } res.push(c.as_os_str()); @@ -1388,7 +1413,7 @@ impl PathBuf { // `path` is a pure relative path } else if need_sep { - self.inner.push(MAIN_SEP_STR); + self.inner.push(MAIN_SEPARATOR_STR); } self.inner.push(path); @@ -2700,6 +2725,41 @@ impl Path { self._strip_prefix(base.as_ref()) } + /// Returns a path with the optional prefix removed. + /// + /// If `base` is not a prefix of `self` (i.e., [`starts_with`] returns `false`), returns the original path (`self`) + /// + /// [`starts_with`]: Path::starts_with + /// + /// # Examples + /// + /// ``` + /// #![feature(trim_prefix_suffix)] + /// use std::path::Path; + /// + /// let path = Path::new("/test/haha/foo.txt"); + /// + /// // Prefix present - remove it + /// assert_eq!(path.trim_prefix("/"), Path::new("test/haha/foo.txt")); + /// assert_eq!(path.trim_prefix("/test"), Path::new("haha/foo.txt")); + /// assert_eq!(path.trim_prefix("/test/"), Path::new("haha/foo.txt")); + /// assert_eq!(path.trim_prefix("/test/haha/foo.txt"), Path::new("")); + /// assert_eq!(path.trim_prefix("/test/haha/foo.txt/"), Path::new("")); + /// + /// // Prefix absent - return original + /// assert_eq!(path.trim_prefix("test"), path); + /// assert_eq!(path.trim_prefix("/te"), path); + /// assert_eq!(path.trim_prefix("/haha"), path); + /// ``` + #[must_use = "this returns the remaining path as a new path, without modifying the original"] + #[unstable(feature = "trim_prefix_suffix", issue = "142312")] + pub fn trim_prefix

(&self, base: P) -> &Path + where + P: AsRef, + { + self._strip_prefix(base.as_ref()).unwrap_or(self) + } + fn _strip_prefix(&self, base: &Path) -> Result<&Path, StripPrefixError> { iter_after(self.components(), base.components()) .map(|c| c.as_path()) @@ -3294,6 +3354,34 @@ impl Path { fs::canonicalize(self) } + /// Makes the path absolute without accessing the filesystem. + /// + /// This is an alias to [`path::absolute`](absolute). + /// + /// # Errors + /// + /// This function may return an error in the following situations: + /// + /// * If the path is syntactically invalid; in particular, if it is empty. + /// * If getting the [current directory][crate::env::current_dir] fails. + /// + /// # Examples + /// + /// ```no_run + /// #![feature(path_absolute_method)] + /// use std::path::Path; + /// + /// let path = Path::new("foo/./bar"); + /// let absolute = path.absolute()?; + /// assert!(absolute.is_absolute()); + /// # Ok::<(), std::io::Error>(()) + /// ``` + #[unstable(feature = "path_absolute_method", issue = "153328")] + #[inline] + pub fn absolute(&self) -> io::Result { + absolute(self) + } + /// Normalize a path, including `..` without traversing the filesystem. /// /// Returns an error if normalization would leave leading `..` components. @@ -3827,9 +3915,9 @@ impl<'a> IntoIterator for &'a Path { } macro_rules! impl_cmp { - (<$($life:lifetime),*> $lhs:ty, $rhs: ty) => { + ($lhs:ty, $rhs: ty) => { #[stable(feature = "partialeq_path", since = "1.6.0")] - impl<$($life),*> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { ::eq(self, other) @@ -3837,7 +3925,7 @@ macro_rules! impl_cmp { } #[stable(feature = "partialeq_path", since = "1.6.0")] - impl<$($life),*> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { ::eq(self, other) @@ -3845,7 +3933,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { ::partial_cmp(self, other) @@ -3853,7 +3941,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { ::partial_cmp(self, other) @@ -3862,16 +3950,16 @@ macro_rules! impl_cmp { }; } -impl_cmp!(<> PathBuf, Path); -impl_cmp!(<'a> PathBuf, &'a Path); -impl_cmp!(<'a> Cow<'a, Path>, Path); -impl_cmp!(<'a, 'b> Cow<'a, Path>, &'b Path); -impl_cmp!(<'a> Cow<'a, Path>, PathBuf); +impl_cmp!(PathBuf, Path); +impl_cmp!(PathBuf, &Path); +impl_cmp!(Cow<'_, Path>, Path); +impl_cmp!(Cow<'_, Path>, &Path); +impl_cmp!(Cow<'_, Path>, PathBuf); macro_rules! impl_cmp_os_str { - (<$($life:lifetime),*> $lhs:ty, $rhs: ty) => { + ($lhs:ty, $rhs: ty) => { #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { ::eq(self, other.as_ref()) @@ -3879,7 +3967,7 @@ macro_rules! impl_cmp_os_str { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { ::eq(self.as_ref(), other) @@ -3887,7 +3975,7 @@ macro_rules! impl_cmp_os_str { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { ::partial_cmp(self, other.as_ref()) @@ -3895,7 +3983,7 @@ macro_rules! impl_cmp_os_str { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { ::partial_cmp(self.as_ref(), other) @@ -3904,20 +3992,20 @@ macro_rules! impl_cmp_os_str { }; } -impl_cmp_os_str!(<> PathBuf, OsStr); -impl_cmp_os_str!(<'a> PathBuf, &'a OsStr); -impl_cmp_os_str!(<'a> PathBuf, Cow<'a, OsStr>); -impl_cmp_os_str!(<> PathBuf, OsString); -impl_cmp_os_str!(<> Path, OsStr); -impl_cmp_os_str!(<'a> Path, &'a OsStr); -impl_cmp_os_str!(<'a> Path, Cow<'a, OsStr>); -impl_cmp_os_str!(<> Path, OsString); -impl_cmp_os_str!(<'a> &'a Path, OsStr); -impl_cmp_os_str!(<'a, 'b> &'a Path, Cow<'b, OsStr>); -impl_cmp_os_str!(<'a> &'a Path, OsString); -impl_cmp_os_str!(<'a> Cow<'a, Path>, OsStr); -impl_cmp_os_str!(<'a, 'b> Cow<'a, Path>, &'b OsStr); -impl_cmp_os_str!(<'a> Cow<'a, Path>, OsString); +impl_cmp_os_str!(PathBuf, OsStr); +impl_cmp_os_str!(PathBuf, &OsStr); +impl_cmp_os_str!(PathBuf, Cow<'_, OsStr>); +impl_cmp_os_str!(PathBuf, OsString); +impl_cmp_os_str!(Path, OsStr); +impl_cmp_os_str!(Path, &OsStr); +impl_cmp_os_str!(Path, Cow<'_, OsStr>); +impl_cmp_os_str!(Path, OsString); +impl_cmp_os_str!(&Path, OsStr); +impl_cmp_os_str!(&Path, Cow<'_, OsStr>); +impl_cmp_os_str!(&Path, OsString); +impl_cmp_os_str!(Cow<'_, Path>, OsStr); +impl_cmp_os_str!(Cow<'_, Path>, &OsStr); +impl_cmp_os_str!(Cow<'_, Path>, OsString); #[stable(since = "1.7.0", feature = "strip_prefix")] impl fmt::Display for StripPrefixError { diff --git a/std/src/prelude/v1.rs b/std/src/prelude/v1.rs index af9d28ebad356..ee57e031c959c 100644 --- a/std/src/prelude/v1.rs +++ b/std/src/prelude/v1.rs @@ -79,7 +79,7 @@ mod ambiguous_macros_only { #[doc(no_inline)] pub use self::ambiguous_macros_only::{vec, panic}; -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "1.95.0")] #[doc(no_inline)] pub use core::prelude::v1::cfg_select; diff --git a/std/src/process.rs b/std/src/process.rs index 6838bb422b0e0..321b68b3225ad 100644 --- a/std/src/process.rs +++ b/std/src/process.rs @@ -156,6 +156,7 @@ target_env = "sgx", target_os = "xous", target_os = "trusty", + target_os = "hermit", )) ))] mod tests; @@ -1380,6 +1381,7 @@ impl Output { /// # Examples /// /// ``` + /// # #![allow(unused_features)] /// #![feature(exit_status_error)] /// # #[cfg(all(unix, not(target_os = "android"), not(all(target_vendor = "apple", not(target_os = "macos")))))] { /// use std::process::Command; @@ -1959,6 +1961,7 @@ impl crate::sealed::Sealed for ExitStatusError {} pub struct ExitStatusError(imp::ExitStatusError); #[unstable(feature = "exit_status_error", issue = "84908")] +#[doc(test(attr(allow(unused_features))))] impl ExitStatusError { /// Reports the exit code, if applicable, from an `ExitStatusError`. /// @@ -2464,7 +2467,7 @@ impl Child { #[cfg_attr(not(test), rustc_diagnostic_item = "process_exit")] pub fn exit(code: i32) -> ! { crate::rt::cleanup(); - crate::sys::os::exit(code) + crate::sys::exit::exit(code) } /// Terminates the process in an abnormal fashion. @@ -2545,7 +2548,7 @@ pub fn abort() -> ! { #[must_use] #[stable(feature = "getpid", since = "1.26.0")] pub fn id() -> u32 { - crate::sys::os::getpid() + imp::getpid() } /// A trait for implementing arbitrary return types in the `main` function. diff --git a/std/src/random.rs b/std/src/random.rs index 3994c5cfaf6f4..a18dcf98ec7fc 100644 --- a/std/src/random.rs +++ b/std/src/random.rs @@ -37,7 +37,7 @@ use crate::sys::random as sys; /// Horizon, Cygwin | `getrandom` /// AIX, Hurd, L4Re, QNX | `/dev/urandom` /// Redox | `/scheme/rand` -/// RTEMS | [`arc4random_buf`](https://docs.rtems.org/branches/master/bsp-howto/getentropy.html) +/// RTEMS | [`arc4random_buf`](https://docs.rtems.org/branches/main/bsp-howto/getentropy.html) /// SGX | [`rdrand`](https://en.wikipedia.org/wiki/RDRAND) /// SOLID | `SOLID_RNG_SampleRandomBytes` /// TEEOS | `TEE_GenerateRandom` diff --git a/std/src/rt.rs b/std/src/rt.rs index 11c0a0b9daf7b..1e7de695ddae7 100644 --- a/std/src/rt.rs +++ b/std/src/rt.rs @@ -187,7 +187,7 @@ fn lang_start_internal( cleanup(); // Guard against multiple threads calling `libc::exit` concurrently. // See the documentation for `unique_thread_exit` for more information. - crate::sys::exit_guard::unique_thread_exit(); + crate::sys::exit::unique_thread_exit(); ret_code }) diff --git a/std/src/sync/lazy_lock.rs b/std/src/sync/lazy_lock.rs index 7274b5d10c75b..9bdde0ae4a537 100644 --- a/std/src/sync/lazy_lock.rs +++ b/std/src/sync/lazy_lock.rs @@ -105,15 +105,6 @@ impl T> LazyLock { LazyLock { once: Once::new(), data: UnsafeCell::new(Data { f: ManuallyDrop::new(f) }) } } - /// Creates a new lazy value that is already initialized. - #[inline] - #[cfg(test)] - pub(crate) fn preinit(value: T) -> LazyLock { - let once = Once::new(); - once.call_once(|| {}); - LazyLock { once, data: UnsafeCell::new(Data { value: ManuallyDrop::new(value) }) } - } - /// Consumes this `LazyLock` returning the stored value. /// /// Returns `Ok(value)` if `Lazy` is initialized and `Err(f)` otherwise. @@ -404,6 +395,19 @@ impl fmt::Debug for LazyLock { } } +#[stable(feature = "from_wrapper_impls", since = "CURRENT_RUSTC_VERSION")] +impl From for LazyLock { + /// Constructs a `LazyLock` that starts already initialized + /// with the provided value. + #[inline] + fn from(value: T) -> Self { + LazyLock { + once: Once::new_complete(), + data: UnsafeCell::new(Data { value: ManuallyDrop::new(value) }), + } + } +} + #[cold] #[inline(never)] fn panic_poisoned() -> ! { diff --git a/std/src/sync/mpmc/mod.rs b/std/src/sync/mpmc/mod.rs index 8df81a580f7b8..16ae8a88370be 100644 --- a/std/src/sync/mpmc/mod.rs +++ b/std/src/sync/mpmc/mod.rs @@ -623,6 +623,33 @@ impl Sender { _ => false, } } + + /// Returns `true` if the channel is disconnected. + /// + /// Note that a return value of `false` does not guarantee the channel will + /// remain connected. The channel may be disconnected immediately after this method + /// returns, so a subsequent [`Sender::send`] may still fail with [`SendError`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(mpmc_channel)] + /// + /// use std::sync::mpmc::channel; + /// + /// let (tx, rx) = channel::(); + /// assert!(!tx.is_disconnected()); + /// drop(rx); + /// assert!(tx.is_disconnected()); + /// ``` + #[unstable(feature = "mpmc_channel", issue = "126840")] + pub fn is_disconnected(&self) -> bool { + match &self.flavor { + SenderFlavor::Array(chan) => chan.is_disconnected(), + SenderFlavor::List(chan) => chan.is_disconnected(), + SenderFlavor::Zero(chan) => chan.is_disconnected(), + } + } } #[unstable(feature = "mpmc_channel", issue = "126840")] @@ -1349,6 +1376,33 @@ impl Receiver { pub fn iter(&self) -> Iter<'_, T> { Iter { rx: self } } + + /// Returns `true` if the channel is disconnected. + /// + /// Note that a return value of `false` does not guarantee the channel will + /// remain connected. The channel may be disconnected immediately after this method + /// returns, so a subsequent [`Receiver::recv`] may still fail with [`RecvError`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(mpmc_channel)] + /// + /// use std::sync::mpmc::channel; + /// + /// let (tx, rx) = channel::(); + /// assert!(!rx.is_disconnected()); + /// drop(tx); + /// assert!(rx.is_disconnected()); + /// ``` + #[unstable(feature = "mpmc_channel", issue = "126840")] + pub fn is_disconnected(&self) -> bool { + match &self.flavor { + ReceiverFlavor::Array(chan) => chan.is_disconnected(), + ReceiverFlavor::List(chan) => chan.is_disconnected(), + ReceiverFlavor::Zero(chan) => chan.is_disconnected(), + } + } } #[unstable(feature = "mpmc_channel", issue = "126840")] diff --git a/std/src/sync/mpmc/zero.rs b/std/src/sync/mpmc/zero.rs index f1ecf80fcb9f6..c743462501922 100644 --- a/std/src/sync/mpmc/zero.rs +++ b/std/src/sync/mpmc/zero.rs @@ -316,4 +316,10 @@ impl Channel { pub(crate) fn is_full(&self) -> bool { true } + + /// Returns `true` if the channel is disconnected. + pub(crate) fn is_disconnected(&self) -> bool { + let inner = self.inner.lock().unwrap(); + inner.is_disconnected + } } diff --git a/std/src/sync/mpsc.rs b/std/src/sync/mpsc.rs index 0ae23f6e13bf2..a1c49bb83010c 100644 --- a/std/src/sync/mpsc.rs +++ b/std/src/sync/mpsc.rs @@ -607,6 +607,29 @@ impl Sender { pub fn send(&self, t: T) -> Result<(), SendError> { self.inner.send(t) } + + /// Returns `true` if the channel is disconnected. + /// + /// Note that a return value of `false` does not guarantee the channel will + /// remain connected. The channel may be disconnected immediately after this method + /// returns, so a subsequent [`Sender::send`] may still fail with [`SendError`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(mpsc_is_disconnected)] + /// + /// use std::sync::mpsc::channel; + /// + /// let (tx, rx) = channel::(); + /// assert!(!tx.is_disconnected()); + /// drop(rx); + /// assert!(tx.is_disconnected()); + /// ``` + #[unstable(feature = "mpsc_is_disconnected", issue = "153668")] + pub fn is_disconnected(&self) -> bool { + self.inner.is_disconnected() + } } #[stable(feature = "rust1", since = "1.0.0")] @@ -1038,6 +1061,29 @@ impl Receiver { pub fn try_iter(&self) -> TryIter<'_, T> { TryIter { rx: self } } + + /// Returns `true` if the channel is disconnected. + /// + /// Note that a return value of `false` does not guarantee the channel will + /// remain connected. The channel may be disconnected immediately after this method + /// returns, so a subsequent [`Receiver::recv`] may still fail with [`RecvError`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(mpsc_is_disconnected)] + /// + /// use std::sync::mpsc::channel; + /// + /// let (tx, rx) = channel::(); + /// assert!(!rx.is_disconnected()); + /// drop(tx); + /// assert!(rx.is_disconnected()); + /// ``` + #[unstable(feature = "mpsc_is_disconnected", issue = "153668")] + pub fn is_disconnected(&self) -> bool { + self.inner.is_disconnected() + } } #[stable(feature = "rust1", since = "1.0.0")] diff --git a/std/src/sync/once.rs b/std/src/sync/once.rs index bcfc9f581fd28..2556d1897b642 100644 --- a/std/src/sync/once.rs +++ b/std/src/sync/once.rs @@ -84,6 +84,13 @@ impl Once { Once { inner: sys::Once::new() } } + /// Creates a new `Once` value that starts already completed. + #[inline] + #[must_use] + pub(crate) const fn new_complete() -> Once { + Once { inner: sys::Once::new_complete() } + } + /// Performs an initialization routine once and only once. The given closure /// will be executed if this is the first time `call_once` has been called, /// and otherwise the routine will *not* be invoked. diff --git a/std/src/sync/poison/rwlock.rs b/std/src/sync/poison/rwlock.rs index acfeb96900cc9..c01ee17eecda3 100644 --- a/std/src/sync/poison/rwlock.rs +++ b/std/src/sync/poison/rwlock.rs @@ -56,24 +56,36 @@ use crate::sys::sync as sys; /// # Examples /// /// ``` -/// use std::sync::RwLock; +/// use std::sync::{Arc, RwLock}; +/// use std::thread; +/// use std::time::Duration; /// -/// let lock = RwLock::new(5); +/// let data = Arc::new(RwLock::new(5)); /// -/// // many reader locks can be held at once -/// { -/// let r1 = lock.read().unwrap(); -/// let r2 = lock.read().unwrap(); -/// assert_eq!(*r1, 5); -/// assert_eq!(*r2, 5); -/// } // read locks are dropped at this point +/// // Multiple readers can access in parallel. +/// for i in 0..3 { +/// let lock_clone = Arc::clone(&data); /// -/// // only one write lock may be held, however -/// { -/// let mut w = lock.write().unwrap(); -/// *w += 1; -/// assert_eq!(*w, 6); -/// } // write lock is dropped here +/// thread::spawn(move || { +/// let value = lock_clone.read().unwrap(); +/// +/// println!("Reader {}: Read value {}, now holding lock...", i, *value); +/// +/// // Simulating a long read operation +/// thread::sleep(Duration::from_secs(1)); +/// +/// println!("Reader {}: Dropping lock.", i); +/// // Read lock unlocked when going out of scope. +/// }); +/// } +/// +/// thread::sleep(Duration::from_millis(100)); // Wait for readers to start +/// +/// // While all readers can proceed, a call to .write() has to wait for +// // current active reader locks. +/// let mut writable_data = data.write().unwrap(); +/// println!("Writer proceeds..."); +/// *writable_data += 1; /// ``` /// /// [`Mutex`]: super::Mutex @@ -370,7 +382,8 @@ impl RwLock { /// /// # Panics /// - /// This function might panic when called if the lock is already held by the current thread. + /// This function might panic when called if the lock is already held by the current thread + /// in read or write mode. /// /// # Examples /// @@ -467,7 +480,8 @@ impl RwLock { /// /// # Panics /// - /// This function might panic when called if the lock is already held by the current thread. + /// This function might panic when called if the lock is already held by the current thread + /// in read or write mode. /// /// # Examples /// diff --git a/std/src/sys/args/uefi.rs b/std/src/sys/args/uefi.rs index 02dada382eff0..edf6f6873f8d2 100644 --- a/std/src/sys/args/uefi.rs +++ b/std/src/sys/args/uefi.rs @@ -93,7 +93,7 @@ fn parse_lp_cmd_line(code_units: &[u16]) -> Option> { // If not `in_quotes`, a space or tab ends the argument. SPACE if !in_quotes => { ret_val.push(OsString::from(&cur[..])); - cur.truncate(0); + cur.clear(); // Skip whitespace. while code_units_iter.next_if_eq(&Ok(SPACE)).is_some() {} diff --git a/std/src/sys/args/unix.rs b/std/src/sys/args/unix.rs index 0dfbd5f03eba9..7a592c2b079dd 100644 --- a/std/src/sys/args/unix.rs +++ b/std/src/sys/args/unix.rs @@ -164,7 +164,7 @@ mod imp { // of this used `[[NSProcessInfo processInfo] arguments]`. #[cfg(target_vendor = "apple")] mod imp { - use crate::ffi::{c_char, c_int}; + use crate::ffi::c_char; pub unsafe fn init(_argc: isize, _argv: *const *const u8) { // No need to initialize anything in here, `libdyld.dylib` has already @@ -172,12 +172,6 @@ mod imp { } pub fn argc_argv() -> (isize, *const *const c_char) { - unsafe extern "C" { - // These functions are in crt_externs.h. - fn _NSGetArgc() -> *mut c_int; - fn _NSGetArgv() -> *mut *mut *mut c_char; - } - // SAFETY: The returned pointer points to a static initialized early // in the program lifetime by `libdyld.dylib`, and as such is always // valid. @@ -187,9 +181,9 @@ mod imp { // doesn't exist a lock that we can take. Instead, it is generally // expected that it's only modified in `main` / before other code // runs, so reading this here should be fine. - let argc = unsafe { _NSGetArgc().read() }; + let argc = unsafe { libc::_NSGetArgc().read() }; // SAFETY: Same as above. - let argv = unsafe { _NSGetArgv().read() }; + let argv = unsafe { libc::_NSGetArgv().read() }; // Cast from `*mut *mut c_char` to `*const *const c_char` (argc as isize, argv.cast()) diff --git a/std/src/sys/args/windows.rs b/std/src/sys/args/windows.rs index c1988657ff1b1..bd26db7fea553 100644 --- a/std/src/sys/args/windows.rs +++ b/std/src/sys/args/windows.rs @@ -12,9 +12,9 @@ use crate::num::NonZero; use crate::os::windows::prelude::*; use crate::path::{Path, PathBuf}; use crate::sys::helpers::WStrUnits; -use crate::sys::pal::os::current_exe; use crate::sys::pal::{ensure_no_nuls, fill_utf16_buf}; use crate::sys::path::get_long_path; +use crate::sys::paths::current_exe; use crate::sys::{AsInner, c, to_u16s}; use crate::{io, iter, ptr}; @@ -106,7 +106,7 @@ fn parse_lp_cmd_line<'a, F: Fn() -> OsString>( // If not `in_quotes`, a space or tab ends the argument. SPACE | TAB if !in_quotes => { ret_val.push(OsString::from_wide(&cur[..])); - cur.truncate(0); + cur.clear(); // Skip whitespace. code_units.advance_while(|w| w == SPACE || w == TAB); diff --git a/std/src/sys/args/xous.rs b/std/src/sys/args/xous.rs index 2010bad14d1fb..9025ed4f1354c 100644 --- a/std/src/sys/args/xous.rs +++ b/std/src/sys/args/xous.rs @@ -1,9 +1,8 @@ pub use super::common::Args; -use crate::sys::pal::os::get_application_parameters; -use crate::sys::pal::os::params::ArgumentList; +use crate::sys::pal::params::{self, ArgumentList}; pub fn args() -> Args { - let Some(params) = get_application_parameters() else { + let Some(params) = params::get() else { return Args::new(vec![]); }; diff --git a/std/src/sys/env/uefi.rs b/std/src/sys/env/uefi.rs index af16a02642a4c..bc2aed4231797 100644 --- a/std/src/sys/env/uefi.rs +++ b/std/src/sys/env/uefi.rs @@ -43,7 +43,20 @@ mod uefi_env { pub(crate) fn unset(key: &OsStr) -> io::Result<()> { let mut key_ptr = helpers::os_string_to_raw(key) .ok_or(io::const_error!(io::ErrorKind::InvalidInput, "invalid key"))?; - unsafe { set_raw(key_ptr.as_mut_ptr(), crate::ptr::null_mut()) } + let r = unsafe { set_raw(key_ptr.as_mut_ptr(), crate::ptr::null_mut()) }; + + // The UEFI Shell spec only lists `EFI_SUCCESS` as a possible return value for + // `SetEnv`, but the edk2 implementation can return errors. Allow most of these + // errors to bubble up to the caller, but ignore `NotFound` errors; deleting a + // nonexistent variable is not listed as an error condition of + // `std::env::remove_var`. + if let Err(err) = &r + && err.kind() == io::ErrorKind::NotFound + { + Ok(()) + } else { + r + } } pub(crate) fn get_all() -> io::Result> { diff --git a/std/src/sys/env/unix.rs b/std/src/sys/env/unix.rs index 66805ce3fa71e..7a19f97b3ad50 100644 --- a/std/src/sys/env/unix.rs +++ b/std/src/sys/env/unix.rs @@ -38,8 +38,25 @@ pub unsafe fn environ() -> *mut *const *const c_char { unsafe { libc::_NSGetEnviron() as *mut *const *const c_char } } +// On FreeBSD, environ comes from CRT rather than libc +#[cfg(target_os = "freebsd")] +pub unsafe fn environ() -> *mut *const *const c_char { + use crate::sync::LazyLock; + + struct Environ(*mut *const *const c_char); + unsafe impl Send for Environ {} + unsafe impl Sync for Environ {} + + static ENVIRON: LazyLock = LazyLock::new(|| { + Environ(unsafe { + libc::dlsym(libc::RTLD_DEFAULT, c"environ".as_ptr()) as *mut *const *const c_char + }) + }); + ENVIRON.0 +} + // Use the `environ` static which is part of POSIX. -#[cfg(not(target_vendor = "apple"))] +#[cfg(not(any(target_os = "freebsd", target_vendor = "apple")))] pub unsafe fn environ() -> *mut *const *const c_char { unsafe extern "C" { static mut environ: *const *const c_char; diff --git a/std/src/sys/env/wasi.rs b/std/src/sys/env/wasi.rs index c970aac182604..6b892376fd0cf 100644 --- a/std/src/sys/env/wasi.rs +++ b/std/src/sys/env/wasi.rs @@ -1,11 +1,16 @@ use core::slice::memchr; pub use super::common::Env; -use crate::ffi::{CStr, OsStr, OsString}; +use crate::ffi::{CStr, OsStr, OsString, c_char}; use crate::io; use crate::os::wasi::prelude::*; use crate::sys::helpers::run_with_cstr; -use crate::sys::pal::os::{cvt, libc}; +use crate::sys::pal::cvt; + +// This is not available yet in libc. +unsafe extern "C" { + fn __wasilibc_get_environ() -> *mut *mut c_char; +} cfg_select! { target_feature = "atomics" => { @@ -37,7 +42,7 @@ pub fn env() -> Env { // Use `__wasilibc_get_environ` instead of `environ` here so that we // don't require wasi-libc to eagerly initialize the environment // variables. - let mut environ = libc::__wasilibc_get_environ(); + let mut environ = __wasilibc_get_environ(); let mut result = Vec::new(); if !environ.is_null() { diff --git a/std/src/sys/env/xous.rs b/std/src/sys/env/xous.rs index 8f65f30d35fcc..f576cfa0025a1 100644 --- a/std/src/sys/env/xous.rs +++ b/std/src/sys/env/xous.rs @@ -2,21 +2,19 @@ pub use super::common::Env; use crate::collections::HashMap; use crate::ffi::{OsStr, OsString}; use crate::io; -use crate::sync::atomic::{Atomic, AtomicUsize, Ordering}; -use crate::sync::{Mutex, Once}; -use crate::sys::pal::os::{get_application_parameters, params}; +use crate::sync::{Mutex, OnceLock}; +use crate::sys::pal::params; -static ENV: Atomic = AtomicUsize::new(0); -static ENV_INIT: Once = Once::new(); type EnvStore = Mutex>; +static ENV: OnceLock = OnceLock::new(); + fn get_env_store() -> &'static EnvStore { - ENV_INIT.call_once(|| { - let env_store = EnvStore::default(); - if let Some(params) = get_application_parameters() { + ENV.get_or_init(|| { + let mut env_store = HashMap::new(); + if let Some(params) = params::get() { for param in params { if let Ok(envs) = params::EnvironmentBlock::try_from(¶m) { - let mut env_store = env_store.lock().unwrap(); for env in envs { env_store.insert(env.key.into(), env.value.into()); } @@ -24,17 +22,12 @@ fn get_env_store() -> &'static EnvStore { } } } - ENV.store(Box::into_raw(Box::new(env_store)) as _, Ordering::Relaxed) - }); - unsafe { &*core::ptr::with_exposed_provenance::(ENV.load(Ordering::Relaxed)) } + Mutex::new(env_store) + }) } pub fn env() -> Env { - let clone_to_vec = |map: &HashMap| -> Vec<_> { - map.iter().map(|(k, v)| (k.clone(), v.clone())).collect() - }; - - let env = clone_to_vec(&*get_env_store().lock().unwrap()); + let env = get_env_store().lock().unwrap().iter().map(|(k, v)| (k.clone(), v.clone())).collect(); Env::new(env) } diff --git a/std/src/sys/exit_guard.rs b/std/src/sys/exit.rs similarity index 60% rename from std/src/sys/exit_guard.rs rename to std/src/sys/exit.rs index e7d7a478a5baa..53fb92ba077e0 100644 --- a/std/src/sys/exit_guard.rs +++ b/std/src/sys/exit.rs @@ -19,8 +19,7 @@ cfg_select! { /// * If it is called again on the same thread as the first call, it will abort. /// * If it is called again on a different thread, it will wait in a loop /// (waiting for the process to exit). - #[cfg_attr(any(test, doctest), allow(dead_code))] - pub(crate) fn unique_thread_exit() { + pub fn unique_thread_exit() { use crate::ffi::c_int; use crate::ptr; use crate::sync::atomic::AtomicPtr; @@ -62,9 +61,83 @@ cfg_select! { /// /// Mitigation is ***NOT*** implemented on this platform, either because this platform /// is not affected, or because mitigation is not yet implemented for this platform. - #[cfg_attr(any(test, doctest), allow(dead_code))] - pub(crate) fn unique_thread_exit() { + #[cfg_attr(any(test, doctest), expect(dead_code))] + pub fn unique_thread_exit() { // Mitigation not required on platforms where `exit` is thread-safe. } } } + +pub fn exit(code: i32) -> ! { + cfg_select! { + target_os = "hermit" => { + unsafe { hermit_abi::exit(code) } + } + target_os = "linux" => { + unsafe { + unique_thread_exit(); + libc::exit(code) + } + } + target_os = "motor" => { + moto_rt::process::exit(code) + } + all(target_vendor = "fortanix", target_env = "sgx") => { + crate::sys::pal::abi::exit_with_code(code as _) + } + target_os = "solid_asp3" => { + rtabort!("exit({}) called", code) + } + target_os = "teeos" => { + let _ = code; + panic!("TA should not call `exit`") + } + target_os = "uefi" => { + use r_efi::base::Status; + + use crate::os::uefi::env; + + if let (Some(boot_services), Some(handle)) = + (env::boot_services(), env::try_image_handle()) + { + let boot_services = boot_services.cast::(); + let _ = unsafe { + ((*boot_services.as_ptr()).exit)( + handle.as_ptr(), + Status::from_usize(code as usize), + 0, + crate::ptr::null_mut(), + ) + }; + } + crate::intrinsics::abort() + } + any( + target_family = "unix", + target_os = "wasi", + ) => { + unsafe { libc::exit(code as crate::ffi::c_int) } + } + target_os = "vexos" => { + let _ = code; + + unsafe { + vex_sdk::vexSystemExitRequest(); + + loop { + vex_sdk::vexTasksRun(); + } + } + } + target_os = "windows" => { + unsafe { crate::sys::pal::c::ExitProcess(code as u32) } + } + target_os = "xous" => { + crate::os::xous::ffi::exit(code as u32) + } + _ => { + let _ = code; + crate::intrinsics::abort() + } + } +} diff --git a/std/src/sys/fs/hermit.rs b/std/src/sys/fs/hermit.rs index 1e281eb0d9d18..5992766b5a42d 100644 --- a/std/src/sys/fs/hermit.rs +++ b/std/src/sys/fs/hermit.rs @@ -109,15 +109,15 @@ pub struct DirBuilder { impl FileAttr { pub fn modified(&self) -> io::Result { - Ok(SystemTime::new(self.stat_val.st_mtim.tv_sec, self.stat_val.st_mtim.tv_nsec)) + SystemTime::new(self.stat_val.st_mtim.tv_sec, self.stat_val.st_mtim.tv_nsec.into()) } pub fn accessed(&self) -> io::Result { - Ok(SystemTime::new(self.stat_val.st_atim.tv_sec, self.stat_val.st_atim.tv_nsec)) + SystemTime::new(self.stat_val.st_atim.tv_sec, self.stat_val.st_atim.tv_nsec.into()) } pub fn created(&self) -> io::Result { - Ok(SystemTime::new(self.stat_val.st_ctim.tv_sec, self.stat_val.st_ctim.tv_nsec)) + SystemTime::new(self.stat_val.st_ctim.tv_sec, self.stat_val.st_ctim.tv_nsec.into()) } pub fn size(&self) -> u64 { diff --git a/std/src/sys/fs/unix.rs b/std/src/sys/fs/unix.rs index 3ca84db0f47fc..9b0ef5539d32b 100644 --- a/std/src/sys/fs/unix.rs +++ b/std/src/sys/fs/unix.rs @@ -634,7 +634,7 @@ impl FileAttr { } #[cfg(any( - target_os = "vxworks", + all(target_os = "vxworks", vxworks_lt_25_09), target_os = "espidf", target_os = "vita", target_os = "rtems", @@ -643,7 +643,12 @@ impl FileAttr { SystemTime::new(self.stat.st_mtime as i64, 0) } - #[cfg(any(target_os = "horizon", target_os = "hurd", target_os = "nuttx"))] + #[cfg(any( + target_os = "horizon", + target_os = "hurd", + target_os = "nuttx", + all(target_os = "vxworks", not(vxworks_lt_25_09)) + ))] pub fn modified(&self) -> io::Result { SystemTime::new(self.stat.st_mtim.tv_sec as i64, self.stat.st_mtim.tv_nsec as i64) } @@ -669,7 +674,7 @@ impl FileAttr { } #[cfg(any( - target_os = "vxworks", + all(target_os = "vxworks", vxworks_lt_25_09), target_os = "espidf", target_os = "vita", target_os = "rtems" @@ -678,7 +683,12 @@ impl FileAttr { SystemTime::new(self.stat.st_atime as i64, 0) } - #[cfg(any(target_os = "horizon", target_os = "hurd", target_os = "nuttx"))] + #[cfg(any( + target_os = "horizon", + target_os = "hurd", + target_os = "nuttx", + all(target_os = "vxworks", not(vxworks_lt_25_09)) + ))] pub fn accessed(&self) -> io::Result { SystemTime::new(self.stat.st_atim.tv_sec as i64, self.stat.st_atim.tv_nsec as i64) } @@ -1862,7 +1872,12 @@ fn file_time_to_timespec(time: Option) -> io::Result io::ErrorKind::InvalidInput, "timestamp is too small to set as a file time", )), - None => Ok(libc::timespec { tv_sec: 0, tv_nsec: libc::UTIME_OMIT as _ }), + None => Ok({ + let mut ts = libc::timespec::default(); + ts.tv_sec = 0; + ts.tv_nsec = libc::UTIME_OMIT as _; + ts + }), } } @@ -2132,9 +2147,6 @@ pub fn link(original: &CStr, link: &CStr) -> io::Result<()> { // Android has `linkat` on newer versions, but we happen to know // `link` always has the correct behavior, so it's here as well. target_os = "android", - // wasi-sdk-29-and-prior have a buggy `linkat` so use `link` instead - // until wasi-sdk is updated (see WebAssembly/wasi-libc#690) - target_os = "wasi", // Other misc platforms target_os = "horizon", target_os = "vita", diff --git a/std/src/sys/fs/vexos.rs b/std/src/sys/fs/vexos.rs index 81083a4fa81d3..5f75bcd92421b 100644 --- a/std/src/sys/fs/vexos.rs +++ b/std/src/sys/fs/vexos.rs @@ -12,8 +12,8 @@ use crate::sys::{unsupported, unsupported_err}; #[path = "unsupported.rs"] mod unsupported_fs; pub use unsupported_fs::{ - DirBuilder, FileTimes, canonicalize, link, readlink, remove_dir_all, rename, rmdir, symlink, - unlink, + Dir, DirBuilder, FileTimes, canonicalize, link, readlink, remove_dir_all, rename, rmdir, + symlink, unlink, }; /// VEXos file descriptor. diff --git a/std/src/sys/io/error/windows.rs b/std/src/sys/io/error/windows.rs index d7607082a30a0..c093443f30339 100644 --- a/std/src/sys/io/error/windows.rs +++ b/std/src/sys/io/error/windows.rs @@ -1,6 +1,9 @@ use crate::sys::pal::{api, c}; use crate::{io, ptr}; +#[cfg(test)] +mod tests; + pub fn errno() -> i32 { api::get_last_error().code as i32 } diff --git a/std/src/sys/pal/windows/os/tests.rs b/std/src/sys/io/error/windows/tests.rs similarity index 93% rename from std/src/sys/pal/windows/os/tests.rs rename to std/src/sys/io/error/windows/tests.rs index 458d6e11c2098..7fc545ad00666 100644 --- a/std/src/sys/pal/windows/os/tests.rs +++ b/std/src/sys/io/error/windows/tests.rs @@ -1,5 +1,5 @@ use crate::io::Error; -use crate::sys::c; +use crate::sys::pal::c; // tests `error_string` above #[test] diff --git a/std/src/sys/mod.rs b/std/src/sys/mod.rs index 5436c144d3330..fe0c103952414 100644 --- a/std/src/sys/mod.rs +++ b/std/src/sys/mod.rs @@ -11,13 +11,14 @@ pub mod backtrace; pub mod cmath; pub mod env; pub mod env_consts; -pub mod exit_guard; +pub mod exit; pub mod fd; pub mod fs; pub mod io; pub mod net; pub mod os_str; pub mod path; +pub mod paths; pub mod pipe; pub mod platform_version; pub mod process; diff --git a/std/src/sys/net/connection/sgx.rs b/std/src/sys/net/connection/sgx.rs index 8c9c17d3f1714..6a625664494b5 100644 --- a/std/src/sys/net/connection/sgx.rs +++ b/std/src/sys/net/connection/sgx.rs @@ -68,8 +68,8 @@ impl fmt::Debug for TcpStream { /// /// SGX doesn't support DNS resolution but rather accepts hostnames in /// the same place as socket addresses. So, to make e.g. -/// ```rust -/// TcpStream::connect("example.com:80")` +/// ```rust,ignore (incomplete example) +/// TcpStream::connect("example.com:80") /// ``` /// work, the DNS lookup returns a special error (`NonIpSockAddr`) instead, /// which contains the hostname being looked up. When `.to_socket_addrs()` diff --git a/std/src/sys/net/connection/socket/unix.rs b/std/src/sys/net/connection/socket/unix.rs index 5e20c0ffdfa6a..f3c860804de03 100644 --- a/std/src/sys/net/connection/socket/unix.rs +++ b/std/src/sys/net/connection/socket/unix.rs @@ -684,7 +684,7 @@ fn on_resolver_failure() { use crate::sys; // If the version fails to parse, we treat it the same as "not glibc". - if let Some(version) = sys::os::glibc_version() { + if let Some(version) = sys::pal::conf::glibc_version() { if version < (2, 26) { unsafe { libc::res_init() }; } diff --git a/std/src/sys/net/connection/uefi/tcp.rs b/std/src/sys/net/connection/uefi/tcp.rs index 1e58db0d70468..85962ce880d55 100644 --- a/std/src/sys/net/connection/uefi/tcp.rs +++ b/std/src/sys/net/connection/uefi/tcp.rs @@ -9,7 +9,9 @@ pub(crate) enum Tcp { V4(tcp4::Tcp4), } -// SAFETY: UEFI has no threads. +// SAFETY: UEFI has no regular threads, and as per +// std does not support being invoked from "irregular threads" such as interrupt handlers or other +// CPU cores that run outside the scope of UEFI. unsafe impl Send for Tcp {} impl Tcp { diff --git a/std/src/sys/pal/hermit/mod.rs b/std/src/sys/pal/hermit/mod.rs index db64f8d882e24..53f6ddd7065d7 100644 --- a/std/src/sys/pal/hermit/mod.rs +++ b/std/src/sys/pal/hermit/mod.rs @@ -1,7 +1,7 @@ -//! System bindings for HermitCore +//! System bindings for Hermit //! //! This module contains the facade (aka platform-specific) implementations of -//! OS level functionality for HermitCore. +//! OS level functionality for Hermit. //! //! This is all super highly experimental and not actually intended for //! wide/production use yet, it's still all in the experimental category. This @@ -22,7 +22,7 @@ use crate::os::raw::c_char; use crate::sys::env; pub mod futex; -pub mod os; +#[path = "../unix/time.rs"] pub mod time; pub fn unsupported() -> io::Result { @@ -30,7 +30,7 @@ pub fn unsupported() -> io::Result { } pub fn unsupported_err() -> io::Error { - io::const_error!(io::ErrorKind::Unsupported, "operation not supported on HermitCore yet") + io::const_error!(io::ErrorKind::Unsupported, "operation not supported on Hermit yet") } pub fn abort_internal() -> ! { diff --git a/std/src/sys/pal/hermit/os.rs b/std/src/sys/pal/hermit/os.rs deleted file mode 100644 index 48a7cdcd2f763..0000000000000 --- a/std/src/sys/pal/hermit/os.rs +++ /dev/null @@ -1,66 +0,0 @@ -use super::hermit_abi; -use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::path::{self, PathBuf}; -use crate::sys::unsupported; -use crate::{fmt, io}; - -pub fn getcwd() -> io::Result { - Ok(PathBuf::from("/")) -} - -pub fn chdir(_: &path::Path) -> io::Result<()> { - unsupported() -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on hermit yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -pub fn temp_dir() -> PathBuf { - PathBuf::from("/tmp") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(code: i32) -> ! { - unsafe { hermit_abi::exit(code) } -} - -pub fn getpid() -> u32 { - unsafe { hermit_abi::getpid() as u32 } -} diff --git a/std/src/sys/pal/hermit/time.rs b/std/src/sys/pal/hermit/time.rs deleted file mode 100644 index b9851eb6754d6..0000000000000 --- a/std/src/sys/pal/hermit/time.rs +++ /dev/null @@ -1,110 +0,0 @@ -use hermit_abi::{self, timespec}; - -use crate::cmp::Ordering; -use crate::hash::{Hash, Hasher}; -use crate::time::Duration; - -const NSEC_PER_SEC: i32 = 1_000_000_000; - -#[derive(Copy, Clone, Debug)] -pub struct Timespec { - pub t: timespec, -} - -impl Timespec { - pub const MAX: Timespec = Self::new(i64::MAX, 1_000_000_000 - 1); - - pub const MIN: Timespec = Self::new(i64::MIN, 0); - - pub const fn zero() -> Timespec { - Timespec { t: timespec { tv_sec: 0, tv_nsec: 0 } } - } - - pub const fn new(tv_sec: i64, tv_nsec: i32) -> Timespec { - assert!(tv_nsec >= 0 && tv_nsec < NSEC_PER_SEC); - // SAFETY: The assert above checks tv_nsec is within the valid range - Timespec { t: timespec { tv_sec, tv_nsec } } - } - - pub fn sub_timespec(&self, other: &Timespec) -> Result { - fn sub_ge_to_unsigned(a: i64, b: i64) -> u64 { - debug_assert!(a >= b); - a.wrapping_sub(b).cast_unsigned() - } - - if self >= other { - // Logic here is identical to Unix version of `Timestamp::sub_timespec`, - // check comments there why operations do not overflow. - Ok(if self.t.tv_nsec >= other.t.tv_nsec { - Duration::new( - sub_ge_to_unsigned(self.t.tv_sec, other.t.tv_sec), - (self.t.tv_nsec - other.t.tv_nsec) as u32, - ) - } else { - Duration::new( - sub_ge_to_unsigned(self.t.tv_sec - 1, other.t.tv_sec), - (self.t.tv_nsec + NSEC_PER_SEC - other.t.tv_nsec) as u32, - ) - }) - } else { - match other.sub_timespec(self) { - Ok(d) => Err(d), - Err(d) => Ok(d), - } - } - } - - pub fn checked_add_duration(&self, other: &Duration) -> Option { - let mut secs = self.t.tv_sec.checked_add_unsigned(other.as_secs())?; - - // Nano calculations can't overflow because nanos are <1B which fit - // in a u32. - let mut nsec = other.subsec_nanos() + u32::try_from(self.t.tv_nsec).unwrap(); - if nsec >= NSEC_PER_SEC.try_into().unwrap() { - nsec -= u32::try_from(NSEC_PER_SEC).unwrap(); - secs = secs.checked_add(1)?; - } - Some(Timespec { t: timespec { tv_sec: secs, tv_nsec: nsec as _ } }) - } - - pub fn checked_sub_duration(&self, other: &Duration) -> Option { - let mut secs = self.t.tv_sec.checked_sub_unsigned(other.as_secs())?; - - // Similar to above, nanos can't overflow. - let mut nsec = self.t.tv_nsec as i32 - other.subsec_nanos() as i32; - if nsec < 0 { - nsec += NSEC_PER_SEC as i32; - secs = secs.checked_sub(1)?; - } - Some(Timespec { t: timespec { tv_sec: secs, tv_nsec: nsec as _ } }) - } -} - -impl PartialEq for Timespec { - fn eq(&self, other: &Timespec) -> bool { - self.t.tv_sec == other.t.tv_sec && self.t.tv_nsec == other.t.tv_nsec - } -} - -impl Eq for Timespec {} - -impl PartialOrd for Timespec { - fn partial_cmp(&self, other: &Timespec) -> Option { - Some(self.cmp(other)) - } -} - -impl Ord for Timespec { - fn cmp(&self, other: &Timespec) -> Ordering { - let me = (self.t.tv_sec, self.t.tv_nsec); - let other = (other.t.tv_sec, other.t.tv_nsec); - me.cmp(&other) - } -} - -impl Hash for Timespec { - fn hash(&self, state: &mut H) { - self.t.tv_sec.hash(state); - self.t.tv_nsec.hash(state); - } -} diff --git a/std/src/sys/pal/motor/mod.rs b/std/src/sys/pal/motor/mod.rs index a520375a4bbff..705413cbe0a79 100644 --- a/std/src/sys/pal/motor/mod.rs +++ b/std/src/sys/pal/motor/mod.rs @@ -1,7 +1,5 @@ #![allow(unsafe_op_in_unsafe_fn)] -pub mod os; - pub use moto_rt::futex; use crate::io; diff --git a/std/src/sys/pal/motor/os.rs b/std/src/sys/pal/motor/os.rs deleted file mode 100644 index cdf66e3958dbe..0000000000000 --- a/std/src/sys/pal/motor/os.rs +++ /dev/null @@ -1,72 +0,0 @@ -use super::map_motor_error; -use crate::error::Error as StdError; -use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::os::motor::ffi::OsStrExt; -use crate::path::{self, PathBuf}; -use crate::{fmt, io}; - -pub fn getcwd() -> io::Result { - moto_rt::fs::getcwd().map(PathBuf::from).map_err(map_motor_error) -} - -pub fn chdir(path: &path::Path) -> io::Result<()> { - moto_rt::fs::chdir(path.as_os_str().as_str()).map_err(map_motor_error) -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on this platform yet".fmt(f) - } -} - -impl StdError for JoinPathsError { - #[allow(deprecated)] - fn description(&self) -> &str { - "not supported on this platform yet" - } -} - -pub fn current_exe() -> io::Result { - moto_rt::process::current_exe().map(PathBuf::from).map_err(map_motor_error) -} - -pub fn temp_dir() -> PathBuf { - PathBuf::from(moto_rt::fs::TEMP_DIR) -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(code: i32) -> ! { - moto_rt::process::exit(code) -} - -pub fn getpid() -> u32 { - panic!("Pids on Motor OS are u64.") -} diff --git a/std/src/sys/pal/sgx/abi/mod.rs b/std/src/sys/pal/sgx/abi/mod.rs index 1c6c681d4c179..3314f4f3b6223 100644 --- a/std/src/sys/pal/sgx/abi/mod.rs +++ b/std/src/sys/pal/sgx/abi/mod.rs @@ -96,7 +96,7 @@ extern "C" fn entry(p1: u64, p2: u64, p3: u64, secondary: bool, p4: u64, p5: u64 } } -pub(super) fn exit_with_code(code: isize) -> ! { +pub fn exit_with_code(code: isize) -> ! { if code != 0 { if let Some(mut out) = panic::SgxPanicOutput::new() { let _ = write!(out, "Exited with status code {code}"); diff --git a/std/src/sys/pal/sgx/abi/usercalls/alloc.rs b/std/src/sys/pal/sgx/abi/usercalls/alloc.rs index aaf380d1bef47..c2694316249a3 100644 --- a/std/src/sys/pal/sgx/abi/usercalls/alloc.rs +++ b/std/src/sys/pal/sgx/abi/usercalls/alloc.rs @@ -8,7 +8,6 @@ use crate::cell::UnsafeCell; use crate::convert::TryInto; use crate::mem::{self, ManuallyDrop, MaybeUninit}; use crate::ops::{CoerceUnsized, Deref, DerefMut, Index, IndexMut}; -use crate::pin::PinCoerceUnsized; use crate::ptr::{self, NonNull}; use crate::slice::SliceIndex; use crate::{cmp, intrinsics, slice}; @@ -773,9 +772,6 @@ where #[unstable(feature = "sgx_platform", issue = "56975")] impl, U> CoerceUnsized> for UserRef {} -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for UserRef {} - #[unstable(feature = "sgx_platform", issue = "56975")] impl Index for UserRef<[T]> where diff --git a/std/src/sys/pal/sgx/mod.rs b/std/src/sys/pal/sgx/mod.rs index 1de3ca4a5d79c..2b284cc40b94b 100644 --- a/std/src/sys/pal/sgx/mod.rs +++ b/std/src/sys/pal/sgx/mod.rs @@ -10,7 +10,6 @@ use crate::sync::atomic::{Atomic, AtomicBool, Ordering}; pub mod abi; mod libunwind_integration; -pub mod os; pub mod thread_parking; pub mod waitqueue; diff --git a/std/src/sys/pal/sgx/os.rs b/std/src/sys/pal/sgx/os.rs deleted file mode 100644 index ba47af7ff88d7..0000000000000 --- a/std/src/sys/pal/sgx/os.rs +++ /dev/null @@ -1,65 +0,0 @@ -use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::path::{self, PathBuf}; -use crate::sys::{sgx_ineffective, unsupported}; -use crate::{fmt, io}; - -pub fn getcwd() -> io::Result { - unsupported() -} - -pub fn chdir(_: &path::Path) -> io::Result<()> { - sgx_ineffective(()) -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported in SGX yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -pub fn temp_dir() -> PathBuf { - panic!("no filesystem in SGX") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(code: i32) -> ! { - super::abi::exit_with_code(code as _) -} - -pub fn getpid() -> u32 { - panic!("no pids in SGX") -} diff --git a/std/src/sys/pal/solid/error.rs b/std/src/sys/pal/solid/error.rs index 3e85cdb3c1d9f..a737abcc04eda 100644 --- a/std/src/sys/pal/solid/error.rs +++ b/std/src/sys/pal/solid/error.rs @@ -3,6 +3,14 @@ use super::{abi, itron}; use crate::io; use crate::sys::net; +// SOLID directly maps `errno`s to μITRON error codes. +impl SolidError { + #[inline] + pub(crate) fn as_io_error(self) -> crate::io::Error { + crate::io::Error::from_raw_os_error(self.as_raw()) + } +} + /// Describe the specified SOLID error code. Returns `None` if it's an /// undefined error code. /// diff --git a/std/src/sys/pal/solid/mod.rs b/std/src/sys/pal/solid/mod.rs index 1376af8304cf6..c3f9e47945901 100644 --- a/std/src/sys/pal/solid/mod.rs +++ b/std/src/sys/pal/solid/mod.rs @@ -19,7 +19,6 @@ pub mod itron { // `error` is `pub(crate)` so that it can be accessed by `itron/error.rs` as // `crate::sys::error` pub(crate) mod error; -pub mod os; pub use self::itron::thread_parking; // SAFETY: must be called only once during runtime initialization. diff --git a/std/src/sys/pal/solid/os.rs b/std/src/sys/pal/solid/os.rs deleted file mode 100644 index c336a1042da40..0000000000000 --- a/std/src/sys/pal/solid/os.rs +++ /dev/null @@ -1,72 +0,0 @@ -use super::{itron, unsupported}; -use crate::ffi::{OsStr, OsString}; -use crate::path::{self, PathBuf}; -use crate::{fmt, io}; - -// `solid` directly maps `errno`s to μITRON error codes. -impl itron::error::ItronError { - #[inline] - pub(crate) fn as_io_error(self) -> crate::io::Error { - crate::io::Error::from_raw_os_error(self.as_raw()) - } -} - -pub fn getcwd() -> io::Result { - unsupported() -} - -pub fn chdir(_: &path::Path) -> io::Result<()> { - unsupported() -} - -pub struct SplitPaths<'a>(&'a !); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - *self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on this platform yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -pub fn temp_dir() -> PathBuf { - panic!("no standard temporary directory on this platform") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(code: i32) -> ! { - rtabort!("exit({}) called", code); -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/std/src/sys/pal/teeos/conf.rs b/std/src/sys/pal/teeos/conf.rs new file mode 100644 index 0000000000000..1d13a283c458b --- /dev/null +++ b/std/src/sys/pal/teeos/conf.rs @@ -0,0 +1,5 @@ +// Hardcoded to return 4096, since `sysconf` is only implemented as a stub. +pub fn page_size() -> usize { + // unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize }; + 4096 +} diff --git a/std/src/sys/pal/teeos/mod.rs b/std/src/sys/pal/teeos/mod.rs index f76c26d3c966c..5caed277dbf59 100644 --- a/std/src/sys/pal/teeos/mod.rs +++ b/std/src/sys/pal/teeos/mod.rs @@ -6,7 +6,7 @@ #![allow(unused_variables)] #![allow(dead_code)] -pub mod os; +pub mod conf; #[path = "../unix/time.rs"] pub mod time; diff --git a/std/src/sys/pal/teeos/os.rs b/std/src/sys/pal/teeos/os.rs deleted file mode 100644 index a4b1d3c6ae670..0000000000000 --- a/std/src/sys/pal/teeos/os.rs +++ /dev/null @@ -1,76 +0,0 @@ -//! Implementation of `std::os` functionality for teeos - -use core::marker::PhantomData; - -use super::unsupported; -use crate::ffi::{OsStr, OsString}; -use crate::path::PathBuf; -use crate::{fmt, io, path}; - -// Hardcoded to return 4096, since `sysconf` is only implemented as a stub. -pub fn page_size() -> usize { - // unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize }; - 4096 -} - -// Everything below are stubs and copied from unsupported.rs - -pub fn getcwd() -> io::Result { - unsupported() -} - -pub fn chdir(_: &path::Path) -> io::Result<()> { - unsupported() -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on this platform yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -pub fn temp_dir() -> PathBuf { - panic!("no filesystem on this platform") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(_code: i32) -> ! { - panic!("TA should not call `exit`") -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/std/src/sys/pal/trusty/mod.rs b/std/src/sys/pal/trusty/mod.rs index b785c2dbb7892..ec2d938ed8367 100644 --- a/std/src/sys/pal/trusty/mod.rs +++ b/std/src/sys/pal/trusty/mod.rs @@ -3,7 +3,5 @@ #[path = "../unsupported/common.rs"] #[deny(unsafe_op_in_unsafe_fn)] mod common; -#[path = "../unsupported/os.rs"] -pub mod os; pub use common::*; diff --git a/std/src/sys/pal/uefi/mod.rs b/std/src/sys/pal/uefi/mod.rs index e4a8f50e4274d..67499d2c6f17c 100644 --- a/std/src/sys/pal/uefi/mod.rs +++ b/std/src/sys/pal/uefi/mod.rs @@ -14,7 +14,6 @@ #![forbid(unsafe_op_in_unsafe_fn)] pub mod helpers; -pub mod os; pub mod system_time; #[cfg(test)] diff --git a/std/src/sys/pal/unix/conf.rs b/std/src/sys/pal/unix/conf.rs new file mode 100644 index 0000000000000..a97173a1a35a1 --- /dev/null +++ b/std/src/sys/pal/unix/conf.rs @@ -0,0 +1,97 @@ +#[cfg(test)] +mod tests; + +#[cfg(not(target_os = "espidf"))] +pub fn page_size() -> usize { + unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize } +} + +/// Returns the value for [`confstr(key, ...)`][posix_confstr]. Currently only +/// used on Darwin, but should work on any unix (in case we need to get +/// `_CS_PATH` or `_CS_V[67]_ENV` in the future). +/// +/// [posix_confstr]: +/// https://pubs.opengroup.org/onlinepubs/9699919799/functions/confstr.html +// +// FIXME: Support `confstr` in Miri. +#[cfg(all(target_vendor = "apple", not(miri)))] +pub fn confstr( + key: crate::ffi::c_int, + size_hint: Option, +) -> crate::io::Result { + use crate::ffi::OsString; + use crate::io; + use crate::os::unix::ffi::OsStringExt; + + let mut buf: Vec = Vec::with_capacity(0); + let mut bytes_needed_including_nul = size_hint + .unwrap_or_else(|| { + // Treat "None" as "do an extra call to get the length". In theory + // we could move this into the loop below, but it's hard to do given + // that it isn't 100% clear if it's legal to pass 0 for `len` when + // the buffer isn't null. + unsafe { libc::confstr(key, core::ptr::null_mut(), 0) } + }) + .max(1); + // If the value returned by `confstr` is greater than the len passed into + // it, then the value was truncated, meaning we need to retry. Note that + // while `confstr` results don't seem to change for a process, it's unclear + // if this is guaranteed anywhere, so looping does seem required. + while bytes_needed_including_nul > buf.capacity() { + // We write into the spare capacity of `buf`. This lets us avoid + // changing buf's `len`, which both simplifies `reserve` computation, + // allows working with `Vec` instead of `Vec>`, and + // may avoid a copy, since the Vec knows that none of the bytes are needed + // when reallocating (well, in theory anyway). + buf.reserve(bytes_needed_including_nul); + // `confstr` returns + // - 0 in the case of errors: we break and return an error. + // - The number of bytes written, iff the provided buffer is enough to + // hold the entire value: we break and return the data in `buf`. + // - Otherwise, the number of bytes needed (including nul): we go + // through the loop again. + bytes_needed_including_nul = + unsafe { libc::confstr(key, buf.as_mut_ptr().cast(), buf.capacity()) }; + } + // `confstr` returns 0 in the case of an error. + if bytes_needed_including_nul == 0 { + return Err(io::Error::last_os_error()); + } + // Safety: `confstr(..., buf.as_mut_ptr(), buf.capacity())` returned a + // non-zero value, meaning `bytes_needed_including_nul` bytes were + // initialized. + unsafe { + buf.set_len(bytes_needed_including_nul); + // Remove the NUL-terminator. + let last_byte = buf.pop(); + // ... and smoke-check that it *was* a NUL-terminator. + assert_eq!(last_byte, Some(0), "`confstr` provided a string which wasn't nul-terminated"); + }; + Ok(OsString::from_vec(buf)) +} + +#[cfg(all(target_os = "linux", target_env = "gnu"))] +pub fn glibc_version() -> Option<(usize, usize)> { + use crate::ffi::CStr; + + unsafe extern "C" { + fn gnu_get_libc_version() -> *const libc::c_char; + } + let version_cstr = unsafe { CStr::from_ptr(gnu_get_libc_version()) }; + if let Ok(version_str) = version_cstr.to_str() { + parse_glibc_version(version_str) + } else { + None + } +} + +/// Returns Some((major, minor)) if the string is a valid "x.y" version, +/// ignoring any extra dot-separated parts. Otherwise return None. +#[cfg(all(target_os = "linux", target_env = "gnu"))] +fn parse_glibc_version(version: &str) -> Option<(usize, usize)> { + let mut parsed_ints = version.split('.').map(str::parse::).fuse(); + match (parsed_ints.next(), parsed_ints.next()) { + (Some(Ok(major)), Some(Ok(minor))) => Some((major, minor)), + _ => None, + } +} diff --git a/std/src/sys/pal/unix/os/tests.rs b/std/src/sys/pal/unix/conf/tests.rs similarity index 100% rename from std/src/sys/pal/unix/os/tests.rs rename to std/src/sys/pal/unix/conf/tests.rs diff --git a/std/src/sys/pal/unix/mod.rs b/std/src/sys/pal/unix/mod.rs index 6127bb98f80ef..0be150a0bfaa8 100644 --- a/std/src/sys/pal/unix/mod.rs +++ b/std/src/sys/pal/unix/mod.rs @@ -2,12 +2,12 @@ use crate::io; +pub mod conf; #[cfg(target_os = "fuchsia")] pub mod fuchsia; pub mod futex; #[cfg(target_os = "linux")] pub mod linux; -pub mod os; pub mod stack_overflow; pub mod sync; pub mod thread_parking; @@ -169,15 +169,15 @@ pub unsafe fn init(argc: isize, argv: *const *const u8, sigpipe: u8) { pub const SIG_DFL: u8 = 3; } - let (sigpipe_attr_specified, handler) = match sigpipe { + let (on_broken_pipe_used, handler) = match sigpipe { sigpipe::DEFAULT => (false, Some(libc::SIG_IGN)), sigpipe::INHERIT => (true, None), sigpipe::SIG_IGN => (true, Some(libc::SIG_IGN)), sigpipe::SIG_DFL => (true, Some(libc::SIG_DFL)), _ => unreachable!(), }; - if sigpipe_attr_specified { - ON_BROKEN_PIPE_FLAG_USED.store(true, crate::sync::atomic::Ordering::Relaxed); + if on_broken_pipe_used { + ON_BROKEN_PIPE_USED.store(true, crate::sync::atomic::Ordering::Relaxed); } if let Some(handler) = handler { rtassert!(signal(libc::SIGPIPE, handler) != libc::SIG_ERR); @@ -199,7 +199,7 @@ pub unsafe fn init(argc: isize, argv: *const *const u8, sigpipe: u8) { target_os = "vxworks", target_os = "vita", )))] -static ON_BROKEN_PIPE_FLAG_USED: crate::sync::atomic::Atomic = +static ON_BROKEN_PIPE_USED: crate::sync::atomic::Atomic = crate::sync::atomic::AtomicBool::new(false); #[cfg(not(any( @@ -211,8 +211,8 @@ static ON_BROKEN_PIPE_FLAG_USED: crate::sync::atomic::Atomic = target_os = "vita", target_os = "nuttx", )))] -pub(crate) fn on_broken_pipe_flag_used() -> bool { - ON_BROKEN_PIPE_FLAG_USED.load(crate::sync::atomic::Ordering::Relaxed) +pub(crate) fn on_broken_pipe_used() -> bool { + ON_BROKEN_PIPE_USED.load(crate::sync::atomic::Ordering::Relaxed) } // SAFETY: must be called only once during runtime cleanup. diff --git a/std/src/sys/pal/unix/stack_overflow.rs b/std/src/sys/pal/unix/stack_overflow.rs index 040fda75a5080..5d53de7fb7e21 100644 --- a/std/src/sys/pal/unix/stack_overflow.rs +++ b/std/src/sys/pal/unix/stack_overflow.rs @@ -70,7 +70,7 @@ mod imp { use super::thread_info::{delete_current_info, set_current_info, with_current_info}; use crate::ops::Range; use crate::sync::atomic::{Atomic, AtomicBool, AtomicPtr, AtomicUsize, Ordering}; - use crate::sys::pal::unix::os; + use crate::sys::pal::unix::conf; use crate::{io, mem, ptr}; // Signal handler for the SIGSEGV and SIGBUS handlers. We've got guard pages @@ -150,7 +150,7 @@ mod imp { /// Must be called only once #[forbid(unsafe_op_in_unsafe_fn)] pub unsafe fn init() { - PAGE_SIZE.store(os::page_size(), Ordering::Relaxed); + PAGE_SIZE.store(conf::page_size(), Ordering::Relaxed); let mut guard_page_range = unsafe { install_main_guard() }; @@ -429,6 +429,11 @@ mod imp { #[forbid(unsafe_op_in_unsafe_fn)] unsafe fn install_main_guard_linux(page_size: usize) -> Option> { + // See the corresponding conditional in init(). + // Avoid stack_start_aligned, which makes slow syscalls to read /proc/self/maps + if cfg!(panic = "immediate-abort") { + return None; + } // Linux doesn't allocate the whole stack right away, and // the kernel has its own stack-guard mechanism to fault // when growing too close to an existing mapping. If we map @@ -456,6 +461,10 @@ mod imp { #[forbid(unsafe_op_in_unsafe_fn)] #[cfg(target_os = "freebsd")] unsafe fn install_main_guard_freebsd(page_size: usize) -> Option> { + // See the corresponding conditional in install_main_guard_linux(). + if cfg!(panic = "immediate-abort") { + return None; + } // FreeBSD's stack autogrows, and optionally includes a guard page // at the bottom. If we try to remap the bottom of the stack // ourselves, FreeBSD's guard page moves upwards. So we'll just use @@ -489,6 +498,10 @@ mod imp { #[forbid(unsafe_op_in_unsafe_fn)] unsafe fn install_main_guard_bsds(page_size: usize) -> Option> { + // See the corresponding conditional in install_main_guard_linux(). + if cfg!(panic = "immediate-abort") { + return None; + } // OpenBSD stack already includes a guard page, and stack is // immutable. // NetBSD stack includes the guard page. diff --git a/std/src/sys/pal/unix/time.rs b/std/src/sys/pal/unix/time.rs index fbea94ec84e79..26fb6d3d7cf2d 100644 --- a/std/src/sys/pal/unix/time.rs +++ b/std/src/sys/pal/unix/time.rs @@ -1,3 +1,4 @@ +use core::mem; use core::num::niche_types::Nanoseconds; use crate::io; @@ -6,8 +7,12 @@ use crate::time::Duration; const NSEC_PER_SEC: u64 = 1_000_000_000; #[allow(dead_code)] // Used for pthread condvar timeouts -pub const TIMESPEC_MAX: libc::timespec = - libc::timespec { tv_sec: ::MAX, tv_nsec: 1_000_000_000 - 1 }; +pub const TIMESPEC_MAX: libc::timespec = { + let mut ts = unsafe { mem::zeroed::() }; + ts.tv_sec = ::MAX; + ts.tv_nsec = 1_000_000_000 - 1; + ts +}; // This additional constant is only used when calling // `libc::pthread_cond_timedwait`. @@ -17,7 +22,7 @@ pub(in crate::sys) const TIMESPEC_MAX_CAPPED: libc::timespec = libc::timespec { tv_nsec: (u64::MAX % NSEC_PER_SEC) as i64, }; -#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)] +#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)] pub(crate) struct Timespec { pub tv_sec: i64, pub tv_nsec: Nanoseconds, @@ -66,6 +71,7 @@ impl Timespec { } } + #[allow(dead_code)] pub fn now(clock: libc::clockid_t) -> Timespec { use crate::mem::MaybeUninit; use crate::sys::cvt; @@ -163,9 +169,11 @@ impl Timespec { #[allow(dead_code)] pub fn to_timespec(&self) -> Option { - Some(libc::timespec { - tv_sec: self.tv_sec.try_into().ok()?, - tv_nsec: self.tv_nsec.as_inner().try_into().ok()?, + Some({ + let mut ts = libc::timespec::default(); + ts.tv_sec = self.tv_sec.try_into().ok()?; + ts.tv_nsec = self.tv_nsec.as_inner().try_into().ok()?; + ts }) } diff --git a/std/src/sys/pal/unsupported/mod.rs b/std/src/sys/pal/unsupported/mod.rs index 0f157819d5a66..c4b14ab44436f 100644 --- a/std/src/sys/pal/unsupported/mod.rs +++ b/std/src/sys/pal/unsupported/mod.rs @@ -1,6 +1,4 @@ #![deny(unsafe_op_in_unsafe_fn)] -pub mod os; - mod common; pub use common::*; diff --git a/std/src/sys/pal/unsupported/os.rs b/std/src/sys/pal/unsupported/os.rs deleted file mode 100644 index cb925ef4348db..0000000000000 --- a/std/src/sys/pal/unsupported/os.rs +++ /dev/null @@ -1,65 +0,0 @@ -use super::unsupported; -use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::path::{self, PathBuf}; -use crate::{fmt, io}; - -pub fn getcwd() -> io::Result { - unsupported() -} - -pub fn chdir(_: &path::Path) -> io::Result<()> { - unsupported() -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on this platform yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -pub fn temp_dir() -> PathBuf { - panic!("no filesystem on this platform") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(_code: i32) -> ! { - crate::intrinsics::abort() -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/std/src/sys/pal/vexos/mod.rs b/std/src/sys/pal/vexos/mod.rs index 16aa3f088f04b..61bbe78f718af 100644 --- a/std/src/sys/pal/vexos/mod.rs +++ b/std/src/sys/pal/vexos/mod.rs @@ -1,5 +1,3 @@ -pub mod os; - #[expect(dead_code)] #[path = "../unsupported/common.rs"] mod unsupported_common; diff --git a/std/src/sys/pal/vexos/os.rs b/std/src/sys/pal/vexos/os.rs deleted file mode 100644 index 303b452a078ff..0000000000000 --- a/std/src/sys/pal/vexos/os.rs +++ /dev/null @@ -1,19 +0,0 @@ -#[expect(dead_code)] -#[path = "../unsupported/os.rs"] -mod unsupported_os; -pub use unsupported_os::{ - JoinPathsError, SplitPaths, chdir, current_exe, getcwd, getpid, home_dir, join_paths, - split_paths, temp_dir, -}; - -pub use super::unsupported; - -pub fn exit(_code: i32) -> ! { - unsafe { - vex_sdk::vexSystemExitRequest(); - - loop { - vex_sdk::vexTasksRun(); - } - } -} diff --git a/std/src/sys/pal/wasi/conf.rs b/std/src/sys/pal/wasi/conf.rs new file mode 100644 index 0000000000000..cf76ae733358e --- /dev/null +++ b/std/src/sys/pal/wasi/conf.rs @@ -0,0 +1,4 @@ +#[allow(dead_code)] +pub fn page_size() -> usize { + unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize } +} diff --git a/std/src/sys/pal/wasi/helpers.rs b/std/src/sys/pal/wasi/helpers.rs deleted file mode 100644 index 4f2eb1148f0b3..0000000000000 --- a/std/src/sys/pal/wasi/helpers.rs +++ /dev/null @@ -1,11 +0,0 @@ -#![forbid(unsafe_op_in_unsafe_fn)] - -pub fn abort_internal() -> ! { - unsafe { libc::abort() } -} - -#[inline] -#[cfg(target_env = "p1")] -pub(crate) fn err2io(err: wasi::Errno) -> crate::io::Error { - crate::io::Error::from_raw_os_error(err.raw().into()) -} diff --git a/std/src/sys/pal/wasi/mod.rs b/std/src/sys/pal/wasi/mod.rs index 9b49db9af6b05..6f60993509253 100644 --- a/std/src/sys/pal/wasi/mod.rs +++ b/std/src/sys/pal/wasi/mod.rs @@ -4,34 +4,63 @@ //! OS level functionality for WASI. Currently this includes both WASIp1 and //! WASIp2. +use crate::io; + +pub mod conf; #[allow(unused)] #[path = "../wasm/atomics/futex.rs"] pub mod futex; - -pub mod os; pub mod stack_overflow; #[path = "../unix/time.rs"] pub mod time; +#[cfg(not(target_env = "p1"))] +mod cabi_realloc; + #[path = "../unsupported/common.rs"] #[deny(unsafe_op_in_unsafe_fn)] -#[allow(unused)] +#[expect(dead_code)] mod common; +pub use common::{cleanup, init, unsupported}; -pub use common::*; +pub fn abort_internal() -> ! { + unsafe { libc::abort() } +} -mod helpers; +#[inline] +#[cfg(target_env = "p1")] +pub(crate) fn err2io(err: wasi::Errno) -> crate::io::Error { + crate::io::Error::from_raw_os_error(err.raw().into()) +} -// The following exports are listed individually to work around Rust's glob -// import conflict rules. If we glob export `helpers` and `common` together, -// then the compiler complains about conflicts. +#[doc(hidden)] +pub trait IsMinusOne { + fn is_minus_one(&self) -> bool; +} -pub(crate) use helpers::abort_internal; -#[cfg(target_env = "p1")] -pub(crate) use helpers::err2io; -#[cfg(not(target_env = "p1"))] -pub use os::IsMinusOne; -pub use os::{cvt, cvt_r}; +macro_rules! impl_is_minus_one { + ($($t:ident)*) => ($(impl IsMinusOne for $t { + fn is_minus_one(&self) -> bool { + *self == -1 + } + })*) +} -#[cfg(not(target_env = "p1"))] -mod cabi_realloc; +impl_is_minus_one! { i8 i16 i32 i64 isize } + +pub fn cvt(t: T) -> io::Result { + if t.is_minus_one() { Err(io::Error::last_os_error()) } else { Ok(t) } +} + +pub fn cvt_r(mut f: F) -> io::Result +where + T: IsMinusOne, + F: FnMut() -> T, +{ + loop { + match cvt(f()) { + Err(ref e) if e.is_interrupted() => {} + other => return other, + } + } +} diff --git a/std/src/sys/pal/wasi/os.rs b/std/src/sys/pal/wasi/os.rs deleted file mode 100644 index 285be3ca9fda4..0000000000000 --- a/std/src/sys/pal/wasi/os.rs +++ /dev/null @@ -1,143 +0,0 @@ -#![forbid(unsafe_op_in_unsafe_fn)] - -use crate::ffi::{CStr, OsStr, OsString}; -use crate::marker::PhantomData; -use crate::os::wasi::prelude::*; -use crate::path::{self, PathBuf}; -use crate::sys::helpers::run_path_with_cstr; -use crate::sys::unsupported; -use crate::{fmt, io}; - -// Add a few symbols not in upstream `libc` just yet. -pub mod libc { - pub use libc::*; - - unsafe extern "C" { - pub fn getcwd(buf: *mut c_char, size: size_t) -> *mut c_char; - pub fn chdir(dir: *const c_char) -> c_int; - pub fn __wasilibc_get_environ() -> *mut *mut c_char; - } -} - -pub fn getcwd() -> io::Result { - let mut buf = Vec::with_capacity(512); - loop { - unsafe { - let ptr = buf.as_mut_ptr() as *mut libc::c_char; - if !libc::getcwd(ptr, buf.capacity()).is_null() { - let len = CStr::from_ptr(buf.as_ptr() as *const libc::c_char).to_bytes().len(); - buf.set_len(len); - buf.shrink_to_fit(); - return Ok(PathBuf::from(OsString::from_vec(buf))); - } else { - let error = io::Error::last_os_error(); - if error.raw_os_error() != Some(libc::ERANGE) { - return Err(error); - } - } - - // Trigger the internal buffer resizing logic of `Vec` by requiring - // more space than the current capacity. - let cap = buf.capacity(); - buf.set_len(cap); - buf.reserve(1); - } - } -} - -pub fn chdir(p: &path::Path) -> io::Result<()> { - let result = run_path_with_cstr(p, &|p| unsafe { Ok(libc::chdir(p.as_ptr())) })?; - match result == (0 as libc::c_int) { - true => Ok(()), - false => Err(io::Error::last_os_error()), - } -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on wasm yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -#[allow(dead_code)] -pub fn page_size() -> usize { - unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize } -} - -pub fn temp_dir() -> PathBuf { - panic!("no filesystem on wasm") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(code: i32) -> ! { - unsafe { libc::exit(code) } -} - -pub fn getpid() -> u32 { - panic!("unsupported"); -} - -#[doc(hidden)] -pub trait IsMinusOne { - fn is_minus_one(&self) -> bool; -} - -macro_rules! impl_is_minus_one { - ($($t:ident)*) => ($(impl IsMinusOne for $t { - fn is_minus_one(&self) -> bool { - *self == -1 - } - })*) -} - -impl_is_minus_one! { i8 i16 i32 i64 isize } - -pub fn cvt(t: T) -> io::Result { - if t.is_minus_one() { Err(io::Error::last_os_error()) } else { Ok(t) } -} - -pub fn cvt_r(mut f: F) -> io::Result -where - T: IsMinusOne, - F: FnMut() -> T, -{ - loop { - match cvt(f()) { - Err(ref e) if e.is_interrupted() => {} - other => return other, - } - } -} diff --git a/std/src/sys/pal/wasm/mod.rs b/std/src/sys/pal/wasm/mod.rs index 5f56eddd6a819..24a2ab8eca30f 100644 --- a/std/src/sys/pal/wasm/mod.rs +++ b/std/src/sys/pal/wasm/mod.rs @@ -16,9 +16,6 @@ #![deny(unsafe_op_in_unsafe_fn)] -#[path = "../unsupported/os.rs"] -pub mod os; - #[cfg(target_feature = "atomics")] #[path = "atomics/futex.rs"] pub mod futex; diff --git a/std/src/sys/pal/windows/mod.rs b/std/src/sys/pal/windows/mod.rs index 0cd9152614716..b67ba37749789 100644 --- a/std/src/sys/pal/windows/mod.rs +++ b/std/src/sys/pal/windows/mod.rs @@ -18,7 +18,6 @@ pub mod c; #[cfg(not(target_vendor = "win7"))] pub mod futex; pub mod handle; -pub mod os; pub mod time; cfg_select! { // We don't care about printing nice error messages for panic=immediate-abort diff --git a/std/src/sys/pal/xous/mod.rs b/std/src/sys/pal/xous/mod.rs index 87c99068929c3..b5b3fd91b4fa6 100644 --- a/std/src/sys/pal/xous/mod.rs +++ b/std/src/sys/pal/xous/mod.rs @@ -1,7 +1,54 @@ #![forbid(unsafe_op_in_unsafe_fn)] -pub mod os; +pub mod params; #[path = "../unsupported/common.rs"] mod common; pub use common::*; + +#[cfg(not(test))] +#[cfg(feature = "panic-unwind")] +mod eh_unwinding { + pub(crate) struct EhFrameFinder; + pub(crate) static mut EH_FRAME_ADDRESS: usize = 0; + pub(crate) static EH_FRAME_SETTINGS: EhFrameFinder = EhFrameFinder; + + unsafe impl unwind::EhFrameFinder for EhFrameFinder { + fn find(&self, _pc: usize) -> Option { + if unsafe { EH_FRAME_ADDRESS == 0 } { + None + } else { + Some(unwind::FrameInfo { + text_base: None, + kind: unwind::FrameInfoKind::EhFrame(unsafe { EH_FRAME_ADDRESS }), + }) + } + } + } +} + +#[cfg(not(test))] +mod c_compat { + use crate::os::xous::ffi::exit; + + unsafe extern "C" { + fn main() -> u32; + } + + #[unsafe(no_mangle)] + pub extern "C" fn abort() { + exit(1); + } + + #[unsafe(no_mangle)] + pub extern "C" fn _start(eh_frame: usize, params: *mut u8) { + #[cfg(feature = "panic-unwind")] + { + unsafe { super::eh_unwinding::EH_FRAME_ADDRESS = eh_frame }; + unwind::set_custom_eh_frame_finder(&super::eh_unwinding::EH_FRAME_SETTINGS).ok(); + } + + unsafe { super::params::set(params) }; + exit(unsafe { main() }); + } +} diff --git a/std/src/sys/pal/xous/os.rs b/std/src/sys/pal/xous/os.rs deleted file mode 100644 index cd7b7b59d1127..0000000000000 --- a/std/src/sys/pal/xous/os.rs +++ /dev/null @@ -1,128 +0,0 @@ -use super::unsupported; -use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::path::{self, PathBuf}; -use crate::sync::atomic::{Atomic, AtomicPtr, Ordering}; -use crate::{fmt, io}; - -pub(crate) mod params; - -static PARAMS_ADDRESS: Atomic<*mut u8> = AtomicPtr::new(core::ptr::null_mut()); - -#[cfg(not(test))] -#[cfg(feature = "panic-unwind")] -mod eh_unwinding { - pub(crate) struct EhFrameFinder; - pub(crate) static mut EH_FRAME_ADDRESS: usize = 0; - pub(crate) static EH_FRAME_SETTINGS: EhFrameFinder = EhFrameFinder; - - unsafe impl unwind::EhFrameFinder for EhFrameFinder { - fn find(&self, _pc: usize) -> Option { - if unsafe { EH_FRAME_ADDRESS == 0 } { - None - } else { - Some(unwind::FrameInfo { - text_base: None, - kind: unwind::FrameInfoKind::EhFrame(unsafe { EH_FRAME_ADDRESS }), - }) - } - } - } -} - -#[cfg(not(test))] -mod c_compat { - use crate::os::xous::ffi::exit; - unsafe extern "C" { - fn main() -> u32; - } - - #[unsafe(no_mangle)] - pub extern "C" fn abort() { - exit(1); - } - - #[unsafe(no_mangle)] - pub extern "C" fn _start(eh_frame: usize, params_address: usize) { - #[cfg(feature = "panic-unwind")] - { - unsafe { super::eh_unwinding::EH_FRAME_ADDRESS = eh_frame }; - unwind::set_custom_eh_frame_finder(&super::eh_unwinding::EH_FRAME_SETTINGS).ok(); - } - - if params_address != 0 { - let params_address = crate::ptr::with_exposed_provenance_mut::(params_address); - if unsafe { - super::params::ApplicationParameters::new_from_ptr(params_address).is_some() - } { - super::PARAMS_ADDRESS.store(params_address, core::sync::atomic::Ordering::Relaxed); - } - } - exit(unsafe { main() }); - } -} - -pub fn getcwd() -> io::Result { - unsupported() -} - -pub fn chdir(_: &path::Path) -> io::Result<()> { - unsupported() -} - -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); - -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") -} - -impl<'a> Iterator for SplitPaths<'a> { - type Item = PathBuf; - fn next(&mut self) -> Option { - self.0 - } -} - -#[derive(Debug)] -pub struct JoinPathsError; - -pub fn join_paths(_paths: I) -> Result -where - I: Iterator, - T: AsRef, -{ - Err(JoinPathsError) -} - -impl fmt::Display for JoinPathsError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - "not supported on this platform yet".fmt(f) - } -} - -impl crate::error::Error for JoinPathsError {} - -pub fn current_exe() -> io::Result { - unsupported() -} - -pub(crate) fn get_application_parameters() -> Option { - let params_address = PARAMS_ADDRESS.load(Ordering::Relaxed); - unsafe { params::ApplicationParameters::new_from_ptr(params_address) } -} - -pub fn temp_dir() -> PathBuf { - panic!("no filesystem on this platform") -} - -pub fn home_dir() -> Option { - None -} - -pub fn exit(code: i32) -> ! { - crate::os::xous::ffi::exit(code as u32); -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/std/src/sys/pal/xous/os/params.rs b/std/src/sys/pal/xous/params.rs similarity index 67% rename from std/src/sys/pal/xous/os/params.rs rename to std/src/sys/pal/xous/params.rs index 0d02cf35477f9..d6f671e9a6b68 100644 --- a/std/src/sys/pal/xous/os/params.rs +++ b/std/src/sys/pal/xous/params.rs @@ -1,75 +1,100 @@ -/// Xous passes a pointer to the parameter block as the second argument. -/// This is used for passing flags such as environment variables. The -/// format of the argument block is: -/// -/// #[repr(C)] -/// struct BlockHeader { -/// /// Magic number that identifies this block. Must be printable ASCII. -/// magic: [u8; 4], -/// -/// /// The size of the data block. Does not include this header. May be 0. -/// size: u32, -/// -/// /// The contents of this block. Varies depending on the block type. -/// data: [u8; 0], -/// } -/// -/// There is a BlockHeader at the start that has magic `AppP`, and the data -/// that follows is the number of blocks present: -/// -/// #[repr(C)] -/// struct ApplicationParameters { -/// magic: b"AppP", -/// size: 4u32, -/// -/// /// The size of the entire application slice, in bytes, including all headers -/// length: u32, -/// -/// /// Number of application parameters present. Must be at least 1 (this block) -/// entries: (parameter_count as u32).to_bytes_le(), -/// } -/// -/// #[repr(C)] -/// struct EnvironmentBlock { -/// magic: b"EnvB", -/// -/// /// Total number of bytes, excluding this header -/// size: 2+data.len(), -/// -/// /// The number of environment variables -/// count: u16, -/// -/// /// Environment variable iteration -/// data: [u8; 0], -/// } -/// -/// Environment variables are present in an `EnvB` block. The `data` section is -/// a sequence of bytes of the form: -/// -/// (u16 /* key_len */; [0u8; key_len as usize] /* key */, -/// u16 /* val_len */ [0u8; val_len as usize]) -/// -/// #[repr(C)] -/// struct ArgumentList { -/// magic: b"ArgL", -/// -/// /// Total number of bytes, excluding this header -/// size: 2+data.len(), -/// -/// /// The number of arguments variables -/// count: u16, -/// -/// /// Argument variable iteration -/// data: [u8; 0], -/// } -/// -/// Args are just an array of strings that represent command line arguments. -/// They are a sequence of the form: -/// -/// (u16 /* val_len */ [0u8; val_len as usize]) -use core::slice; +//! Xous passes a pointer to the parameter block as the second argument. +//! This is used for passing flags such as environment variables. The +//! format of the argument block is: +//! +//! #[repr(C)] +//! struct BlockHeader { +//! /// Magic number that identifies this block. Must be printable ASCII. +//! magic: [u8; 4], +//! +//! /// The size of the data block. Does not include this header. May be 0. +//! size: u32, +//! +//! /// The contents of this block. Varies depending on the block type. +//! data: [u8; 0], +//! } +//! +//! There is a BlockHeader at the start that has magic `AppP`, and the data +//! that follows is the number of blocks present: +//! +//! #[repr(C)] +//! struct ApplicationParameters { +//! magic: b"AppP", +//! size: 4u32, +//! +//! /// The size of the entire application slice, in bytes, including all headers +//! length: u32, +//! +//! /// Number of application parameters present. Must be at least 1 (this block) +//! entries: (parameter_count as u32).to_bytes_le(), +//! } +//! +//! #[repr(C)] +//! struct EnvironmentBlock { +//! magic: b"EnvB", +//! +//! /// Total number of bytes, excluding this header +//! size: 2+data.len(), +//! +//! /// The number of environment variables +//! count: u16, +//! +//! /// Environment variable iteration +//! data: [u8; 0], +//! } +//! +//! Environment variables are present in an `EnvB` block. The `data` section is +//! a sequence of bytes of the form: +//! +//! (u16 /* key_len */; [0u8; key_len as usize] /* key */, +//! u16 /* val_len */ [0u8; val_len as usize]) +//! +//! #[repr(C)] +//! struct ArgumentList { +//! magic: b"ArgL", +//! +//! /// Total number of bytes, excluding this header +//! size: 2+data.len(), +//! +//! /// The number of arguments variables +//! count: u16, +//! +//! /// Argument variable iteration +//! data: [u8; 0], +//! } +//! +//! Args are just an array of strings that represent command line arguments. +//! They are a sequence of the form: +//! +//! (u16 /* val_len */ [0u8; val_len as usize]) use crate::ffi::OsString; +use crate::slice; + +#[cfg(test)] +mod tests; + +static mut PARAMS: *mut u8 = crate::ptr::null_mut(); + +/// Remember the location of the parameter block. +/// +/// # Safety +/// * This function may only be called before `main`. +/// * `data` must either be `null` or point to a valid parameter block. +pub(super) unsafe fn set(data: *mut u8) { + // SAFETY: + // Since this function is called before `main`, there cannot be any threads + // already running. Thus this write cannot race, and all threads will observe + // this write and the parameter block initialization since it happens-before + // their creation. + unsafe { PARAMS = data }; +} + +pub(crate) fn get() -> Option { + // SAFETY: See above. + let data = unsafe { PARAMS }; + unsafe { ApplicationParameters::new_from_ptr(data) } +} /// Magic number indicating we have an environment block const ENV_MAGIC: [u8; 4] = *b"EnvB"; @@ -80,9 +105,6 @@ const ARGS_MAGIC: [u8; 4] = *b"ArgL"; /// Magic number indicating the loader has passed application parameters const PARAMS_MAGIC: [u8; 4] = *b"AppP"; -#[cfg(test)] -mod tests; - pub(crate) struct ApplicationParameters { data: &'static [u8], offset: usize, @@ -90,7 +112,7 @@ pub(crate) struct ApplicationParameters { } impl ApplicationParameters { - pub(crate) unsafe fn new_from_ptr(data: *const u8) -> Option { + unsafe fn new_from_ptr(data: *const u8) -> Option { if data.is_null() { return None; } diff --git a/std/src/sys/pal/xous/os/params/tests.rs b/std/src/sys/pal/xous/params/tests.rs similarity index 100% rename from std/src/sys/pal/xous/os/params/tests.rs rename to std/src/sys/pal/xous/params/tests.rs diff --git a/std/src/sys/pal/zkvm/mod.rs b/std/src/sys/pal/zkvm/mod.rs index 1b18adb811d95..1a64d3c93d701 100644 --- a/std/src/sys/pal/zkvm/mod.rs +++ b/std/src/sys/pal/zkvm/mod.rs @@ -11,7 +11,6 @@ pub const WORD_SIZE: usize = size_of::(); pub mod abi; -pub mod os; use crate::io as std_io; diff --git a/std/src/sys/path/cygwin.rs b/std/src/sys/path/cygwin.rs index 75f0de6beaeb5..494dd91f23140 100644 --- a/std/src/sys/path/cygwin.rs +++ b/std/src/sys/path/cygwin.rs @@ -5,25 +5,20 @@ use crate::sys::cvt; use crate::sys::helpers::run_path_with_cstr; use crate::{io, ptr}; -#[inline] -pub fn is_sep_byte(b: u8) -> bool { - b == b'/' || b == b'\\' -} +path_separator_bytes!(b'/', b'\\'); /// Cygwin always prefers `/` over `\`, and it always converts all `/` to `\` /// internally when calling Win32 APIs. Therefore, the server component of path /// `\\?\UNC\localhost/share` is `localhost/share` on Win32, but `localhost` /// on Cygwin. #[inline] -pub fn is_verbatim_sep(b: u8) -> bool { - b == b'/' || b == b'\\' +pub const fn is_verbatim_sep(b: u8) -> bool { + is_sep_byte(b) } pub use super::windows_prefix::parse_prefix; pub const HAS_PREFIXES: bool = true; -pub const MAIN_SEP_STR: &str = "/"; -pub const MAIN_SEP: char = '/'; unsafe extern "C" { // Doc: https://cygwin.com/cygwin-api/func-cygwin-conv-path.html diff --git a/std/src/sys/path/mod.rs b/std/src/sys/path/mod.rs index 254683bc83f91..bbb7577e186ae 100644 --- a/std/src/sys/path/mod.rs +++ b/std/src/sys/path/mod.rs @@ -1,3 +1,22 @@ +// There's a lot of necessary redundancy in separator definition. Consolidated into a macro to +// prevent transcription errors. +macro_rules! path_separator_bytes { + ($($sep:literal),+) => ( + pub const SEPARATORS: &[char] = &[$($sep as char,)+]; + pub const SEPARATORS_STR: &[&str] = &[$( + match str::from_utf8(&[$sep]) { + Ok(s) => s, + Err(_) => panic!("path_separator_bytes must be ASCII bytes"), + } + ),+]; + + #[inline] + pub const fn is_sep_byte(b: u8) -> bool { + $(b == $sep) ||+ + } + ) +} + cfg_select! { target_os = "windows" => { mod windows; diff --git a/std/src/sys/path/sgx.rs b/std/src/sys/path/sgx.rs index dca61f3ea145d..9b7ab30a9c652 100644 --- a/std/src/sys/path/sgx.rs +++ b/std/src/sys/path/sgx.rs @@ -3,14 +3,11 @@ use crate::io; use crate::path::{Path, PathBuf, Prefix}; use crate::sys::unsupported; -#[inline] -pub fn is_sep_byte(b: u8) -> bool { - b == b'/' -} +path_separator_bytes!(b'/'); #[inline] -pub fn is_verbatim_sep(b: u8) -> bool { - b == b'/' +pub const fn is_verbatim_sep(b: u8) -> bool { + is_sep_byte(b) } pub fn parse_prefix(_: &OsStr) -> Option> { @@ -18,8 +15,6 @@ pub fn parse_prefix(_: &OsStr) -> Option> { } pub const HAS_PREFIXES: bool = false; -pub const MAIN_SEP_STR: &str = "/"; -pub const MAIN_SEP: char = '/'; pub(crate) fn absolute(_path: &Path) -> io::Result { unsupported() diff --git a/std/src/sys/path/uefi.rs b/std/src/sys/path/uefi.rs index 84d634af93cf1..8c911ee5f9c53 100644 --- a/std/src/sys/path/uefi.rs +++ b/std/src/sys/path/uefi.rs @@ -5,17 +5,14 @@ use crate::path::{Path, PathBuf, Prefix}; use crate::sys::pal::helpers; use crate::sys::unsupported_err; +path_separator_bytes!(b'\\'); + const FORWARD_SLASH: u8 = b'/'; const COLON: u8 = b':'; #[inline] -pub fn is_sep_byte(b: u8) -> bool { - b == b'\\' -} - -#[inline] -pub fn is_verbatim_sep(b: u8) -> bool { - b == b'\\' +pub const fn is_verbatim_sep(b: u8) -> bool { + is_sep_byte(b) } pub fn parse_prefix(_: &OsStr) -> Option> { @@ -23,8 +20,6 @@ pub fn parse_prefix(_: &OsStr) -> Option> { } pub const HAS_PREFIXES: bool = true; -pub const MAIN_SEP_STR: &str = "\\"; -pub const MAIN_SEP: char = '\\'; /// UEFI paths can be of 4 types: /// diff --git a/std/src/sys/path/unix.rs b/std/src/sys/path/unix.rs index 611d250db4050..b49c39a9253fa 100644 --- a/std/src/sys/path/unix.rs +++ b/std/src/sys/path/unix.rs @@ -2,14 +2,11 @@ use crate::ffi::OsStr; use crate::path::{Path, PathBuf, Prefix}; use crate::{env, io}; -#[inline] -pub fn is_sep_byte(b: u8) -> bool { - b == b'/' -} +path_separator_bytes!(b'/'); #[inline] -pub fn is_verbatim_sep(b: u8) -> bool { - b == b'/' +pub const fn is_verbatim_sep(b: u8) -> bool { + is_sep_byte(b) } #[inline] @@ -18,8 +15,6 @@ pub fn parse_prefix(_: &OsStr) -> Option> { } pub const HAS_PREFIXES: bool = false; -pub const MAIN_SEP_STR: &str = "/"; -pub const MAIN_SEP: char = '/'; /// Make a POSIX path absolute without changing its semantics. pub(crate) fn absolute(path: &Path) -> io::Result { diff --git a/std/src/sys/path/unsupported_backslash.rs b/std/src/sys/path/unsupported_backslash.rs index 8ed1fdc36e23f..ce1851e938395 100644 --- a/std/src/sys/path/unsupported_backslash.rs +++ b/std/src/sys/path/unsupported_backslash.rs @@ -4,14 +4,11 @@ use crate::io; use crate::path::{Path, PathBuf, Prefix}; use crate::sys::unsupported; -#[inline] -pub fn is_sep_byte(b: u8) -> bool { - b == b'\\' -} +path_separator_bytes!(b'\\'); #[inline] -pub fn is_verbatim_sep(b: u8) -> bool { - b == b'\\' +pub const fn is_verbatim_sep(b: u8) -> bool { + is_sep_byte(b) } pub fn parse_prefix(_: &OsStr) -> Option> { @@ -19,8 +16,6 @@ pub fn parse_prefix(_: &OsStr) -> Option> { } pub const HAS_PREFIXES: bool = true; -pub const MAIN_SEP_STR: &str = "\\"; -pub const MAIN_SEP: char = '\\'; pub(crate) fn absolute(_path: &Path) -> io::Result { unsupported() diff --git a/std/src/sys/path/windows.rs b/std/src/sys/path/windows.rs index 509b13b6ae812..1c7bf50d1907f 100644 --- a/std/src/sys/path/windows.rs +++ b/std/src/sys/path/windows.rs @@ -9,9 +9,9 @@ mod tests; pub use super::windows_prefix::parse_prefix; +path_separator_bytes!(b'\\', b'/'); + pub const HAS_PREFIXES: bool = true; -pub const MAIN_SEP_STR: &str = "\\"; -pub const MAIN_SEP: char = '\\'; /// A null terminated wide string. #[repr(transparent)] @@ -48,12 +48,7 @@ pub fn with_native_path(path: &Path, f: &dyn Fn(&WCStr) -> io::Result) -> } #[inline] -pub fn is_sep_byte(b: u8) -> bool { - b == b'/' || b == b'\\' -} - -#[inline] -pub fn is_verbatim_sep(b: u8) -> bool { +pub const fn is_verbatim_sep(b: u8) -> bool { b == b'\\' } diff --git a/std/src/sys/paths/hermit.rs b/std/src/sys/paths/hermit.rs new file mode 100644 index 0000000000000..36f667d300539 --- /dev/null +++ b/std/src/sys/paths/hermit.rs @@ -0,0 +1,10 @@ +use crate::io; +use crate::path::PathBuf; + +pub fn getcwd() -> io::Result { + Ok(PathBuf::from("/")) +} + +pub fn temp_dir() -> PathBuf { + PathBuf::from("/tmp") +} diff --git a/std/src/sys/paths/mod.rs b/std/src/sys/paths/mod.rs new file mode 100644 index 0000000000000..8880a837af7f9 --- /dev/null +++ b/std/src/sys/paths/mod.rs @@ -0,0 +1,59 @@ +cfg_select! { + target_os = "hermit" => { + mod hermit; + #[expect(dead_code)] + mod unsupported; + mod imp { + pub use super::hermit::{getcwd, temp_dir}; + pub use super::unsupported::{chdir, SplitPaths, split_paths, JoinPathsError, join_paths, current_exe, home_dir}; + } + } + target_os = "motor" => { + mod motor; + #[expect(dead_code)] + mod unsupported; + mod imp { + pub use super::motor::{getcwd, chdir, current_exe, temp_dir}; + pub use super::unsupported::{SplitPaths, split_paths, JoinPathsError, join_paths, home_dir}; + } + } + all(target_vendor = "fortanix", target_env = "sgx") => { + mod sgx; + #[expect(dead_code)] + mod unsupported; + mod imp { + pub use super::sgx::chdir; + pub use super::unsupported::{getcwd, SplitPaths, split_paths, JoinPathsError, join_paths, current_exe, temp_dir, home_dir}; + } + } + target_os = "uefi" => { + mod uefi; + use uefi as imp; + } + target_family = "unix" => { + mod unix; + use unix as imp; + } + target_os = "wasi" => { + mod wasi; + #[expect(dead_code)] + mod unsupported; + mod imp { + pub use super::wasi::{getcwd, chdir, temp_dir}; + pub use super::unsupported::{current_exe, SplitPaths, split_paths, JoinPathsError, join_paths, home_dir}; + } + } + target_os = "windows" => { + mod windows; + use windows as imp; + } + _ => { + mod unsupported; + use unsupported as imp; + } +} + +pub use imp::{ + JoinPathsError, SplitPaths, chdir, current_exe, getcwd, home_dir, join_paths, split_paths, + temp_dir, +}; diff --git a/std/src/sys/paths/motor.rs b/std/src/sys/paths/motor.rs new file mode 100644 index 0000000000000..33d746b13d592 --- /dev/null +++ b/std/src/sys/paths/motor.rs @@ -0,0 +1,20 @@ +use crate::io; +use crate::os::motor::ffi::OsStrExt; +use crate::path::{self, PathBuf}; +use crate::sys::pal::map_motor_error; + +pub fn getcwd() -> io::Result { + moto_rt::fs::getcwd().map(PathBuf::from).map_err(map_motor_error) +} + +pub fn chdir(path: &path::Path) -> io::Result<()> { + moto_rt::fs::chdir(path.as_os_str().as_str()).map_err(map_motor_error) +} + +pub fn current_exe() -> io::Result { + moto_rt::process::current_exe().map(PathBuf::from).map_err(map_motor_error) +} + +pub fn temp_dir() -> PathBuf { + PathBuf::from(moto_rt::fs::TEMP_DIR) +} diff --git a/std/src/sys/paths/sgx.rs b/std/src/sys/paths/sgx.rs new file mode 100644 index 0000000000000..6a4cbe93b1b88 --- /dev/null +++ b/std/src/sys/paths/sgx.rs @@ -0,0 +1,7 @@ +use crate::io; +use crate::path::Path; +use crate::sys::pal::sgx_ineffective; + +pub fn chdir(_: &Path) -> io::Result<()> { + sgx_ineffective(()) +} diff --git a/std/src/sys/pal/uefi/os.rs b/std/src/sys/paths/uefi.rs similarity index 75% rename from std/src/sys/pal/uefi/os.rs rename to std/src/sys/paths/uefi.rs index 5b9785c8371e3..7fddcfdff7724 100644 --- a/std/src/sys/pal/uefi/os.rs +++ b/std/src/sys/paths/uefi.rs @@ -1,13 +1,9 @@ -use r_efi::efi::Status; use r_efi::efi::protocols::{device_path, loaded_image_device_path}; -use super::{helpers, unsupported_err}; use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::os::uefi; use crate::os::uefi::ffi::{OsStrExt, OsStringExt}; use crate::path::{self, PathBuf}; -use crate::ptr::NonNull; +use crate::sys::pal::{helpers, unsupported_err}; use crate::{fmt, io}; const PATHS_SEP: u16 = b';' as u16; @@ -41,16 +37,37 @@ pub fn chdir(p: &path::Path) -> io::Result<()> { if r.is_error() { Err(io::Error::from_raw_os_error(r.as_usize())) } else { Ok(()) } } -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); +pub struct SplitPaths<'a> { + data: crate::os::uefi::ffi::EncodeWide<'a>, + must_yield: bool, +} -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") +pub fn split_paths(unparsed: &OsStr) -> SplitPaths<'_> { + SplitPaths { data: unparsed.encode_wide(), must_yield: true } } impl<'a> Iterator for SplitPaths<'a> { type Item = PathBuf; + fn next(&mut self) -> Option { - self.0 + let must_yield = self.must_yield; + self.must_yield = false; + + let mut in_progress = Vec::new(); + for b in self.data.by_ref() { + if b == PATHS_SEP { + self.must_yield = true; + break; + } else { + in_progress.push(b) + } + } + + if !must_yield && in_progress.is_empty() { + None + } else { + Some(PathBuf::from(OsString::from_wide(&in_progress))) + } } } @@ -98,30 +115,9 @@ pub fn current_exe() -> io::Result { } pub fn temp_dir() -> PathBuf { - panic!("no filesystem on this platform") + panic!("UEFI doesn't have a dedicated temp directory") } pub fn home_dir() -> Option { None } - -pub fn exit(code: i32) -> ! { - if let (Some(boot_services), Some(handle)) = - (uefi::env::boot_services(), uefi::env::try_image_handle()) - { - let boot_services: NonNull = boot_services.cast(); - let _ = unsafe { - ((*boot_services.as_ptr()).exit)( - handle.as_ptr(), - Status::from_usize(code as usize), - 0, - crate::ptr::null_mut(), - ) - }; - } - crate::intrinsics::abort() -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/std/src/sys/pal/unix/os.rs b/std/src/sys/paths/unix.rs similarity index 76% rename from std/src/sys/pal/unix/os.rs rename to std/src/sys/paths/unix.rs index b8280a8f29a02..544d495340db7 100644 --- a/std/src/sys/pal/unix/os.rs +++ b/std/src/sys/paths/unix.rs @@ -2,16 +2,13 @@ #![allow(unused_imports)] // lots of cfg code here -#[cfg(test)] -mod tests; - use libc::{c_char, c_int, c_void}; use crate::ffi::{CStr, OsStr, OsString}; use crate::os::unix::prelude::*; use crate::path::{self, PathBuf}; -use crate::sys::cvt; use crate::sys::helpers::run_path_with_cstr; +use crate::sys::pal::cvt; use crate::{fmt, io, iter, mem, ptr, slice, str}; const PATH_SEPARATOR: u8 = b':'; @@ -50,7 +47,7 @@ pub fn getcwd() -> io::Result { #[cfg(target_os = "espidf")] pub fn chdir(_p: &path::Path) -> io::Result<()> { - super::unsupported::unsupported() + crate::sys::pal::unsupported::unsupported() } #[cfg(not(target_os = "espidf"))] @@ -375,7 +372,7 @@ pub fn current_exe() -> io::Result { #[cfg(any(target_os = "espidf", target_os = "horizon", target_os = "vita"))] pub fn current_exe() -> io::Result { - super::unsupported::unsupported() + crate::sys::pal::unsupported::unsupported() } #[cfg(target_os = "fuchsia")] @@ -396,75 +393,15 @@ pub fn current_exe() -> io::Result { if !path.is_absolute() { getcwd().map(|cwd| cwd.join(path)) } else { Ok(path) } } -#[cfg(not(target_os = "espidf"))] -pub fn page_size() -> usize { - unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize } -} - -// Returns the value for [`confstr(key, ...)`][posix_confstr]. Currently only -// used on Darwin, but should work on any unix (in case we need to get -// `_CS_PATH` or `_CS_V[67]_ENV` in the future). -// -// [posix_confstr]: -// https://pubs.opengroup.org/onlinepubs/9699919799/functions/confstr.html -// -// FIXME: Support `confstr` in Miri. -#[cfg(all(target_vendor = "apple", not(miri)))] -fn confstr(key: c_int, size_hint: Option) -> io::Result { - let mut buf: Vec = Vec::with_capacity(0); - let mut bytes_needed_including_nul = size_hint - .unwrap_or_else(|| { - // Treat "None" as "do an extra call to get the length". In theory - // we could move this into the loop below, but it's hard to do given - // that it isn't 100% clear if it's legal to pass 0 for `len` when - // the buffer isn't null. - unsafe { libc::confstr(key, core::ptr::null_mut(), 0) } - }) - .max(1); - // If the value returned by `confstr` is greater than the len passed into - // it, then the value was truncated, meaning we need to retry. Note that - // while `confstr` results don't seem to change for a process, it's unclear - // if this is guaranteed anywhere, so looping does seem required. - while bytes_needed_including_nul > buf.capacity() { - // We write into the spare capacity of `buf`. This lets us avoid - // changing buf's `len`, which both simplifies `reserve` computation, - // allows working with `Vec` instead of `Vec>`, and - // may avoid a copy, since the Vec knows that none of the bytes are needed - // when reallocating (well, in theory anyway). - buf.reserve(bytes_needed_including_nul); - // `confstr` returns - // - 0 in the case of errors: we break and return an error. - // - The number of bytes written, iff the provided buffer is enough to - // hold the entire value: we break and return the data in `buf`. - // - Otherwise, the number of bytes needed (including nul): we go - // through the loop again. - bytes_needed_including_nul = - unsafe { libc::confstr(key, buf.as_mut_ptr().cast::(), buf.capacity()) }; - } - // `confstr` returns 0 in the case of an error. - if bytes_needed_including_nul == 0 { - return Err(io::Error::last_os_error()); - } - // Safety: `confstr(..., buf.as_mut_ptr(), buf.capacity())` returned a - // non-zero value, meaning `bytes_needed_including_nul` bytes were - // initialized. - unsafe { - buf.set_len(bytes_needed_including_nul); - // Remove the NUL-terminator. - let last_byte = buf.pop(); - // ... and smoke-check that it *was* a NUL-terminator. - assert_eq!(last_byte, Some(0), "`confstr` provided a string which wasn't nul-terminated"); - }; - Ok(OsString::from_vec(buf)) -} - #[cfg(all(target_vendor = "apple", not(miri)))] fn darwin_temp_dir() -> PathBuf { - confstr(libc::_CS_DARWIN_USER_TEMP_DIR, Some(64)).map(PathBuf::from).unwrap_or_else(|_| { - // It failed for whatever reason (there are several possible reasons), - // so return the global one. - PathBuf::from("/tmp") - }) + crate::sys::pal::conf::confstr(libc::_CS_DARWIN_USER_TEMP_DIR, Some(64)) + .map(PathBuf::from) + .unwrap_or_else(|_| { + // It failed for whatever reason (there are several possible reasons), + // so return the global one. + PathBuf::from("/tmp") + }) } pub fn temp_dir() -> PathBuf { @@ -532,40 +469,3 @@ pub fn home_dir() -> Option { } } } - -pub fn exit(code: i32) -> ! { - crate::sys::exit_guard::unique_thread_exit(); - unsafe { libc::exit(code as c_int) } -} - -pub fn getpid() -> u32 { - unsafe { libc::getpid() as u32 } -} - -pub fn getppid() -> u32 { - unsafe { libc::getppid() as u32 } -} - -#[cfg(all(target_os = "linux", target_env = "gnu"))] -pub fn glibc_version() -> Option<(usize, usize)> { - unsafe extern "C" { - fn gnu_get_libc_version() -> *const libc::c_char; - } - let version_cstr = unsafe { CStr::from_ptr(gnu_get_libc_version()) }; - if let Ok(version_str) = version_cstr.to_str() { - parse_glibc_version(version_str) - } else { - None - } -} - -// Returns Some((major, minor)) if the string is a valid "x.y" version, -// ignoring any extra dot-separated parts. Otherwise return None. -#[cfg(all(target_os = "linux", target_env = "gnu"))] -fn parse_glibc_version(version: &str) -> Option<(usize, usize)> { - let mut parsed_ints = version.split('.').map(str::parse::).fuse(); - match (parsed_ints.next(), parsed_ints.next()) { - (Some(Ok(major)), Some(Ok(minor))) => Some((major, minor)), - _ => None, - } -} diff --git a/std/src/sys/pal/zkvm/os.rs b/std/src/sys/paths/unsupported.rs similarity index 87% rename from std/src/sys/pal/zkvm/os.rs rename to std/src/sys/paths/unsupported.rs index cb925ef4348db..024830a254fd7 100644 --- a/std/src/sys/pal/zkvm/os.rs +++ b/std/src/sys/paths/unsupported.rs @@ -1,7 +1,7 @@ -use super::unsupported; use crate::ffi::{OsStr, OsString}; use crate::marker::PhantomData; use crate::path::{self, PathBuf}; +use crate::sys::pal::unsupported; use crate::{fmt, io}; pub fn getcwd() -> io::Result { @@ -55,11 +55,3 @@ pub fn temp_dir() -> PathBuf { pub fn home_dir() -> Option { None } - -pub fn exit(_code: i32) -> ! { - crate::intrinsics::abort() -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/std/src/sys/paths/wasi.rs b/std/src/sys/paths/wasi.rs new file mode 100644 index 0000000000000..1e1f951cd6793 --- /dev/null +++ b/std/src/sys/paths/wasi.rs @@ -0,0 +1,45 @@ +#![forbid(unsafe_op_in_unsafe_fn)] + +use crate::ffi::{CStr, OsString}; +use crate::io; +use crate::os::wasi::prelude::*; +use crate::path::{self, PathBuf}; +use crate::sys::helpers::run_path_with_cstr; + +pub fn getcwd() -> io::Result { + let mut buf = Vec::with_capacity(512); + loop { + unsafe { + let ptr = buf.as_mut_ptr() as *mut libc::c_char; + if !libc::getcwd(ptr, buf.capacity()).is_null() { + let len = CStr::from_ptr(buf.as_ptr() as *const libc::c_char).to_bytes().len(); + buf.set_len(len); + buf.shrink_to_fit(); + return Ok(PathBuf::from(OsString::from_vec(buf))); + } else { + let error = io::Error::last_os_error(); + if error.raw_os_error() != Some(libc::ERANGE) { + return Err(error); + } + } + + // Trigger the internal buffer resizing logic of `Vec` by requiring + // more space than the current capacity. + let cap = buf.capacity(); + buf.set_len(cap); + buf.reserve(1); + } + } +} + +pub fn chdir(p: &path::Path) -> io::Result<()> { + let result = run_path_with_cstr(p, &|p| unsafe { Ok(libc::chdir(p.as_ptr())) })?; + match result == (0 as libc::c_int) { + true => Ok(()), + false => Err(io::Error::last_os_error()), + } +} + +pub fn temp_dir() -> PathBuf { + panic!("not supported by WASI yet") +} diff --git a/std/src/sys/pal/windows/os.rs b/std/src/sys/paths/windows.rs similarity index 85% rename from std/src/sys/pal/windows/os.rs rename to std/src/sys/paths/windows.rs index 3eb6ec8278401..cfdc93847a97a 100644 --- a/std/src/sys/pal/windows/os.rs +++ b/std/src/sys/paths/windows.rs @@ -2,17 +2,13 @@ #![allow(nonstandard_style)] -#[cfg(test)] -mod tests; - -use super::api; -#[cfg(not(target_vendor = "uwp"))] -use super::api::WinError; use crate::ffi::{OsStr, OsString}; use crate::os::windows::ffi::EncodeWide; use crate::os::windows::prelude::*; use crate::path::{self, PathBuf}; -use crate::sys::pal::{c, cvt}; +#[cfg(not(target_vendor = "uwp"))] +use crate::sys::pal::api::WinError; +use crate::sys::pal::{api, c, cvt, fill_utf16_buf, os2path}; use crate::{fmt, io, ptr}; pub struct SplitPaths<'a> { @@ -56,11 +52,7 @@ impl<'a> Iterator for SplitPaths<'a> { } } - if !must_yield && in_progress.is_empty() { - None - } else { - Some(super::os2path(&in_progress)) - } + if !must_yield && in_progress.is_empty() { None } else { Some(os2path(&in_progress)) } } } @@ -104,14 +96,11 @@ impl fmt::Display for JoinPathsError { impl crate::error::Error for JoinPathsError {} pub fn current_exe() -> io::Result { - super::fill_utf16_buf( - |buf, sz| unsafe { c::GetModuleFileNameW(ptr::null_mut(), buf, sz) }, - super::os2path, - ) + fill_utf16_buf(|buf, sz| unsafe { c::GetModuleFileNameW(ptr::null_mut(), buf, sz) }, os2path) } pub fn getcwd() -> io::Result { - super::fill_utf16_buf(|buf, sz| unsafe { c::GetCurrentDirectoryW(sz, buf) }, super::os2path) + fill_utf16_buf(|buf, sz| unsafe { c::GetCurrentDirectoryW(sz, buf) }, os2path) } pub fn chdir(p: &path::Path) -> io::Result<()> { @@ -123,7 +112,7 @@ pub fn chdir(p: &path::Path) -> io::Result<()> { } pub fn temp_dir() -> PathBuf { - super::fill_utf16_buf(|buf, sz| unsafe { c::GetTempPath2W(sz, buf) }, super::os2path).unwrap() + fill_utf16_buf(|buf, sz| unsafe { c::GetTempPath2W(sz, buf) }, os2path).unwrap() } #[cfg(all(not(target_vendor = "uwp"), not(target_vendor = "win7")))] @@ -132,7 +121,7 @@ fn home_dir_crt() -> Option { // Defined in processthreadsapi.h. const CURRENT_PROCESS_TOKEN: usize = -4_isize as usize; - super::fill_utf16_buf( + fill_utf16_buf( |buf, mut sz| { // GetUserProfileDirectoryW does not quite use the usual protocol for // negotiating the buffer size, so we have to translate. @@ -146,7 +135,7 @@ fn home_dir_crt() -> Option { _ => sz - 1, // sz includes the null terminator } }, - super::os2path, + os2path, ) .ok() } @@ -163,7 +152,7 @@ fn home_dir_crt() -> Option { return None; } let _handle = Handle::from_raw_handle(token); - super::fill_utf16_buf( + fill_utf16_buf( |buf, mut sz| { match c::GetUserProfileDirectoryW(token, buf, &mut sz) { 0 if api::get_last_error() != WinError::INSUFFICIENT_BUFFER => 0, @@ -171,7 +160,7 @@ fn home_dir_crt() -> Option { _ => sz - 1, // sz includes the null terminator } }, - super::os2path, + os2path, ) .ok() } @@ -188,11 +177,3 @@ pub fn home_dir() -> Option { .map(PathBuf::from) .or_else(home_dir_crt) } - -pub fn exit(code: i32) -> ! { - unsafe { c::ExitProcess(code as u32) } -} - -pub fn getpid() -> u32 { - unsafe { c::GetCurrentProcessId() } -} diff --git a/std/src/sys/process/mod.rs b/std/src/sys/process/mod.rs index 121d3bc9d5c3c..46f4ebf6db421 100644 --- a/std/src/sys/process/mod.rs +++ b/std/src/sys/process/mod.rs @@ -27,9 +27,11 @@ cfg_select! { mod env; pub use env::CommandEnvs; +#[cfg(target_family = "unix")] +pub use imp::getppid; pub use imp::{ ChildPipe, Command, CommandArgs, EnvKey, ExitCode, ExitStatus, ExitStatusError, Process, Stdio, - read_output, + getpid, read_output, }; #[cfg(any( diff --git a/std/src/sys/process/motor.rs b/std/src/sys/process/motor.rs index a5d0184478904..133633f7bc67b 100644 --- a/std/src/sys/process/motor.rs +++ b/std/src/sys/process/motor.rs @@ -327,3 +327,7 @@ pub fn read_output( ) -> io::Result<()> { Err(io::Error::from_raw_os_error(moto_rt::E_NOT_IMPLEMENTED.into())) } + +pub fn getpid() -> u32 { + panic!("Pids on Motor OS are u64.") +} diff --git a/std/src/sys/process/uefi.rs b/std/src/sys/process/uefi.rs index 31914aeb67c59..88dd4c899b377 100644 --- a/std/src/sys/process/uefi.rs +++ b/std/src/sys/process/uefi.rs @@ -900,3 +900,7 @@ fn env_changes(env: &CommandEnv) -> Option, O Some(result) } + +pub fn getpid() -> u32 { + panic!("no pids on this platform") +} diff --git a/std/src/sys/process/unix/common.rs b/std/src/sys/process/unix/common.rs index f6bbfed61ef31..2d83782b7d0b9 100644 --- a/std/src/sys/process/unix/common.rs +++ b/std/src/sys/process/unix/common.rs @@ -679,3 +679,11 @@ pub fn read_output( } } } + +pub fn getpid() -> u32 { + unsafe { libc::getpid() as u32 } +} + +pub fn getppid() -> u32 { + unsafe { libc::getppid() as u32 } +} diff --git a/std/src/sys/process/unix/mod.rs b/std/src/sys/process/unix/mod.rs index 1938e8f4b737c..dafe7c8c76da5 100644 --- a/std/src/sys/process/unix/mod.rs +++ b/std/src/sys/process/unix/mod.rs @@ -23,5 +23,7 @@ cfg_select! { pub use imp::{ExitStatus, ExitStatusError, Process}; -pub use self::common::{ChildPipe, Command, CommandArgs, ExitCode, Stdio, read_output}; +pub use self::common::{ + ChildPipe, Command, CommandArgs, ExitCode, Stdio, getpid, getppid, read_output, +}; pub use crate::ffi::OsString as EnvKey; diff --git a/std/src/sys/process/unix/unix.rs b/std/src/sys/process/unix/unix.rs index 62d6e0581e6c8..a68be2543bc23 100644 --- a/std/src/sys/process/unix/unix.rs +++ b/std/src/sys/process/unix/unix.rs @@ -356,7 +356,7 @@ impl Command { // If -Zon-broken-pipe is not used, reset SIGPIPE to SIG_DFL for backward compatibility. // // -Zon-broken-pipe is an opportunity to change the default here. - if !crate::sys::pal::on_broken_pipe_flag_used() { + if !crate::sys::pal::on_broken_pipe_used() { #[cfg(target_os = "android")] // see issue #88585 { let mut action: libc::sigaction = mem::zeroed(); @@ -455,7 +455,7 @@ impl Command { use core::sync::atomic::{Atomic, AtomicU8, Ordering}; use crate::mem::MaybeUninit; - use crate::sys::{self, cvt_nz, on_broken_pipe_flag_used}; + use crate::sys::{self, cvt_nz, on_broken_pipe_used}; if self.get_gid().is_some() || self.get_uid().is_some() @@ -537,7 +537,7 @@ impl Command { // Only glibc 2.24+ posix_spawn() supports returning ENOENT directly. #[cfg(all(target_os = "linux", target_env = "gnu"))] { - if let Some(version) = sys::os::glibc_version() { + if let Some(version) = sys::pal::conf::glibc_version() { if version < (2, 24) { return Ok(None); } @@ -731,7 +731,7 @@ impl Command { // If -Zon-broken-pipe is not used, reset SIGPIPE to SIG_DFL for backward compatibility. // // -Zon-broken-pipe is an opportunity to change the default here. - if !on_broken_pipe_flag_used() { + if !on_broken_pipe_used() { let mut default_set = MaybeUninit::::uninit(); cvt(sigemptyset(default_set.as_mut_ptr()))?; cvt(sigaddset(default_set.as_mut_ptr(), libc::SIGPIPE))?; diff --git a/std/src/sys/process/unsupported.rs b/std/src/sys/process/unsupported.rs index 455c38e55b7ba..9ed66a559117c 100644 --- a/std/src/sys/process/unsupported.rs +++ b/std/src/sys/process/unsupported.rs @@ -327,3 +327,7 @@ pub fn read_output( ) -> io::Result<()> { match out.diverge() {} } + +pub fn getpid() -> u32 { + panic!("no pids on this platform") +} diff --git a/std/src/sys/process/windows.rs b/std/src/sys/process/windows.rs index b40833ad212c4..deb4243d314e2 100644 --- a/std/src/sys/process/windows.rs +++ b/std/src/sys/process/windows.rs @@ -976,3 +976,7 @@ impl<'a> fmt::Debug for CommandArgs<'a> { f.debug_list().entries(self.iter.clone()).finish() } } + +pub fn getpid() -> u32 { + unsafe { c::GetCurrentProcessId() } +} diff --git a/std/src/sys/sync/condvar/xous.rs b/std/src/sys/sync/condvar/xous.rs index 21a1587214a11..5d1b14443c62a 100644 --- a/std/src/sys/sync/condvar/xous.rs +++ b/std/src/sys/sync/condvar/xous.rs @@ -38,7 +38,7 @@ impl Condvar { // possible for `counter` to decrease due to a condvar timing out, in which // case the corresponding `timed_out` will increase accordingly. let Ok(waiter_count) = - self.counter.fetch_update(Ordering::Relaxed, Ordering::Relaxed, |counter| { + self.counter.try_update(Ordering::Relaxed, Ordering::Relaxed, |counter| { if counter == 0 { return None; } else { diff --git a/std/src/sys/sync/once/futex.rs b/std/src/sys/sync/once/futex.rs index 096f1d879ef26..236bc9ca4b7c7 100644 --- a/std/src/sys/sync/once/futex.rs +++ b/std/src/sys/sync/once/futex.rs @@ -75,6 +75,11 @@ impl Once { Once { state_and_queued: Futex::new(INCOMPLETE) } } + #[inline] + pub const fn new_complete() -> Once { + Once { state_and_queued: Futex::new(COMPLETE) } + } + #[inline] pub fn is_completed(&self) -> bool { // Use acquire ordering to make all initialization changes visible to the diff --git a/std/src/sys/sync/once/mod.rs b/std/src/sys/sync/once/mod.rs index aeea884b9f617..5796c6d207dba 100644 --- a/std/src/sys/sync/once/mod.rs +++ b/std/src/sys/sync/once/mod.rs @@ -12,7 +12,7 @@ cfg_select! { all(target_os = "windows", not(target_vendor="win7")), target_os = "linux", target_os = "android", - all(target_arch = "wasm32", target_feature = "atomics"), + all(target_family = "wasm", target_feature = "atomics"), target_os = "freebsd", target_os = "motor", target_os = "openbsd", diff --git a/std/src/sys/sync/once/no_threads.rs b/std/src/sys/sync/once/no_threads.rs index 576bbf644cbed..42fe2417307aa 100644 --- a/std/src/sys/sync/once/no_threads.rs +++ b/std/src/sys/sync/once/no_threads.rs @@ -39,6 +39,11 @@ impl Once { Once { state: Cell::new(State::Incomplete) } } + #[inline] + pub const fn new_complete() -> Once { + Once { state: Cell::new(State::Complete) } + } + #[inline] pub fn is_completed(&self) -> bool { self.state.get() == State::Complete diff --git a/std/src/sys/sync/once/queue.rs b/std/src/sys/sync/once/queue.rs index d7219a7361cff..f64f6523d1432 100644 --- a/std/src/sys/sync/once/queue.rs +++ b/std/src/sys/sync/once/queue.rs @@ -121,6 +121,11 @@ impl Once { Once { state_and_queue: AtomicPtr::new(ptr::without_provenance_mut(INCOMPLETE)) } } + #[inline] + pub const fn new_complete() -> Once { + Once { state_and_queue: AtomicPtr::new(ptr::without_provenance_mut(COMPLETE)) } + } + #[inline] pub fn is_completed(&self) -> bool { // An `Acquire` load is enough because that makes all the initialization diff --git a/std/src/sys/sync/rwlock/futex.rs b/std/src/sys/sync/rwlock/futex.rs index 961819cae8d6e..0e8e954de0758 100644 --- a/std/src/sys/sync/rwlock/futex.rs +++ b/std/src/sys/sync/rwlock/futex.rs @@ -86,7 +86,7 @@ impl RwLock { #[inline] pub fn try_read(&self) -> bool { self.state - .fetch_update(Acquire, Relaxed, |s| is_read_lockable(s).then(|| s + READ_LOCKED)) + .try_update(Acquire, Relaxed, |s| is_read_lockable(s).then(|| s + READ_LOCKED)) .is_ok() } @@ -164,7 +164,7 @@ impl RwLock { #[inline] pub fn try_write(&self) -> bool { self.state - .fetch_update(Acquire, Relaxed, |s| is_unlocked(s).then(|| s + WRITE_LOCKED)) + .try_update(Acquire, Relaxed, |s| is_unlocked(s).then(|| s + WRITE_LOCKED)) .is_ok() } diff --git a/std/src/sys/sync/rwlock/no_threads.rs b/std/src/sys/sync/rwlock/no_threads.rs index 573d0d602dbd6..6b919bde80bb5 100644 --- a/std/src/sys/sync/rwlock/no_threads.rs +++ b/std/src/sys/sync/rwlock/no_threads.rs @@ -37,8 +37,10 @@ impl RwLock { #[inline] pub fn write(&self) { - if self.mode.replace(-1) != 0 { - rtabort!("rwlock locked for reading") + if self.mode.get() == 0 { + self.mode.set(-1); + } else { + rtabort!("rwlock locked for reading"); } } diff --git a/std/src/sys/sync/rwlock/queue.rs b/std/src/sys/sync/rwlock/queue.rs index 62f084acfd259..b41a65f7303b2 100644 --- a/std/src/sys/sync/rwlock/queue.rs +++ b/std/src/sys/sync/rwlock/queue.rs @@ -329,7 +329,7 @@ impl RwLock { #[inline] pub fn try_read(&self) -> bool { - self.state.fetch_update(Acquire, Relaxed, read_lock).is_ok() + self.state.try_update(Acquire, Relaxed, read_lock).is_ok() } #[inline] @@ -343,7 +343,7 @@ impl RwLock { pub fn try_write(&self) -> bool { // Atomically set the `LOCKED` bit. This is lowered to a single atomic instruction on most // modern processors (e.g. "lock bts" on x86 and "ldseta" on modern AArch64), and therefore - // is more efficient than `fetch_update(lock(true))`, which can spuriously fail if a new + // is more efficient than `try_update(lock(true))`, which can spuriously fail if a new // node is appended to the queue. self.state.fetch_or(LOCKED, Acquire).addr() & LOCKED == 0 } @@ -453,7 +453,7 @@ impl RwLock { #[inline] pub unsafe fn read_unlock(&self) { - match self.state.fetch_update(Release, Acquire, |state| { + match self.state.try_update(Release, Acquire, |state| { if state.addr() & QUEUED == 0 { // If there are no threads queued, simply decrement the reader count. let count = state.addr() - (SINGLE | LOCKED); diff --git a/std/src/sys/sync/thread_parking/mod.rs b/std/src/sys/sync/thread_parking/mod.rs index 74b5b72b19a75..9d5a0a996b115 100644 --- a/std/src/sys/sync/thread_parking/mod.rs +++ b/std/src/sys/sync/thread_parking/mod.rs @@ -3,7 +3,7 @@ cfg_select! { all(target_os = "windows", not(target_vendor = "win7")), target_os = "linux", target_os = "android", - all(target_arch = "wasm32", target_feature = "atomics"), + all(target_family = "wasm", target_feature = "atomics"), target_os = "freebsd", target_os = "openbsd", target_os = "dragonfly", diff --git a/std/src/sys/thread/teeos.rs b/std/src/sys/thread/teeos.rs index 5e71f757eaa4b..aa679e780c18c 100644 --- a/std/src/sys/thread/teeos.rs +++ b/std/src/sys/thread/teeos.rs @@ -1,5 +1,5 @@ use crate::mem::{self, ManuallyDrop}; -use crate::sys::os; +use crate::sys::pal::conf; use crate::thread::ThreadInit; use crate::time::Duration; use crate::{cmp, io, ptr}; @@ -52,7 +52,7 @@ impl Thread { // multiple of the system page size. Because it's definitely // >= PTHREAD_STACK_MIN, it must be an alignment issue. // Round up to the nearest page and try again. - let page_size = os::page_size(); + let page_size = conf::page_size(); let stack_size = (stack_size + page_size - 1) & (-(page_size as isize - 1) as usize - 1); assert_eq!(unsafe { libc::pthread_attr_setstacksize(&mut attr, stack_size) }, 0); diff --git a/std/src/sys/thread/unix.rs b/std/src/sys/thread/unix.rs index b758737d00c64..2f3ef1741cdfc 100644 --- a/std/src/sys/thread/unix.rs +++ b/std/src/sys/thread/unix.rs @@ -44,15 +44,6 @@ impl Thread { // unsafe: see thread::Builder::spawn_unchecked for safety requirements #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub unsafe fn new(stack: usize, init: Box) -> io::Result { - // FIXME: remove this block once wasi-sdk is updated with the fix from - // https://github.com/WebAssembly/wasi-libc/pull/716 - // WASI does not support threading via pthreads. While wasi-libc provides - // pthread stubs, pthread_create returns EAGAIN, which causes confusing - // errors. We return UNSUPPORTED_PLATFORM directly instead. - if cfg!(all(target_os = "wasi", not(target_feature = "atomics"))) { - return Err(io::Error::UNSUPPORTED_PLATFORM); - } - let data = init; let mut attr: mem::MaybeUninit = mem::MaybeUninit::uninit(); assert_eq!(libc::pthread_attr_init(attr.as_mut_ptr()), 0); @@ -85,7 +76,7 @@ impl Thread { // multiple of the system page size. Because it's definitely // >= PTHREAD_STACK_MIN, it must be an alignment issue. // Round up to the nearest page and try again. - let page_size = sys::os::page_size(); + let page_size = sys::pal::conf::page_size(); let stack_size = (stack_size + page_size - 1) & (-(page_size as isize - 1) as usize - 1); @@ -579,10 +570,10 @@ pub fn sleep(dur: Duration) { // nanosleep will fill in `ts` with the remaining time. unsafe { while secs > 0 || nsecs > 0 { - let mut ts = libc::timespec { - tv_sec: cmp::min(libc::time_t::MAX as u64, secs) as libc::time_t, - tv_nsec: nsecs, - }; + let mut ts = libc::timespec::default(); + ts.tv_sec = cmp::min(libc::time_t::MAX as u64, secs) as libc::time_t; + ts.tv_nsec = nsecs; + secs -= ts.tv_sec as u64; let ts_ptr = &raw mut ts; let r = nanosleep(ts_ptr, ts_ptr); diff --git a/std/src/sys/thread_local/os.rs b/std/src/sys/thread_local/os.rs index 3f06c9bd1d774..e1d9d80c97b62 100644 --- a/std/src/sys/thread_local/os.rs +++ b/std/src/sys/thread_local/os.rs @@ -62,25 +62,7 @@ pub macro thread_local_inner { // by translating it into a `cfg`ed block and recursing. // https://doc.rust-lang.org/reference/conditional-compilation.html#railroad-ConfigurationPredicate - (@align $final_align:ident, cfg_attr(true, $($cfg_rhs:tt)*) $(, $($attr_rest:tt)+)?) => { - #[cfg(true)] - { - $crate::thread::local_impl::thread_local_inner!(@align $final_align, $($cfg_rhs)*); - } - - $($crate::thread::local_impl::thread_local_inner!(@align $final_align, $($attr_rest)+);)? - }, - - (@align $final_align:ident, cfg_attr(false, $($cfg_rhs:tt)*) $(, $($attr_rest:tt)+)?) => { - #[cfg(false)] - { - $crate::thread::local_impl::thread_local_inner!(@align $final_align, $($cfg_rhs)*); - } - - $($crate::thread::local_impl::thread_local_inner!(@align $final_align, $($attr_rest)+);)? - }, - - (@align $final_align:ident, cfg_attr($cfg_pred:meta, $($cfg_rhs:tt)*) $(, $($attr_rest:tt)+)?) => { + (@align $final_align:ident, cfg_attr($cfg_pred:expr, $($cfg_rhs:tt)*) $(, $($attr_rest:tt)+)?) => { #[cfg($cfg_pred)] { $crate::thread::local_impl::thread_local_inner!(@align $final_align, $($cfg_rhs)*); diff --git a/std/src/sys/time/hermit.rs b/std/src/sys/time/hermit.rs index 18ece2e3010d0..4e8e5dfe21c8a 100644 --- a/std/src/sys/time/hermit.rs +++ b/std/src/sys/time/hermit.rs @@ -1,18 +1,21 @@ use hermit_abi::{self, CLOCK_MONOTONIC, CLOCK_REALTIME}; -use crate::hash::Hash; +use crate::io; use crate::sys::pal::time::Timespec; use crate::time::Duration; +fn clock_gettime(clock: hermit_abi::clockid_t) -> Timespec { + let mut t = hermit_abi::timespec { tv_sec: 0, tv_nsec: 0 }; + unsafe { hermit_abi::clock_gettime(clock, &raw mut t) }.unwrap(); + Timespec::new(t.tv_sec, t.tv_nsec.into()).unwrap() +} + #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)] pub struct Instant(Timespec); impl Instant { pub fn now() -> Instant { - let mut time: Timespec = Timespec::zero(); - let _ = unsafe { hermit_abi::clock_gettime(CLOCK_MONOTONIC, &raw mut time.t) }; - - Instant(time) + Instant(clock_gettime(CLOCK_MONOTONIC)) } pub fn checked_sub_instant(&self, other: &Instant) -> Option { @@ -38,15 +41,12 @@ impl SystemTime { pub const MIN: SystemTime = SystemTime(Timespec::MIN); - pub fn new(tv_sec: i64, tv_nsec: i32) -> SystemTime { - SystemTime(Timespec::new(tv_sec, tv_nsec)) + pub fn new(tv_sec: i64, tv_nsec: i64) -> Result { + Ok(SystemTime(Timespec::new(tv_sec, tv_nsec)?)) } pub fn now() -> SystemTime { - let mut time: Timespec = Timespec::zero(); - let _ = unsafe { hermit_abi::clock_gettime(CLOCK_REALTIME, &raw mut time.t) }; - - SystemTime(time) + SystemTime(clock_gettime(CLOCK_REALTIME)) } pub fn sub_time(&self, other: &SystemTime) -> Result { diff --git a/std/src/thread/functions.rs b/std/src/thread/functions.rs index 95d7aaf518408..70642108e1e01 100644 --- a/std/src/thread/functions.rs +++ b/std/src/thread/functions.rs @@ -168,7 +168,11 @@ pub fn yield_now() { imp::yield_now() } -/// Determines whether the current thread is unwinding because of panic. +/// Determines whether the current thread is panicking. +/// +/// This returns `true` both when the thread is unwinding due to a panic, +/// or executing a panic hook. Note that the latter case will still happen +/// when `panic=abort` is set. /// /// A common use of this feature is to poison shared resources when writing /// unsafe code, by checking `panicking` when the `drop` is called. @@ -309,14 +313,14 @@ pub fn sleep(dur: Duration) { /// /// | Platform | System call | /// |-----------|----------------------------------------------------------------------| -/// | Linux | [clock_nanosleep] (Monotonic clock) | -/// | BSD except OpenBSD | [clock_nanosleep] (Monotonic Clock)] | -/// | Android | [clock_nanosleep] (Monotonic Clock)] | -/// | Solaris | [clock_nanosleep] (Monotonic Clock)] | -/// | Illumos | [clock_nanosleep] (Monotonic Clock)] | -/// | Dragonfly | [clock_nanosleep] (Monotonic Clock)] | -/// | Hurd | [clock_nanosleep] (Monotonic Clock)] | -/// | Vxworks | [clock_nanosleep] (Monotonic Clock)] | +/// | Linux | [clock_nanosleep] (Monotonic Clock) | +/// | BSD except OpenBSD | [clock_nanosleep] (Monotonic Clock) | +/// | Android | [clock_nanosleep] (Monotonic Clock) | +/// | Solaris | [clock_nanosleep] (Monotonic Clock) | +/// | Illumos | [clock_nanosleep] (Monotonic Clock) | +/// | Dragonfly | [clock_nanosleep] (Monotonic Clock) | +/// | Hurd | [clock_nanosleep] (Monotonic Clock) | +/// | Vxworks | [clock_nanosleep] (Monotonic Clock) | /// | Apple | `mach_wait_until` | /// | Other | `sleep_until` uses [`sleep`] and does not issue a syscall itself | /// diff --git a/std/src/thread/local.rs b/std/src/thread/local.rs index 1318d8dc27809..5de001838faff 100644 --- a/std/src/thread/local.rs +++ b/std/src/thread/local.rs @@ -198,41 +198,10 @@ pub macro thread_local_process_attrs { ); ), - // it's a nested `cfg_attr(true, ...)`; recurse into RHS - ( - [$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; - @processing_cfg_attr { pred: ($($predicate:tt)*), rhs: [cfg_attr(true, $($cfg_rhs:tt)*) $(, $($attr_rhs:tt)*)?] }; - $($rest:tt)* - ) => ( - $crate::thread::local_impl::thread_local_process_attrs!( - [] []; - @processing_cfg_attr { pred: (true), rhs: [$($cfg_rhs)*] }; - [$($prev_align_attrs)*] [$($prev_other_attrs)*]; - @processing_cfg_attr { pred: ($($predicate)*), rhs: [$($($attr_rhs)*)?] }; - $($rest)* - ); - ), - - // it's a nested `cfg_attr(false, ...)`; recurse into RHS - ( - [$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; - @processing_cfg_attr { pred: ($($predicate:tt)*), rhs: [cfg_attr(false, $($cfg_rhs:tt)*) $(, $($attr_rhs:tt)*)?] }; - $($rest:tt)* - ) => ( - $crate::thread::local_impl::thread_local_process_attrs!( - [] []; - @processing_cfg_attr { pred: (false), rhs: [$($cfg_rhs)*] }; - [$($prev_align_attrs)*] [$($prev_other_attrs)*]; - @processing_cfg_attr { pred: ($($predicate)*), rhs: [$($($attr_rhs)*)?] }; - $($rest)* - ); - ), - - // it's a nested `cfg_attr(..., ...)`; recurse into RHS ( [$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; - @processing_cfg_attr { pred: ($($predicate:tt)*), rhs: [cfg_attr($cfg_lhs:meta, $($cfg_rhs:tt)*) $(, $($attr_rhs:tt)*)?] }; + @processing_cfg_attr { pred: ($($predicate:tt)*), rhs: [cfg_attr($cfg_lhs:expr, $($cfg_rhs:tt)*) $(, $($attr_rhs:tt)*)?] }; $($rest:tt)* ) => ( $crate::thread::local_impl::thread_local_process_attrs!( @@ -268,28 +237,8 @@ pub macro thread_local_process_attrs { ); ), - // `cfg_attr(true, ...)` attribute; parse it - ([$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; #[cfg_attr(true, $($cfg_rhs:tt)*)] $($rest:tt)*) => ( - $crate::thread::local_impl::thread_local_process_attrs!( - [] []; - @processing_cfg_attr { pred: (true), rhs: [$($cfg_rhs)*] }; - [$($prev_align_attrs)*] [$($prev_other_attrs)*]; - $($rest)* - ); - ), - - // `cfg_attr(false, ...)` attribute; parse it - ([$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; #[cfg_attr(false, $($cfg_rhs:tt)*)] $($rest:tt)*) => ( - $crate::thread::local_impl::thread_local_process_attrs!( - [] []; - @processing_cfg_attr { pred: (false), rhs: [$($cfg_rhs)*] }; - [$($prev_align_attrs)*] [$($prev_other_attrs)*]; - $($rest)* - ); - ), - // `cfg_attr(..., ...)` attribute; parse it - ([$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; #[cfg_attr($cfg_pred:meta, $($cfg_rhs:tt)*)] $($rest:tt)*) => ( + ([$($prev_align_attrs:tt)*] [$($prev_other_attrs:tt)*]; #[cfg_attr($cfg_pred:expr, $($cfg_rhs:tt)*)] $($rest:tt)*) => ( $crate::thread::local_impl::thread_local_process_attrs!( [] []; @processing_cfg_attr { pred: ($cfg_pred), rhs: [$($cfg_rhs)*] }; diff --git a/std/tests/env.rs b/std/tests/env.rs index b53fd69b7070b..9d624d5592ce7 100644 --- a/std/tests/env.rs +++ b/std/tests/env.rs @@ -59,6 +59,23 @@ fn split_paths_unix() { assert!(check_parse("/:/usr/local", &mut ["/", "/usr/local"])); } +#[test] +#[cfg(target_os = "uefi")] +fn split_paths_uefi() { + use std::path::PathBuf; + + fn check_parse(unparsed: &str, parsed: &[&str]) -> bool { + split_paths(unparsed).collect::>() + == parsed.iter().map(|s| PathBuf::from(*s)).collect::>() + } + + assert!(check_parse("", &mut [""])); + assert!(check_parse(";;", &mut ["", "", ""])); + assert!(check_parse(r"fs0:\", &mut [r"fs0:\"])); + assert!(check_parse(r"fs0:\;", &mut [r"fs0:\", ""])); + assert!(check_parse(r"fs0:\;fs0:\boot\", &mut [r"fs0:\", r"fs0:\boot\"])); +} + #[test] #[cfg(unix)] fn join_paths_unix() { diff --git a/std/tests/env_modify.rs b/std/tests/env_modify.rs index 4cd87bf7a0027..3404ca537acca 100644 --- a/std/tests/env_modify.rs +++ b/std/tests/env_modify.rs @@ -1,6 +1,5 @@ // These tests are in a separate integration test as they modify the environment, // and would otherwise cause some other tests to fail. -#![feature(cfg_select)] use std::env::*; use std::ffi::{OsStr, OsString}; diff --git a/std/tests/floats/f128.rs b/std/tests/floats/f128.rs deleted file mode 100644 index d20762023caf1..0000000000000 --- a/std/tests/floats/f128.rs +++ /dev/null @@ -1,320 +0,0 @@ -#![cfg(target_has_reliable_f128)] - -use std::f128::consts; -use std::ops::{Add, Div, Mul, Sub}; - -// Note these tolerances make sense around zero, but not for more extreme exponents. - -/// Default tolerances. Works for values that should be near precise but not exact. Roughly -/// the precision carried by `100 * 100`. -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -const TOL: f128 = 1e-12; - -/// For operations that are near exact, usually not involving math of different -/// signs. -const TOL_PRECISE: f128 = 1e-28; - -/// Tolerances for math that is allowed to be imprecise, usually due to multiple chained -/// operations. -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -const TOL_IMPR: f128 = 1e-10; - -/// Compare by representation -#[allow(unused_macros)] -macro_rules! assert_f128_biteq { - ($a:expr, $b:expr) => { - let (l, r): (&f128, &f128) = (&$a, &$b); - let lb = l.to_bits(); - let rb = r.to_bits(); - assert_eq!(lb, rb, "float {l:?} is not bitequal to {r:?}.\na: {lb:#034x}\nb: {rb:#034x}"); - }; -} - -#[test] -fn test_num_f128() { - // FIXME(f128): replace with a `test_num` call once the required `fmodl`/`fmodf128` - // function is available on all platforms. - let ten = 10f128; - let two = 2f128; - assert_eq!(ten.add(two), ten + two); - assert_eq!(ten.sub(two), ten - two); - assert_eq!(ten.mul(two), ten * two); - assert_eq!(ten.div(two), ten / two); -} - -// Many math functions allow for less accurate results, so the next tolerance up is used - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_powf() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_eq!(1.0f128.powf(1.0), 1.0); - assert_approx_eq!(3.4f128.powf(4.5), 246.40818323761892815995637964326426756, TOL_IMPR); - assert_approx_eq!(2.7f128.powf(-3.2), 0.041652009108526178281070304373500889273, TOL_IMPR); - assert_approx_eq!((-3.1f128).powf(2.0), 9.6100000000000005506706202140776519387, TOL_IMPR); - assert_approx_eq!(5.9f128.powf(-2.0), 0.028727377190462507313100483690639638451, TOL_IMPR); - assert_eq!(8.3f128.powf(0.0), 1.0); - assert!(nan.powf(2.0).is_nan()); - assert_eq!(inf.powf(2.0), inf); - assert_eq!(neg_inf.powf(3.0), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_exp() { - assert_eq!(1.0, 0.0f128.exp()); - assert_approx_eq!(consts::E, 1.0f128.exp(), TOL); - assert_approx_eq!(148.41315910257660342111558004055227962348775, 5.0f128.exp(), TOL); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(inf, inf.exp()); - assert_eq!(0.0, neg_inf.exp()); - assert!(nan.exp().is_nan()); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_exp2() { - assert_eq!(32.0, 5.0f128.exp2()); - assert_eq!(1.0, 0.0f128.exp2()); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(inf, inf.exp2()); - assert_eq!(0.0, neg_inf.exp2()); - assert!(nan.exp2().is_nan()); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_ln() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_approx_eq!(1.0f128.exp().ln(), 1.0, TOL); - assert!(nan.ln().is_nan()); - assert_eq!(inf.ln(), inf); - assert!(neg_inf.ln().is_nan()); - assert!((-2.3f128).ln().is_nan()); - assert_eq!((-0.0f128).ln(), neg_inf); - assert_eq!(0.0f128.ln(), neg_inf); - assert_approx_eq!(4.0f128.ln(), 1.3862943611198906188344642429163531366, TOL); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_log() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_eq!(10.0f128.log(10.0), 1.0); - assert_approx_eq!(2.3f128.log(3.5), 0.66485771361478710036766645911922010272, TOL); - assert_eq!(1.0f128.exp().log(1.0f128.exp()), 1.0); - assert!(1.0f128.log(1.0).is_nan()); - assert!(1.0f128.log(-13.9).is_nan()); - assert!(nan.log(2.3).is_nan()); - assert_eq!(inf.log(10.0), inf); - assert!(neg_inf.log(8.8).is_nan()); - assert!((-2.3f128).log(0.1).is_nan()); - assert_eq!((-0.0f128).log(2.0), neg_inf); - assert_eq!(0.0f128.log(7.0), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_log2() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_approx_eq!(10.0f128.log2(), 3.32192809488736234787031942948939017, TOL); - assert_approx_eq!(2.3f128.log2(), 1.2016338611696504130002982471978765921, TOL); - assert_approx_eq!(1.0f128.exp().log2(), 1.4426950408889634073599246810018921381, TOL); - assert!(nan.log2().is_nan()); - assert_eq!(inf.log2(), inf); - assert!(neg_inf.log2().is_nan()); - assert!((-2.3f128).log2().is_nan()); - assert_eq!((-0.0f128).log2(), neg_inf); - assert_eq!(0.0f128.log2(), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_log10() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_eq!(10.0f128.log10(), 1.0); - assert_approx_eq!(2.3f128.log10(), 0.36172783601759284532595218865859309898, TOL); - assert_approx_eq!(1.0f128.exp().log10(), 0.43429448190325182765112891891660508222, TOL); - assert_eq!(1.0f128.log10(), 0.0); - assert!(nan.log10().is_nan()); - assert_eq!(inf.log10(), inf); - assert!(neg_inf.log10().is_nan()); - assert!((-2.3f128).log10().is_nan()); - assert_eq!((-0.0f128).log10(), neg_inf); - assert_eq!(0.0f128.log10(), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_asinh() { - // Lower accuracy results are allowed, use increased tolerances - assert_eq!(0.0f128.asinh(), 0.0f128); - assert_eq!((-0.0f128).asinh(), -0.0f128); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(inf.asinh(), inf); - assert_eq!(neg_inf.asinh(), neg_inf); - assert!(nan.asinh().is_nan()); - assert!((-0.0f128).asinh().is_sign_negative()); - - // issue 63271 - assert_approx_eq!(2.0f128.asinh(), 1.443635475178810342493276740273105f128, TOL_IMPR); - assert_approx_eq!((-2.0f128).asinh(), -1.443635475178810342493276740273105f128, TOL_IMPR); - // regression test for the catastrophic cancellation fixed in 72486 - assert_approx_eq!( - (-67452098.07139316f128).asinh(), - -18.720075426274544393985484294000831757220, - TOL_IMPR - ); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f128, 60.0f128.sinh().asinh(), TOL_IMPR); - // mul needed for approximate comparison to be meaningful - assert_approx_eq!(1.0f128, 1e-15f128.sinh().asinh() * 1e15f128, TOL_IMPR); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_acosh() { - assert_eq!(1.0f128.acosh(), 0.0f128); - assert!(0.999f128.acosh().is_nan()); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(inf.acosh(), inf); - assert!(neg_inf.acosh().is_nan()); - assert!(nan.acosh().is_nan()); - assert_approx_eq!(2.0f128.acosh(), 1.31695789692481670862504634730796844f128, TOL_IMPR); - assert_approx_eq!(3.0f128.acosh(), 1.76274717403908605046521864995958461f128, TOL_IMPR); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f128, 60.0f128.cosh().acosh(), TOL_IMPR); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_atanh() { - assert_eq!(0.0f128.atanh(), 0.0f128); - assert_eq!((-0.0f128).atanh(), -0.0f128); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(1.0f128.atanh(), inf); - assert_eq!((-1.0f128).atanh(), neg_inf); - assert!(2f128.atanh().atanh().is_nan()); - assert!((-2f128).atanh().atanh().is_nan()); - assert!(inf.atanh().is_nan()); - assert!(neg_inf.atanh().is_nan()); - assert!(nan.atanh().is_nan()); - assert_approx_eq!(0.5f128.atanh(), 0.54930614433405484569762261846126285f128, TOL_IMPR); - assert_approx_eq!((-0.5f128).atanh(), -0.54930614433405484569762261846126285f128, TOL_IMPR); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_gamma() { - // precision can differ among platforms - assert_approx_eq!(1.0f128.gamma(), 1.0f128, TOL_IMPR); - assert_approx_eq!(2.0f128.gamma(), 1.0f128, TOL_IMPR); - assert_approx_eq!(3.0f128.gamma(), 2.0f128, TOL_IMPR); - assert_approx_eq!(4.0f128.gamma(), 6.0f128, TOL_IMPR); - assert_approx_eq!(5.0f128.gamma(), 24.0f128, TOL_IMPR); - assert_approx_eq!(0.5f128.gamma(), consts::PI.sqrt(), TOL_IMPR); - assert_approx_eq!((-0.5f128).gamma(), -2.0 * consts::PI.sqrt(), TOL_IMPR); - assert_eq!(0.0f128.gamma(), f128::INFINITY); - assert_eq!((-0.0f128).gamma(), f128::NEG_INFINITY); - assert!((-1.0f128).gamma().is_nan()); - assert!((-2.0f128).gamma().is_nan()); - assert!(f128::NAN.gamma().is_nan()); - assert!(f128::NEG_INFINITY.gamma().is_nan()); - assert_eq!(f128::INFINITY.gamma(), f128::INFINITY); - assert_eq!(1760.9f128.gamma(), f128::INFINITY); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_ln_gamma() { - assert_approx_eq!(1.0f128.ln_gamma().0, 0.0f128, TOL_IMPR); - assert_eq!(1.0f128.ln_gamma().1, 1); - assert_approx_eq!(2.0f128.ln_gamma().0, 0.0f128, TOL_IMPR); - assert_eq!(2.0f128.ln_gamma().1, 1); - assert_approx_eq!(3.0f128.ln_gamma().0, 2.0f128.ln(), TOL_IMPR); - assert_eq!(3.0f128.ln_gamma().1, 1); - assert_approx_eq!((-0.5f128).ln_gamma().0, (2.0 * consts::PI.sqrt()).ln(), TOL_IMPR); - assert_eq!((-0.5f128).ln_gamma().1, -1); -} - -#[test] -fn test_real_consts() { - let pi: f128 = consts::PI; - let frac_pi_2: f128 = consts::FRAC_PI_2; - let frac_pi_3: f128 = consts::FRAC_PI_3; - let frac_pi_4: f128 = consts::FRAC_PI_4; - let frac_pi_6: f128 = consts::FRAC_PI_6; - let frac_pi_8: f128 = consts::FRAC_PI_8; - let frac_1_pi: f128 = consts::FRAC_1_PI; - let frac_2_pi: f128 = consts::FRAC_2_PI; - - assert_approx_eq!(frac_pi_2, pi / 2f128, TOL_PRECISE); - assert_approx_eq!(frac_pi_3, pi / 3f128, TOL_PRECISE); - assert_approx_eq!(frac_pi_4, pi / 4f128, TOL_PRECISE); - assert_approx_eq!(frac_pi_6, pi / 6f128, TOL_PRECISE); - assert_approx_eq!(frac_pi_8, pi / 8f128, TOL_PRECISE); - assert_approx_eq!(frac_1_pi, 1f128 / pi, TOL_PRECISE); - assert_approx_eq!(frac_2_pi, 2f128 / pi, TOL_PRECISE); - - #[cfg(not(miri))] - #[cfg(target_has_reliable_f128_math)] - { - let frac_2_sqrtpi: f128 = consts::FRAC_2_SQRT_PI; - let sqrt2: f128 = consts::SQRT_2; - let frac_1_sqrt2: f128 = consts::FRAC_1_SQRT_2; - let e: f128 = consts::E; - let log2_e: f128 = consts::LOG2_E; - let log10_e: f128 = consts::LOG10_E; - let ln_2: f128 = consts::LN_2; - let ln_10: f128 = consts::LN_10; - - assert_approx_eq!(frac_2_sqrtpi, 2f128 / pi.sqrt(), TOL_PRECISE); - assert_approx_eq!(sqrt2, 2f128.sqrt(), TOL_PRECISE); - assert_approx_eq!(frac_1_sqrt2, 1f128 / 2f128.sqrt(), TOL_PRECISE); - assert_approx_eq!(log2_e, e.log2(), TOL_PRECISE); - assert_approx_eq!(log10_e, e.log10(), TOL_PRECISE); - assert_approx_eq!(ln_2, 2f128.ln(), TOL_PRECISE); - assert_approx_eq!(ln_10, 10f128.ln(), TOL_PRECISE); - } -} diff --git a/std/tests/floats/f16.rs b/std/tests/floats/f16.rs deleted file mode 100644 index cc0960765f411..0000000000000 --- a/std/tests/floats/f16.rs +++ /dev/null @@ -1,297 +0,0 @@ -#![cfg(target_has_reliable_f16)] - -use std::f16::consts; - -/// Tolerance for results on the order of 10.0e-2 -#[allow(unused)] -const TOL_N2: f16 = 0.0001; - -/// Tolerance for results on the order of 10.0e+0 -#[allow(unused)] -const TOL_0: f16 = 0.01; - -/// Tolerance for results on the order of 10.0e+2 -#[allow(unused)] -const TOL_P2: f16 = 0.5; - -/// Tolerance for results on the order of 10.0e+4 -#[allow(unused)] -const TOL_P4: f16 = 10.0; - -/// Compare by representation -#[allow(unused_macros)] -macro_rules! assert_f16_biteq { - ($a:expr, $b:expr) => { - let (l, r): (&f16, &f16) = (&$a, &$b); - let lb = l.to_bits(); - let rb = r.to_bits(); - assert_eq!(lb, rb, "float {l:?} ({lb:#04x}) is not bitequal to {r:?} ({rb:#04x})"); - }; -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_powf() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_eq!(1.0f16.powf(1.0), 1.0); - assert_approx_eq!(3.4f16.powf(4.5), 246.408183, TOL_P2); - assert_approx_eq!(2.7f16.powf(-3.2), 0.041652, TOL_N2); - assert_approx_eq!((-3.1f16).powf(2.0), 9.61, TOL_P2); - assert_approx_eq!(5.9f16.powf(-2.0), 0.028727, TOL_N2); - assert_eq!(8.3f16.powf(0.0), 1.0); - assert!(nan.powf(2.0).is_nan()); - assert_eq!(inf.powf(2.0), inf); - assert_eq!(neg_inf.powf(3.0), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_exp() { - assert_eq!(1.0, 0.0f16.exp()); - assert_approx_eq!(2.718282, 1.0f16.exp(), TOL_0); - assert_approx_eq!(148.413159, 5.0f16.exp(), TOL_0); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(inf, inf.exp()); - assert_eq!(0.0, neg_inf.exp()); - assert!(nan.exp().is_nan()); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_exp2() { - assert_eq!(32.0, 5.0f16.exp2()); - assert_eq!(1.0, 0.0f16.exp2()); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(inf, inf.exp2()); - assert_eq!(0.0, neg_inf.exp2()); - assert!(nan.exp2().is_nan()); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_ln() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_approx_eq!(1.0f16.exp().ln(), 1.0, TOL_0); - assert!(nan.ln().is_nan()); - assert_eq!(inf.ln(), inf); - assert!(neg_inf.ln().is_nan()); - assert!((-2.3f16).ln().is_nan()); - assert_eq!((-0.0f16).ln(), neg_inf); - assert_eq!(0.0f16.ln(), neg_inf); - assert_approx_eq!(4.0f16.ln(), 1.386294, TOL_0); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_log() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_eq!(10.0f16.log(10.0), 1.0); - assert_approx_eq!(2.3f16.log(3.5), 0.664858, TOL_0); - assert_eq!(1.0f16.exp().log(1.0f16.exp()), 1.0); - assert!(1.0f16.log(1.0).is_nan()); - assert!(1.0f16.log(-13.9).is_nan()); - assert!(nan.log(2.3).is_nan()); - assert_eq!(inf.log(10.0), inf); - assert!(neg_inf.log(8.8).is_nan()); - assert!((-2.3f16).log(0.1).is_nan()); - assert_eq!((-0.0f16).log(2.0), neg_inf); - assert_eq!(0.0f16.log(7.0), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_log2() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_approx_eq!(10.0f16.log2(), 3.321928, TOL_0); - assert_approx_eq!(2.3f16.log2(), 1.201634, TOL_0); - assert_approx_eq!(1.0f16.exp().log2(), 1.442695, TOL_0); - assert!(nan.log2().is_nan()); - assert_eq!(inf.log2(), inf); - assert!(neg_inf.log2().is_nan()); - assert!((-2.3f16).log2().is_nan()); - assert_eq!((-0.0f16).log2(), neg_inf); - assert_eq!(0.0f16.log2(), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_log10() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_eq!(10.0f16.log10(), 1.0); - assert_approx_eq!(2.3f16.log10(), 0.361728, TOL_0); - assert_approx_eq!(1.0f16.exp().log10(), 0.434294, TOL_0); - assert_eq!(1.0f16.log10(), 0.0); - assert!(nan.log10().is_nan()); - assert_eq!(inf.log10(), inf); - assert!(neg_inf.log10().is_nan()); - assert!((-2.3f16).log10().is_nan()); - assert_eq!((-0.0f16).log10(), neg_inf); - assert_eq!(0.0f16.log10(), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_asinh() { - assert_eq!(0.0f16.asinh(), 0.0f16); - assert_eq!((-0.0f16).asinh(), -0.0f16); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(inf.asinh(), inf); - assert_eq!(neg_inf.asinh(), neg_inf); - assert!(nan.asinh().is_nan()); - assert!((-0.0f16).asinh().is_sign_negative()); - // issue 63271 - assert_approx_eq!(2.0f16.asinh(), 1.443635475178810342493276740273105f16, TOL_0); - assert_approx_eq!((-2.0f16).asinh(), -1.443635475178810342493276740273105f16, TOL_0); - // regression test for the catastrophic cancellation fixed in 72486 - assert_approx_eq!((-200.0f16).asinh(), -5.991470797049389, TOL_0); - - // test for low accuracy from issue 104548 - assert_approx_eq!(10.0f16, 10.0f16.sinh().asinh(), TOL_0); - // mul needed for approximate comparison to be meaningful - assert_approx_eq!(1.0f16, 1e-3f16.sinh().asinh() * 1e3f16, TOL_0); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_acosh() { - assert_eq!(1.0f16.acosh(), 0.0f16); - assert!(0.999f16.acosh().is_nan()); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(inf.acosh(), inf); - assert!(neg_inf.acosh().is_nan()); - assert!(nan.acosh().is_nan()); - assert_approx_eq!(2.0f16.acosh(), 1.31695789692481670862504634730796844f16, TOL_0); - assert_approx_eq!(3.0f16.acosh(), 1.76274717403908605046521864995958461f16, TOL_0); - - // test for low accuracy from issue 104548 - assert_approx_eq!(10.0f16, 10.0f16.cosh().acosh(), TOL_P2); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_atanh() { - assert_eq!(0.0f16.atanh(), 0.0f16); - assert_eq!((-0.0f16).atanh(), -0.0f16); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(1.0f16.atanh(), inf); - assert_eq!((-1.0f16).atanh(), neg_inf); - assert!(2f16.atanh().atanh().is_nan()); - assert!((-2f16).atanh().atanh().is_nan()); - assert!(inf.atanh().is_nan()); - assert!(neg_inf.atanh().is_nan()); - assert!(nan.atanh().is_nan()); - assert_approx_eq!(0.5f16.atanh(), 0.54930614433405484569762261846126285f16, TOL_0); - assert_approx_eq!((-0.5f16).atanh(), -0.54930614433405484569762261846126285f16, TOL_0); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_gamma() { - // precision can differ among platforms - assert_approx_eq!(1.0f16.gamma(), 1.0f16, TOL_0); - assert_approx_eq!(2.0f16.gamma(), 1.0f16, TOL_0); - assert_approx_eq!(3.0f16.gamma(), 2.0f16, TOL_0); - assert_approx_eq!(4.0f16.gamma(), 6.0f16, TOL_0); - assert_approx_eq!(5.0f16.gamma(), 24.0f16, TOL_0); - assert_approx_eq!(0.5f16.gamma(), consts::PI.sqrt(), TOL_0); - assert_approx_eq!((-0.5f16).gamma(), -2.0 * consts::PI.sqrt(), TOL_0); - assert_eq!(0.0f16.gamma(), f16::INFINITY); - assert_eq!((-0.0f16).gamma(), f16::NEG_INFINITY); - assert!((-1.0f16).gamma().is_nan()); - assert!((-2.0f16).gamma().is_nan()); - assert!(f16::NAN.gamma().is_nan()); - assert!(f16::NEG_INFINITY.gamma().is_nan()); - assert_eq!(f16::INFINITY.gamma(), f16::INFINITY); - assert_eq!(171.71f16.gamma(), f16::INFINITY); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_ln_gamma() { - assert_approx_eq!(1.0f16.ln_gamma().0, 0.0f16, TOL_0); - assert_eq!(1.0f16.ln_gamma().1, 1); - assert_approx_eq!(2.0f16.ln_gamma().0, 0.0f16, TOL_0); - assert_eq!(2.0f16.ln_gamma().1, 1); - assert_approx_eq!(3.0f16.ln_gamma().0, 2.0f16.ln(), TOL_0); - assert_eq!(3.0f16.ln_gamma().1, 1); - assert_approx_eq!((-0.5f16).ln_gamma().0, (2.0 * consts::PI.sqrt()).ln(), TOL_0); - assert_eq!((-0.5f16).ln_gamma().1, -1); -} - -#[test] -fn test_real_consts() { - let pi: f16 = consts::PI; - let frac_pi_2: f16 = consts::FRAC_PI_2; - let frac_pi_3: f16 = consts::FRAC_PI_3; - let frac_pi_4: f16 = consts::FRAC_PI_4; - let frac_pi_6: f16 = consts::FRAC_PI_6; - let frac_pi_8: f16 = consts::FRAC_PI_8; - let frac_1_pi: f16 = consts::FRAC_1_PI; - let frac_2_pi: f16 = consts::FRAC_2_PI; - - assert_approx_eq!(frac_pi_2, pi / 2f16, TOL_0); - assert_approx_eq!(frac_pi_3, pi / 3f16, TOL_0); - assert_approx_eq!(frac_pi_4, pi / 4f16, TOL_0); - assert_approx_eq!(frac_pi_6, pi / 6f16, TOL_0); - assert_approx_eq!(frac_pi_8, pi / 8f16, TOL_0); - assert_approx_eq!(frac_1_pi, 1f16 / pi, TOL_0); - assert_approx_eq!(frac_2_pi, 2f16 / pi, TOL_0); - - #[cfg(not(miri))] - #[cfg(target_has_reliable_f16_math)] - { - let frac_2_sqrtpi: f16 = consts::FRAC_2_SQRT_PI; - let sqrt2: f16 = consts::SQRT_2; - let frac_1_sqrt2: f16 = consts::FRAC_1_SQRT_2; - let e: f16 = consts::E; - let log2_e: f16 = consts::LOG2_E; - let log10_e: f16 = consts::LOG10_E; - let ln_2: f16 = consts::LN_2; - let ln_10: f16 = consts::LN_10; - - assert_approx_eq!(frac_2_sqrtpi, 2f16 / pi.sqrt(), TOL_0); - assert_approx_eq!(sqrt2, 2f16.sqrt(), TOL_0); - assert_approx_eq!(frac_1_sqrt2, 1f16 / 2f16.sqrt(), TOL_0); - assert_approx_eq!(log2_e, e.log2(), TOL_0); - assert_approx_eq!(log10_e, e.log10(), TOL_0); - assert_approx_eq!(ln_2, 2f16.ln(), TOL_0); - assert_approx_eq!(ln_10, 10f16.ln(), TOL_0); - } -} diff --git a/std/tests/floats/f32.rs b/std/tests/floats/f32.rs deleted file mode 100644 index 3acd067091415..0000000000000 --- a/std/tests/floats/f32.rs +++ /dev/null @@ -1,258 +0,0 @@ -use std::f32::consts; - -/// Miri adds some extra errors to float functions; make sure the tests still pass. -/// These values are purely used as a canary to test against and are thus not a stable guarantee Rust provides. -/// They serve as a way to get an idea of the real precision of floating point operations on different platforms. -const APPROX_DELTA: f32 = if cfg!(miri) { 1e-3 } else { 1e-6 }; - -#[allow(unused_macros)] -macro_rules! assert_f32_biteq { - ($left : expr, $right : expr) => { - let l: &f32 = &$left; - let r: &f32 = &$right; - let lb = l.to_bits(); - let rb = r.to_bits(); - assert_eq!(lb, rb, "float {l} ({lb:#010x}) is not bitequal to {r} ({rb:#010x})"); - }; -} - -#[test] -fn test_powf() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_eq!(1.0f32.powf(1.0), 1.0); - assert_approx_eq!(3.4f32.powf(4.5), 246.408218, APPROX_DELTA); - assert_approx_eq!(2.7f32.powf(-3.2), 0.041652); - assert_approx_eq!((-3.1f32).powf(2.0), 9.61, APPROX_DELTA); - assert_approx_eq!(5.9f32.powf(-2.0), 0.028727); - assert_eq!(8.3f32.powf(0.0), 1.0); - assert!(nan.powf(2.0).is_nan()); - assert_eq!(inf.powf(2.0), inf); - assert_eq!(neg_inf.powf(3.0), neg_inf); -} - -#[test] -fn test_exp() { - assert_eq!(1.0, 0.0f32.exp()); - assert_approx_eq!(2.718282, 1.0f32.exp(), APPROX_DELTA); - assert_approx_eq!(148.413162, 5.0f32.exp(), APPROX_DELTA); - - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - let nan: f32 = f32::NAN; - assert_eq!(inf, inf.exp()); - assert_eq!(0.0, neg_inf.exp()); - assert!(nan.exp().is_nan()); -} - -#[test] -fn test_exp2() { - assert_approx_eq!(32.0, 5.0f32.exp2(), APPROX_DELTA); - assert_eq!(1.0, 0.0f32.exp2()); - - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - let nan: f32 = f32::NAN; - assert_eq!(inf, inf.exp2()); - assert_eq!(0.0, neg_inf.exp2()); - assert!(nan.exp2().is_nan()); -} - -#[test] -fn test_ln() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_approx_eq!(1.0f32.exp().ln(), 1.0); - assert!(nan.ln().is_nan()); - assert_eq!(inf.ln(), inf); - assert!(neg_inf.ln().is_nan()); - assert!((-2.3f32).ln().is_nan()); - assert_eq!((-0.0f32).ln(), neg_inf); - assert_eq!(0.0f32.ln(), neg_inf); - assert_approx_eq!(4.0f32.ln(), 1.386294, APPROX_DELTA); -} - -#[test] -fn test_log() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_approx_eq!(10.0f32.log(10.0), 1.0); - assert_approx_eq!(2.3f32.log(3.5), 0.664858); - assert_approx_eq!(1.0f32.exp().log(1.0f32.exp()), 1.0, APPROX_DELTA); - assert!(1.0f32.log(1.0).is_nan()); - assert!(1.0f32.log(-13.9).is_nan()); - assert!(nan.log(2.3).is_nan()); - assert_eq!(inf.log(10.0), inf); - assert!(neg_inf.log(8.8).is_nan()); - assert!((-2.3f32).log(0.1).is_nan()); - assert_eq!((-0.0f32).log(2.0), neg_inf); - assert_eq!(0.0f32.log(7.0), neg_inf); -} - -#[test] -fn test_log2() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_approx_eq!(10.0f32.log2(), 3.321928, APPROX_DELTA); - assert_approx_eq!(2.3f32.log2(), 1.201634); - assert_approx_eq!(1.0f32.exp().log2(), 1.442695, APPROX_DELTA); - assert!(nan.log2().is_nan()); - assert_eq!(inf.log2(), inf); - assert!(neg_inf.log2().is_nan()); - assert!((-2.3f32).log2().is_nan()); - assert_eq!((-0.0f32).log2(), neg_inf); - assert_eq!(0.0f32.log2(), neg_inf); -} - -#[test] -fn test_log10() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_approx_eq!(10.0f32.log10(), 1.0); - assert_approx_eq!(2.3f32.log10(), 0.361728); - assert_approx_eq!(1.0f32.exp().log10(), 0.434294); - assert_eq!(1.0f32.log10(), 0.0); - assert!(nan.log10().is_nan()); - assert_eq!(inf.log10(), inf); - assert!(neg_inf.log10().is_nan()); - assert!((-2.3f32).log10().is_nan()); - assert_eq!((-0.0f32).log10(), neg_inf); - assert_eq!(0.0f32.log10(), neg_inf); -} - -#[test] -fn test_asinh() { - assert_eq!(0.0f32.asinh(), 0.0f32); - assert_eq!((-0.0f32).asinh(), -0.0f32); - - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - let nan: f32 = f32::NAN; - assert_eq!(inf.asinh(), inf); - assert_eq!(neg_inf.asinh(), neg_inf); - assert!(nan.asinh().is_nan()); - assert!((-0.0f32).asinh().is_sign_negative()); // issue 63271 - assert_approx_eq!(2.0f32.asinh(), 1.443635475178810342493276740273105f32); - assert_approx_eq!((-2.0f32).asinh(), -1.443635475178810342493276740273105f32); - // regression test for the catastrophic cancellation fixed in 72486 - assert_approx_eq!((-3000.0f32).asinh(), -8.699514775987968673236893537700647f32, APPROX_DELTA); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f32, 60.0f32.sinh().asinh(), APPROX_DELTA); - // mul needed for approximate comparison to be meaningful - assert_approx_eq!(1.0f32, 1e-15f32.sinh().asinh() * 1e15f32); -} - -#[test] -fn test_acosh() { - assert_eq!(1.0f32.acosh(), 0.0f32); - assert!(0.999f32.acosh().is_nan()); - - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - let nan: f32 = f32::NAN; - assert_eq!(inf.acosh(), inf); - assert!(neg_inf.acosh().is_nan()); - assert!(nan.acosh().is_nan()); - assert_approx_eq!(2.0f32.acosh(), 1.31695789692481670862504634730796844f32); - assert_approx_eq!(3.0f32.acosh(), 1.76274717403908605046521864995958461f32); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f32, 60.0f32.cosh().acosh(), APPROX_DELTA); -} - -#[test] -fn test_atanh() { - assert_eq!(0.0f32.atanh(), 0.0f32); - assert_eq!((-0.0f32).atanh(), -0.0f32); - - let inf32: f32 = f32::INFINITY; - let neg_inf32: f32 = f32::NEG_INFINITY; - assert_eq!(1.0f32.atanh(), inf32); - assert_eq!((-1.0f32).atanh(), neg_inf32); - - assert!(2f64.atanh().atanh().is_nan()); - assert!((-2f64).atanh().atanh().is_nan()); - - let inf64: f32 = f32::INFINITY; - let neg_inf64: f32 = f32::NEG_INFINITY; - let nan32: f32 = f32::NAN; - assert!(inf64.atanh().is_nan()); - assert!(neg_inf64.atanh().is_nan()); - assert!(nan32.atanh().is_nan()); - - assert_approx_eq!(0.5f32.atanh(), 0.54930614433405484569762261846126285f32); - assert_approx_eq!((-0.5f32).atanh(), -0.54930614433405484569762261846126285f32); -} - -#[test] -fn test_gamma() { - // precision can differ between platforms - assert_approx_eq!(1.0f32.gamma(), 1.0f32, APPROX_DELTA); - assert_approx_eq!(2.0f32.gamma(), 1.0f32, APPROX_DELTA); - assert_approx_eq!(3.0f32.gamma(), 2.0f32, APPROX_DELTA); - assert_approx_eq!(4.0f32.gamma(), 6.0f32, APPROX_DELTA); - assert_approx_eq!(5.0f32.gamma(), 24.0f32, APPROX_DELTA); - assert_approx_eq!(0.5f32.gamma(), consts::PI.sqrt(), APPROX_DELTA); - assert_approx_eq!((-0.5f32).gamma(), -2.0 * consts::PI.sqrt(), APPROX_DELTA); - assert_eq!(0.0f32.gamma(), f32::INFINITY); - assert_eq!((-0.0f32).gamma(), f32::NEG_INFINITY); - assert!((-1.0f32).gamma().is_nan()); - assert!((-2.0f32).gamma().is_nan()); - assert!(f32::NAN.gamma().is_nan()); - assert!(f32::NEG_INFINITY.gamma().is_nan()); - assert_eq!(f32::INFINITY.gamma(), f32::INFINITY); - assert_eq!(171.71f32.gamma(), f32::INFINITY); -} - -#[test] -fn test_ln_gamma() { - assert_approx_eq!(1.0f32.ln_gamma().0, 0.0f32); - assert_eq!(1.0f32.ln_gamma().1, 1); - assert_approx_eq!(2.0f32.ln_gamma().0, 0.0f32); - assert_eq!(2.0f32.ln_gamma().1, 1); - assert_approx_eq!(3.0f32.ln_gamma().0, 2.0f32.ln()); - assert_eq!(3.0f32.ln_gamma().1, 1); - assert_approx_eq!((-0.5f32).ln_gamma().0, (2.0 * consts::PI.sqrt()).ln(), APPROX_DELTA); - assert_eq!((-0.5f32).ln_gamma().1, -1); -} - -#[test] -fn test_real_consts() { - let pi: f32 = consts::PI; - let frac_pi_2: f32 = consts::FRAC_PI_2; - let frac_pi_3: f32 = consts::FRAC_PI_3; - let frac_pi_4: f32 = consts::FRAC_PI_4; - let frac_pi_6: f32 = consts::FRAC_PI_6; - let frac_pi_8: f32 = consts::FRAC_PI_8; - let frac_1_pi: f32 = consts::FRAC_1_PI; - let frac_2_pi: f32 = consts::FRAC_2_PI; - let frac_2_sqrtpi: f32 = consts::FRAC_2_SQRT_PI; - let sqrt2: f32 = consts::SQRT_2; - let frac_1_sqrt2: f32 = consts::FRAC_1_SQRT_2; - let e: f32 = consts::E; - let log2_e: f32 = consts::LOG2_E; - let log10_e: f32 = consts::LOG10_E; - let ln_2: f32 = consts::LN_2; - let ln_10: f32 = consts::LN_10; - - assert_approx_eq!(frac_pi_2, pi / 2f32); - assert_approx_eq!(frac_pi_3, pi / 3f32, APPROX_DELTA); - assert_approx_eq!(frac_pi_4, pi / 4f32); - assert_approx_eq!(frac_pi_6, pi / 6f32); - assert_approx_eq!(frac_pi_8, pi / 8f32); - assert_approx_eq!(frac_1_pi, 1f32 / pi); - assert_approx_eq!(frac_2_pi, 2f32 / pi); - assert_approx_eq!(frac_2_sqrtpi, 2f32 / pi.sqrt()); - assert_approx_eq!(sqrt2, 2f32.sqrt()); - assert_approx_eq!(frac_1_sqrt2, 1f32 / 2f32.sqrt()); - assert_approx_eq!(log2_e, e.log2()); - assert_approx_eq!(log10_e, e.log10()); - assert_approx_eq!(ln_2, 2f32.ln()); - assert_approx_eq!(ln_10, 10f32.ln(), APPROX_DELTA); -} diff --git a/std/tests/floats/f64.rs b/std/tests/floats/f64.rs deleted file mode 100644 index fccf20097278b..0000000000000 --- a/std/tests/floats/f64.rs +++ /dev/null @@ -1,249 +0,0 @@ -use std::f64::consts; - -#[allow(unused_macros)] -macro_rules! assert_f64_biteq { - ($left : expr, $right : expr) => { - let l: &f64 = &$left; - let r: &f64 = &$right; - let lb = l.to_bits(); - let rb = r.to_bits(); - assert_eq!(lb, rb, "float {l} ({lb:#018x}) is not bitequal to {r} ({rb:#018x})"); - }; -} - -#[test] -fn test_powf() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_eq!(1.0f64.powf(1.0), 1.0); - assert_approx_eq!(3.4f64.powf(4.5), 246.408183); - assert_approx_eq!(2.7f64.powf(-3.2), 0.041652); - assert_approx_eq!((-3.1f64).powf(2.0), 9.61); - assert_approx_eq!(5.9f64.powf(-2.0), 0.028727); - assert_eq!(8.3f64.powf(0.0), 1.0); - assert!(nan.powf(2.0).is_nan()); - assert_eq!(inf.powf(2.0), inf); - assert_eq!(neg_inf.powf(3.0), neg_inf); -} - -#[test] -fn test_exp() { - assert_eq!(1.0, 0.0f64.exp()); - assert_approx_eq!(2.718282, 1.0f64.exp()); - assert_approx_eq!(148.413159, 5.0f64.exp()); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(inf, inf.exp()); - assert_eq!(0.0, neg_inf.exp()); - assert!(nan.exp().is_nan()); -} - -#[test] -fn test_exp2() { - assert_approx_eq!(32.0, 5.0f64.exp2()); - assert_eq!(1.0, 0.0f64.exp2()); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(inf, inf.exp2()); - assert_eq!(0.0, neg_inf.exp2()); - assert!(nan.exp2().is_nan()); -} - -#[test] -fn test_ln() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_approx_eq!(1.0f64.exp().ln(), 1.0); - assert!(nan.ln().is_nan()); - assert_eq!(inf.ln(), inf); - assert!(neg_inf.ln().is_nan()); - assert!((-2.3f64).ln().is_nan()); - assert_eq!((-0.0f64).ln(), neg_inf); - assert_eq!(0.0f64.ln(), neg_inf); - assert_approx_eq!(4.0f64.ln(), 1.386294); -} - -#[test] -fn test_log() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_approx_eq!(10.0f64.log(10.0), 1.0); - assert_approx_eq!(2.3f64.log(3.5), 0.664858); - assert_approx_eq!(1.0f64.exp().log(1.0f64.exp()), 1.0); - assert!(1.0f64.log(1.0).is_nan()); - assert!(1.0f64.log(-13.9).is_nan()); - assert!(nan.log(2.3).is_nan()); - assert_eq!(inf.log(10.0), inf); - assert!(neg_inf.log(8.8).is_nan()); - assert!((-2.3f64).log(0.1).is_nan()); - assert_eq!((-0.0f64).log(2.0), neg_inf); - assert_eq!(0.0f64.log(7.0), neg_inf); -} - -#[test] -fn test_log2() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_approx_eq!(10.0f64.log2(), 3.321928); - assert_approx_eq!(2.3f64.log2(), 1.201634); - assert_approx_eq!(1.0f64.exp().log2(), 1.442695); - assert!(nan.log2().is_nan()); - assert_eq!(inf.log2(), inf); - assert!(neg_inf.log2().is_nan()); - assert!((-2.3f64).log2().is_nan()); - assert_eq!((-0.0f64).log2(), neg_inf); - assert_eq!(0.0f64.log2(), neg_inf); -} - -#[test] -fn test_log10() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_approx_eq!(10.0f64.log10(), 1.0); - assert_approx_eq!(2.3f64.log10(), 0.361728); - assert_approx_eq!(1.0f64.exp().log10(), 0.434294); - assert_eq!(1.0f64.log10(), 0.0); - assert!(nan.log10().is_nan()); - assert_eq!(inf.log10(), inf); - assert!(neg_inf.log10().is_nan()); - assert!((-2.3f64).log10().is_nan()); - assert_eq!((-0.0f64).log10(), neg_inf); - assert_eq!(0.0f64.log10(), neg_inf); -} - -#[test] -fn test_asinh() { - assert_eq!(0.0f64.asinh(), 0.0f64); - assert_eq!((-0.0f64).asinh(), -0.0f64); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(inf.asinh(), inf); - assert_eq!(neg_inf.asinh(), neg_inf); - assert!(nan.asinh().is_nan()); - assert!((-0.0f64).asinh().is_sign_negative()); - // issue 63271 - assert_approx_eq!(2.0f64.asinh(), 1.443635475178810342493276740273105f64); - assert_approx_eq!((-2.0f64).asinh(), -1.443635475178810342493276740273105f64); - // regression test for the catastrophic cancellation fixed in 72486 - assert_approx_eq!((-67452098.07139316f64).asinh(), -18.72007542627454439398548429400083); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f64, 60.0f64.sinh().asinh()); - // mul needed for approximate comparison to be meaningful - assert_approx_eq!(1.0f64, 1e-15f64.sinh().asinh() * 1e15f64); -} - -#[test] -fn test_acosh() { - assert_eq!(1.0f64.acosh(), 0.0f64); - assert!(0.999f64.acosh().is_nan()); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(inf.acosh(), inf); - assert!(neg_inf.acosh().is_nan()); - assert!(nan.acosh().is_nan()); - assert_approx_eq!(2.0f64.acosh(), 1.31695789692481670862504634730796844f64); - assert_approx_eq!(3.0f64.acosh(), 1.76274717403908605046521864995958461f64); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f64, 60.0f64.cosh().acosh()); -} - -#[test] -fn test_atanh() { - assert_eq!(0.0f64.atanh(), 0.0f64); - assert_eq!((-0.0f64).atanh(), -0.0f64); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(1.0f64.atanh(), inf); - assert_eq!((-1.0f64).atanh(), neg_inf); - assert!(2f64.atanh().atanh().is_nan()); - assert!((-2f64).atanh().atanh().is_nan()); - assert!(inf.atanh().is_nan()); - assert!(neg_inf.atanh().is_nan()); - assert!(nan.atanh().is_nan()); - assert_approx_eq!(0.5f64.atanh(), 0.54930614433405484569762261846126285f64); - assert_approx_eq!((-0.5f64).atanh(), -0.54930614433405484569762261846126285f64); -} - -#[test] -fn test_gamma() { - // precision can differ between platforms - assert_approx_eq!(1.0f64.gamma(), 1.0f64); - assert_approx_eq!(2.0f64.gamma(), 1.0f64); - assert_approx_eq!(3.0f64.gamma(), 2.0f64); - assert_approx_eq!(4.0f64.gamma(), 6.0f64); - assert_approx_eq!(5.0f64.gamma(), 24.0f64); - assert_approx_eq!(0.5f64.gamma(), consts::PI.sqrt()); - assert_approx_eq!((-0.5f64).gamma(), -2.0 * consts::PI.sqrt()); - assert_eq!(0.0f64.gamma(), f64::INFINITY); - assert_eq!((-0.0f64).gamma(), f64::NEG_INFINITY); - assert!((-1.0f64).gamma().is_nan()); - assert!((-2.0f64).gamma().is_nan()); - assert!(f64::NAN.gamma().is_nan()); - assert!(f64::NEG_INFINITY.gamma().is_nan()); - assert_eq!(f64::INFINITY.gamma(), f64::INFINITY); - assert_eq!(171.71f64.gamma(), f64::INFINITY); -} - -#[test] -fn test_ln_gamma() { - assert_approx_eq!(1.0f64.ln_gamma().0, 0.0f64); - assert_eq!(1.0f64.ln_gamma().1, 1); - assert_approx_eq!(2.0f64.ln_gamma().0, 0.0f64); - assert_eq!(2.0f64.ln_gamma().1, 1); - assert_approx_eq!(3.0f64.ln_gamma().0, 2.0f64.ln()); - assert_eq!(3.0f64.ln_gamma().1, 1); - assert_approx_eq!((-0.5f64).ln_gamma().0, (2.0 * consts::PI.sqrt()).ln()); - assert_eq!((-0.5f64).ln_gamma().1, -1); -} - -#[test] -fn test_real_consts() { - let pi: f64 = consts::PI; - let frac_pi_2: f64 = consts::FRAC_PI_2; - let frac_pi_3: f64 = consts::FRAC_PI_3; - let frac_pi_4: f64 = consts::FRAC_PI_4; - let frac_pi_6: f64 = consts::FRAC_PI_6; - let frac_pi_8: f64 = consts::FRAC_PI_8; - let frac_1_pi: f64 = consts::FRAC_1_PI; - let frac_2_pi: f64 = consts::FRAC_2_PI; - let frac_2_sqrtpi: f64 = consts::FRAC_2_SQRT_PI; - let sqrt2: f64 = consts::SQRT_2; - let frac_1_sqrt2: f64 = consts::FRAC_1_SQRT_2; - let e: f64 = consts::E; - let log2_e: f64 = consts::LOG2_E; - let log10_e: f64 = consts::LOG10_E; - let ln_2: f64 = consts::LN_2; - let ln_10: f64 = consts::LN_10; - - assert_approx_eq!(frac_pi_2, pi / 2f64); - assert_approx_eq!(frac_pi_3, pi / 3f64); - assert_approx_eq!(frac_pi_4, pi / 4f64); - assert_approx_eq!(frac_pi_6, pi / 6f64); - assert_approx_eq!(frac_pi_8, pi / 8f64); - assert_approx_eq!(frac_1_pi, 1f64 / pi); - assert_approx_eq!(frac_2_pi, 2f64 / pi); - assert_approx_eq!(frac_2_sqrtpi, 2f64 / pi.sqrt()); - assert_approx_eq!(sqrt2, 2f64.sqrt()); - assert_approx_eq!(frac_1_sqrt2, 1f64 / 2f64.sqrt()); - assert_approx_eq!(log2_e, e.log2()); - assert_approx_eq!(log10_e, e.log10()); - assert_approx_eq!(ln_2, 2f64.ln()); - assert_approx_eq!(ln_10, 10f64.ln()); -} diff --git a/std/tests/floats/lib.rs b/std/tests/floats/lib.rs deleted file mode 100644 index 8bb8eb4bfc1ae..0000000000000 --- a/std/tests/floats/lib.rs +++ /dev/null @@ -1,43 +0,0 @@ -#![feature(f16, f128, float_gamma, float_minimum_maximum, cfg_target_has_reliable_f16_f128)] -#![expect(internal_features)] // for reliable_f16_f128 - -use std::fmt; -use std::ops::{Add, Div, Mul, Rem, Sub}; - -/// Verify that floats are within a tolerance of each other, 1.0e-6 by default. -macro_rules! assert_approx_eq { - ($a:expr, $b:expr) => {{ assert_approx_eq!($a, $b, 1.0e-6) }}; - ($a:expr, $b:expr, $lim:expr) => {{ - let (a, b) = (&$a, &$b); - let diff = (*a - *b).abs(); - assert!( - diff <= $lim, - "{a:?} is not approximately equal to {b:?} (threshold {lim:?}, difference {diff:?})", - lim = $lim - ); - }}; -} - -/// Helper function for testing numeric operations -pub fn test_num(ten: T, two: T) -where - T: PartialEq - + Add - + Sub - + Mul - + Div - + Rem - + fmt::Debug - + Copy, -{ - assert_eq!(ten.add(two), ten + two); - assert_eq!(ten.sub(two), ten - two); - assert_eq!(ten.mul(two), ten * two); - assert_eq!(ten.div(two), ten / two); - assert_eq!(ten.rem(two), ten % two); -} - -mod f128; -mod f16; -mod f32; -mod f64; diff --git a/std/tests/path.rs b/std/tests/path.rs index 4094b7acd8749..8997b8ad192dc 100644 --- a/std/tests/path.rs +++ b/std/tests/path.rs @@ -2291,6 +2291,26 @@ fn display_format_flags() { assert_eq!(format!("a{:#<5}b", Path::new("a").display()), "aa####b"); } +#[test] +fn display_path_with_padding_no_align() { + assert_eq!(format!("{:10}", Path::new("/foo/bar").display()), "/foo/bar "); +} + +#[test] +fn display_path_with_padding_align_left() { + assert_eq!(format!("{:<10}", Path::new("/foo/bar").display()), "/foo/bar "); +} + +#[test] +fn display_path_with_padding_align_right() { + assert_eq!(format!("{:>10}", Path::new("/foo/bar").display()), " /foo/bar"); +} + +#[test] +fn display_path_with_padding_align_center() { + assert_eq!(format!("{:^10}", Path::new("/foo/bar").display()), " /foo/bar "); +} + #[test] fn into_rc() { let orig = "hello/world"; diff --git a/std/tests/sync/mpmc.rs b/std/tests/sync/mpmc.rs index bf80ab96a88bd..db221ff15890e 100644 --- a/std/tests/sync/mpmc.rs +++ b/std/tests/sync/mpmc.rs @@ -475,7 +475,6 @@ fn stress_recv_timeout_two_threads() { }); let mut recv_count = 0; - let mut got_timeout = false; loop { match rx.recv_timeout(timeout) { Ok(n) => { @@ -483,7 +482,6 @@ fn stress_recv_timeout_two_threads() { recv_count += 1; } Err(RecvTimeoutError::Timeout) => { - got_timeout = true; continue; } Err(RecvTimeoutError::Disconnected) => break, @@ -491,7 +489,6 @@ fn stress_recv_timeout_two_threads() { } assert_eq!(recv_count, stress); - assert!(got_timeout); } #[test] diff --git a/std/tests/sync/mpsc.rs b/std/tests/sync/mpsc.rs index 9de4a71987b8e..4dc4b955da7c2 100644 --- a/std/tests/sync/mpsc.rs +++ b/std/tests/sync/mpsc.rs @@ -438,7 +438,6 @@ fn stress_recv_timeout_two_threads() { }); let mut recv_count = 0; - let mut got_timeout = false; loop { match rx.recv_timeout(timeout) { Ok(n) => { @@ -446,7 +445,6 @@ fn stress_recv_timeout_two_threads() { recv_count += 1; } Err(RecvTimeoutError::Timeout) => { - got_timeout = true; continue; } Err(RecvTimeoutError::Disconnected) => break, @@ -454,7 +452,6 @@ fn stress_recv_timeout_two_threads() { } assert_eq!(recv_count, stress); - assert!(got_timeout); } #[test] diff --git a/std/tests/sync/oneshot.rs b/std/tests/sync/oneshot.rs index 6a87c72b9cb5b..6eaacfbc6497d 100644 --- a/std/tests/sync/oneshot.rs +++ b/std/tests/sync/oneshot.rs @@ -89,15 +89,15 @@ fn send_before_recv_timeout() { assert!(sender.send(22i128).is_ok()); - let start = Instant::now(); - let timeout = Duration::from_secs(1); match receiver.recv_timeout(timeout) { Ok(22) => {} _ => panic!("expected Ok(22)"), } - assert!(start.elapsed() < timeout); + // FIXME(#152648): There previously was a timing assertion here. + // This was removed, because under load there's no guarantee that the main thread is + // scheduled and run before `timeout` expires } #[test] @@ -127,6 +127,7 @@ fn recv_before_send() { } #[test] +#[ignore = "Inherently flaky and has caused several CI failures"] fn recv_timeout_before_send() { let (sender, receiver) = oneshot::channel(); @@ -135,6 +136,8 @@ fn recv_timeout_before_send() { sender.send(99u128).unwrap(); }); + // FIXME(#152145): Under load, there's no guarantee that thread `t` has + // ever been scheduled and run before this timeout expires. match receiver.recv_timeout(Duration::from_secs(1)) { Ok(99) => {} _ => panic!("expected Ok(99)"), @@ -240,7 +243,9 @@ fn recv_deadline_passed() { } assert!(start.elapsed() >= timeout); - assert!(start.elapsed() < timeout * 3); + // FIXME(#152878): An upper-bound assertion on the elapsed time was removed, + // because CI runners can starve individual threads for a surprisingly long + // time, leading to flaky failures. } #[test] @@ -249,12 +254,16 @@ fn recv_time_passed() { let start = Instant::now(); let timeout = Duration::from_millis(100); + match receiver.recv_timeout(timeout) { Err(RecvTimeoutError::Timeout(_)) => {} _ => panic!("expected timeout error"), } + assert!(start.elapsed() >= timeout); - assert!(start.elapsed() < timeout * 3); + // FIXME(#152878): An upper-bound assertion on the elapsed time was removed, + // because CI runners can starve individual threads for a surprisingly long + // time, leading to flaky failures. } #[test] diff --git a/std/tests/volatile-fat-ptr.rs b/std/tests/volatile-fat-ptr.rs index b005c12c6187b..406eb7c80afb5 100644 --- a/std/tests/volatile-fat-ptr.rs +++ b/std/tests/volatile-fat-ptr.rs @@ -1,6 +1,3 @@ -#![allow(stable_features)] -#![feature(volatile)] - use std::ptr::{read_volatile, write_volatile}; #[test] diff --git a/std/tests/windows_unix_socket.rs b/std/tests/windows_unix_socket.rs index 1f20cf586ca25..1d16ec9ed8414 100644 --- a/std/tests/windows_unix_socket.rs +++ b/std/tests/windows_unix_socket.rs @@ -5,10 +5,24 @@ // in the future, will test both unix and windows uds use std::io::{Read, Write}; use std::os::windows::net::{UnixListener, UnixStream}; -use std::thread; +use std::{mem, thread}; + +macro_rules! skip_nonapplicable_oses { + () => { + // UDS have been available under Windows since Insider Preview Build + // 17063. "Redstone 4" (RS4, version 1803, build number 17134) is + // therefore the first official release to include it. + if !is_windows_10_v1803_or_greater() { + println!("Not running this test on too-old Windows."); + return; + } + }; +} #[test] fn win_uds_smoke_bind_connect() { + skip_nonapplicable_oses!(); + let tmp = std::env::temp_dir(); let sock_path = tmp.join("rust-test-uds-smoke.sock"); let _ = std::fs::remove_file(&sock_path); @@ -32,6 +46,8 @@ fn win_uds_smoke_bind_connect() { #[test] fn win_uds_echo() { + skip_nonapplicable_oses!(); + let tmp = std::env::temp_dir(); let sock_path = tmp.join("rust-test-uds-echo.sock"); let _ = std::fs::remove_file(&sock_path); @@ -68,14 +84,19 @@ fn win_uds_echo() { #[test] fn win_uds_path_too_long() { + skip_nonapplicable_oses!(); + let tmp = std::env::temp_dir(); let long_path = tmp.join("a".repeat(200)); let result = UnixListener::bind(&long_path); assert!(result.is_err()); let _ = std::fs::remove_file(&long_path); } + #[test] fn win_uds_existing_bind() { + skip_nonapplicable_oses!(); + let tmp = std::env::temp_dir(); let sock_path = tmp.join("rust-test-uds-existing.sock"); let _ = std::fs::remove_file(&sock_path); @@ -85,3 +106,115 @@ fn win_uds_existing_bind() { drop(listener); let _ = std::fs::remove_file(&sock_path); } + +/// Returns true if we are currently running on Windows 10 v1803 (RS4) or greater. +fn is_windows_10_v1803_or_greater() -> bool { + is_windows_version_greater_or_equal(NTDDI_WIN10_RS4) +} + +/// Returns true if we are currently running on the given version of Windows +/// 10 (or newer). +fn is_windows_version_greater_or_equal(min_version: u32) -> bool { + is_windows_version_or_greater(HIBYTE(OSVER(min_version)), LOBYTE(OSVER(min_version)), 0, 0) +} + +/// Checks if we are running a version of Windows newer than the specified one. +fn is_windows_version_or_greater( + major: u8, + minor: u8, + service_pack: u8, + build_number: u32, +) -> bool { + let mut osvi = OSVERSIONINFOEXW { + dwOSVersionInfoSize: mem::size_of::() as _, + dwMajorVersion: u32::from(major), + dwMinorVersion: u32::from(minor), + wServicePackMajor: u16::from(service_pack), + dwBuildNumber: build_number, + ..OSVERSIONINFOEXW::default() + }; + + // SAFETY: this function is always safe to call. + let condmask = unsafe { + VerSetConditionMask( + VerSetConditionMask( + VerSetConditionMask( + VerSetConditionMask(0, VER_MAJORVERSION, VER_GREATER_EQUAL as _), + VER_MINORVERSION, + VER_GREATER_EQUAL as _, + ), + VER_SERVICEPACKMAJOR, + VER_GREATER_EQUAL as _, + ), + VER_BUILDNUMBER, + VER_GREATER_EQUAL as _, + ) + }; + + // SAFETY: osvi needs to point to a memory region valid for at least + // dwOSVersionInfoSize bytes, which is the case here. + (unsafe { + RtlVerifyVersionInfo( + &raw mut osvi, + VER_MAJORVERSION | VER_MINORVERSION | VER_SERVICEPACKMAJOR, + condmask, + ) + }) == STATUS_SUCCESS +} + +#[expect(non_snake_case)] +const fn HIBYTE(x: u16) -> u8 { + ((x >> 8) & 0xFF) as u8 +} + +#[expect(non_snake_case)] +const fn LOBYTE(x: u16) -> u8 { + (x & 0xFF) as u8 +} + +#[expect(non_snake_case)] +const fn OSVER(x: u32) -> u16 { + ((x & OSVERSION_MASK) >> 16) as u16 +} + +// Inlined bindings because outside of `std` here. + +type NTSTATUS = i32; +const STATUS_SUCCESS: NTSTATUS = 0; + +#[expect(non_camel_case_types)] +type VER_FLAGS = u32; +const VER_BUILDNUMBER: VER_FLAGS = 4u32; +const VER_GREATER_EQUAL: VER_FLAGS = 3u32; +const VER_MAJORVERSION: VER_FLAGS = 2u32; +const VER_MINORVERSION: VER_FLAGS = 1u32; +const VER_SERVICEPACKMAJOR: VER_FLAGS = 32u32; + +const OSVERSION_MASK: u32 = 4294901760u32; +const NTDDI_WIN10_RS4: u32 = 167772165u32; + +#[expect(non_snake_case)] +#[repr(C)] +#[derive(Clone, Copy)] +struct OSVERSIONINFOEXW { + pub dwOSVersionInfoSize: u32, + pub dwMajorVersion: u32, + pub dwMinorVersion: u32, + pub dwBuildNumber: u32, + pub dwPlatformId: u32, + pub szCSDVersion: [u16; 128], + pub wServicePackMajor: u16, + pub wServicePackMinor: u16, + pub wSuiteMask: u16, + pub wProductType: u8, + pub wReserved: u8, +} + +impl Default for OSVERSIONINFOEXW { + fn default() -> Self { + unsafe { core::mem::zeroed() } + } +} + +windows_link::link!("ntdll.dll" "system" fn RtlVerifyVersionInfo(versioninfo : *const OSVERSIONINFOEXW, typemask : u32, conditionmask : u64) -> NTSTATUS); +windows_link::link!("kernel32.dll" "system" fn VerSetConditionMask(conditionmask : u64, typemask : VER_FLAGS, condition : u8) -> u64); diff --git a/std_detect/src/detect/os/darwin/aarch64.rs b/std_detect/src/detect/os/darwin/aarch64.rs index a23d65a23d811..5805d5cc36460 100644 --- a/std_detect/src/detect/os/darwin/aarch64.rs +++ b/std_detect/src/detect/os/darwin/aarch64.rs @@ -81,6 +81,7 @@ pub(crate) fn detect_features() -> cache::Initializer { let sme_f64f64 = _sysctlbyname(c"hw.optional.arm.FEAT_SME_F64F64"); let sme_i16i64 = _sysctlbyname(c"hw.optional.arm.FEAT_SME_I16I64"); let ssbs = _sysctlbyname(c"hw.optional.arm.FEAT_SSBS"); + let sve_b16b16 = _sysctlbyname(c"hw.optional.arm.FEAT_SVE_B16B16"); let wfxt = _sysctlbyname(c"hw.optional.arm.FEAT_WFxT"); // The following features are not exposed by `is_aarch64_feature_detected`, @@ -160,6 +161,7 @@ pub(crate) fn detect_features() -> cache::Initializer { enable_feature(Feature::sme_f64f64, sme_f64f64); enable_feature(Feature::sme_i16i64, sme_i16i64); enable_feature(Feature::ssbs, ssbs); + enable_feature(Feature::sve_b16b16, sve_b16b16); enable_feature(Feature::wfxt, wfxt); value diff --git a/std_detect/src/detect/os/x86.rs b/std_detect/src/detect/os/x86.rs index f2205ba07dd41..b24ef6a37ef55 100644 --- a/std_detect/src/detect/os/x86.rs +++ b/std_detect/src/detect/os/x86.rs @@ -202,6 +202,28 @@ pub(crate) fn detect_features() -> cache::Initializer { // Test `XCR0.APX[19]` with the mask `0b1000_0000_0000_0000_0000 == 0x80000` let os_apx_support = xcr0 & 0x80000 == 0x80000; + if os_amx_support { + enable(extended_features_edx, 24, Feature::amx_tile); + enable(extended_features_edx, 25, Feature::amx_int8); + enable(extended_features_edx, 22, Feature::amx_bf16); + enable(extended_features_eax_leaf_1, 21, Feature::amx_fp16); + enable(extended_features_edx_leaf_1, 8, Feature::amx_complex); + + if max_basic_leaf >= 0x1e { + let CpuidResult { eax: amx_feature_flags_eax, .. } = + __cpuid_count(0x1e_u32, 1); + + enable(amx_feature_flags_eax, 4, Feature::amx_fp8); + enable(amx_feature_flags_eax, 6, Feature::amx_tf32); + enable(amx_feature_flags_eax, 7, Feature::amx_avx512); + enable(amx_feature_flags_eax, 8, Feature::amx_movrs); + } + } + + if os_apx_support { + enable(extended_features_edx_leaf_1, 21, Feature::apxf); + } + // Only if the OS and the CPU support saving/restoring the AVX // registers we enable `xsave` support: if os_avx_support { @@ -236,9 +258,10 @@ pub(crate) fn detect_features() -> cache::Initializer { enable(extended_features_ebx, 5, Feature::avx2); // "Short" versions of AVX512 instructions - enable(extended_features_eax_leaf_1, 4, Feature::avxvnni); - enable(extended_features_eax_leaf_1, 23, Feature::avxifma); - enable(extended_features_edx_leaf_1, 4, Feature::avxvnniint8); + let avxvnni = enable(extended_features_eax_leaf_1, 4, Feature::avxvnni); + let avxvnniint8 = enable(extended_features_eax_leaf_1, 23, Feature::avxifma); + let avxvnniint16 = + enable(extended_features_edx_leaf_1, 4, Feature::avxvnniint8); enable(extended_features_edx_leaf_1, 5, Feature::avxneconvert); enable(extended_features_edx_leaf_1, 10, Feature::avxvnniint16); @@ -269,37 +292,18 @@ pub(crate) fn detect_features() -> cache::Initializer { enable(extended_features_edx, 8, Feature::avx512vp2intersect); enable(extended_features_edx, 23, Feature::avx512fp16); enable(extended_features_eax_leaf_1, 5, Feature::avx512bf16); - } - } - - if os_amx_support { - enable(extended_features_edx, 24, Feature::amx_tile); - enable(extended_features_edx, 25, Feature::amx_int8); - enable(extended_features_edx, 22, Feature::amx_bf16); - enable(extended_features_eax_leaf_1, 21, Feature::amx_fp16); - enable(extended_features_edx_leaf_1, 8, Feature::amx_complex); - - if max_basic_leaf >= 0x1e { - let CpuidResult { eax: amx_feature_flags_eax, .. } = - __cpuid_count(0x1e_u32, 1); - - enable(amx_feature_flags_eax, 4, Feature::amx_fp8); - enable(amx_feature_flags_eax, 6, Feature::amx_tf32); - enable(amx_feature_flags_eax, 7, Feature::amx_avx512); - enable(amx_feature_flags_eax, 8, Feature::amx_movrs); - } - } - - if os_apx_support { - enable(extended_features_edx_leaf_1, 21, Feature::apxf); - } - let avx10_1 = enable(extended_features_edx_leaf_1, 19, Feature::avx10_1); - if avx10_1 { - let CpuidResult { ebx, .. } = __cpuid(0x24); - let avx10_version = ebx & 0xff; - if avx10_version >= 2 { - value.set(Feature::avx10_2 as u32); + let avx10_1 = enable(extended_features_edx_leaf_1, 19, Feature::avx10_1); + if avx10_1 { + let CpuidResult { ebx, .. } = __cpuid(0x24); + let avx10_version = ebx & 0xff; + + // AVX10.2 supports masked versions of dot-product instructions available in avxvnni etc, + // so it doesn't make sense to have it without the unmasked versions + if avx10_version >= 2 && avxvnni && avxvnniint8 && avxvnniint16 { + value.set(Feature::avx10_2 as u32); + } + } } } } diff --git a/std_detect/src/lib.rs b/std_detect/src/lib.rs index 5e1d21bbfd17d..f9d79df670a0f 100644 --- a/std_detect/src/lib.rs +++ b/std_detect/src/lib.rs @@ -15,7 +15,7 @@ //! * `s390x`: [`is_s390x_feature_detected`] #![unstable(feature = "stdarch_internal", issue = "none")] -#![feature(staged_api, cfg_select, doc_cfg, allow_internal_unstable)] +#![feature(staged_api, doc_cfg, allow_internal_unstable)] #![deny(rust_2018_idioms)] #![allow(clippy::shadow_reuse)] #![cfg_attr(test, allow(unused_imports))] diff --git a/std_detect/tests/cpu-detection.rs b/std_detect/tests/cpu-detection.rs index 196abfdb7c4dd..0aad088af7de5 100644 --- a/std_detect/tests/cpu-detection.rs +++ b/std_detect/tests/cpu-detection.rs @@ -1,4 +1,4 @@ -#![allow(internal_features)] +#![allow(internal_features, unused_features)] #![feature(stdarch_internal)] #![cfg_attr(target_arch = "arm", feature(stdarch_arm_feature_detection))] #![cfg_attr( diff --git a/std_detect/tests/macro_trailing_commas.rs b/std_detect/tests/macro_trailing_commas.rs index 29bd3f1162a42..a60b34acb872f 100644 --- a/std_detect/tests/macro_trailing_commas.rs +++ b/std_detect/tests/macro_trailing_commas.rs @@ -1,4 +1,4 @@ -#![allow(internal_features)] +#![allow(internal_features, unused_features)] #![cfg_attr( any( target_arch = "arm", diff --git a/stdarch/.github/workflows/main.yml b/stdarch/.github/workflows/main.yml index 6cf0e9f02fe54..3749ed1f6ac81 100644 --- a/stdarch/.github/workflows/main.yml +++ b/stdarch/.github/workflows/main.yml @@ -8,7 +8,7 @@ jobs: name: Check Style runs-on: ubuntu-latest steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v6 - name: Install Rust run: rustup update nightly --no-self-update && rustup default nightly - run: ci/style.sh @@ -18,7 +18,7 @@ jobs: needs: [style] runs-on: ubuntu-latest steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v6 - name: Install Rust run: rustup update nightly --no-self-update && rustup default nightly - run: ci/dox.sh @@ -30,7 +30,7 @@ jobs: needs: [style] runs-on: ubuntu-latest steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v6 - name: Install Rust run: rustup update nightly --no-self-update && rustup default nightly - run: cargo test --manifest-path crates/stdarch-verify/Cargo.toml @@ -96,6 +96,8 @@ jobs: os: ubuntu-latest - tuple: loongarch64-unknown-linux-gnu os: ubuntu-latest + - tuple: hexagon-unknown-linux-musl + os: ubuntu-latest - tuple: wasm32-wasip1 os: ubuntu-latest @@ -207,9 +209,14 @@ jobs: tuple: amdgcn-amd-amdhsa os: ubuntu-latest norun: true + - target: + tuple: hexagon-unknown-linux-musl + os: ubuntu-latest + norun: true + build_std: true steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v6 - name: Install Rust run: | rustup update nightly --no-self-update @@ -278,7 +285,7 @@ jobs: build_std: true steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v6 - name: Install Rust run: | rustup update nightly --no-self-update @@ -300,10 +307,10 @@ jobs: # Check that the generated files agree with the checked-in versions. check-stdarch-gen: needs: [style] - name: Check stdarch-gen-{arm, loongarch} output + name: Check stdarch-gen-{arm, loongarch, hexagon} output runs-on: ubuntu-latest steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v6 - name: Install Rust run: rustup update nightly && rustup default nightly && rustup component add rustfmt - name: Check arm spec @@ -318,6 +325,10 @@ jobs: run: | cargo run --bin=stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lasx.spec git diff --exit-code + - name: Check hexagon + run: | + cargo run -p stdarch-gen-hexagon --release + git diff --exit-code conclusion: needs: diff --git a/stdarch/Cargo.lock b/stdarch/Cargo.lock index 70f09adf2c857..7e7cb592889a8 100644 --- a/stdarch/Cargo.lock +++ b/stdarch/Cargo.lock @@ -4,18 +4,18 @@ version = 4 [[package]] name = "aho-corasick" -version = "1.1.3" +version = "1.1.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8e60d3430d3a69478ad0993f19238d2df97c507009a52b3c10addcd7f6bcb916" +checksum = "ddd31a130427c27518df266943a5308ed92d4b226cc639f5a8f1002816174301" dependencies = [ "memchr", ] [[package]] name = "anstream" -version = "0.6.20" +version = "0.6.21" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3ae563653d1938f79b1ab1b5e668c87c76a9930414574a6583a7b7e11a8e6192" +checksum = "43d5b281e737544384e969a5ccad3f1cdd24b48086a0fc1b2a5262a26b8f4f4a" dependencies = [ "anstyle", "anstyle-parse", @@ -28,9 +28,9 @@ dependencies = [ [[package]] name = "anstyle" -version = "1.0.11" +version = "1.0.13" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "862ed96ca487e809f1c8e5a8447f6ee2cf102f846893800b20cebdf541fc6bbd" +checksum = "5192cca8006f1fd4f7237516f40fa183bb07f8fbdfedaa0036de5ea9b0b45e78" [[package]] name = "anstyle-parse" @@ -43,29 +43,29 @@ dependencies = [ [[package]] name = "anstyle-query" -version = "1.1.4" +version = "1.1.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9e231f6134f61b71076a3eab506c379d4f36122f2af15a9ff04415ea4c3339e2" +checksum = "40c48f72fd53cd289104fc64099abca73db4166ad86ea0b4341abe65af83dadc" dependencies = [ - "windows-sys 0.60.2", + "windows-sys", ] [[package]] name = "anstyle-wincon" -version = "3.0.10" +version = "3.0.11" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3e0633414522a32ffaac8ac6cc8f748e090c5717661fddeea04219e2344f5f2a" +checksum = "291e6a250ff86cd4a820112fb8898808a366d8f9f58ce16d1f538353ad55747d" dependencies = [ "anstyle", "once_cell_polyfill", - "windows-sys 0.60.2", + "windows-sys", ] [[package]] name = "anyhow" -version = "1.0.99" +version = "1.0.101" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b0674a1ddeecb70197781e945de4b3b8ffb61fa939a5597bcf48503737663100" +checksum = "5f0e0fee31ef5ed1ba1316088939cea399010ed7731dba877ed44aeb407a75ea" [[package]] name = "assert-instr-macro" @@ -84,15 +84,15 @@ checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8" [[package]] name = "bitflags" -version = "2.9.4" +version = "2.10.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2261d10cca569e4643e526d8dc2e62e433cc8aba21ab764233731f8d369bf394" +checksum = "812e12b5285cc515a9c72a5c1d3b6d46a19dac5acfef5265968c166106e31dd3" [[package]] name = "cc" -version = "1.2.36" +version = "1.2.55" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5252b3d2648e5eedbc1a6f501e3c795e07025c1e93bbf8bbdd6eef7f447a6d54" +checksum = "47b26a0954ae34af09b50f0de26458fa95369a0d478d8236d3f93082b219bd29" dependencies = [ "find-msvc-tools", "shlex", @@ -100,15 +100,15 @@ dependencies = [ [[package]] name = "cfg-if" -version = "1.0.3" +version = "1.0.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2fd1289c04a9ea8cb22300a459a72a385d7c73d3259e2ed7dcb2af674838cfa9" +checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" [[package]] name = "clap" -version = "4.5.47" +version = "4.5.58" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7eac00902d9d136acd712710d71823fb8ac8004ca445a89e73a41d45aa712931" +checksum = "63be97961acde393029492ce0be7a1af7e323e6bae9511ebfac33751be5e6806" dependencies = [ "clap_builder", "clap_derive", @@ -116,9 +116,9 @@ dependencies = [ [[package]] name = "clap_builder" -version = "4.5.47" +version = "4.5.58" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2ad9bbf750e73b5884fb8a211a9424a1906c1e156724260fdae972f31d70e1d6" +checksum = "7f13174bda5dfd69d7e947827e5af4b0f2f94a4a3ee92912fba07a66150f21e2" dependencies = [ "anstream", "anstyle", @@ -128,9 +128,9 @@ dependencies = [ [[package]] name = "clap_derive" -version = "4.5.47" +version = "4.5.55" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bbfd7eae0b0f1a6e63d4b13c9c478de77c2eb546fba158ad50b4203dc24b9f9c" +checksum = "a92793da1a46a5f2a02a6f4c46c6496b28c43638adea8306fcb0caa1634f24e5" dependencies = [ "heck", "proc-macro2", @@ -140,9 +140,9 @@ dependencies = [ [[package]] name = "clap_lex" -version = "0.7.5" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b94f61472cee1439c0b966b47e3aca9ae07e45d070759512cd390ea2bebc6675" +checksum = "3a822ea5bc7590f9d40f1ba12c0dc3c2760f3482c6984db1573ad11031420831" [[package]] name = "colorchoice" @@ -185,9 +185,9 @@ checksum = "d0a5c400df2834b80a4c3327b3aad3a4c4cd4de0629063962b03235697506a28" [[package]] name = "darling" -version = "0.20.11" +version = "0.21.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fc7f46116c46ff9ab3eb1597a45688b6715c6e628b5c133e288e709a29bcb4ee" +checksum = "9cdf337090841a411e2a7f3deb9187445851f91b309c0c0a29e05f74a00a48c0" dependencies = [ "darling_core", "darling_macro", @@ -195,9 +195,9 @@ dependencies = [ [[package]] name = "darling_core" -version = "0.20.11" +version = "0.21.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0d00b9596d185e565c2207a0b01f8bd1a135483d02d9b7b0a54b11da8d53412e" +checksum = "1247195ecd7e3c85f83c8d2a366e4210d588e802133e1e355180a9870b517ea4" dependencies = [ "fnv", "ident_case", @@ -209,9 +209,9 @@ dependencies = [ [[package]] name = "darling_macro" -version = "0.20.11" +version = "0.21.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fc34b93ccb385b40dc71c6fceac4b2ad23662c7eeb248cf10d529b7e055b6ead" +checksum = "d38308df82d1080de0afee5d069fa14b0326a88c14f15c5ccda35b4a6c414c81" dependencies = [ "darling_core", "quote", @@ -231,10 +231,10 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "48c757948c5ede0e46177b7add2e67155f70e33c07fea8284df6576da70b3719" [[package]] -name = "env_logger" -version = "0.8.4" +name = "env_filter" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a19187fea3ac7e84da7dacf48de0c45d63c6a76f9490dae389aead16c243fce3" +checksum = "7a1c3cc8e57274ec99de65301228b537f1e4eedc1b8e0f9411c6caac8ae7308f" dependencies = [ "log", "regex", @@ -253,6 +253,16 @@ dependencies = [ "termcolor", ] +[[package]] +name = "env_logger" +version = "0.11.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b2daee4ea451f429a58296525ddf28b45a3b64f1acf6587e2067437bb11e218d" +dependencies = [ + "env_filter", + "log", +] + [[package]] name = "equivalent" version = "1.0.2" @@ -261,9 +271,9 @@ checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f" [[package]] name = "find-msvc-tools" -version = "0.1.1" +version = "0.1.9" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7fd99930f64d146689264c637b5af2f0233a933bef0d8570e2526bf9e083192d" +checksum = "5baebc0774151f905a1a2cc41989300b1e6fbb29aff0ceffa1064fdd3088d582" [[package]] name = "fnv" @@ -271,17 +281,37 @@ version = "1.0.7" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "3f9eec918d3f24069decb9af1554cad7c880e2da24a9afd88aca000531ab82c1" +[[package]] +name = "foldhash" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2" + [[package]] name = "getrandom" -version = "0.2.16" +version = "0.2.17" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "335ff9f135e4384c8150d6f27c6daed433577f86b4750418338c01a1a2528592" +checksum = "ff2abc00be7fca6ebc474524697ae276ad847ad0a6b3faa4bcb027e9a4614ad0" dependencies = [ "cfg-if", "libc", "wasi", ] +[[package]] +name = "getrandom" +version = "0.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "139ef39800118c7683f2fd3c98c1b23c09ae076556b435f8e9064ae108aaeeec" +dependencies = [ + "cfg-if", + "libc", + "r-efi", + "rand_core 0.10.0", + "wasip2", + "wasip3", +] + [[package]] name = "hashbrown" version = "0.12.3" @@ -293,6 +323,15 @@ name = "hashbrown" version = "0.15.5" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "9229cfe53dfd69f0609a49f65461bd93001ea1ef889cd5529dd176593f5338a1" +dependencies = [ + "foldhash", +] + +[[package]] +name = "hashbrown" +version = "0.16.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "841d1cc9bed7f9236f321df977030373f4a4163ae1a7dbfe1a51a2c1a51d9100" [[package]] name = "heck" @@ -308,9 +347,15 @@ checksum = "fc0fef456e4baa96da950455cd02c081ca953b141298e41db3fc7e36b1da849c" [[package]] name = "humantime" -version = "2.2.0" +version = "2.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9b112acc8b3adf4b107a8ec20977da0273a8c386765a3ec0229bd500a1443f9f" +checksum = "135b12329e5e3ce057a9f972339ea52bc954fe1e9358ef27f95e89716fbc5424" + +[[package]] +name = "id-arena" +version = "2.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3d3067d79b975e8844ca9eb072e16b31c3c1c36928edf9c6789548c524d0d954" [[package]] name = "ident_case" @@ -330,12 +375,14 @@ dependencies = [ [[package]] name = "indexmap" -version = "2.11.0" +version = "2.13.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f2481980430f9f78649238835720ddccc57e52df14ffce1c6f37391d61b563e9" +checksum = "7714e70437a7dc3ac8eb7e6f8df75fd8eb422675fc7678aff7364301092b1017" dependencies = [ "equivalent", - "hashbrown 0.15.5", + "hashbrown 0.16.1", + "serde", + "serde_core", ] [[package]] @@ -357,20 +404,20 @@ dependencies = [ [[package]] name = "is-terminal" -version = "0.4.16" +version = "0.4.17" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e04d7f318608d35d4b61ddd75cbdaee86b023ebe2bd5a66ee0915f0bf93095a9" +checksum = "3640c1c38b8e4e43584d8df18be5fc6b0aa314ce6ebf51b53313d4306cca8e46" dependencies = [ "hermit-abi", "libc", - "windows-sys 0.59.0", + "windows-sys", ] [[package]] name = "is_terminal_polyfill" -version = "1.70.1" +version = "1.70.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7943c866cc5cd64cbc25b2e01621d07fa8eb2a1a23160ee81ce38704e97b8ecf" +checksum = "a6cb138bb79a146c1bd460005623e142ef0181e3d0219cb493e02f7d08a35695" [[package]] name = "itertools" @@ -383,15 +430,21 @@ dependencies = [ [[package]] name = "itoa" -version = "1.0.15" +version = "1.0.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = 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"registry+https://github.com/rust-lang/crates.io-index" -checksum = "271414315aff87387382ec3d271b52d7ae78726f5d44ac98b4f4030c91880486" +checksum = "ecc8ac4bc1dc3381b7f59c34f00b67e18f910c2c0f50015669dde7def656a736" +dependencies = [ + "anyhow", + "id-arena", + "indexmap 2.13.0", + "log", + "semver", + "serde", + "serde_derive", + "serde_json", + "unicode-xid", + "wasmparser 0.244.0", +] [[package]] -name = "xml-rs" -version = "0.8.27" +name = "xml" +version = "1.2.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6fd8403733700263c6eb89f192880191f1b83e332f7a20371ddcf421c4a337c7" +checksum = "b8aa498d22c9bbaf482329839bc5620c46be275a19a812e9a22a2b07529a642a" [[package]] name = "yaml-rust" @@ -1020,20 +1130,26 @@ dependencies = [ [[package]] name = "zerocopy" -version = "0.8.27" +version = "0.8.39" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0894878a5fa3edfd6da3f88c4805f4c8558e2b996227a3d864f47fe11e38282c" +checksum = "db6d35d663eadb6c932438e763b262fe1a70987f9ae936e60158176d710cae4a" dependencies = [ "zerocopy-derive", ] [[package]] name = "zerocopy-derive" -version = "0.8.27" +version = "0.8.39" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "88d2b8d9c68ad2b9e4340d7832716a4d21a22a1154777ad56ea55c51a9cf3831" +checksum = "4122cd3169e94605190e77839c9a40d40ed048d305bfdc146e7df40ab0f3e517" dependencies = [ "proc-macro2", "quote", "syn", ] + +[[package]] +name = "zmij" +version = "1.0.21" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b8848ee67ecc8aedbaf3e4122217aff892639231befc6a1b58d29fff4c2cabaa" diff --git a/stdarch/Cargo.toml b/stdarch/Cargo.toml index 5979096439118..e3963a69879a1 100644 --- a/stdarch/Cargo.toml +++ b/stdarch/Cargo.toml @@ -1,5 +1,5 @@ [workspace] -resolver = "1" +resolver = "3" members = [ "crates/*", "examples", diff --git a/stdarch/ci/docker/hexagon-unknown-linux-musl/Dockerfile b/stdarch/ci/docker/hexagon-unknown-linux-musl/Dockerfile new file mode 100644 index 0000000000000..f6c0efd94629a --- /dev/null +++ b/stdarch/ci/docker/hexagon-unknown-linux-musl/Dockerfile @@ -0,0 +1,46 @@ +FROM ubuntu:25.10 + +RUN apt-get update && apt-get install -y --no-install-recommends \ + gcc \ + libc6-dev \ + ca-certificates \ + curl \ + zstd \ + file \ + make \ + libc++1 \ + libglib2.0-0t64 \ + libunwind-20 \ + liburing2 \ + llvm + +# The Hexagon toolchain requires libc++ and libunwind at runtime - create symlinks from versioned files +RUN cd /usr/lib/x86_64-linux-gnu && \ + for f in libc++.so.1.0.*; do ln -sf "$f" libc++.so.1; done && \ + for f in libc++abi.so.1.0.*; do ln -sf "$f" libc++abi.so.1; done && \ + for f in libunwind.so.1.0.*; do ln -sf "$f" libunwind.so.1; done + +# Download and install the Hexagon cross toolchain from +# https://github.com/quic/toolchain_for_hexagon/releases/tag/v21.1.8 +# Includes clang cross-compiler, musl sysroot, and qemu-hexagon. +# +# The tarball contains directories with restrictive (0700) permissions. +# In rootless Podman, chmod fails on tar-extracted files within the same +# layer due to overlayfs limitations in user namespaces. Splitting into +# two RUN steps lets chmod work via overlayfs copy-up from the lower layer. +RUN curl -L -o /tmp/hexagon-toolchain.tar.zst \ + https://artifacts.codelinaro.org/artifactory/codelinaro-toolchain-for-hexagon/21.1.8/clang+llvm-21.1.8-cross-hexagon-unknown-linux-musl.tar.zst && \ + mkdir -p /opt/hexagon-toolchain && \ + cd /opt/hexagon-toolchain && \ + (unzstd -c /tmp/hexagon-toolchain.tar.zst | tar -xf - --strip-components=2 --no-same-permissions || true) && \ + rm /tmp/hexagon-toolchain.tar.zst +RUN find /opt/hexagon-toolchain -type d -exec chmod a+rx {} + 2>/dev/null; \ + find /opt/hexagon-toolchain -type f -exec chmod a+r {} + 2>/dev/null; \ + find /opt/hexagon-toolchain -type f -perm /111 -exec chmod a+rx {} + 2>/dev/null; \ + /opt/hexagon-toolchain/bin/hexagon-unknown-linux-musl-clang --version + +ENV PATH="/opt/hexagon-toolchain/bin:${PATH}" \ + CARGO_TARGET_HEXAGON_UNKNOWN_LINUX_MUSL_LINKER=hexagon-unknown-linux-musl-clang \ + CARGO_TARGET_HEXAGON_UNKNOWN_LINUX_MUSL_RUNNER="qemu-hexagon -L /opt/hexagon-toolchain/target/hexagon-unknown-linux-musl" \ + CARGO_UNSTABLE_BUILD_STD_FEATURES=llvm-libunwind \ + OBJDUMP=llvm-objdump diff --git a/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile index 2743896375cf3..a357449d51e3d 100644 --- a/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile +++ b/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile @@ -12,7 +12,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \ build-essential \ lld -RUN wget http://ci-mirrors.rust-lang.org/stdarch/sde-external-9.58.0-2025-06-16-lin.tar.xz -O sde.tar.xz +RUN wget http://ci-mirrors.rust-lang.org/stdarch/sde-external-10.5.0-2026-01-13-lin.tar.xz -O sde.tar.xz RUN mkdir intel-sde RUN tar -xJf sde.tar.xz --strip-components=1 -C intel-sde ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/intel-sde/sde64 \ diff --git a/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def b/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def index 342f7d83a63e3..acf023ed0dc49 100644 --- a/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def +++ b/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def @@ -12,7 +12,7 @@ # CPUID_VERSION = 1.0 # Input => Output # EAX ECX => EAX EBX ECX EDX -00000000 ******** => 00000024 756e6547 6c65746e 49656e69 +00000000 ******** => 00000029 756e6547 6c65746e 49656e69 00000001 ******** => 00400f10 00100800 7ffaf3ff bfebfbff 00000002 ******** => 76035a01 00f0b6ff 00000000 00c10000 00000003 ******** => 00000000 00000000 00000000 00000000 @@ -48,6 +48,7 @@ 0000001e 00000001 => 000001ff 00000000 00000000 00000000 00000024 00000000 => 00000001 00070002 00000000 00000000 #AVX10 00000024 00000001 => 00000000 00000000 00000004 00000000 +00000029 ******** => 00000000 00000001 00000000 00000000 80000000 ******** => 80000008 00000000 00000000 00000000 80000001 ******** => 00000000 00000000 00000121 2c100000 80000002 ******** => 00000000 00000000 00000000 00000000 diff --git a/stdarch/ci/run.sh b/stdarch/ci/run.sh index 8a0b5fa26f66c..ea012b42f983b 100755 --- a/stdarch/ci/run.sh +++ b/stdarch/ci/run.sh @@ -50,6 +50,9 @@ case ${TARGET} in riscv*) export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+zk,+zks,+zbb,+zbc" ;; + hexagon*) + export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+hvxv60,+hvx-length128b" + ;; esac echo "RUSTFLAGS=${RUSTFLAGS}" diff --git a/stdarch/crates/core_arch/src/aarch64/mod.rs b/stdarch/crates/core_arch/src/aarch64/mod.rs index b48bdac57e7db..d7295659c3c9a 100644 --- a/stdarch/crates/core_arch/src/aarch64/mod.rs +++ b/stdarch/crates/core_arch/src/aarch64/mod.rs @@ -17,6 +17,10 @@ mod mte; #[unstable(feature = "stdarch_aarch64_mte", issue = "129010")] pub use self::mte::*; +mod rand; +#[unstable(feature = "stdarch_aarch64_rand", issue = "153514")] +pub use self::rand::*; + mod neon; #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub use self::neon::*; diff --git a/stdarch/crates/core_arch/src/aarch64/mte.rs b/stdarch/crates/core_arch/src/aarch64/mte.rs index c400f774bcce0..a5031a45c1a0e 100644 --- a/stdarch/crates/core_arch/src/aarch64/mte.rs +++ b/stdarch/crates/core_arch/src/aarch64/mte.rs @@ -3,35 +3,17 @@ //! [ACLE documentation](https://arm-software.github.io/acle/main/acle.html#markdown-toc-mte-intrinsics) unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.irg" - )] + #[link_name = "llvm.aarch64.irg"] fn irg_(ptr: *const (), exclude: i64) -> *const (); - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.gmi" - )] + #[link_name = "llvm.aarch64.gmi"] fn gmi_(ptr: *const (), exclude: i64) -> i64; - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.ldg" - )] + #[link_name = "llvm.aarch64.ldg"] fn ldg_(ptr: *const (), tag_ptr: *const ()) -> *const (); - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.stg" - )] + #[link_name = "llvm.aarch64.stg"] fn stg_(tagged_ptr: *const (), addr_to_tag: *const ()); - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.addg" - )] + #[link_name = "llvm.aarch64.addg"] fn addg_(ptr: *const (), value: i64) -> *const (); - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.subp" - )] + #[link_name = "llvm.aarch64.subp"] fn subp_(ptr_a: *const (), ptr_b: *const ()) -> i64; } @@ -127,42 +109,46 @@ mod test { use super::*; use stdarch_test::assert_instr; - #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(irg))] // FIXME: MSVC `dumpbin` doesn't support MTE + // Instruction tests are separate because the functions use generics. + // + // FIXME: As of 2026 MSVC `dumpbin` doesn't support MTE. + + #[cfg_attr(not(target_env = "msvc"), assert_instr(irg))] #[allow(dead_code)] #[target_feature(enable = "mte")] unsafe fn test_arm_mte_create_random_tag(src: *const (), mask: u64) -> *const () { __arm_mte_create_random_tag(src, mask) } - #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(addg))] + #[cfg_attr(not(target_env = "msvc"), assert_instr(addg))] #[allow(dead_code)] #[target_feature(enable = "mte")] unsafe fn test_arm_mte_increment_tag(src: *const ()) -> *const () { __arm_mte_increment_tag::<1, _>(src) } - #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(gmi))] + #[cfg_attr(not(target_env = "msvc"), assert_instr(gmi))] #[allow(dead_code)] #[target_feature(enable = "mte")] unsafe fn test_arm_mte_exclude_tag(src: *const (), excluded: u64) -> u64 { __arm_mte_exclude_tag(src, excluded) } - #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stg))] + #[cfg_attr(not(target_env = "msvc"), assert_instr(stg))] #[allow(dead_code)] #[target_feature(enable = "mte")] unsafe fn test_arm_mte_set_tag(src: *const ()) { __arm_mte_set_tag(src) } - #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldg))] + #[cfg_attr(not(target_env = "msvc"), assert_instr(ldg))] #[allow(dead_code)] #[target_feature(enable = "mte")] unsafe fn test_arm_mte_get_tag(src: *const ()) -> *const () { __arm_mte_get_tag(src) } - #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(subp))] + #[cfg_attr(not(target_env = "msvc"), assert_instr(subp))] #[allow(dead_code)] #[target_feature(enable = "mte")] unsafe fn test_arm_mte_ptrdiff(a: *const (), b: *const ()) -> i64 { diff --git a/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/stdarch/crates/core_arch/src/aarch64/neon/generated.rs index 9507b71106dd1..74af50016690b 100644 --- a/stdarch/crates/core_arch/src/aarch64/neon/generated.rs +++ b/stdarch/crates/core_arch/src/aarch64/neon/generated.rs @@ -49,7 +49,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 { #[inline(always)] #[target_feature(enable = "jsconv")] #[cfg_attr(test, assert_instr(fjcvtzs))] -#[stable(feature = "stdarch_aarch64_jscvt", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_aarch64_jscvt", since = "1.95.0")] pub fn __jcvt(a: f64) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( @@ -1565,7 +1565,7 @@ pub fn vceqh_f16(a: f16, b: f16) -> u16 { #[inline(always)] #[cfg_attr(test, assert_instr(fcmeq))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t { let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0); @@ -1576,7 +1576,7 @@ pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcmeq))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vceqzq_f16(a: float16x8_t) -> uint16x8_t { let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); @@ -4092,7 +4092,7 @@ pub fn vcmlaq_rot90_laneq_f32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_f32( @@ -4113,7 +4113,7 @@ pub fn vcopy_lane_f32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { @@ -4137,7 +4137,7 @@ pub fn vcopy_lane_s8(a: int8x8_t, b: int8x8_ #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { @@ -4157,7 +4157,7 @@ pub fn vcopy_lane_s16(a: int16x4_t, b: int16 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { @@ -4175,7 +4175,7 @@ pub fn vcopy_lane_s32(a: int32x2_t, b: int32 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { @@ -4199,7 +4199,7 @@ pub fn vcopy_lane_u8(a: uint8x8_t, b: uint8x #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_u16( @@ -4222,7 +4222,7 @@ pub fn vcopy_lane_u16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_u32( @@ -4243,7 +4243,7 @@ pub fn vcopy_lane_u32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { @@ -4267,7 +4267,7 @@ pub fn vcopy_lane_p8(a: poly8x8_t, b: poly8x #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_p16( @@ -4290,7 +4290,7 @@ pub fn vcopy_lane_p16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_f32( @@ -4312,7 +4312,7 @@ pub fn vcopy_laneq_f32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_s8(a: int8x8_t, b: int8x16_t) -> int8x8_t { @@ -4338,7 +4338,7 @@ pub fn vcopy_laneq_s8(a: int8x8_t, b: int8x1 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_s16( @@ -4362,7 +4362,7 @@ pub fn vcopy_laneq_s16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_s32( @@ -4384,7 +4384,7 @@ pub fn vcopy_laneq_s32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_u8( @@ -4413,7 +4413,7 @@ pub fn vcopy_laneq_u8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_u16( @@ -4437,7 +4437,7 @@ pub fn vcopy_laneq_u16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_u32( @@ -4459,7 +4459,7 @@ pub fn vcopy_laneq_u32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_p8( @@ -4488,7 +4488,7 @@ pub fn vcopy_laneq_p8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_p16( @@ -4624,7 +4624,7 @@ pub fn vcopyq_lane_p64( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s8(a: int8x16_t, b: int8x8_t) -> int8x16_t { @@ -4994,7 +4994,7 @@ pub fn vcopyq_lane_s8(a: int8x16_t, b: int8x #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s16( @@ -5022,7 +5022,7 @@ pub fn vcopyq_lane_s16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s32( @@ -5046,7 +5046,7 @@ pub fn vcopyq_lane_s32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u8( @@ -5419,7 +5419,7 @@ pub fn vcopyq_lane_u8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u16( @@ -5447,7 +5447,7 @@ pub fn vcopyq_lane_u16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u32( @@ -5471,7 +5471,7 @@ pub fn vcopyq_lane_u32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_p8( @@ -5844,7 +5844,7 @@ pub fn vcopyq_lane_p8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_p16( @@ -5872,7 +5872,7 @@ pub fn vcopyq_lane_p16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_f32( @@ -5895,7 +5895,7 @@ pub fn vcopyq_laneq_f32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_f64( @@ -5916,7 +5916,7 @@ pub fn vcopyq_laneq_f64( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s8( @@ -6287,7 +6287,7 @@ pub fn vcopyq_laneq_s8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s16( @@ -6314,7 +6314,7 @@ pub fn vcopyq_laneq_s16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s32( @@ -6337,7 +6337,7 @@ pub fn vcopyq_laneq_s32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s64( @@ -6358,7 +6358,7 @@ pub fn vcopyq_laneq_s64( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u8( @@ -6729,7 +6729,7 @@ pub fn vcopyq_laneq_u8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u16( @@ -6756,7 +6756,7 @@ pub fn vcopyq_laneq_u16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u32( @@ -6779,7 +6779,7 @@ pub fn vcopyq_laneq_u32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u64( @@ -6800,7 +6800,7 @@ pub fn vcopyq_laneq_u64( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_p8( @@ -7171,7 +7171,7 @@ pub fn vcopyq_laneq_p8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_p16( @@ -7198,7 +7198,7 @@ pub fn vcopyq_laneq_p16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_p64( @@ -7283,7 +7283,7 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtn2))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t { vcombine_f16(a, vcvt_f16_f32(b)) @@ -7293,7 +7293,7 @@ pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtl2))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t { vcvt_f32_f16(vget_high_f16(a)) @@ -7532,7 +7532,7 @@ pub fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { @@ -7549,7 +7549,7 @@ pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { @@ -7630,7 +7630,7 @@ pub fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { @@ -7647,7 +7647,7 @@ pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { @@ -8218,7 +8218,7 @@ pub fn vcvth_u64_f16(a: f16) -> u64 { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { @@ -8235,7 +8235,7 @@ pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { @@ -8316,7 +8316,7 @@ pub fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { @@ -8333,7 +8333,7 @@ pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { @@ -8566,7 +8566,7 @@ pub fn vcvtmd_u64_f64(a: f64) -> u64 { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { @@ -8583,7 +8583,7 @@ pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { @@ -8664,7 +8664,7 @@ pub fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { @@ -8681,7 +8681,7 @@ pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { @@ -8914,7 +8914,7 @@ pub fn vcvtnd_u64_f64(a: f64) -> u64 { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { @@ -8931,7 +8931,7 @@ pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { @@ -9012,7 +9012,7 @@ pub fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { @@ -9029,7 +9029,7 @@ pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { @@ -9493,7 +9493,7 @@ pub fn vcvtxd_f32_f64(a: f64) -> f32 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fdiv))] pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -9503,7 +9503,7 @@ pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fdiv))] pub fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -10108,7 +10108,7 @@ pub fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfma_lane_f16( a: float16x4_t, @@ -10124,7 +10124,7 @@ pub fn vfma_lane_f16( #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfma_laneq_f16( a: float16x4_t, @@ -10140,7 +10140,7 @@ pub fn vfma_laneq_f16( #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmaq_lane_f16( a: float16x8_t, @@ -10156,7 +10156,7 @@ pub fn vfmaq_lane_f16( #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmaq_laneq_f16( a: float16x8_t, @@ -10434,7 +10434,7 @@ pub fn vfmad_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlal2))] pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { @@ -10452,7 +10452,7 @@ pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3 #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlal2))] pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { @@ -10472,7 +10472,7 @@ pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlal_lane_high_f16( r: float32x2_t, @@ -10489,7 +10489,7 @@ pub fn vfmlal_lane_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlal_laneq_high_f16( r: float32x2_t, @@ -10506,7 +10506,7 @@ pub fn vfmlal_laneq_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlalq_lane_high_f16( r: float32x4_t, @@ -10523,7 +10523,7 @@ pub fn vfmlalq_lane_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlalq_laneq_high_f16( r: float32x4_t, @@ -10540,7 +10540,7 @@ pub fn vfmlalq_laneq_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlal_lane_low_f16( r: float32x2_t, @@ -10557,7 +10557,7 @@ pub fn vfmlal_lane_low_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlal_laneq_low_f16( r: float32x2_t, @@ -10574,7 +10574,7 @@ pub fn vfmlal_laneq_low_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlalq_lane_low_f16( r: float32x4_t, @@ -10591,7 +10591,7 @@ pub fn vfmlalq_lane_low_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlalq_laneq_low_f16( r: float32x4_t, @@ -10606,7 +10606,7 @@ pub fn vfmlalq_laneq_low_f16( #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlal))] pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { @@ -10624,7 +10624,7 @@ pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32 #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlal))] pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { @@ -10642,7 +10642,7 @@ pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3 #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlsl2))] pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { @@ -10660,7 +10660,7 @@ pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3 #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlsl2))] pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { @@ -10680,7 +10680,7 @@ pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlsl_lane_high_f16( r: float32x2_t, @@ -10697,7 +10697,7 @@ pub fn vfmlsl_lane_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlsl_laneq_high_f16( r: float32x2_t, @@ -10714,7 +10714,7 @@ pub fn vfmlsl_laneq_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlslq_lane_high_f16( r: float32x4_t, @@ -10731,7 +10731,7 @@ pub fn vfmlslq_lane_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlslq_laneq_high_f16( r: float32x4_t, @@ -10748,7 +10748,7 @@ pub fn vfmlslq_laneq_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlsl_lane_low_f16( r: float32x2_t, @@ -10765,7 +10765,7 @@ pub fn vfmlsl_lane_low_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlsl_laneq_low_f16( r: float32x2_t, @@ -10782,7 +10782,7 @@ pub fn vfmlsl_laneq_low_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlslq_lane_low_f16( r: float32x4_t, @@ -10799,7 +10799,7 @@ pub fn vfmlslq_lane_low_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlslq_laneq_low_f16( r: float32x4_t, @@ -10814,7 +10814,7 @@ pub fn vfmlslq_laneq_low_f16( #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlsl))] pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { @@ -10832,7 +10832,7 @@ pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32 #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlsl))] pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { @@ -10863,7 +10863,7 @@ pub fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfms_lane_f16( a: float16x4_t, @@ -10879,7 +10879,7 @@ pub fn vfms_lane_f16( #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfms_laneq_f16( a: float16x4_t, @@ -10895,7 +10895,7 @@ pub fn vfms_laneq_f16( #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmsq_lane_f16( a: float16x8_t, @@ -10911,7 +10911,7 @@ pub fn vfmsq_lane_f16( #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmsq_laneq_f16( a: float16x8_t, @@ -11488,16 +11488,9 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v1f64.p0" - )] - fn _vld1_f64_x2(a: *const f64) -> float64x1x2_t; - } - _vld1_f64_x2(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1_f64_x2(ptr: *const f64) -> float64x1x2_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"] @@ -11506,16 +11499,9 @@ pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v1f64.p0" - )] - fn _vld1_f64_x3(a: *const f64) -> float64x1x3_t; - } - _vld1_f64_x3(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1_f64_x3(ptr: *const f64) -> float64x1x3_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"] @@ -11524,16 +11510,9 @@ pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v1f64.p0" - )] - fn _vld1_f64_x4(a: *const f64) -> float64x1x4_t; - } - _vld1_f64_x4(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1_f64_x4(ptr: *const f64) -> float64x1x4_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"] @@ -11542,16 +11521,9 @@ pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v2f64.p0" - )] - fn _vld1q_f64_x2(a: *const f64) -> float64x2x2_t; - } - _vld1q_f64_x2(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1q_f64_x2(ptr: *const f64) -> float64x2x2_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"] @@ -11560,16 +11532,9 @@ pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v2f64.p0" - )] - fn _vld1q_f64_x3(a: *const f64) -> float64x2x3_t; - } - _vld1q_f64_x3(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1q_f64_x3(ptr: *const f64) -> float64x2x3_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"] @@ -11578,16 +11543,9 @@ pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v2f64.p0" - )] - fn _vld1q_f64_x4(a: *const f64) -> float64x2x4_t; - } - _vld1q_f64_x4(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1q_f64_x4(ptr: *const f64) -> float64x2x4_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"] @@ -11652,14 +11610,7 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v1f64.p0" - )] - fn _vld2_f64(ptr: *const float64x1_t) -> float64x1x2_t; - } - _vld2_f64(a as _) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"] @@ -11962,28 +11913,12 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2))] pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { transmute(vld2q_s64(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { - let mut ret_val: uint64x2x2_t = transmute(vld2q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"] #[doc = "## Safety"] @@ -12047,14 +11982,7 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v1f64.p0" - )] - fn _vld3_f64(ptr: *const float64x1_t) -> float64x1x3_t; - } - _vld3_f64(a as _) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"] @@ -12389,29 +12317,12 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { transmute(vld3q_s64(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { - let mut ret_val: uint64x2x3_t = transmute(vld3q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"] #[doc = "## Safety"] @@ -12475,14 +12386,7 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v1f64.p0" - )] - fn _vld4_f64(ptr: *const float64x1_t) -> float64x1x4_t; - } - _vld4_f64(a as _) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"] @@ -12825,30 +12729,12 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { transmute(vld4q_s64(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { - let mut ret_val: uint64x2x4_t = transmute(vld4q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"] #[doc = "## Safety"] @@ -12858,6 +12744,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) -> int64x1_t { static_assert!(LANE == 0); let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64); @@ -12876,6 +12763,7 @@ pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64); @@ -12894,6 +12782,7 @@ pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12907,6 +12796,7 @@ pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_ #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) -> uint64x1_t { static_assert!(LANE == 0); transmute(vldap1_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12920,6 +12810,7 @@ pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12933,6 +12824,7 @@ pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) -> poly64x1_t { static_assert!(LANE == 0); transmute(vldap1_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12946,6 +12838,7 @@ pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1q_lane_p64(ptr: *const p64, src: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(LANE, 1); transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) @@ -13639,7 +13532,14 @@ pub fn vmaxh_f16(a: f16, b: f16) -> f16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnm))] pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - unsafe { simd_fmax(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v1f64" + )] + fn _vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; + } + unsafe { _vmaxnm_f64(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"] @@ -13648,7 +13548,14 @@ pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnm))] pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - unsafe { simd_fmax(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v2f64" + )] + fn _vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { _vmaxnmq_f64(a, b) } } #[doc = "Floating-point Maximum Number"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmh_f16)"] @@ -13658,7 +13565,14 @@ pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxnm))] pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 { - f16::max(a, b) + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.f16" + )] + fn _vmaxnmh_f16(a: f16, b: f16) -> f16; + } + unsafe { _vmaxnmh_f16(a, b) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f16)"] @@ -13668,7 +13582,14 @@ pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 { #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxnmv))] pub fn vmaxnmv_f16(a: float16x4_t) -> f16 { - unsafe { simd_reduce_max(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f16.v4f16" + )] + fn _vmaxnmv_f16(a: float16x4_t) -> f16; + } + unsafe { _vmaxnmv_f16(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f16)"] @@ -13678,7 +13599,14 @@ pub fn vmaxnmv_f16(a: float16x4_t) -> f16 { #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxnmv))] pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 { - unsafe { simd_reduce_max(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f16.v8f16" + )] + fn _vmaxnmvq_f16(a: float16x8_t) -> f16; + } + unsafe { _vmaxnmvq_f16(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"] @@ -13687,7 +13615,14 @@ pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmp))] pub fn vmaxnmv_f32(a: float32x2_t) -> f32 { - unsafe { simd_reduce_max(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32" + )] + fn _vmaxnmv_f32(a: float32x2_t) -> f32; + } + unsafe { _vmaxnmv_f32(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"] @@ -13696,7 +13631,14 @@ pub fn vmaxnmv_f32(a: float32x2_t) -> f32 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmp))] pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 { - unsafe { simd_reduce_max(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64" + )] + fn _vmaxnmvq_f64(a: float64x2_t) -> f64; + } + unsafe { _vmaxnmvq_f64(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"] @@ -13705,7 +13647,14 @@ pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmv))] pub fn vmaxnmvq_f32(a: float32x4_t) -> f32 { - unsafe { simd_reduce_max(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f32.v4f32" + )] + fn _vmaxnmvq_f32(a: float32x4_t) -> f32; + } + unsafe { _vmaxnmvq_f32(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f16)"] @@ -13953,7 +13902,14 @@ pub fn vminh_f16(a: f16, b: f16) -> f16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminnm))] pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - unsafe { simd_fmin(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v1f64" + )] + fn _vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; + } + unsafe { _vminnm_f64(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"] @@ -13962,7 +13918,14 @@ pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminnm))] pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - unsafe { simd_fmin(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v2f64" + )] + fn _vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + unsafe { _vminnmq_f64(a, b) } } #[doc = "Floating-point Minimum Number"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmh_f16)"] @@ -13972,7 +13935,14 @@ pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminnm))] pub fn vminnmh_f16(a: f16, b: f16) -> f16 { - f16::min(a, b) + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.f16" + )] + fn _vminnmh_f16(a: f16, b: f16) -> f16; + } + unsafe { _vminnmh_f16(a, b) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f16)"] @@ -13982,7 +13952,14 @@ pub fn vminnmh_f16(a: f16, b: f16) -> f16 { #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminnmv))] pub fn vminnmv_f16(a: float16x4_t) -> f16 { - unsafe { simd_reduce_min(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f16.v4f16" + )] + fn _vminnmv_f16(a: float16x4_t) -> f16; + } + unsafe { _vminnmv_f16(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f16)"] @@ -13992,7 +13969,14 @@ pub fn vminnmv_f16(a: float16x4_t) -> f16 { #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminnmv))] pub fn vminnmvq_f16(a: float16x8_t) -> f16 { - unsafe { simd_reduce_min(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f16.v8f16" + )] + fn _vminnmvq_f16(a: float16x8_t) -> f16; + } + unsafe { _vminnmvq_f16(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"] @@ -14001,7 +13985,14 @@ pub fn vminnmvq_f16(a: float16x8_t) -> f16 { #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vminnmv_f32(a: float32x2_t) -> f32 { - unsafe { simd_reduce_min(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32" + )] + fn _vminnmv_f32(a: float32x2_t) -> f32; + } + unsafe { _vminnmv_f32(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"] @@ -14010,7 +14001,14 @@ pub fn vminnmv_f32(a: float32x2_t) -> f32 { #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vminnmvq_f64(a: float64x2_t) -> f64 { - unsafe { simd_reduce_min(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64" + )] + fn _vminnmvq_f64(a: float64x2_t) -> f64; + } + unsafe { _vminnmvq_f64(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"] @@ -14019,7 +14017,14 @@ pub fn vminnmvq_f64(a: float64x2_t) -> f64 { #[cfg_attr(test, assert_instr(fminnmv))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vminnmvq_f32(a: float32x4_t) -> f32 { - unsafe { simd_reduce_min(a) } + unsafe extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f32.v4f32" + )] + fn _vminnmvq_f32(a: float32x4_t) -> f32; + } + unsafe { _vminnmvq_f32(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f16)"] @@ -14238,26 +14243,7 @@ pub fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlal_high_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmlal_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"] @@ -14272,26 +14258,7 @@ pub fn vmlal_high_laneq_s16( c: int16x8_t, ) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlal_high_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmlal_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"] @@ -14302,13 +14269,7 @@ pub fn vmlal_high_laneq_s16( #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlal_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlal_high_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmlal_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"] @@ -14323,13 +14284,7 @@ pub fn vmlal_high_laneq_s32( c: int32x4_t, ) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlal_high_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmlal_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"] @@ -14344,26 +14299,7 @@ pub fn vmlal_high_lane_u16( c: uint16x4_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlal_high_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmlal_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"] @@ -14378,26 +14314,7 @@ pub fn vmlal_high_laneq_u16( c: uint16x8_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlal_high_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmlal_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"] @@ -14412,13 +14329,7 @@ pub fn vmlal_high_lane_u32( c: uint32x2_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlal_high_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmlal_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"] @@ -14433,13 +14344,7 @@ pub fn vmlal_high_laneq_u32( c: uint32x4_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlal_high_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmlal_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"] @@ -14582,26 +14487,7 @@ pub fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsl_high_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmlsl_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"] @@ -14616,26 +14502,7 @@ pub fn vmlsl_high_laneq_s16( c: int16x8_t, ) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlsl_high_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmlsl_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"] @@ -14646,13 +14513,7 @@ pub fn vmlsl_high_laneq_s16( #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmlsl_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlsl_high_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmlsl_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"] @@ -14667,13 +14528,7 @@ pub fn vmlsl_high_laneq_s32( c: int32x4_t, ) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsl_high_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmlsl_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"] @@ -14688,26 +14543,7 @@ pub fn vmlsl_high_lane_u16( c: uint16x4_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsl_high_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmlsl_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"] @@ -14722,26 +14558,7 @@ pub fn vmlsl_high_laneq_u16( c: uint16x8_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmlsl_high_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmlsl_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32; 8])) } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"] @@ -14756,13 +14573,7 @@ pub fn vmlsl_high_lane_u32( c: uint32x2_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmlsl_high_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmlsl_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"] @@ -14777,13 +14588,7 @@ pub fn vmlsl_high_laneq_u32( c: uint32x4_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmlsl_high_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmlsl_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32; 4])) } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"] @@ -15078,16 +14883,11 @@ pub fn vmul_lane_f64(a: float64x1_t, b: float64x1_t) -> float64 #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmul_laneq_f16(a: float16x4_t, b: float16x8_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 4])) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f16)"] @@ -15095,29 +14895,11 @@ pub fn vmul_laneq_f16(a: float16x4_t, b: float16x8_t) -> float1 #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulq_laneq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 8])) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64)"] @@ -15211,25 +14993,7 @@ pub fn vmulh_laneq_f16(a: f16, b: float16x8_t) -> f16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmull_high_s16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmull_high_s16(a, simd_shuffle!(b, b, [LANE as u32; 8])) } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"] @@ -15240,25 +15004,7 @@ pub fn vmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32 #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmull_high_s16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmull_high_s16(a, simd_shuffle!(b, b, [LANE as u32; 8])) } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"] @@ -15269,12 +15015,7 @@ pub fn vmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int3 #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmull_high_s32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmull_high_s32(a, simd_shuffle!(b, b, [LANE as u32; 4])) } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"] @@ -15285,12 +15026,7 @@ pub fn vmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64 #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmull_high_s32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmull_high_s32(a, simd_shuffle!(b, b, [LANE as u32; 4])) } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"] @@ -15301,25 +15037,7 @@ pub fn vmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int6 #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmull_high_u16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmull_high_u16(a, simd_shuffle!(b, b, [LANE as u32; 8])) } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"] @@ -15330,25 +15048,7 @@ pub fn vmull_high_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uin #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmull_high_u16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmull_high_u16(a, simd_shuffle!(b, b, [LANE as u32; 8])) } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"] @@ -15359,12 +15059,7 @@ pub fn vmull_high_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> ui #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmull_high_u32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmull_high_u32(a, simd_shuffle!(b, b, [LANE as u32; 4])) } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"] @@ -15375,12 +15070,7 @@ pub fn vmull_high_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uin #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmull_high_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmull_high_u32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmull_high_u32(a, simd_shuffle!(b, b, [LANE as u32; 4])) } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"] @@ -15543,7 +15233,7 @@ pub fn vmull_p64(a: p64, b: p64) -> p128 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { static_assert!(LANE == 0); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 2])) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)"] @@ -15554,7 +15244,7 @@ pub fn vmulq_lane_f64(a: float64x2_t, b: float64x1_t) -> float6 #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32; 2])) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)"] @@ -15602,7 +15292,7 @@ pub fn vmuld_laneq_f64(a: f64, b: float64x2_t) -> f64 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmulx))] pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -15619,7 +15309,7 @@ pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmulx))] pub fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -15702,16 +15392,11 @@ pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulx_lane_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmulx_f16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmulx_f16(a, simd_shuffle!(b, b, [LANE as u32; 4])) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f16)"] @@ -15719,16 +15404,11 @@ pub fn vmulx_lane_f16(a: float16x4_t, b: float16x4_t) -> float1 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulx_laneq_f16(a: float16x4_t, b: float16x8_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmulx_f16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmulx_f16(a, simd_shuffle!(b, b, [LANE as u32; 4])) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f16)"] @@ -15736,29 +15416,11 @@ pub fn vmulx_laneq_f16(a: float16x4_t, b: float16x8_t) -> float #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulxq_lane_f16(a: float16x8_t, b: float16x4_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmulxq_f16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmulxq_f16(a, simd_shuffle!(b, b, [LANE as u32; 8])) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f16)"] @@ -15766,29 +15428,11 @@ pub fn vmulxq_lane_f16(a: float16x8_t, b: float16x4_t) -> float #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulxq_laneq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - unsafe { - vmulxq_f16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) - } + unsafe { vmulxq_f16(a, simd_shuffle!(b, b, [LANE as u32; 8])) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)"] @@ -15799,7 +15443,7 @@ pub fn vmulxq_laneq_f16(a: float16x8_t, b: float16x8_t) -> floa #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulx_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32; 2])) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)"] @@ -15810,7 +15454,7 @@ pub fn vmulx_lane_f32(a: float32x2_t, b: float32x2_t) -> float3 #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulx_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32; 2])) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)"] @@ -15821,12 +15465,7 @@ pub fn vmulx_laneq_f32(a: float32x2_t, b: float32x4_t) -> float #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - unsafe { - vmulxq_f32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmulxq_f32(a, simd_shuffle!(b, b, [LANE as u32; 4])) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)"] @@ -15837,12 +15476,7 @@ pub fn vmulxq_lane_f32(a: float32x4_t, b: float32x2_t) -> float #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - unsafe { - vmulxq_f32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) - } + unsafe { vmulxq_f32(a, simd_shuffle!(b, b, [LANE as u32; 4])) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)"] @@ -15853,7 +15487,7 @@ pub fn vmulxq_laneq_f32(a: float32x4_t, b: float32x4_t) -> floa #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32; 2])) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64)"] @@ -16023,7 +15657,7 @@ pub fn vmulxh_laneq_f16(a: f16, b: float16x8_t) -> f16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vmulxq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { static_assert!(LANE == 0); - unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } + unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32; 2])) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)"] @@ -16128,18 +15762,15 @@ pub fn vpaddd_u64(a: uint64x2_t) -> u64 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(faddp))] pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.faddp.v8f16" - )] - fn _vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + simd_add(even, odd) } - unsafe { _vpaddq_f16(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"] @@ -16148,14 +15779,11 @@ pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.faddp.v4f32" - )] - fn _vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + simd_add(even, odd) } - unsafe { _vpaddq_f32(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"] @@ -16164,14 +15792,11 @@ pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.faddp.v2f64" - )] - fn _vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + simd_add(even, odd) } - unsafe { _vpaddq_f64(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"] @@ -16180,14 +15805,11 @@ pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v16i8" - )] - fn _vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>()); + simd_add(even, odd) } - unsafe { _vpaddq_s8(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"] @@ -16196,14 +15818,11 @@ pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v8i16" - )] - fn _vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + simd_add(even, odd) } - unsafe { _vpaddq_s16(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"] @@ -16212,14 +15831,11 @@ pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v4i32" - )] - fn _vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + simd_add(even, odd) } - unsafe { _vpaddq_s32(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"] @@ -16228,126 +15844,69 @@ pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v2i64" - )] - fn _vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + simd_add(even, odd) } - unsafe { _vpaddq_s64(a, b) } -} -#[doc = "Add Pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(addp))] -pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { transmute(vpaddq_s8(transmute(a), transmute(b))) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; unsafe { - let ret_val: uint8x16_t = transmute(vpaddq_s8(transmute(a), transmute(b))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>()); + simd_add(even, odd) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"] #[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(addp))] -pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { transmute(vpaddq_s16(transmute(a), transmute(b))) } -} -#[doc = "Add Pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; unsafe { - let ret_val: uint16x8_t = transmute(vpaddq_s16(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + simd_add(even, odd) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"] #[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(addp))] -pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { transmute(vpaddq_s32(transmute(a), transmute(b))) } -} -#[doc = "Add Pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) }; unsafe { - let ret_val: uint32x4_t = transmute(vpaddq_s32(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + simd_add(even, odd) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"] #[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(addp))] -pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - unsafe { transmute(vpaddq_s64(transmute(a), transmute(b))) } -} -#[doc = "Add Pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) }; unsafe { - let ret_val: uint64x2_t = transmute(vpaddq_s64(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + simd_add(even, odd) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxp))] pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -16364,7 +15923,7 @@ pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxp))] pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -16381,7 +15940,7 @@ pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxnmp))] pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -16398,7 +15957,7 @@ pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxnmp))] pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -16655,7 +16214,7 @@ pub fn vpmaxs_f32(a: float32x2_t) -> f32 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminp))] pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -16672,7 +16231,7 @@ pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminp))] pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -16689,7 +16248,7 @@ pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminnmp))] pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -16706,7 +16265,7 @@ pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminnmp))] pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -18098,8 +17657,7 @@ pub fn vqnegd_s64(a: i64) -> i64 { pub fn vqrdmlah_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); unsafe { - let c: int16x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); vqrdmlah_s16(a, b, c) } } @@ -18113,7 +17671,7 @@ pub fn vqrdmlah_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4 pub fn vqrdmlah_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]); vqrdmlah_s32(a, b, c) } } @@ -18127,8 +17685,7 @@ pub fn vqrdmlah_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2 pub fn vqrdmlah_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); unsafe { - let c: int16x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); vqrdmlah_s16(a, b, c) } } @@ -18142,7 +17699,7 @@ pub fn vqrdmlah_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x pub fn vqrdmlah_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]); vqrdmlah_s32(a, b, c) } } @@ -18156,20 +17713,7 @@ pub fn vqrdmlah_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x pub fn vqrdmlahq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); unsafe { - let c: int16x8_t = simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); + let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]); vqrdmlahq_s16(a, b, c) } } @@ -18183,8 +17727,7 @@ pub fn vqrdmlahq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x pub fn vqrdmlahq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); unsafe { - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); vqrdmlahq_s32(a, b, c) } } @@ -18198,20 +17741,7 @@ pub fn vqrdmlahq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x pub fn vqrdmlahq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); unsafe { - let c: int16x8_t = simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); + let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]); vqrdmlahq_s16(a, b, c) } } @@ -18225,8 +17755,7 @@ pub fn vqrdmlahq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16 pub fn vqrdmlahq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); unsafe { - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); vqrdmlahq_s32(a, b, c) } } @@ -18372,8 +17901,7 @@ pub fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 { pub fn vqrdmlsh_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); unsafe { - let c: int16x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); vqrdmlsh_s16(a, b, c) } } @@ -18387,7 +17915,7 @@ pub fn vqrdmlsh_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4 pub fn vqrdmlsh_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]); vqrdmlsh_s32(a, b, c) } } @@ -18401,8 +17929,7 @@ pub fn vqrdmlsh_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2 pub fn vqrdmlsh_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); unsafe { - let c: int16x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); vqrdmlsh_s16(a, b, c) } } @@ -18416,7 +17943,7 @@ pub fn vqrdmlsh_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x pub fn vqrdmlsh_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); unsafe { - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32; 2]); vqrdmlsh_s32(a, b, c) } } @@ -18430,20 +17957,7 @@ pub fn vqrdmlsh_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x pub fn vqrdmlshq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); unsafe { - let c: int16x8_t = simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); + let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]); vqrdmlshq_s16(a, b, c) } } @@ -18457,8 +17971,7 @@ pub fn vqrdmlshq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x pub fn vqrdmlshq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); unsafe { - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); vqrdmlshq_s32(a, b, c) } } @@ -18472,20 +17985,7 @@ pub fn vqrdmlshq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x pub fn vqrdmlshq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); unsafe { - let c: int16x8_t = simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); + let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32; 8]); vqrdmlshq_s16(a, b, c) } } @@ -18499,8 +17999,7 @@ pub fn vqrdmlshq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16 pub fn vqrdmlshq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); unsafe { - let c: int32x4_t = - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32; 4]); vqrdmlshq_s32(a, b, c) } } @@ -19732,7 +19231,6 @@ pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t { #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19740,38 +19238,8 @@ pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x16x2_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19779,43 +19247,8 @@ pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { unsafe { transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { - let mut a: uint8x16x2_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19823,38 +19256,8 @@ pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x16x2_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19862,40 +19265,6 @@ pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { unsafe { transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { - let mut a: poly8x16x2_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -19948,7 +19317,6 @@ pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t { #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19956,46 +19324,8 @@ pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x16x3_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = - transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20003,51 +19333,8 @@ pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { unsafe { transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { - let mut a: uint8x16x3_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = - transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20055,46 +19342,8 @@ pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x16x3_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = - transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20102,48 +19351,6 @@ pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { unsafe { transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { - let mut a: poly8x16x3_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = - transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -20208,7 +19415,6 @@ pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t { #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20224,58 +19430,8 @@ pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x16x4_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.3 = unsafe { - simd_shuffle!( - a.3, - a.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20291,63 +19447,8 @@ pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { - let mut a: uint8x16x4_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.3 = unsafe { - simd_shuffle!( - a.3, - a.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vqtbl4q( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20363,58 +19464,8 @@ pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x16x4_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.3 = unsafe { - simd_shuffle!( - a.3, - a.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20429,60 +19480,6 @@ pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { )) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { - let mut a: poly8x16x4_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.3 = unsafe { - simd_shuffle!( - a.3, - a.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(vqtbl4q( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1)"] #[inline(always)] @@ -20622,7 +19619,6 @@ pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t { #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20630,39 +19626,8 @@ pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x16x2_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20670,46 +19635,8 @@ pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { unsafe { transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { - let mut b: uint8x16x2_t = b; - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = - transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20717,39 +19644,8 @@ pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x16x2_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20757,43 +19653,6 @@ pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { unsafe { transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { - let mut b: poly8x16x2_t = b; - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = - transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -20833,159 +19692,30 @@ fn vqtbx3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t unsafe { _vqtbx3q(a, b, c, d, e) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t { - vqtbx3(a, b.0, b.1, b.2, c) -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_s8)"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t { - vqtbx3q(a, b.0, b.1, b.2, c) -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { - unsafe { - transmute(vqtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x16x3_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_s8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { - unsafe { - transmute(vqtbx3q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )) - } +pub fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t { + vqtbx3(a, b.0, b.1, b.2, c) } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_s8)"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { - let mut b: uint8x16x3_t = b; - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vqtbx3q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } +pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t { + vqtbx3q(a, b.0, b.1, b.2, c) } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { +pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbx3( transmute(a), @@ -20997,58 +19727,31 @@ pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x16x3_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; +pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { unsafe { - let ret_val: poly8x8_t = transmute(vqtbx3( + transmute(vqtbx3q( transmute(a), transmute(b.0), transmute(b.1), transmute(b.2), c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + )) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { +pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { unsafe { - transmute(vqtbx3q( + transmute(vqtbx3( transmute(a), transmute(b.0), transmute(b.1), @@ -21060,50 +19763,18 @@ pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { - let mut b: poly8x16x3_t = b; - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; unsafe { - let ret_val: poly8x16_t = transmute(vqtbx3q( + transmute(vqtbx3q( transmute(a), transmute(b.0), transmute(b.1), transmute(b.2), c, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + )) } } #[doc = "Extended table look-up"] @@ -21187,7 +19858,6 @@ pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t { #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21204,60 +19874,8 @@ pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x16x4_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.3 = unsafe { - simd_shuffle!( - b.3, - b.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21274,66 +19892,8 @@ pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { - let mut b: uint8x16x4_t = b; - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.3 = unsafe { - simd_shuffle!( - b.3, - b.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vqtbx4q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21350,60 +19910,8 @@ pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x16x4_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.3 = unsafe { - simd_shuffle!( - b.3, - b.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21419,63 +19927,6 @@ pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { )) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { - let mut b: poly8x16x4_t = b; - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.3 = unsafe { - simd_shuffle!( - b.3, - b.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(vqtbx4q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} #[doc = "Rotate and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrax1q_u64)"] #[inline(always)] @@ -21832,7 +20283,7 @@ pub fn vrecpxh_f16(a: f16) -> f16 { #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { @@ -21843,7 +20294,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { @@ -21855,7 +20306,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { @@ -21866,7 +20317,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { @@ -21881,7 +20332,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { @@ -21892,7 +20343,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { @@ -21906,7 +20357,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { @@ -21917,7 +20368,7 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { @@ -23496,7 +21947,7 @@ pub fn vrnd64z_f64(a: float64x1_t) -> float64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintz))] pub fn vrnd_f16(a: float16x4_t) -> float16x4_t { @@ -23506,7 +21957,7 @@ pub fn vrnd_f16(a: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintz))] pub fn vrndq_f16(a: float16x8_t) -> float16x8_t { @@ -23552,7 +22003,7 @@ pub fn vrndq_f64(a: float64x2_t) -> float64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frinta))] pub fn vrnda_f16(a: float16x4_t) -> float16x4_t { @@ -23562,7 +22013,7 @@ pub fn vrnda_f16(a: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frinta))] pub fn vrndaq_f16(a: float16x8_t) -> float16x8_t { @@ -23628,7 +22079,7 @@ pub fn vrndh_f16(a: f16) -> f16 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frinti))] pub fn vrndi_f16(a: float16x4_t) -> float16x4_t { @@ -23645,7 +22096,7 @@ pub fn vrndi_f16(a: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frinti))] pub fn vrndiq_f16(a: float16x8_t) -> float16x8_t { @@ -23743,7 +22194,7 @@ pub fn vrndih_f16(a: f16) -> f16 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintm))] pub fn vrndm_f16(a: float16x4_t) -> float16x4_t { @@ -23753,7 +22204,7 @@ pub fn vrndm_f16(a: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintm))] pub fn vrndmq_f16(a: float16x8_t) -> float16x8_t { @@ -23874,7 +22325,7 @@ pub fn vrndns_f32(a: f32) -> f32 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintp))] pub fn vrndp_f16(a: float16x4_t) -> float16x4_t { @@ -23884,7 +22335,7 @@ pub fn vrndp_f16(a: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintp))] pub fn vrndpq_f16(a: float16x8_t) -> float16x8_t { @@ -23940,7 +22391,7 @@ pub fn vrndph_f16(a: f16) -> f16 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintx))] pub fn vrndx_f16(a: float16x4_t) -> float16x4_t { @@ -23950,7 +22401,7 @@ pub fn vrndx_f16(a: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintx))] pub fn vrndxq_f16(a: float16x8_t) -> float16x8_t { @@ -25453,7 +23904,7 @@ pub fn vsqadds_u32(a: u32, b: i32) -> u32 { #[inline(always)] #[cfg_attr(test, assert_instr(fsqrt))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t { unsafe { simd_fsqrt(a) } @@ -25463,7 +23914,7 @@ pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fsqrt))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vsqrtq_f16(a: float16x8_t) -> float16x8_t { unsafe { simd_fsqrt(a) } @@ -25523,14 +23974,7 @@ pub fn vsqrth_f16(a: f16) -> f16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v8i8" - )] - fn _vsri_n_s8(a: int8x8_t, b: int8x8_t, n: i32) -> int8x8_t; - } - unsafe { _vsri_n_s8(a, b, N) } + unsafe { super::shift_right_and_insert!(u8, 8, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"] @@ -25541,14 +23985,7 @@ pub fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v16i8" - )] - fn _vsriq_n_s8(a: int8x16_t, b: int8x16_t, n: i32) -> int8x16_t; - } - unsafe { _vsriq_n_s8(a, b, N) } + unsafe { super::shift_right_and_insert!(u8, 16, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"] @@ -25559,14 +23996,7 @@ pub fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v4i16" - )] - fn _vsri_n_s16(a: int16x4_t, b: int16x4_t, n: i32) -> int16x4_t; - } - unsafe { _vsri_n_s16(a, b, N) } + unsafe { super::shift_right_and_insert!(u16, 4, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"] @@ -25577,14 +24007,7 @@ pub fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v8i16" - )] - fn _vsriq_n_s16(a: int16x8_t, b: int16x8_t, n: i32) -> int16x8_t; - } - unsafe { _vsriq_n_s16(a, b, N) } + unsafe { super::shift_right_and_insert!(u16, 8, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"] @@ -25594,15 +24017,8 @@ pub fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v2i32" - )] - fn _vsri_n_s32(a: int32x2_t, b: int32x2_t, n: i32) -> int32x2_t; - } - unsafe { _vsri_n_s32(a, b, N) } + static_assert!(N >= 1 && N <= 32); + unsafe { super::shift_right_and_insert!(u32, 2, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"] @@ -25613,14 +24029,7 @@ pub fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v4i32" - )] - fn _vsriq_n_s32(a: int32x4_t, b: int32x4_t, n: i32) -> int32x4_t; - } - unsafe { _vsriq_n_s32(a, b, N) } + unsafe { super::shift_right_and_insert!(u32, 4, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"] @@ -25631,14 +24040,7 @@ pub fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { static_assert!(N >= 1 && N <= 64); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v1i64" - )] - fn _vsri_n_s64(a: int64x1_t, b: int64x1_t, n: i32) -> int64x1_t; - } - unsafe { _vsri_n_s64(a, b, N) } + unsafe { super::shift_right_and_insert!(u64, 1, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"] @@ -25649,14 +24051,7 @@ pub fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsriq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { static_assert!(N >= 1 && N <= 64); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v2i64" - )] - fn _vsriq_n_s64(a: int64x2_t, b: int64x2_t, n: i32) -> int64x2_t; - } - unsafe { _vsriq_n_s64(a, b, N) } + unsafe { super::shift_right_and_insert!(u64, 2, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"] @@ -25818,7 +24213,7 @@ pub fn vsriq_n_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(bfxil, N = 2))] pub fn vsrid_n_s64(a: i64, b: i64) -> i64 { static_assert!(N >= 1 && N <= 64); unsafe { transmute(vsri_n_s64::(transmute(a), transmute(b))) } @@ -25829,7 +24224,7 @@ pub fn vsrid_n_s64(a: i64, b: i64) -> i64 { #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(bfxil, N = 2))] pub fn vsrid_n_u64(a: u64, b: u64) -> u64 { static_assert!(N >= 1 && N <= 64); unsafe { transmute(vsri_n_u64::(transmute(a), transmute(b))) } @@ -26325,16 +24720,9 @@ pub unsafe fn vst1q_lane_f64(a: *mut f64, b: float64x2_t) { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(st1))] +#[cfg_attr(test, assert_instr(stp))] pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v1f64.p0" - )] - fn _vst2_f64(a: float64x1_t, b: float64x1_t, ptr: *mut i8); - } - _vst2_f64(b.0, b.1, a as _) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"] @@ -26411,14 +24799,7 @@ pub unsafe fn vst2_lane_u64(a: *mut u64, b: uint64x1x2_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v2f64.p0" - )] - fn _vst2q_f64(a: float64x2_t, b: float64x2_t, ptr: *mut i8); - } - _vst2q_f64(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(f64, 2, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"] @@ -26429,14 +24810,7 @@ pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v2i64.p0" - )] - fn _vst2q_s64(a: int64x2_t, b: int64x2_t, ptr: *mut i8); - } - _vst2q_s64(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i64, 2, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"] @@ -26581,14 +24955,7 @@ pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v1f64.p0" - )] - fn _vst3_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t, ptr: *mut i8); - } - _vst3_f64(b.0, b.1, b.2, a as _) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"] @@ -26665,14 +25032,7 @@ pub unsafe fn vst3_lane_u64(a: *mut u64, b: uint64x1x3_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v2f64.p0" - )] - fn _vst3q_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t, ptr: *mut i8); - } - _vst3q_f64(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(f64, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"] @@ -26683,14 +25043,7 @@ pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v2i64.p0" - )] - fn _vst3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t, ptr: *mut i8); - } - _vst3q_s64(b.0, b.1, b.2, a as _) + crate::core_arch::macros::interleaving_store!(i64, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"] @@ -26835,14 +25188,7 @@ pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v1f64.p0" - )] - fn _vst4_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t, d: float64x1_t, ptr: *mut i8); - } - _vst4_f64(b.0, b.1, b.2, b.3, a as _) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"] @@ -26933,14 +25279,7 @@ pub unsafe fn vst4_lane_u64(a: *mut u64, b: uint64x1x4_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v2f64.p0" - )] - fn _vst4q_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t, d: float64x2_t, ptr: *mut i8); - } - _vst4q_f64(b.0, b.1, b.2, b.3, a as _) + crate::core_arch::macros::interleaving_store!(f64, 2, 4, a, b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"] @@ -26951,14 +25290,7 @@ pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v2i64.p0" - )] - fn _vst4q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, ptr: *mut i8); - } - _vst4q_s64(b.0, b.1, b.2, b.3, a as _) + crate::core_arch::macros::interleaving_store!(i64, 2, 4, a, b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"] @@ -27122,6 +25454,7 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { static_assert!(LANE == 0); unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } @@ -27133,6 +25466,7 @@ pub fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { static_assert_uimm_bits!(LANE, 1); unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } @@ -27144,6 +25478,7 @@ pub fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { static_assert!(LANE == 0); unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } @@ -27155,6 +25490,7 @@ pub fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { static_assert_uimm_bits!(LANE, 1); unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } @@ -27166,6 +25502,7 @@ pub fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { static_assert!(LANE == 0); unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } @@ -27177,6 +25514,7 @@ pub fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { static_assert_uimm_bits!(LANE, 1); unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } @@ -27188,6 +25526,7 @@ pub fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { static_assert!(LANE == 0); let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; @@ -27203,6 +25542,7 @@ pub fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1q_lane_s64(ptr: *mut i64, val: int64x2_t) { static_assert_uimm_bits!(LANE, 1); let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; @@ -27462,7 +25802,6 @@ pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27470,26 +25809,8 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x2_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27497,23 +25818,6 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x2_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -27529,7 +25833,6 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27541,31 +25844,8 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x3_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let x = uint8x16x2_t( - vcombine_u8(a.0, a.1), - vcombine_u8(a.2, unsafe { crate::mem::zeroed() }), - ); - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27577,28 +25857,6 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x3_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let x = poly8x16x2_t( - vcombine_p8(a.0, a.1), - vcombine_p8(a.2, unsafe { crate::mem::zeroed() }), - ); - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -27611,7 +25869,6 @@ pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27620,29 +25877,8 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x4_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let x = uint8x16x2_t(vcombine_u8(a.0, a.1), vcombine_u8(a.2, a.3)); - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27650,26 +25886,6 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3)); unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x4_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3)); - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"] #[inline(always)] @@ -27739,7 +25955,6 @@ pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t { #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27747,28 +25962,8 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x2_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = - transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27776,25 +25971,6 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x2_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = - transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -27821,7 +25997,6 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t { #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27839,36 +26014,8 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x3_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let x = uint8x16x2_t( - vcombine_u8(b.0, b.1), - vcombine_u8(b.2, unsafe { crate::mem::zeroed() }), - ); - unsafe { - let ret_val: uint8x8_t = transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), - a, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27886,33 +26033,6 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x3_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let x = poly8x16x2_t( - vcombine_p8(b.0, b.1), - vcombine_p8(b.2, unsafe { crate::mem::zeroed() }), - ); - unsafe { - let ret_val: poly8x8_t = transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), - a, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -27931,7 +26051,6 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27946,34 +26065,8 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x4_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbx2( - transmute(a), - transmute(vcombine_u8(b.0, b.1)), - transmute(vcombine_u8(b.2, b.3)), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27987,36 +26080,11 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { )) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x4_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbx2( - transmute(a), - transmute(vcombine_p8(b.0, b.1)), - transmute(vcombine_p8(b.2, b.3)), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -28026,7 +26094,7 @@ pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -28252,7 +26320,7 @@ pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -28262,7 +26330,7 @@ pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -28762,7 +26830,7 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -28772,7 +26840,7 @@ pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -28998,7 +27066,7 @@ pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -29008,7 +27076,7 @@ pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -29252,7 +27320,7 @@ pub fn vxarq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -29262,7 +27330,7 @@ pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -29488,7 +27556,7 @@ pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -29498,7 +27566,7 @@ pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { diff --git a/stdarch/crates/core_arch/src/aarch64/neon/mod.rs b/stdarch/crates/core_arch/src/aarch64/neon/mod.rs index b172b57f32543..2fbd2255aa0fd 100644 --- a/stdarch/crates/core_arch/src/aarch64/neon/mod.rs +++ b/stdarch/crates/core_arch/src/aarch64/neon/mod.rs @@ -70,6 +70,30 @@ pub struct float64x2x4_t( pub float64x2_t, ); +/// Helper for the 'shift right and insert' functions. +macro_rules! shift_right_and_insert { + ($ty:ty, $width:literal, $N:expr, $a:expr, $b:expr) => {{ + type V = Simd<$ty, $width>; + + if $N as u32 == <$ty>::BITS { + $a + } else { + let a: V = transmute($a); + let b: V = transmute($b); + + let mask = <$ty>::MAX >> $N; + let kept: V = simd_and(a, V::splat(!mask)); + + let shift_counts = V::splat($N as $ty); + let shifted = simd_shr(b, shift_counts); + + transmute(simd_or(kept, shifted)) + } + }}; +} + +pub(crate) use shift_right_and_insert; + /// Duplicate vector element to vector or scalar #[inline] #[target_feature(enable = "neon")] @@ -569,47 +593,46 @@ mod tests { use crate::core_arch::aarch64::test_support::*; use crate::core_arch::arm_shared::test_support::*; use crate::core_arch::{aarch64::neon::*, aarch64::*, simd::*}; - use std::mem::transmute; use stdarch_test::simd_test; #[simd_test(enable = "neon")] - unsafe fn test_vadd_f64() { - let a = 1.; - let b = 8.; - let e = 9.; - let r: f64 = transmute(vadd_f64(transmute(a), transmute(b))); + fn test_vadd_f64() { + let a = f64x1::from_array([1.]); + let b = f64x1::from_array([8.]); + let e = f64x1::from_array([9.]); + let r = f64x1::from(vadd_f64(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vaddq_f64() { + fn test_vaddq_f64() { let a = f64x2::new(1., 2.); let b = f64x2::new(8., 7.); let e = f64x2::new(9., 9.); - let r: f64x2 = transmute(vaddq_f64(transmute(a), transmute(b))); + let r = f64x2::from(vaddq_f64(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vadd_s64() { - let a = 1_i64; - let b = 8_i64; - let e = 9_i64; - let r: i64 = transmute(vadd_s64(transmute(a), transmute(b))); + fn test_vadd_s64() { + let a = i64x1::from_array([1]); + let b = i64x1::from_array([8]); + let e = i64x1::from_array([9]); + let r = i64x1::from(vadd_s64(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vadd_u64() { - let a = 1_u64; - let b = 8_u64; - let e = 9_u64; - let r: u64 = transmute(vadd_u64(transmute(a), transmute(b))); + fn test_vadd_u64() { + let a = u64x1::from_array([1]); + let b = u64x1::from_array([8]); + let e = u64x1::from_array([9]); + let r = u64x1::from(vadd_u64(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vaddd_s64() { + fn test_vaddd_s64() { let a = 1_i64; let b = 8_i64; let e = 9_i64; @@ -618,7 +641,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vaddd_u64() { + fn test_vaddd_u64() { let a = 1_u64; let b = 8_u64; let e = 9_u64; @@ -627,25 +650,25 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vext_p64() { - let a: i64x1 = i64x1::new(0); - let b: i64x1 = i64x1::new(1); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vext_p64::<0>(transmute(a), transmute(b))); + fn test_vext_p64() { + let a = u64x1::new(0); + let b = u64x1::new(1); + let e = u64x1::new(0); + let r = u64x1::from(vext_p64::<0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vext_f64() { - let a: f64x1 = f64x1::new(0.); - let b: f64x1 = f64x1::new(1.); - let e: f64x1 = f64x1::new(0.); - let r: f64x1 = transmute(vext_f64::<0>(transmute(a), transmute(b))); + fn test_vext_f64() { + let a = f64x1::new(0.); + let b = f64x1::new(1.); + let e = f64x1::new(0.); + let r = f64x1::from(vext_f64::<0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vshld_n_s64() { + fn test_vshld_n_s64() { let a: i64 = 1; let e: i64 = 4; let r: i64 = vshld_n_s64::<2>(a); @@ -653,7 +676,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vshld_n_u64() { + fn test_vshld_n_u64() { let a: u64 = 1; let e: u64 = 4; let r: u64 = vshld_n_u64::<2>(a); @@ -661,7 +684,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vshrd_n_s64() { + fn test_vshrd_n_s64() { let a: i64 = 4; let e: i64 = 1; let r: i64 = vshrd_n_s64::<2>(a); @@ -669,7 +692,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vshrd_n_u64() { + fn test_vshrd_n_u64() { let a: u64 = 4; let e: u64 = 1; let r: u64 = vshrd_n_u64::<2>(a); @@ -677,7 +700,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vsrad_n_s64() { + fn test_vsrad_n_s64() { let a: i64 = 1; let b: i64 = 4; let e: i64 = 2; @@ -686,7 +709,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vsrad_n_u64() { + fn test_vsrad_n_u64() { let a: u64 = 1; let b: u64 = 4; let e: u64 = 2; @@ -695,298 +718,575 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vdup_n_f64() { + fn test_vdup_n_f64() { let a: f64 = 3.3; let e = f64x1::new(3.3); - let r: f64x1 = transmute(vdup_n_f64(a)); + let r = f64x1::from(vdup_n_f64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vdup_n_p64() { + fn test_vdup_n_p64() { let a: u64 = 3; let e = u64x1::new(3); - let r: u64x1 = transmute(vdup_n_p64(a)); + let r = u64x1::from(vdup_n_p64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vdupq_n_f64() { + fn test_vdupq_n_f64() { let a: f64 = 3.3; let e = f64x2::new(3.3, 3.3); - let r: f64x2 = transmute(vdupq_n_f64(a)); + let r = f64x2::from(vdupq_n_f64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vdupq_n_p64() { + fn test_vdupq_n_p64() { let a: u64 = 3; let e = u64x2::new(3, 3); - let r: u64x2 = transmute(vdupq_n_p64(a)); + let r = u64x2::from(vdupq_n_p64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vmov_n_p64() { + fn test_vmov_n_p64() { let a: u64 = 3; let e = u64x1::new(3); - let r: u64x1 = transmute(vmov_n_p64(a)); + let r = u64x1::from(vmov_n_p64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vmov_n_f64() { + fn test_vmov_n_f64() { let a: f64 = 3.3; let e = f64x1::new(3.3); - let r: f64x1 = transmute(vmov_n_f64(a)); + let r = f64x1::from(vmov_n_f64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vmovq_n_p64() { + fn test_vmovq_n_p64() { let a: u64 = 3; let e = u64x2::new(3, 3); - let r: u64x2 = transmute(vmovq_n_p64(a)); + let r = u64x2::from(vmovq_n_p64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vmovq_n_f64() { + fn test_vmovq_n_f64() { let a: f64 = 3.3; let e = f64x2::new(3.3, 3.3); - let r: f64x2 = transmute(vmovq_n_f64(a)); + let r = f64x2::from(vmovq_n_f64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vget_high_f64() { + fn test_vget_high_f64() { let a = f64x2::new(1.0, 2.0); let e = f64x1::new(2.0); - let r: f64x1 = transmute(vget_high_f64(transmute(a))); + let r = f64x1::from(vget_high_f64(a.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vget_high_p64() { + fn test_vget_high_p64() { let a = u64x2::new(1, 2); let e = u64x1::new(2); - let r: u64x1 = transmute(vget_high_p64(transmute(a))); + let r = u64x1::from(vget_high_p64(a.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vget_low_f64() { + fn test_vget_low_f64() { let a = f64x2::new(1.0, 2.0); let e = f64x1::new(1.0); - let r: f64x1 = transmute(vget_low_f64(transmute(a))); + let r = f64x1::from(vget_low_f64(a.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vget_low_p64() { + fn test_vget_low_p64() { let a = u64x2::new(1, 2); let e = u64x1::new(1); - let r: u64x1 = transmute(vget_low_p64(transmute(a))); + let r = u64x1::from(vget_low_p64(a.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vget_lane_f64() { + fn test_vget_lane_f64() { let v = f64x1::new(1.0); - let r = vget_lane_f64::<0>(transmute(v)); + let r = vget_lane_f64::<0>(v.into()); assert_eq!(r, 1.0); } #[simd_test(enable = "neon")] - unsafe fn test_vgetq_lane_f64() { + fn test_vgetq_lane_f64() { let v = f64x2::new(0.0, 1.0); - let r = vgetq_lane_f64::<1>(transmute(v)); + let r = vgetq_lane_f64::<1>(v.into()); assert_eq!(r, 1.0); - let r = vgetq_lane_f64::<0>(transmute(v)); + let r = vgetq_lane_f64::<0>(v.into()); assert_eq!(r, 0.0); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vcopy_lane_s64::<0, 0>(transmute(a), transmute(b))); + fn test_vcopy_lane_s64() { + let a = i64x1::new(1); + let b = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let e = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let r = i64x1::from(vcopy_lane_s64::<0, 0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_u64() { - let a: u64x1 = u64x1::new(1); - let b: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcopy_lane_u64::<0, 0>(transmute(a), transmute(b))); + fn test_vcopy_lane_u64() { + let a = u64x1::new(1); + let b = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); + let e = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); + let r = u64x1::from(vcopy_lane_u64::<0, 0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_p64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vcopy_lane_p64::<0, 0>(transmute(a), transmute(b))); + fn test_vcopy_lane_p64() { + let a = u64x1::new(1); + let b = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let e = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let r = u64x1::from(vcopy_lane_p64::<0, 0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_f64() { - let a: f64 = 1.; - let b: f64 = 0.; - let e: f64 = 0.; - let r: f64 = transmute(vcopy_lane_f64::<0, 0>(transmute(a), transmute(b))); + fn test_vcopy_lane_f64() { + let a = f64x1::from_array([1.]); + let b = f64x1::from_array([0.]); + let e = f64x1::from_array([0.]); + let r = f64x1::from(vcopy_lane_f64::<0, 0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vcopy_laneq_s64::<0, 1>(transmute(a), transmute(b))); + fn test_vcopy_laneq_s64() { + let a = i64x1::new(1); + let b = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); + let e = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let r = i64x1::from(vcopy_laneq_s64::<0, 1>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_u64() { - let a: u64x1 = u64x1::new(1); - let b: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcopy_laneq_u64::<0, 1>(transmute(a), transmute(b))); + fn test_vcopy_laneq_u64() { + let a = u64x1::new(1); + let b = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); + let e = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); + let r = u64x1::from(vcopy_laneq_u64::<0, 1>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_p64() { - let a: i64x1 = i64x1::new(1); - let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vcopy_laneq_p64::<0, 1>(transmute(a), transmute(b))); + fn test_vcopy_laneq_p64() { + let a = u64x1::new(1); + let b = u64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); + let e = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let r = u64x1::from(vcopy_laneq_p64::<0, 1>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_f64() { - let a: f64 = 1.; - let b: f64x2 = f64x2::new(0., 0.5); - let e: f64 = 0.5; - let r: f64 = transmute(vcopy_laneq_f64::<0, 1>(transmute(a), transmute(b))); + fn test_vcopy_laneq_f64() { + let a = f64x1::from_array([1.]); + let b = f64x2::from_array([0., 0.5]); + let e = f64x1::from_array([0.5]); + let r = f64x1::from(vcopy_laneq_f64::<0, 1>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vbsl_f64() { + fn test_vbsl_f64() { let a = u64x1::new(0x8000000000000000); let b = f64x1::new(-1.23f64); let c = f64x1::new(2.34f64); let e = f64x1::new(-2.34f64); - let r: f64x1 = transmute(vbsl_f64(transmute(a), transmute(b), transmute(c))); + let r = f64x1::from(vbsl_f64(a.into(), b.into(), c.into())); assert_eq!(r, e); } + #[simd_test(enable = "neon")] - unsafe fn test_vbsl_p64() { + fn test_vbsl_p64() { let a = u64x1::new(1); let b = u64x1::new(u64::MAX); let c = u64x1::new(u64::MIN); let e = u64x1::new(1); - let r: u64x1 = transmute(vbsl_p64(transmute(a), transmute(b), transmute(c))); + let r = u64x1::from(vbsl_p64(a.into(), b.into(), c.into())); assert_eq!(r, e); } + #[simd_test(enable = "neon")] - unsafe fn test_vbslq_f64() { + fn test_vbslq_f64() { let a = u64x2::new(1, 0x8000000000000000); let b = f64x2::new(f64::MAX, -1.23f64); let c = f64x2::new(f64::MIN, 2.34f64); let e = f64x2::new(f64::MIN, -2.34f64); - let r: f64x2 = transmute(vbslq_f64(transmute(a), transmute(b), transmute(c))); + let r = f64x2::from(vbslq_f64(a.into(), b.into(), c.into())); assert_eq!(r, e); } + #[simd_test(enable = "neon")] - unsafe fn test_vbslq_p64() { + fn test_vbslq_p64() { let a = u64x2::new(u64::MAX, 1); let b = u64x2::new(u64::MAX, u64::MAX); let c = u64x2::new(u64::MIN, u64::MIN); let e = u64x2::new(u64::MAX, 1); - let r: u64x2 = transmute(vbslq_p64(transmute(a), transmute(b), transmute(c))); + let r = u64x2::from(vbslq_p64(a.into(), b.into(), c.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vld1_f64() { + fn test_vld1_f64() { let a: [f64; 2] = [0., 1.]; let e = f64x1::new(1.); - let r: f64x1 = transmute(vld1_f64(a[1..].as_ptr())); + let r = unsafe { f64x1::from(vld1_f64(a[1..].as_ptr())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1q_f64() { + fn test_vld1q_f64() { let a: [f64; 3] = [0., 1., 2.]; let e = f64x2::new(1., 2.); - let r: f64x2 = transmute(vld1q_f64(a[1..].as_ptr())); + let r = unsafe { f64x2::from(vld1q_f64(a[1..].as_ptr())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1_dup_f64() { + fn test_vld1_dup_f64() { let a: [f64; 2] = [1., 42.]; let e = f64x1::new(42.); - let r: f64x1 = transmute(vld1_dup_f64(a[1..].as_ptr())); + let r = unsafe { f64x1::from(vld1_dup_f64(a[1..].as_ptr())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1q_dup_f64() { + fn test_vld1q_dup_f64() { let elem: f64 = 42.; let e = f64x2::new(42., 42.); - let r: f64x2 = transmute(vld1q_dup_f64(&elem)); + let r = unsafe { f64x2::from(vld1q_dup_f64(&elem)) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1_lane_f64() { + fn test_vld1_lane_f64() { let a = f64x1::new(0.); let elem: f64 = 42.; let e = f64x1::new(42.); - let r: f64x1 = transmute(vld1_lane_f64::<0>(&elem, transmute(a))); + let r = unsafe { f64x1::from(vld1_lane_f64::<0>(&elem, a.into())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1q_lane_f64() { + fn test_vld1q_lane_f64() { let a = f64x2::new(0., 1.); let elem: f64 = 42.; let e = f64x2::new(0., 42.); - let r: f64x2 = transmute(vld1q_lane_f64::<1>(&elem, transmute(a))); + let r = unsafe { f64x2::from(vld1q_lane_f64::<1>(&elem, a.into())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vst1_f64() { + fn test_vst1_f64() { let mut vals = [0_f64; 2]; let a = f64x1::new(1.); - vst1_f64(vals[1..].as_mut_ptr(), transmute(a)); + unsafe { + vst1_f64(vals[1..].as_mut_ptr(), a.into()); + } assert_eq!(vals[0], 0.); assert_eq!(vals[1], 1.); } #[simd_test(enable = "neon")] - unsafe fn test_vst1q_f64() { + fn test_vst1q_f64() { let mut vals = [0_f64; 3]; let a = f64x2::new(1., 2.); - vst1q_f64(vals[1..].as_mut_ptr(), transmute(a)); + unsafe { + vst1q_f64(vals[1..].as_mut_ptr(), a.into()); + } assert_eq!(vals[0], 0.); assert_eq!(vals[1], 1.); assert_eq!(vals[2], 2.); } + + macro_rules! wide_store_load_roundtrip { + ($elem_ty:ty, $len:expr, $vec_ty:ty, $store:expr, $load:expr) => { + let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty); + let a: $vec_ty = transmute(vals); + let mut tmp = [0 as $elem_ty; $len]; + $store(tmp.as_mut_ptr().cast(), a); + let r: $vec_ty = $load(tmp.as_ptr().cast()); + let out: [$elem_ty; $len] = transmute(r); + assert_eq!(out, vals); + }; + } + + macro_rules! wide_store_load_roundtrip_fp16 { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[simd_test(enable = "neon,fp16")] + #[cfg(not(target_arch = "arm64ec"))] + unsafe fn $name() { + wide_store_load_roundtrip! $args; + } + )* + }; + } + + wide_store_load_roundtrip_fp16! { + test_vld1_f16_x2(f16, 8, float16x4x2_t, vst1_f16_x2, vld1_f16_x2); + test_vld1_f16_x3(f16, 12, float16x4x3_t, vst1_f16_x3, vld1_f16_x3); + test_vld1_f16_x4(f16, 16, float16x4x4_t, vst1_f16_x4, vld1_f16_x4); + + test_vld1q_f16_x2(f16, 16, float16x8x2_t, vst1q_f16_x2, vld1q_f16_x2); + test_vld1q_f16_x3(f16, 24, float16x8x3_t, vst1q_f16_x3, vld1q_f16_x3); + test_vld1q_f16_x4(f16, 32, float16x8x4_t, vst1q_f16_x4, vld1q_f16_x4); + + test_vld2_f16_x2(f16, 8, float16x4x2_t, vst2_f16, vld2_f16); + test_vld2_f16_x3(f16, 12, float16x4x3_t, vst3_f16, vld3_f16); + test_vld2_f16_x4(f16, 16, float16x4x4_t, vst4_f16, vld4_f16); + + test_vld2q_f16_x2(f16, 16, float16x8x2_t, vst2q_f16, vld2q_f16); + test_vld3q_f16_x3(f16, 24, float16x8x3_t, vst3q_f16, vld3q_f16); + test_vld4q_f16_x4(f16, 32, float16x8x4_t, vst4q_f16, vld4q_f16); + } + + macro_rules! wide_store_load_roundtrip_aes { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[simd_test(enable = "neon,aes")] + unsafe fn $name() { + wide_store_load_roundtrip! $args; + } + )* + }; + } + + wide_store_load_roundtrip_aes! { + test_vld1_p64_x2(p64, 2, poly64x1x2_t, vst1_p64_x2, vld1_p64_x2); + test_vld1_p64_x3(p64, 3, poly64x1x3_t, vst1_p64_x3, vld1_p64_x3); + test_vld1_p64_x4(p64, 4, poly64x1x4_t, vst1_p64_x4, vld1_p64_x4); + + test_vld1q_p64_x2(p64, 4, poly64x2x2_t, vst1q_p64_x2, vld1q_p64_x2); + test_vld1q_p64_x3(p64, 6, poly64x2x3_t, vst1q_p64_x3, vld1q_p64_x3); + test_vld1q_p64_x4(p64, 8, poly64x2x4_t, vst1q_p64_x4, vld1q_p64_x4); + } + + macro_rules! wide_store_load_roundtrip_neon { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[simd_test(enable = "neon")] + unsafe fn $name() { + wide_store_load_roundtrip! $args; + } + )* + }; + } + + wide_store_load_roundtrip_neon! { + test_vld1_f32_x2(f32, 4, float32x2x2_t, vst1_f32_x2, vld1_f32_x2); + test_vld1_f32_x3(f32, 6, float32x2x3_t, vst1_f32_x3, vld1_f32_x3); + test_vld1_f32_x4(f32, 8, float32x2x4_t, vst1_f32_x4, vld1_f32_x4); + + test_vld1q_f32_x2(f32, 8, float32x4x2_t, vst1q_f32_x2, vld1q_f32_x2); + test_vld1q_f32_x3(f32, 12, float32x4x3_t, vst1q_f32_x3, vld1q_f32_x3); + test_vld1q_f32_x4(f32, 16, float32x4x4_t, vst1q_f32_x4, vld1q_f32_x4); + + test_vld1_f64_x2(f64, 2, float64x1x2_t, vst1_f64_x2, vld1_f64_x2); + test_vld1_f64_x3(f64, 3, float64x1x3_t, vst1_f64_x3, vld1_f64_x3); + test_vld1_f64_x4(f64, 4, float64x1x4_t, vst1_f64_x4, vld1_f64_x4); + + test_vld1q_f64_x2(f64, 4, float64x2x2_t, vst1q_f64_x2, vld1q_f64_x2); + test_vld1q_f64_x3(f64, 6, float64x2x3_t, vst1q_f64_x3, vld1q_f64_x3); + test_vld1q_f64_x4(f64, 8, float64x2x4_t, vst1q_f64_x4, vld1q_f64_x4); + + test_vld1_s8_x2(i8, 16, int8x8x2_t, vst1_s8_x2, vld1_s8_x2); + test_vld1_s8_x3(i8, 24, int8x8x3_t, vst1_s8_x3, vld1_s8_x3); + test_vld1_s8_x4(i8, 32, int8x8x4_t, vst1_s8_x4, vld1_s8_x4); + + test_vld1q_s8_x2(i8, 32, int8x16x2_t, vst1q_s8_x2, vld1q_s8_x2); + test_vld1q_s8_x3(i8, 48, int8x16x3_t, vst1q_s8_x3, vld1q_s8_x3); + test_vld1q_s8_x4(i8, 64, int8x16x4_t, vst1q_s8_x4, vld1q_s8_x4); + + test_vld1_s16_x2(i16, 8, int16x4x2_t, vst1_s16_x2, vld1_s16_x2); + test_vld1_s16_x3(i16, 12, int16x4x3_t, vst1_s16_x3, vld1_s16_x3); + test_vld1_s16_x4(i16, 16, int16x4x4_t, vst1_s16_x4, vld1_s16_x4); + + test_vld1q_s16_x2(i16, 16, int16x8x2_t, vst1q_s16_x2, vld1q_s16_x2); + test_vld1q_s16_x3(i16, 24, int16x8x3_t, vst1q_s16_x3, vld1q_s16_x3); + test_vld1q_s16_x4(i16, 32, int16x8x4_t, vst1q_s16_x4, vld1q_s16_x4); + + test_vld1_s32_x2(i32, 4, int32x2x2_t, vst1_s32_x2, vld1_s32_x2); + test_vld1_s32_x3(i32, 6, int32x2x3_t, vst1_s32_x3, vld1_s32_x3); + test_vld1_s32_x4(i32, 8, int32x2x4_t, vst1_s32_x4, vld1_s32_x4); + + test_vld1q_s32_x2(i32, 8, int32x4x2_t, vst1q_s32_x2, vld1q_s32_x2); + test_vld1q_s32_x3(i32, 12, int32x4x3_t, vst1q_s32_x3, vld1q_s32_x3); + test_vld1q_s32_x4(i32, 16, int32x4x4_t, vst1q_s32_x4, vld1q_s32_x4); + + test_vld1_s64_x2(i64, 2, int64x1x2_t, vst1_s64_x2, vld1_s64_x2); + test_vld1_s64_x3(i64, 3, int64x1x3_t, vst1_s64_x3, vld1_s64_x3); + test_vld1_s64_x4(i64, 4, int64x1x4_t, vst1_s64_x4, vld1_s64_x4); + + test_vld1q_s64_x2(i64, 4, int64x2x2_t, vst1q_s64_x2, vld1q_s64_x2); + test_vld1q_s64_x3(i64, 6, int64x2x3_t, vst1q_s64_x3, vld1q_s64_x3); + test_vld1q_s64_x4(i64, 8, int64x2x4_t, vst1q_s64_x4, vld1q_s64_x4); + + test_vld1_u8_x2(u8, 16, uint8x8x2_t, vst1_u8_x2, vld1_u8_x2); + test_vld1_u8_x3(u8, 24, uint8x8x3_t, vst1_u8_x3, vld1_u8_x3); + test_vld1_u8_x4(u8, 32, uint8x8x4_t, vst1_u8_x4, vld1_u8_x4); + + test_vld1q_u8_x2(u8, 32, uint8x16x2_t, vst1q_u8_x2, vld1q_u8_x2); + test_vld1q_u8_x3(u8, 48, uint8x16x3_t, vst1q_u8_x3, vld1q_u8_x3); + test_vld1q_u8_x4(u8, 64, uint8x16x4_t, vst1q_u8_x4, vld1q_u8_x4); + + test_vld1_u16_x2(u16, 8, uint16x4x2_t, vst1_u16_x2, vld1_u16_x2); + test_vld1_u16_x3(u16, 12, uint16x4x3_t, vst1_u16_x3, vld1_u16_x3); + test_vld1_u16_x4(u16, 16, uint16x4x4_t, vst1_u16_x4, vld1_u16_x4); + + test_vld1q_u16_x2(u16, 16, uint16x8x2_t, vst1q_u16_x2, vld1q_u16_x2); + test_vld1q_u16_x3(u16, 24, uint16x8x3_t, vst1q_u16_x3, vld1q_u16_x3); + test_vld1q_u16_x4(u16, 32, uint16x8x4_t, vst1q_u16_x4, vld1q_u16_x4); + + test_vld1_u32_x2(u32, 4, uint32x2x2_t, vst1_u32_x2, vld1_u32_x2); + test_vld1_u32_x3(u32, 6, uint32x2x3_t, vst1_u32_x3, vld1_u32_x3); + test_vld1_u32_x4(u32, 8, uint32x2x4_t, vst1_u32_x4, vld1_u32_x4); + + test_vld1q_u32_x2(u32, 8, uint32x4x2_t, vst1q_u32_x2, vld1q_u32_x2); + test_vld1q_u32_x3(u32, 12, uint32x4x3_t, vst1q_u32_x3, vld1q_u32_x3); + test_vld1q_u32_x4(u32, 16, uint32x4x4_t, vst1q_u32_x4, vld1q_u32_x4); + + test_vld1_u64_x2(u64, 2, uint64x1x2_t, vst1_u64_x2, vld1_u64_x2); + test_vld1_u64_x3(u64, 3, uint64x1x3_t, vst1_u64_x3, vld1_u64_x3); + test_vld1_u64_x4(u64, 4, uint64x1x4_t, vst1_u64_x4, vld1_u64_x4); + + test_vld1q_u64_x2(u64, 4, uint64x2x2_t, vst1q_u64_x2, vld1q_u64_x2); + test_vld1q_u64_x3(u64, 6, uint64x2x3_t, vst1q_u64_x3, vld1q_u64_x3); + test_vld1q_u64_x4(u64, 8, uint64x2x4_t, vst1q_u64_x4, vld1q_u64_x4); + + test_vld1_p8_x2(p8, 16, poly8x8x2_t, vst1_p8_x2, vld1_p8_x2); + test_vld1_p8_x3(p8, 24, poly8x8x3_t, vst1_p8_x3, vld1_p8_x3); + test_vld1_p8_x4(p8, 32, poly8x8x4_t, vst1_p8_x4, vld1_p8_x4); + + test_vld1q_p8_x2(p8, 32, poly8x16x2_t, vst1q_p8_x2, vld1q_p8_x2); + test_vld1q_p8_x3(p8, 48, poly8x16x3_t, vst1q_p8_x3, vld1q_p8_x3); + test_vld1q_p8_x4(p8, 64, poly8x16x4_t, vst1q_p8_x4, vld1q_p8_x4); + + test_vld1_p16_x2(p16, 8, poly16x4x2_t, vst1_p16_x2, vld1_p16_x2); + test_vld1_p16_x3(p16, 12, poly16x4x3_t, vst1_p16_x3, vld1_p16_x3); + test_vld1_p16_x4(p16, 16, poly16x4x4_t, vst1_p16_x4, vld1_p16_x4); + + test_vld1q_p16_x2(p16, 16, poly16x8x2_t, vst1q_p16_x2, vld1q_p16_x2); + test_vld1q_p16_x3(p16, 24, poly16x8x3_t, vst1q_p16_x3, vld1q_p16_x3); + test_vld1q_p16_x4(p16, 32, poly16x8x4_t, vst1q_p16_x4, vld1q_p16_x4); + } + + wide_store_load_roundtrip_neon! { + test_vld2_f32_x2(f32, 4, float32x2x2_t, vst2_f32, vld2_f32); + test_vld2_f32_x3(f32, 6, float32x2x3_t, vst3_f32, vld3_f32); + test_vld2_f32_x4(f32, 8, float32x2x4_t, vst4_f32, vld4_f32); + + test_vld2q_f32_x2(f32, 8, float32x4x2_t, vst2q_f32, vld2q_f32); + test_vld3q_f32_x3(f32, 12, float32x4x3_t, vst3q_f32, vld3q_f32); + test_vld4q_f32_x4(f32, 16, float32x4x4_t, vst4q_f32, vld4q_f32); + + test_vld2_f64_x2(f64, 2, float64x1x2_t, vst2_f64, vld2_f64); + test_vld2_f64_x3(f64, 3, float64x1x3_t, vst3_f64, vld3_f64); + test_vld2_f64_x4(f64, 4, float64x1x4_t, vst4_f64, vld4_f64); + + test_vld2q_f64_x2(f64, 4, float64x2x2_t, vst2q_f64, vld2q_f64); + test_vld3q_f64_x3(f64, 6, float64x2x3_t, vst3q_f64, vld3q_f64); + test_vld4q_f64_x4(f64, 8, float64x2x4_t, vst4q_f64, vld4q_f64); + + test_vld2_s8_x2(i8, 16, int8x8x2_t, vst2_s8, vld2_s8); + test_vld2_s8_x3(i8, 24, int8x8x3_t, vst3_s8, vld3_s8); + test_vld2_s8_x4(i8, 32, int8x8x4_t, vst4_s8, vld4_s8); + + test_vld2q_s8_x2(i8, 32, int8x16x2_t, vst2q_s8, vld2q_s8); + test_vld3q_s8_x3(i8, 48, int8x16x3_t, vst3q_s8, vld3q_s8); + test_vld4q_s8_x4(i8, 64, int8x16x4_t, vst4q_s8, vld4q_s8); + + test_vld2_s16_x2(i16, 8, int16x4x2_t, vst2_s16, vld2_s16); + test_vld2_s16_x3(i16, 12, int16x4x3_t, vst3_s16, vld3_s16); + test_vld2_s16_x4(i16, 16, int16x4x4_t, vst4_s16, vld4_s16); + + test_vld2q_s16_x2(i16, 16, int16x8x2_t, vst2q_s16, vld2q_s16); + test_vld3q_s16_x3(i16, 24, int16x8x3_t, vst3q_s16, vld3q_s16); + test_vld4q_s16_x4(i16, 32, int16x8x4_t, vst4q_s16, vld4q_s16); + + test_vld2_s32_x2(i32, 4, int32x2x2_t, vst2_s32, vld2_s32); + test_vld2_s32_x3(i32, 6, int32x2x3_t, vst3_s32, vld3_s32); + test_vld2_s32_x4(i32, 8, int32x2x4_t, vst4_s32, vld4_s32); + + test_vld2q_s32_x2(i32, 8, int32x4x2_t, vst2q_s32, vld2q_s32); + test_vld3q_s32_x3(i32, 12, int32x4x3_t, vst3q_s32, vld3q_s32); + test_vld4q_s32_x4(i32, 16, int32x4x4_t, vst4q_s32, vld4q_s32); + + test_vld2_s64_x2(i64, 2, int64x1x2_t, vst2_s64, vld2_s64); + test_vld2_s64_x3(i64, 3, int64x1x3_t, vst3_s64, vld3_s64); + test_vld2_s64_x4(i64, 4, int64x1x4_t, vst4_s64, vld4_s64); + + test_vld2q_s64_x2(i64, 4, int64x2x2_t, vst2q_s64, vld2q_s64); + test_vld3q_s64_x3(i64, 6, int64x2x3_t, vst3q_s64, vld3q_s64); + test_vld4q_s64_x4(i64, 8, int64x2x4_t, vst4q_s64, vld4q_s64); + + test_vld2_u8_x2(u8, 16, uint8x8x2_t, vst2_u8, vld2_u8); + test_vld2_u8_x3(u8, 24, uint8x8x3_t, vst3_u8, vld3_u8); + test_vld2_u8_x4(u8, 32, uint8x8x4_t, vst4_u8, vld4_u8); + + test_vld2q_u8_x2(u8, 32, uint8x16x2_t, vst2q_u8, vld2q_u8); + test_vld3q_u8_x3(u8, 48, uint8x16x3_t, vst3q_u8, vld3q_u8); + test_vld4q_u8_x4(u8, 64, uint8x16x4_t, vst4q_u8, vld4q_u8); + + test_vld2_u16_x2(u16, 8, uint16x4x2_t, vst2_u16, vld2_u16); + test_vld2_u16_x3(u16, 12, uint16x4x3_t, vst3_u16, vld3_u16); + test_vld2_u16_x4(u16, 16, uint16x4x4_t, vst4_u16, vld4_u16); + + test_vld2q_u16_x2(u16, 16, uint16x8x2_t, vst2q_u16, vld2q_u16); + test_vld3q_u16_x3(u16, 24, uint16x8x3_t, vst3q_u16, vld3q_u16); + test_vld4q_u16_x4(u16, 32, uint16x8x4_t, vst4q_u16, vld4q_u16); + + test_vld2_u32_x2(u32, 4, uint32x2x2_t, vst2_u32, vld2_u32); + test_vld2_u32_x3(u32, 6, uint32x2x3_t, vst3_u32, vld3_u32); + test_vld2_u32_x4(u32, 8, uint32x2x4_t, vst4_u32, vld4_u32); + + test_vld2q_u32_x2(u32, 8, uint32x4x2_t, vst2q_u32, vld2q_u32); + test_vld3q_u32_x3(u32, 12, uint32x4x3_t, vst3q_u32, vld3q_u32); + test_vld4q_u32_x4(u32, 16, uint32x4x4_t, vst4q_u32, vld4q_u32); + + test_vld2_u64_x2(u64, 2, uint64x1x2_t, vst2_u64, vld2_u64); + test_vld2_u64_x3(u64, 3, uint64x1x3_t, vst3_u64, vld3_u64); + test_vld2_u64_x4(u64, 4, uint64x1x4_t, vst4_u64, vld4_u64); + + test_vld2q_u64_x2(u64, 4, uint64x2x2_t, vst2q_u64, vld2q_u64); + test_vld3q_u64_x3(u64, 6, uint64x2x3_t, vst3q_u64, vld3q_u64); + test_vld4q_u64_x4(u64, 8, uint64x2x4_t, vst4q_u64, vld4q_u64); + + test_vld2_p8_x2(p8, 16, poly8x8x2_t, vst2_p8, vld2_p8); + test_vld2_p8_x3(p8, 24, poly8x8x3_t, vst3_p8, vld3_p8); + test_vld2_p8_x4(p8, 32, poly8x8x4_t, vst4_p8, vld4_p8); + + test_vld2q_p8_x2(p8, 32, poly8x16x2_t, vst2q_p8, vld2q_p8); + test_vld3q_p8_x3(p8, 48, poly8x16x3_t, vst3q_p8, vld3q_p8); + test_vld4q_p8_x4(p8, 64, poly8x16x4_t, vst4q_p8, vld4q_p8); + + test_vld2_p16_x2(p16, 8, poly16x4x2_t, vst2_p16, vld2_p16); + test_vld2_p16_x3(p16, 12, poly16x4x3_t, vst3_p16, vld3_p16); + test_vld2_p16_x4(p16, 16, poly16x4x4_t, vst4_p16, vld4_p16); + + test_vld2q_p16_x2(p16, 16, poly16x8x2_t, vst2q_p16, vld2q_p16); + test_vld3q_p16_x3(p16, 24, poly16x8x3_t, vst3q_p16, vld3q_p16); + test_vld4q_p16_x4(p16, 32, poly16x8x4_t, vst4q_p16, vld4q_p16); + } } #[cfg(test)] diff --git a/stdarch/crates/core_arch/src/aarch64/rand.rs b/stdarch/crates/core_arch/src/aarch64/rand.rs new file mode 100644 index 0000000000000..3f52cf2ce8657 --- /dev/null +++ b/stdarch/crates/core_arch/src/aarch64/rand.rs @@ -0,0 +1,48 @@ +//! AArch64 Random Number intrinsics +//! +//! [ACLE documentation](https://arm-software.github.io/acle/main/acle.html#random-number-generation-intrinsics) + +#[cfg(test)] +use stdarch_test::assert_instr; + +unsafe extern "unadjusted" { + #[link_name = "llvm.aarch64.rndr"] + fn rndr_() -> Tuple; + + #[link_name = "llvm.aarch64.rndrrs"] + fn rndrrs_() -> Tuple; +} + +#[repr(C)] +struct Tuple { + bits: u64, + status: bool, +} + +/// Stores a 64-bit random number into the object pointed to by the argument and returns +/// zero. If the implementation could not generate a random number within a reasonable +/// period of time the object pointed to by the input is set to zero and a non-zero value +/// is returned. +#[inline] +#[target_feature(enable = "rand")] +#[cfg_attr(test, assert_instr(mrs))] +#[unstable(feature = "stdarch_aarch64_rand", issue = "153514")] +pub unsafe fn __rndr(value: *mut u64) -> i32 { + let Tuple { bits, status } = rndr_(); + unsafe { *value = bits }; + status as i32 +} + +/// Reseeds the random number generator. After that stores a 64-bit random number into +/// the object pointed to by the argument and returns zero. If the implementation could +/// not generate a random number within a reasonable period of time the object pointed +/// to by the input is set to zero and a non-zero value is returned. +#[inline] +#[target_feature(enable = "rand")] +#[cfg_attr(test, assert_instr(mrs))] +#[unstable(feature = "stdarch_aarch64_rand", issue = "153514")] +pub unsafe fn __rndrrs(value: *mut u64) -> i32 { + let Tuple { bits, status } = rndrrs_(); + unsafe { *value = bits }; + status as i32 +} diff --git a/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs index 3b67208182cb0..4a846e2877462 100644 --- a/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs @@ -821,7 +821,7 @@ pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -851,7 +851,7 @@ pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1422,7 +1422,7 @@ pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1444,7 +1444,7 @@ pub fn vabs_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1673,7 +1673,7 @@ pub fn vabsh_f16(a: f16) -> f16 { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1695,7 +1695,7 @@ pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -3879,7 +3879,7 @@ pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -3907,7 +3907,7 @@ pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4529,7 +4529,7 @@ pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4559,7 +4559,7 @@ pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4647,7 +4647,7 @@ pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4677,7 +4677,7 @@ pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4765,7 +4765,7 @@ pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4787,7 +4787,7 @@ pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4851,7 +4851,7 @@ pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4873,7 +4873,7 @@ pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4937,7 +4937,7 @@ pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4959,7 +4959,7 @@ pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5317,7 +5317,7 @@ pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5339,7 +5339,7 @@ pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5655,7 +5655,7 @@ pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5678,7 +5678,7 @@ pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5701,7 +5701,7 @@ pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5723,7 +5723,7 @@ pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6039,7 +6039,7 @@ pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6062,7 +6062,7 @@ pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6085,7 +6085,7 @@ pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6107,7 +6107,7 @@ pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6423,7 +6423,7 @@ pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6446,7 +6446,7 @@ pub fn vclez_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6769,7 +6769,7 @@ pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6791,7 +6791,7 @@ pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -7107,7 +7107,7 @@ pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -7130,7 +7130,7 @@ pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -7812,7 +7812,7 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8041,7 +8041,7 @@ pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8065,7 +8065,7 @@ pub fn vcreate_f16(a: u64) -> float16x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8577,7 +8577,7 @@ pub fn vcreate_p64(a: u64) -> poly64x1_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8599,7 +8599,7 @@ pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8621,7 +8621,7 @@ pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8643,7 +8643,7 @@ pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8665,7 +8665,7 @@ pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8688,7 +8688,7 @@ pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8795,7 +8795,7 @@ pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8830,7 +8830,7 @@ pub fn vcvt_n_f16_s16(a: int16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8865,7 +8865,7 @@ pub fn vcvtq_n_f16_s16(a: int16x8_t) -> float16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8900,7 +8900,7 @@ pub fn vcvt_n_f16_u16(a: uint16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9087,7 +9087,7 @@ pub fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9122,7 +9122,7 @@ pub fn vcvt_n_s16_f16(a: float16x4_t) -> int16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9233,7 +9233,7 @@ pub fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9268,7 +9268,7 @@ pub fn vcvt_n_u16_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9378,7 +9378,7 @@ pub fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9400,7 +9400,7 @@ pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9480,7 +9480,7 @@ pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9502,7 +9502,7 @@ pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -10140,7 +10140,7 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -10149,7 +10149,7 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { #[cfg(not(target_arch = "arm64ec"))] pub fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"] @@ -10165,7 +10165,7 @@ pub fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -10174,13 +10174,7 @@ pub fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { #[cfg(not(target_arch = "arm64ec"))] pub fn vdupq_lane_f16(a: float16x4_t) -> float16x8_t { static_assert_uimm_bits!(N, 2); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"] @@ -10341,7 +10335,7 @@ pub fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { )] pub fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"] @@ -10364,7 +10358,7 @@ pub fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { )] pub fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"] @@ -10387,7 +10381,7 @@ pub fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { )] pub fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 2); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"] @@ -10410,13 +10404,7 @@ pub fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { )] pub fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { static_assert_uimm_bits!(N, 2); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"] @@ -10439,13 +10427,7 @@ pub fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { )] pub fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(N, 2); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"] @@ -10468,13 +10450,7 @@ pub fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { )] pub fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { static_assert_uimm_bits!(N, 2); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"] @@ -10497,13 +10473,7 @@ pub fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { )] pub fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"] @@ -10526,13 +10496,7 @@ pub fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { )] pub fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"] @@ -10555,13 +10519,7 @@ pub fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { )] pub fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"] @@ -10584,16 +10542,7 @@ pub fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { )] pub fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"] @@ -10616,16 +10565,7 @@ pub fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { )] pub fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"] @@ -10648,16 +10588,7 @@ pub fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { )] pub fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"] @@ -10719,7 +10650,7 @@ pub fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -10728,7 +10659,7 @@ pub fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { #[cfg(not(target_arch = "arm64ec"))] pub fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"] @@ -10744,7 +10675,7 @@ pub fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -10753,13 +10684,7 @@ pub fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { #[cfg(not(target_arch = "arm64ec"))] pub fn vdupq_laneq_f16(a: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"] @@ -10920,7 +10845,7 @@ pub fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { )] pub fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"] @@ -10943,7 +10868,7 @@ pub fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { )] pub fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"] @@ -10966,7 +10891,7 @@ pub fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { )] pub fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { static_assert_uimm_bits!(N, 3); - unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } + unsafe { simd_shuffle!(a, a, [N as u32; 4]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"] @@ -10989,13 +10914,7 @@ pub fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { )] pub fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"] @@ -11018,13 +10937,7 @@ pub fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { )] pub fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"] @@ -11047,13 +10960,7 @@ pub fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { )] pub fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(N, 3); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"] @@ -11076,13 +10983,7 @@ pub fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { )] pub fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { static_assert_uimm_bits!(N, 4); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"] @@ -11105,13 +11006,7 @@ pub fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { )] pub fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { static_assert_uimm_bits!(N, 4); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"] @@ -11134,13 +11029,7 @@ pub fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { )] pub fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { static_assert_uimm_bits!(N, 4); - unsafe { - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 8]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"] @@ -11163,16 +11052,7 @@ pub fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { )] pub fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { static_assert_uimm_bits!(N, 4); - unsafe { - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"] @@ -11195,16 +11075,7 @@ pub fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { )] pub fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { static_assert_uimm_bits!(N, 4); - unsafe { - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"] @@ -11227,16 +11098,7 @@ pub fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { )] pub fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { static_assert_uimm_bits!(N, 4); - unsafe { - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) - } + unsafe { simd_shuffle!(a, a, [N as u32; 16]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"] @@ -12261,7 +12123,7 @@ pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -12640,7 +12502,7 @@ pub fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -13228,7 +13090,7 @@ pub fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -13250,7 +13112,7 @@ pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -13357,7 +13219,7 @@ pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -13383,7 +13245,7 @@ pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -13494,7 +13356,7 @@ pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -13513,7 +13375,7 @@ pub fn vget_high_f16(a: float16x8_t) -> float16x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -15808,21 +15670,13 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v4f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f16.p0")] - fn _vld1_f16_x2(a: *const f16) -> float16x4x2_t; - } - _vld1_f16_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"] @@ -15834,21 +15688,13 @@ pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v4f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f16.p0")] - fn _vld1_f16_x3(a: *const f16) -> float16x4x3_t; - } - _vld1_f16_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"] @@ -15860,21 +15706,13 @@ pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v4f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f16.p0")] - fn _vld1_f16_x4(a: *const f16) -> float16x4x4_t; - } - _vld1_f16_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"] @@ -15886,21 +15724,13 @@ pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v8f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8f16.p0")] - fn _vld1q_f16_x2(a: *const f16) -> float16x8x2_t; - } - _vld1q_f16_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"] @@ -15912,21 +15742,13 @@ pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v8f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8f16.p0")] - fn _vld1q_f16_x3(a: *const f16) -> float16x8x3_t; - } - _vld1q_f16_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"] @@ -15938,21 +15760,13 @@ pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v8f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8f16.p0")] - fn _vld1q_f16_x4(a: *const f16) -> float16x8x4_t; - } - _vld1q_f16_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"] @@ -16156,10 +15970,10 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -16170,15 +15984,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v2f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2f32.p0")] - fn _vld1_f32_x2(a: *const f32) -> float32x2x2_t; - } - _vld1_f32_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"] @@ -16187,10 +15993,10 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -16201,15 +16007,7 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v2f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2f32.p0")] - fn _vld1_f32_x3(a: *const f32) -> float32x2x3_t; - } - _vld1_f32_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"] @@ -16218,10 +16016,10 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -16232,15 +16030,7 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v2f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2f32.p0")] - fn _vld1_f32_x4(a: *const f32) -> float32x2x4_t; - } - _vld1_f32_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"] @@ -16249,10 +16039,10 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -16263,15 +16053,7 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v4f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f32.p0")] - fn _vld1q_f32_x2(a: *const f32) -> float32x4x2_t; - } - _vld1q_f32_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"] @@ -16280,10 +16062,10 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -16294,15 +16076,7 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v4f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f32.p0")] - fn _vld1q_f32_x3(a: *const f32) -> float32x4x3_t; - } - _vld1q_f32_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"] @@ -16311,10 +16085,10 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -16325,15 +16099,7 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v4f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f32.p0")] - fn _vld1q_f32_x4(a: *const f32) -> float32x4x4_t; - } - _vld1q_f32_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"] @@ -17000,10 +16766,10 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17014,7 +16780,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { - transmute(vld1_s64_x2(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"] @@ -17026,7 +16792,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17037,7 +16803,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { - transmute(vld1_s64_x3(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"] @@ -17049,7 +16815,7 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17060,44 +16826,19 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { - transmute(vld1_s64_x4(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { - transmute(vld1q_s64_x2(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17108,47 +16849,19 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { - let mut ret_val: poly64x2x2_t = transmute(vld1q_s64_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { - transmute(vld1q_s64_x3(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17159,48 +16872,19 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { - let mut ret_val: poly64x2x3_t = transmute(vld1q_s64_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { - transmute(vld1q_s64_x4(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17211,12 +16895,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { - let mut ret_val: poly64x2x4_t = transmute(vld1q_s64_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"] @@ -17329,10 +17008,10 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17343,15 +17022,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v8i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i8.p0")] - fn _vld1_s8_x2(a: *const i8) -> int8x8x2_t; - } - _vld1_s8_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"] @@ -17360,10 +17031,10 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17374,15 +17045,7 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v8i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i8.p0")] - fn _vld1_s8_x3(a: *const i8) -> int8x8x3_t; - } - _vld1_s8_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"] @@ -17391,10 +17054,10 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17405,15 +17068,7 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v8i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i8.p0")] - fn _vld1_s8_x4(a: *const i8) -> int8x8x4_t; - } - _vld1_s8_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"] @@ -17422,10 +17077,10 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17436,15 +17091,7 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v16i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v16i8.p0")] - fn _vld1q_s8_x2(a: *const i8) -> int8x16x2_t; - } - _vld1q_s8_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"] @@ -17453,10 +17100,10 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17467,15 +17114,7 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v16i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v16i8.p0")] - fn _vld1q_s8_x3(a: *const i8) -> int8x16x3_t; - } - _vld1q_s8_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"] @@ -17484,10 +17123,10 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17498,15 +17137,7 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v16i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v16i8.p0")] - fn _vld1q_s8_x4(a: *const i8) -> int8x16x4_t; - } - _vld1q_s8_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"] @@ -17515,10 +17146,10 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17529,15 +17160,7 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v4i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i16.p0")] - fn _vld1_s16_x2(a: *const i16) -> int16x4x2_t; - } - _vld1_s16_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"] @@ -17546,10 +17169,10 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17560,15 +17183,7 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v4i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i16.p0")] - fn _vld1_s16_x3(a: *const i16) -> int16x4x3_t; - } - _vld1_s16_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"] @@ -17577,10 +17192,10 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17591,15 +17206,7 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v4i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i16.p0")] - fn _vld1_s16_x4(a: *const i16) -> int16x4x4_t; - } - _vld1_s16_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"] @@ -17608,10 +17215,10 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17622,15 +17229,7 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v8i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i16.p0")] - fn _vld1q_s16_x2(a: *const i16) -> int16x8x2_t; - } - _vld1q_s16_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"] @@ -17639,10 +17238,10 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17653,15 +17252,7 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v8i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i16.p0")] - fn _vld1q_s16_x3(a: *const i16) -> int16x8x3_t; - } - _vld1q_s16_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"] @@ -17670,10 +17261,10 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17684,15 +17275,7 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v8i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i16.p0")] - fn _vld1q_s16_x4(a: *const i16) -> int16x8x4_t; - } - _vld1q_s16_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"] @@ -17701,10 +17284,10 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17715,15 +17298,7 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v2i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i32.p0")] - fn _vld1_s32_x2(a: *const i32) -> int32x2x2_t; - } - _vld1_s32_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"] @@ -17732,10 +17307,10 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17746,15 +17321,7 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v2i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i32.p0")] - fn _vld1_s32_x3(a: *const i32) -> int32x2x3_t; - } - _vld1_s32_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"] @@ -17763,10 +17330,10 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17777,15 +17344,7 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v2i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i32.p0")] - fn _vld1_s32_x4(a: *const i32) -> int32x2x4_t; - } - _vld1_s32_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"] @@ -17794,10 +17353,10 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17808,15 +17367,7 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v4i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i32.p0")] - fn _vld1q_s32_x2(a: *const i32) -> int32x4x2_t; - } - _vld1q_s32_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"] @@ -17825,10 +17376,10 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17839,15 +17390,7 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v4i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i32.p0")] - fn _vld1q_s32_x3(a: *const i32) -> int32x4x3_t; - } - _vld1q_s32_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"] @@ -17856,10 +17399,10 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17870,15 +17413,7 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v4i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i32.p0")] - fn _vld1q_s32_x4(a: *const i32) -> int32x4x4_t; - } - _vld1q_s32_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"] @@ -17887,10 +17422,10 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17901,15 +17436,7 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v1i64.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v1i64.p0")] - fn _vld1_s64_x2(a: *const i64) -> int64x1x2_t; - } - _vld1_s64_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"] @@ -17918,10 +17445,10 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17932,15 +17459,7 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v1i64.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v1i64.p0")] - fn _vld1_s64_x3(a: *const i64) -> int64x1x3_t; - } - _vld1_s64_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"] @@ -17949,10 +17468,10 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17963,15 +17482,7 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v1i64.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v1i64.p0")] - fn _vld1_s64_x4(a: *const i64) -> int64x1x4_t; - } - _vld1_s64_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"] @@ -17980,10 +17491,10 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17994,15 +17505,7 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v2i64.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i64.p0")] - fn _vld1q_s64_x2(a: *const i64) -> int64x2x2_t; - } - _vld1q_s64_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"] @@ -18011,10 +17514,10 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18025,15 +17528,7 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v2i64.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i64.p0")] - fn _vld1q_s64_x3(a: *const i64) -> int64x2x3_t; - } - _vld1q_s64_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"] @@ -18042,10 +17537,10 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18056,52 +17551,19 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v2i64.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i64.p0")] - fn _vld1q_s64_x4(a: *const i64) -> int64x2x4_t; - } - _vld1q_s64_x4(a) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { - transmute(vld1_s8_x2(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18112,23 +17574,19 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { - let mut ret_val: uint8x8x2_t = transmute(vld1_s8_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18139,20 +17597,19 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { - transmute(vld1_s8_x3(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18162,25 +17619,20 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { - let mut ret_val: uint8x8x3_t = transmute(vld1_s8_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18190,21 +17642,20 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { - transmute(vld1_s8_x4(transmute(a))) +pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18214,26 +17665,20 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { - let mut ret_val: uint8x8x4_t = transmute(vld1_s8_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18243,21 +17688,20 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { - transmute(vld1q_s8_x2(transmute(a))) +pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18267,36 +17711,20 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { - let mut ret_val: uint8x16x2_t = transmute(vld1q_s8_x2(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18306,21 +17734,20 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { - transmute(vld1q_s8_x3(transmute(a))) +pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18330,43 +17757,20 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { - let mut ret_val: uint8x16x3_t = transmute(vld1q_s8_x3(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18376,21 +17780,20 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { - transmute(vld1q_s8_x4(transmute(a))) +pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18400,50 +17803,20 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { - let mut ret_val: uint8x16x4_t = transmute(vld1q_s8_x4(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18453,21 +17826,20 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { - transmute(vld1_s16_x2(transmute(a))) +pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18477,24 +17849,20 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { - let mut ret_val: uint16x4x2_t = transmute(vld1_s16_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18504,21 +17872,20 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { - transmute(vld1_s16_x3(transmute(a))) +pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18528,25 +17895,20 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { - let mut ret_val: uint16x4x3_t = transmute(vld1_s16_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18556,21 +17918,20 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { - transmute(vld1_s16_x4(transmute(a))) +pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18580,26 +17941,20 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { - let mut ret_val: uint16x4x4_t = transmute(vld1_s16_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18609,21 +17964,20 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { - transmute(vld1q_s16_x2(transmute(a))) +pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18633,24 +17987,20 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { - let mut ret_val: uint16x8x2_t = transmute(vld1q_s16_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18660,21 +18010,20 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { - transmute(vld1q_s16_x3(transmute(a))) +pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18684,25 +18033,20 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { - let mut ret_val: uint16x8x3_t = transmute(vld1q_s16_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18712,21 +18056,20 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { - transmute(vld1q_s16_x4(transmute(a))) +pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18736,26 +18079,20 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { - let mut ret_val: uint16x8x4_t = transmute(vld1q_s16_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18765,21 +18102,20 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { - transmute(vld1_s32_x2(transmute(a))) +pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18789,24 +18125,20 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { - let mut ret_val: uint32x2x2_t = transmute(vld1_s32_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val +pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18816,21 +18148,20 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { - transmute(vld1_s32_x3(transmute(a))) +pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18840,25 +18171,20 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { - let mut ret_val: uint32x2x3_t = transmute(vld1_s32_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val +pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18868,21 +18194,20 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { - transmute(vld1_s32_x4(transmute(a))) +pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18892,26 +18217,20 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { - let mut ret_val: uint32x2x4_t = transmute(vld1_s32_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val +pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18921,21 +18240,20 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { - transmute(vld1q_s32_x2(transmute(a))) +pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18945,24 +18263,20 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { - let mut ret_val: uint32x4x2_t = transmute(vld1q_s32_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18972,21 +18286,20 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { - transmute(vld1q_s32_x3(transmute(a))) +pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18996,25 +18309,20 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { - let mut ret_val: uint32x4x3_t = transmute(vld1q_s32_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19024,21 +18332,20 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { - transmute(vld1q_s32_x4(transmute(a))) +pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19048,900 +18355,20 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { - let mut ret_val: uint32x4x4_t = transmute(vld1q_s32_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { - transmute(vld1_s64_x2(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { - transmute(vld1_s64_x3(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { - transmute(vld1_s64_x4(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { - transmute(vld1q_s64_x2(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { - let mut ret_val: uint64x2x2_t = transmute(vld1q_s64_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { - transmute(vld1q_s64_x3(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { - let mut ret_val: uint64x2x3_t = transmute(vld1q_s64_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { - transmute(vld1q_s64_x4(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { - let mut ret_val: uint64x2x4_t = transmute(vld1q_s64_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { - transmute(vld1_s8_x2(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { - let mut ret_val: poly8x8x2_t = transmute(vld1_s8_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { - transmute(vld1_s8_x3(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { - let mut ret_val: poly8x8x3_t = transmute(vld1_s8_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { - transmute(vld1_s8_x4(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { - let mut ret_val: poly8x8x4_t = transmute(vld1_s8_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { - transmute(vld1q_s8_x2(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { - let mut ret_val: poly8x16x2_t = transmute(vld1q_s8_x2(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { - transmute(vld1q_s8_x3(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { - let mut ret_val: poly8x16x3_t = transmute(vld1q_s8_x3(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { - transmute(vld1q_s8_x4(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { - let mut ret_val: poly8x16x4_t = transmute(vld1q_s8_x4(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { - transmute(vld1_s16_x2(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { - let mut ret_val: poly16x4x2_t = transmute(vld1_s16_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { - transmute(vld1_s16_x3(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { - let mut ret_val: poly16x4x3_t = transmute(vld1_s16_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { - transmute(vld1_s16_x4(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { - let mut ret_val: poly16x4x4_t = transmute(vld1_s16_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { - transmute(vld1q_s16_x2(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { - let mut ret_val: poly16x8x2_t = transmute(vld1q_s16_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { - transmute(vld1q_s16_x3(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { - let mut ret_val: poly16x8x3_t = transmute(vld1q_s16_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { - transmute(vld1q_s16_x4(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19952,12 +18379,7 @@ pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { - let mut ret_val: poly16x8x4_t = transmute(vld1q_s16_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val + crate::ptr::read_unaligned(a.cast()) } #[inline(always)] #[rustc_legacy_const_generics(1)] @@ -22195,7 +20617,6 @@ pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22215,38 +20636,10 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { transmute(vld2_s8(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { - let mut ret_val: uint8x8x2_t = transmute(vld2_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22266,50 +20659,10 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { transmute(vld2q_s8(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { - let mut ret_val: uint8x16x2_t = transmute(vld2q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22329,38 +20682,10 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { transmute(vld2_s16(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { - let mut ret_val: uint16x4x2_t = transmute(vld2_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22380,38 +20705,10 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { transmute(vld2q_s16(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { - let mut ret_val: uint16x8x2_t = transmute(vld2q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22431,38 +20728,10 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { transmute(vld2_s32(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { - let mut ret_val: uint32x2x2_t = transmute(vld2_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22482,38 +20751,10 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { transmute(vld2q_s32(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { - let mut ret_val: uint32x4x2_t = transmute(vld2q_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22533,38 +20774,10 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { transmute(vld2_s8(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { - let mut ret_val: poly8x8x2_t = transmute(vld2_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22584,50 +20797,10 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { transmute(vld2q_s8(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { - let mut ret_val: poly8x16x2_t = transmute(vld2q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22647,38 +20820,10 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { transmute(vld2_s16(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { - let mut ret_val: poly16x4x2_t = transmute(vld2_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22697,33 +20842,6 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { transmute(vld2q_s16(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { - let mut ret_val: poly16x8x2_t = transmute(vld2q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] #[doc = "## Safety"] @@ -23780,14 +21898,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v4f16.p0" - )] - fn _vld3_f16(ptr: *const f16) -> float16x4x3_t; - } - _vld3_f16(a as _) + crate::core_arch::macros::deinterleaving_load!(f16, 4, 3, a) } #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] @@ -23804,14 +21915,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v8f16.p0" - )] - fn _vld3q_f16(ptr: *const f16) -> float16x8x3_t; - } - _vld3q_f16(a as _) + crate::core_arch::macros::deinterleaving_load!(f16, 8, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] @@ -23823,14 +21927,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v2f32.p0" - )] - fn _vld3_f32(ptr: *const float32x2_t) -> float32x2x3_t; - } - _vld3_f32(a as _) + crate::core_arch::macros::deinterleaving_load!(f32, 2, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] @@ -23842,14 +21939,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v4f32.p0" - )] - fn _vld3q_f32(ptr: *const float32x4_t) -> float32x4x3_t; - } - _vld3q_f32(a as _) + crate::core_arch::macros::deinterleaving_load!(f32, 4, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] @@ -23861,14 +21951,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v8i8.p0" - )] - fn _vld3_s8(ptr: *const int8x8_t) -> int8x8x3_t; - } - _vld3_s8(a as _) + crate::core_arch::macros::deinterleaving_load!(i8, 8, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] @@ -23880,14 +21963,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v16i8.p0" - )] - fn _vld3q_s8(ptr: *const int8x16_t) -> int8x16x3_t; - } - _vld3q_s8(a as _) + crate::core_arch::macros::deinterleaving_load!(i8, 16, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] @@ -23899,14 +21975,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v4i16.p0" - )] - fn _vld3_s16(ptr: *const int16x4_t) -> int16x4x3_t; - } - _vld3_s16(a as _) + crate::core_arch::macros::deinterleaving_load!(i16, 4, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] @@ -23918,14 +21987,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v8i16.p0" - )] - fn _vld3q_s16(ptr: *const int16x8_t) -> int16x8x3_t; - } - _vld3q_s16(a as _) + crate::core_arch::macros::deinterleaving_load!(i16, 8, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] @@ -23937,14 +21999,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v2i32.p0" - )] - fn _vld3_s32(ptr: *const int32x2_t) -> int32x2x3_t; - } - _vld3_s32(a as _) + crate::core_arch::macros::deinterleaving_load!(i32, 2, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] @@ -23956,14 +22011,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v4i32.p0" - )] - fn _vld3q_s32(ptr: *const int32x4_t) -> int32x4x3_t; - } - _vld3q_s32(a as _) + crate::core_arch::macros::deinterleaving_load!(i32, 4, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] @@ -24783,14 +22831,7 @@ pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v1i64.p0" - )] - fn _vld3_s64(ptr: *const int64x1_t) -> int64x1x3_t; - } - _vld3_s64(a as _) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] @@ -24836,7 +22877,6 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -24856,39 +22896,10 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { transmute(vld3_s8(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { - let mut ret_val: uint8x8x3_t = transmute(vld3_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -24908,57 +22919,10 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { transmute(vld3q_s8(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { - let mut ret_val: uint8x16x3_t = transmute(vld3q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -24978,39 +22942,10 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { transmute(vld3_s16(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { - let mut ret_val: uint16x4x3_t = transmute(vld3_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25030,39 +22965,10 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { transmute(vld3q_s16(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { - let mut ret_val: uint16x8x3_t = transmute(vld3q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25082,39 +22988,10 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { transmute(vld3_s32(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { - let mut ret_val: uint32x2x3_t = transmute(vld3_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25134,39 +23011,10 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { transmute(vld3q_s32(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { - let mut ret_val: uint32x4x3_t = transmute(vld3q_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25186,39 +23034,10 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { transmute(vld3_s8(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { - let mut ret_val: poly8x8x3_t = transmute(vld3_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25238,57 +23057,10 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { transmute(vld3q_s8(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { - let mut ret_val: poly8x16x3_t = transmute(vld3q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25308,39 +23080,10 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { transmute(vld3_s16(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { - let mut ret_val: poly16x4x3_t = transmute(vld3_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25360,34 +23103,6 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { transmute(vld3q_s16(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { - let mut ret_val: poly16x8x3_t = transmute(vld3q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] @@ -26483,14 +24198,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v4f16.p0" - )] - fn _vld4_f16(ptr: *const f16) -> float16x4x4_t; - } - _vld4_f16(a as _) + crate::core_arch::macros::deinterleaving_load!(f16, 4, 4, a) } #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] @@ -26506,14 +24214,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v8f16.p0" - )] - fn _vld4q_f16(ptr: *const f16) -> float16x8x4_t; - } - _vld4q_f16(a as _) + crate::core_arch::macros::deinterleaving_load!(f16, 8, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] @@ -26525,14 +24226,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v2f32.p0" - )] - fn _vld4_f32(ptr: *const float32x2_t) -> float32x2x4_t; - } - _vld4_f32(a as _) + crate::core_arch::macros::deinterleaving_load!(f32, 2, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] @@ -26544,14 +24238,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v4f32.p0" - )] - fn _vld4q_f32(ptr: *const float32x4_t) -> float32x4x4_t; - } - _vld4q_f32(a as _) + crate::core_arch::macros::deinterleaving_load!(f32, 4, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] @@ -26563,14 +24250,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v8i8.p0" - )] - fn _vld4_s8(ptr: *const int8x8_t) -> int8x8x4_t; - } - _vld4_s8(a as _) + crate::core_arch::macros::deinterleaving_load!(i8, 8, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] @@ -26582,14 +24262,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v16i8.p0" - )] - fn _vld4q_s8(ptr: *const int8x16_t) -> int8x16x4_t; - } - _vld4q_s8(a as _) + crate::core_arch::macros::deinterleaving_load!(i8, 16, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] @@ -26601,14 +24274,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v4i16.p0" - )] - fn _vld4_s16(ptr: *const int16x4_t) -> int16x4x4_t; - } - _vld4_s16(a as _) + crate::core_arch::macros::deinterleaving_load!(i16, 4, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] @@ -26620,14 +24286,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v8i16.p0" - )] - fn _vld4q_s16(ptr: *const int16x8_t) -> int16x8x4_t; - } - _vld4q_s16(a as _) + crate::core_arch::macros::deinterleaving_load!(i16, 8, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] @@ -26639,14 +24298,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v2i32.p0" - )] - fn _vld4_s32(ptr: *const int32x2_t) -> int32x2x4_t; - } - _vld4_s32(a as _) + crate::core_arch::macros::deinterleaving_load!(i32, 2, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] @@ -26658,14 +24310,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v4i32.p0" - )] - fn _vld4q_s32(ptr: *const int32x4_t) -> int32x4x4_t; - } - _vld4q_s32(a as _) + crate::core_arch::macros::deinterleaving_load!(i32, 4, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] @@ -27303,290 +24948,9 @@ pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4_lane_s8::(transmute(a), transmute(b))) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_lane_u16(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld4_lane_s16::(transmute(a), transmute(b))) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_lane_u16(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4q_lane_s16::(transmute(a), transmute(b))) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_lane_u32(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld4_lane_s32::(transmute(a), transmute(b))) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_lane_u32(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld4q_lane_s32::(transmute(a), transmute(b))) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_lane_p8(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4_lane_s8::(transmute(a), transmute(b))) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_lane_p16(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld4_lane_s16::(transmute(a), transmute(b))) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4, LANE = 0) -)] -#[rustc_legacy_const_generics(2)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4q_lane_s16::(transmute(a), transmute(b))) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t { - transmute(vld4_s64(transmute(a))) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg(not(target_arch = "arm"))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v1i64.p0" - )] - fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t; - } - _vld4_s64(a as _) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon,v7")] -#[cfg(target_arch = "arm")] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -#[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")] - fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t; - } - _vld4_s64(a as *const i8, 8) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(nop) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { - transmute(vld4_s64(transmute(a))) -} -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27595,22 +24959,23 @@ pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { - transmute(vld4_s8(transmute(a))) +pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4_lane_s8::(transmute(a), transmute(b))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27619,27 +24984,23 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { - let mut ret_val: uint8x8x4_t = transmute(vld4_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld4_lane_u16(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld4_lane_s16::(transmute(a), transmute(b))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27648,22 +25009,23 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { - transmute(vld4q_s8(transmute(a))) +pub unsafe fn vld4q_lane_u16(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4q_lane_s16::(transmute(a), transmute(b))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27672,51 +25034,23 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { - let mut ret_val: uint8x16x4_t = transmute(vld4q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld4_lane_u32(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld4_lane_s32::(transmute(a), transmute(b))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27725,22 +25059,23 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { - transmute(vld4_s16(transmute(a))) +pub unsafe fn vld4q_lane_u32(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld4q_lane_s32::(transmute(a), transmute(b))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27749,27 +25084,23 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { - let mut ret_val: uint16x4x4_t = transmute(vld4_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld4_lane_p8(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4_lane_s8::(transmute(a), transmute(b))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27778,22 +25109,23 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { - transmute(vld4q_s16(transmute(a))) +pub unsafe fn vld4_lane_p16(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld4_lane_s16::(transmute(a), transmute(b))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(ld4, LANE = 0) )] +#[rustc_legacy_const_generics(2)] #[cfg_attr( not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") @@ -27802,26 +25134,21 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { - let mut ret_val: uint16x8x4_t = transmute(vld4q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4q_lane_s16::(transmute(a), transmute(b))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -27831,21 +25158,48 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { - transmute(vld4_s32(transmute(a))) +pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t { + transmute(vld4_s64(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { + crate::ptr::read_unaligned(a.cast()) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] +#[inline(always)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")] + fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t; + } + _vld4_s64(a as *const i8, 8) +} +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) + assert_instr(nop) )] #[cfg_attr( not(target_arch = "arm"), @@ -27855,20 +25209,14 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { - let mut ret_val: uint32x2x4_t = transmute(vld4_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val +pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { + transmute(vld4_s64(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27884,15 +25232,14 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { - transmute(vld4q_s32(transmute(a))) +pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { + transmute(vld4_s8(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27908,20 +25255,14 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { - let mut ret_val: uint32x4x4_t = transmute(vld4q_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { + transmute(vld4q_s8(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27937,15 +25278,14 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { - transmute(vld4_s8(transmute(a))) +pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { + transmute(vld4_s16(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27961,20 +25301,14 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { - let mut ret_val: poly8x8x4_t = transmute(vld4_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { + transmute(vld4q_s16(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27990,15 +25324,14 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { - transmute(vld4q_s8(transmute(a))) +pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { + transmute(vld4_s32(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -28014,44 +25347,14 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { - let mut ret_val: poly8x16x4_t = transmute(vld4q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { + transmute(vld4q_s32(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -28067,15 +25370,14 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { - transmute(vld4_s16(transmute(a))) +pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { + transmute(vld4_s8(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -28091,20 +25393,14 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { - let mut ret_val: poly16x4x4_t = transmute(vld4_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { + transmute(vld4q_s8(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -28120,15 +25416,14 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { - transmute(vld4q_s16(transmute(a))) +pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { + transmute(vld4_s16(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -28145,12 +25440,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { - let mut ret_val: poly16x8x4_t = transmute(vld4q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val + transmute(vld4q_s16(transmute(a))) } #[doc = "Store SIMD&FP register (immediate offset)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"] @@ -28187,7 +25477,7 @@ pub unsafe fn vldrq_p128(a: *const p128) -> p128 { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -28217,7 +25507,7 @@ pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -28593,7 +25883,7 @@ pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -28601,7 +25891,15 @@ pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] #[cfg(not(target_arch = "arm64ec"))] pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe { simd_fmax(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v4f16" + )] + fn _vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vmaxnm_f16(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"] @@ -28615,7 +25913,7 @@ pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -28623,7 +25921,15 @@ pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[cfg(not(target_arch = "arm64ec"))] pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe { simd_fmax(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v8f16" + )] + fn _vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vmaxnmq_f16(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"] @@ -28644,7 +25950,15 @@ pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe { simd_fmax(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v2f32" + )] + fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { _vmaxnm_f32(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"] @@ -28665,7 +25979,15 @@ pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe { simd_fmax(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v4f32" + )] + fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { _vmaxnmq_f32(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"] @@ -28679,7 +26001,7 @@ pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -28709,7 +26031,7 @@ pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -29085,7 +26407,7 @@ pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -29093,7 +26415,15 @@ pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] #[cfg(not(target_arch = "arm64ec"))] pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe { simd_fmin(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v4f16" + )] + fn _vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; + } + unsafe { _vminnm_f16(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"] @@ -29107,7 +26437,7 @@ pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -29115,7 +26445,15 @@ pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[cfg(not(target_arch = "arm64ec"))] pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe { simd_fmin(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v8f16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v8f16" + )] + fn _vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + } + unsafe { _vminnmq_f16(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"] @@ -29136,7 +26474,15 @@ pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe { simd_fmin(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v2f32" + )] + fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + unsafe { _vminnm_f32(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"] @@ -29157,7 +26503,15 @@ pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe { simd_fmin(a, b) } + unsafe extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v4f32" + )] + fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + unsafe { _vminnmq_f32(a, b) } } #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"] @@ -33043,7 +30397,7 @@ pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -33065,7 +30419,7 @@ pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -33130,7 +30484,7 @@ pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -33159,7 +30513,7 @@ pub fn vmul_lane_f16(a: float16x4_t, v: float16x4_t) -> float16 #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -34656,15 +32010,7 @@ pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smull.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v4i32")] - fn _vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t; - } - unsafe { _vmull_s16(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"] @@ -34685,15 +32031,7 @@ pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smull.v2i64" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v2i64")] - fn _vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t; - } - unsafe { _vmull_s32(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"] @@ -34714,15 +32052,7 @@ pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smull.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v8i16")] - fn _vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t; - } - unsafe { _vmull_s8(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"] @@ -34743,15 +32073,7 @@ pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umull.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v8i16")] - fn _vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t; - } - unsafe { _vmull_u8(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"] @@ -34772,15 +32094,7 @@ pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umull.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v4i32")] - fn _vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t; - } - unsafe { _vmull_u16(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"] @@ -34801,15 +32115,7 @@ pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umull.v2i64" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v2i64")] - fn _vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t; - } - unsafe { _vmull_u32(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"] @@ -35131,7 +32437,7 @@ pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -35153,7 +32459,7 @@ pub fn vneg_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -36391,7 +33697,7 @@ pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -38514,7 +35820,7 @@ pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { pub fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); unsafe { - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); + let b: int16x4_t = simd_shuffle!(b, b, [N as u32; 4]); vqdmull_s16(a, b) } } @@ -38540,7 +35846,7 @@ pub fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { pub fn vqdmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); unsafe { - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); + let b: int32x2_t = simd_shuffle!(b, b, [N as u32; 2]); vqdmull_s32(a, b) } } @@ -40100,17 +37406,7 @@ pub fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")] fn _vqrshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t; } - unsafe { - _vqrshrn_n_u16( - a, - const { - uint16x8_t([ - -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, - -N as u16, - ]) - }, - ) - } + unsafe { _vqrshrn_n_u16(a, const { uint16x8_t([-N as u16; 8]) }) } } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] @@ -40126,12 +37422,7 @@ pub fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")] fn _vqrshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t; } - unsafe { - _vqrshrn_n_u32( - a, - const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }, - ) - } + unsafe { _vqrshrn_n_u32(a, const { uint32x4_t([-N as u32; 4]) }) } } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] @@ -40147,7 +37438,7 @@ pub fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")] fn _vqrshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t; } - unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) } + unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64; 2]) }) } } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] @@ -41542,17 +38833,7 @@ pub fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")] fn _vqshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t; } - unsafe { - _vqshrn_n_u16( - a, - const { - uint16x8_t([ - -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, - -N as u16, - ]) - }, - ) - } + unsafe { _vqshrn_n_u16(a, const { uint16x8_t([-N as u16; 8]) }) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] @@ -41568,12 +38849,7 @@ pub fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")] fn _vqshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t; } - unsafe { - _vqshrn_n_u32( - a, - const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }, - ) - } + unsafe { _vqshrn_n_u32(a, const { uint32x4_t([-N as u32; 4]) }) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] @@ -41589,7 +38865,7 @@ pub fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")] fn _vqshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t; } - unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) } + unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64; 2]) }) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] @@ -42473,7 +39749,7 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42503,7 +39779,7 @@ pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42649,7 +39925,7 @@ pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42679,7 +39955,7 @@ pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42768,7 +40044,7 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42791,7 +40067,7 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42818,7 +40094,7 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42841,7 +40117,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42868,7 +40144,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42891,7 +40167,7 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42918,7 +40194,7 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42941,7 +40217,7 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42968,7 +40244,7 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42991,7 +40267,7 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43015,7 +40291,7 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43038,7 +40314,7 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43065,7 +40341,7 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43088,7 +40364,7 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43115,7 +40391,7 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43138,7 +40414,7 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43165,7 +40441,7 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43188,7 +40464,7 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43212,7 +40488,7 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43235,7 +40511,7 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43262,7 +40538,7 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43285,7 +40561,7 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43312,7 +40588,7 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43335,7 +40611,7 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43362,7 +40638,7 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43385,7 +40661,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43416,7 +40692,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43439,7 +40715,7 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43466,7 +40742,7 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43489,7 +40765,7 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43516,7 +40792,7 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43539,7 +40815,7 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43566,7 +40842,7 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43589,7 +40865,7 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43620,7 +40896,7 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43643,7 +40919,7 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43670,7 +40946,7 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43693,7 +40969,7 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43720,7 +40996,7 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43743,7 +41019,7 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43770,7 +41046,7 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43793,7 +41069,7 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43824,7 +41100,7 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43847,7 +41123,7 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43874,7 +41150,7 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43897,7 +41173,7 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43924,7 +41200,7 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43947,7 +41223,7 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43974,7 +41250,7 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43997,7 +41273,7 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44024,7 +41300,7 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44047,7 +41323,7 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44075,7 +41351,7 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44098,7 +41374,7 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44125,7 +41401,7 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44148,7 +41424,7 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44175,7 +41451,7 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44198,7 +41474,7 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44225,7 +41501,7 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44248,7 +41524,7 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44275,7 +41551,7 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44298,7 +41574,7 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44324,7 +41600,7 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44347,7 +41623,7 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44374,7 +41650,7 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44397,7 +41673,7 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44424,7 +41700,7 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44447,7 +41723,7 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44475,7 +41751,7 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44498,7 +41774,7 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44525,7 +41801,7 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44548,7 +41824,7 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44575,7 +41851,7 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44598,7 +41874,7 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44625,7 +41901,7 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44648,7 +41924,7 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44675,7 +41951,7 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44698,7 +41974,7 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44724,7 +42000,7 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44747,7 +42023,7 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44774,7 +42050,7 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44797,7 +42073,7 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44824,7 +42100,7 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44847,7 +42123,7 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44875,7 +42151,7 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44898,7 +42174,7 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44925,7 +42201,7 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44948,7 +42224,7 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44975,7 +42251,7 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44998,7 +42274,7 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45024,7 +42300,7 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45047,7 +42323,7 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45071,7 +42347,7 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45094,7 +42370,7 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45118,7 +42394,7 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45141,7 +42417,7 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45168,7 +42444,7 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45191,7 +42467,7 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45217,7 +42493,7 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45240,7 +42516,7 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -59244,7 +56520,7 @@ pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -59266,7 +56542,7 @@ pub fn vrev64_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -59636,7 +56912,7 @@ pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -59665,7 +56941,7 @@ pub fn vrndn_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -60756,7 +58032,7 @@ pub fn vrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -60786,7 +58062,7 @@ pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -60932,7 +58208,7 @@ pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -60962,7 +58238,7 @@ pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -68621,14 +65897,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v2f32.p0" - )] - fn _vst2_f32(a: float32x2_t, b: float32x2_t, ptr: *mut i8); - } - _vst2_f32(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(f32, 2, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] @@ -68640,14 +65909,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v4f32.p0" - )] - fn _vst2q_f32(a: float32x4_t, b: float32x4_t, ptr: *mut i8); - } - _vst2q_f32(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(f32, 4, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] @@ -68659,14 +65921,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v8i8.p0" - )] - fn _vst2_s8(a: int8x8_t, b: int8x8_t, ptr: *mut i8); - } - _vst2_s8(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i8, 8, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] @@ -68678,14 +65933,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v16i8.p0" - )] - fn _vst2q_s8(a: int8x16_t, b: int8x16_t, ptr: *mut i8); - } - _vst2q_s8(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i8, 16, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] @@ -68697,14 +65945,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v4i16.p0" - )] - fn _vst2_s16(a: int16x4_t, b: int16x4_t, ptr: *mut i8); - } - _vst2_s16(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i16, 4, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] @@ -68716,14 +65957,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v8i16.p0" - )] - fn _vst2q_s16(a: int16x8_t, b: int16x8_t, ptr: *mut i8); - } - _vst2q_s16(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i16, 8, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] @@ -68735,14 +65969,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v2i32.p0" - )] - fn _vst2_s32(a: int32x2_t, b: int32x2_t, ptr: *mut i8); - } - _vst2_s32(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i32, 2, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] @@ -68754,14 +65981,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st2))] pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v4i32.p0" - )] - fn _vst2q_s32(a: int32x4_t, b: int32x4_t, ptr: *mut i8); - } - _vst2q_s32(b.0, b.1, a as _) + crate::core_arch::macros::interleaving_store!(i32, 4, 2, a, b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] @@ -69485,11 +66705,7 @@ pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) { #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v1i64.p0")] - fn _vst2_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, size: i32); - } - _vst2_s64(a as _, b.0, b.1, 8) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] @@ -69501,14 +66717,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st2.v1i64.p0" - )] - fn _vst2_s64(a: int64x1_t, b: int64x1_t, ptr: *mut i8); - } - _vst2_s64(b.0, b.1, a as _) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 2-element structures from two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"] @@ -69853,11 +67062,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) { #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v2f32")] - fn _vst3_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, size: i32); - } - _vst3_f32(a as _, b.0, b.1, b.2, 4) + crate::core_arch::macros::interleaving_store!(f32, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] @@ -69869,11 +67074,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4f32")] - fn _vst3q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, size: i32); - } - _vst3q_f32(a as _, b.0, b.1, b.2, 4) + crate::core_arch::macros::interleaving_store!(f32, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] @@ -69885,11 +67086,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v8i8")] - fn _vst3_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, size: i32); - } - _vst3_s8(a as _, b.0, b.1, b.2, 1) + crate::core_arch::macros::interleaving_store!(i8, 8, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] @@ -69901,11 +67098,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v16i8")] - fn _vst3q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, size: i32); - } - _vst3q_s8(a as _, b.0, b.1, b.2, 1) + crate::core_arch::macros::interleaving_store!(i8, 16, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] @@ -69917,11 +67110,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4i16")] - fn _vst3_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, size: i32); - } - _vst3_s16(a as _, b.0, b.1, b.2, 2) + crate::core_arch::macros::interleaving_store!(i16, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] @@ -69933,11 +67122,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v8i16")] - fn _vst3q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, size: i32); - } - _vst3q_s16(a as _, b.0, b.1, b.2, 2) + crate::core_arch::macros::interleaving_store!(i16, 8, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] @@ -69949,11 +67134,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v2i32")] - fn _vst3_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, size: i32); - } - _vst3_s32(a as _, b.0, b.1, b.2, 4) + crate::core_arch::macros::interleaving_store!(i32, 2, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] @@ -69965,11 +67146,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vst3))] pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4i32")] - fn _vst3q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, size: i32); - } - _vst3q_s32(a as _, b.0, b.1, b.2, 4) + crate::core_arch::macros::interleaving_store!(i32, 4, 3, a, b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] @@ -70773,14 +67950,7 @@ pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st3.v1i64.p0" - )] - fn _vst3_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i8); - } - _vst3_s64(b.0, b.1, b.2, a as _) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] @@ -70792,11 +67962,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v1i64")] - fn _vst3_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, c: int64x1_t, size: i32); - } - _vst3_s64(a as _, b.0, b.1, b.2, 8) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 3-element structures from three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"] @@ -71332,14 +68498,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v2f32.p0" - )] - fn _vst4_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, ptr: *mut i8); - } - _vst4_f32(b.0, b.1, b.2, b.3, a as _) + crate::core_arch::macros::interleaving_store!(f32, 2, 4, a, b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] @@ -71351,14 +68510,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v4f32.p0" - )] - fn _vst4q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, ptr: *mut i8); - } - _vst4q_f32(b.0, b.1, b.2, b.3, a as _) + crate::core_arch::macros::interleaving_store!(f32, 4, 4, a, b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] @@ -71370,14 +68522,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v8i8.p0" - )] - fn _vst4_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8); - } - _vst4_s8(b.0, b.1, b.2, b.3, a as _) + crate::core_arch::macros::interleaving_store!(i8, 8, 4, a, b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] @@ -71389,14 +68534,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v16i8.p0" - )] - fn _vst4q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8); - } - _vst4q_s8(b.0, b.1, b.2, b.3, a as _) + crate::core_arch::macros::interleaving_store!(i8, 16, 4, a, b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] @@ -71408,14 +68546,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v4i16.p0" - )] - fn _vst4_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i8); - } - _vst4_s16(b.0, b.1, b.2, b.3, a as _) + crate::core_arch::macros::interleaving_store!(i16, 4, 4, a, b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] @@ -71427,14 +68558,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v8i16.p0" - )] - fn _vst4q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i8); - } - _vst4q_s16(b.0, b.1, b.2, b.3, a as _) + crate::core_arch::macros::interleaving_store!(i16, 8, 4, a, b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] @@ -71446,14 +68570,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v2i32.p0" - )] - fn _vst4_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i8); - } - _vst4_s32(b.0, b.1, b.2, b.3, a as _) + crate::core_arch::macros::interleaving_store!(i32, 2, 4, a, b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] @@ -71465,14 +68582,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v4i32.p0" - )] - fn _vst4q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i8); - } - _vst4q_s32(b.0, b.1, b.2, b.3, a as _) + crate::core_arch::macros::interleaving_store!(i32, 4, 4, a, b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"] @@ -72196,18 +69306,7 @@ pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) { #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v1i64")] - fn _vst4_s64( - ptr: *mut i8, - a: int64x1_t, - b: int64x1_t, - c: int64x1_t, - d: int64x1_t, - size: i32, - ); - } - _vst4_s64(a as _, b.0, b.1, b.2, b.3, 8) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] @@ -72219,14 +69318,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.st4.v1i64.p0" - )] - fn _vst4_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i8); - } - _vst4_s64(b.0, b.1, b.2, b.3, a as _) + core::ptr::write_unaligned(a.cast(), b) } #[doc = "Store multiple 4-element structures from four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"] @@ -72516,7 +69608,7 @@ pub unsafe fn vstrq_p128(a: *mut p128, b: p128) { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -72538,7 +69630,7 @@ pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -74519,7 +71611,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -74549,7 +71641,7 @@ pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -75832,7 +72924,7 @@ pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -75862,7 +72954,7 @@ pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -76438,7 +73530,7 @@ pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -76468,7 +73560,7 @@ pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", diff --git a/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs b/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs index 1ca8ce2b13954..8a4a6e9228221 100644 --- a/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs +++ b/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs @@ -104,7 +104,7 @@ types! { } types! { - #![cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION"))] + #![cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "1.94.0"))] #![cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] /// Arm-specific 64-bit wide vector of four packed `f16`. @@ -750,7 +750,7 @@ pub struct uint32x4x4_t( #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -763,7 +763,7 @@ pub struct float16x4x2_t(pub float16x4_t, pub float16x4_t); #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -776,7 +776,7 @@ pub struct float16x4x3_t(pub float16x4_t, pub float16x4_t, pub float16x4_t); #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -794,7 +794,7 @@ pub struct float16x4x4_t( #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -807,7 +807,7 @@ pub struct float16x8x2_t(pub float16x8_t, pub float16x8_t); #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -820,7 +820,7 @@ pub struct float16x8x3_t(pub float16x8_t, pub float16x8_t, pub float16x8_t); #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", diff --git a/stdarch/crates/core_arch/src/core_arch_docs.md b/stdarch/crates/core_arch/src/core_arch_docs.md index 7075945754975..9b52fb2af1598 100644 --- a/stdarch/crates/core_arch/src/core_arch_docs.md +++ b/stdarch/crates/core_arch/src/core_arch_docs.md @@ -186,6 +186,7 @@ others at: * [`arm`] * [`aarch64`] * [`amdgpu`] +* [`hexagon`] * [`riscv32`] * [`riscv64`] * [`mips`] @@ -203,6 +204,7 @@ others at: [`arm`]: ../../core/arch/arm/index.html [`aarch64`]: ../../core/arch/aarch64/index.html [`amdgpu`]: ../../core/arch/amdgpu/index.html +[`hexagon`]: ../../core/arch/hexagon/index.html [`riscv32`]: ../../core/arch/riscv32/index.html [`riscv64`]: ../../core/arch/riscv64/index.html [`mips`]: ../../core/arch/mips/index.html diff --git a/stdarch/crates/core_arch/src/hexagon/mod.rs b/stdarch/crates/core_arch/src/hexagon/mod.rs new file mode 100644 index 0000000000000..c370f3da15dfb --- /dev/null +++ b/stdarch/crates/core_arch/src/hexagon/mod.rs @@ -0,0 +1,29 @@ +//! Hexagon architecture intrinsics +//! +//! This module contains intrinsics for the Qualcomm Hexagon DSP architecture, +//! including the Hexagon Vector Extensions (HVX). +//! +//! HVX is a wide SIMD architecture designed for high-performance signal processing, +//! machine learning, and image processing workloads. +//! +//! ## Vector Length Modes +//! +//! HVX supports two vector length modes: +//! - 64-byte mode (512-bit vectors): Use the [`v64`] module +//! - 128-byte mode (1024-bit vectors): Use the [`v128`] module +//! +//! Both modules are available unconditionally, but require the appropriate +//! target features to actually use the intrinsics: +//! - For 64-byte mode: `-C target-feature=+hvx-length64b` +//! - For 128-byte mode: `-C target-feature=+hvx-length128b` +//! +//! Note that HVX v66 and later default to 128-byte mode, while earlier versions +//! (v60-v65) default to 64-byte mode. + +/// HVX intrinsics for 64-byte vector mode (512-bit vectors) +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub mod v64; + +/// HVX intrinsics for 128-byte vector mode (1024-bit vectors) +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub mod v128; diff --git a/stdarch/crates/core_arch/src/hexagon/v128.rs b/stdarch/crates/core_arch/src/hexagon/v128.rs new file mode 100644 index 0000000000000..ef7ff4205c71d --- /dev/null +++ b/stdarch/crates/core_arch/src/hexagon/v128.rs @@ -0,0 +1,7489 @@ +//! Hexagon HVX 128-byte vector mode intrinsics +//! +//! This module provides intrinsics for the Hexagon Vector Extensions (HVX) +//! in 128-byte vector mode (1024-bit vectors). +//! +//! HVX is a wide vector extension designed for high-performance signal processing. +//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61) +//! +//! ## Vector Types +//! +//! In 128-byte mode: +//! - `HvxVector` is 1024 bits (128 bytes) containing 32 x 32-bit values +//! - `HvxVectorPair` is 2048 bits (256 bytes) +//! - `HvxVectorPred` is 1024 bits (128 bytes) for predicate operations +//! +//! To use this module, compile with `-C target-feature=+hvx-length128b`. +//! +//! ## Architecture Versions +//! +//! Different intrinsics require different HVX architecture versions. Use the +//! appropriate target feature to enable the required version: +//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations) +//! - HVX v62: `-C target-feature=+hvxv62` +//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support) +//! - HVX v66: `-C target-feature=+hvxv66` +//! - HVX v68: `-C target-feature=+hvxv68` +//! - HVX v69: `-C target-feature=+hvxv69` +//! - HVX v73: `-C target-feature=+hvxv73` +//! - HVX v79: `-C target-feature=+hvxv79` +//! +//! Each version includes all features from previous versions. + +#![allow(non_camel_case_types)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use crate::intrinsics::simd::{simd_add, simd_and, simd_or, simd_sub, simd_xor}; + +// HVX type definitions for 128-byte vector mode +types! { + #![unstable(feature = "stdarch_hexagon", issue = "151523")] + + /// HVX vector type (1024 bits / 128 bytes) + /// + /// This type represents a single HVX vector register containing 32 x 32-bit values. + pub struct HvxVector(32 x i32); + + /// HVX vector pair type (2048 bits / 256 bytes) + /// + /// This type represents a pair of HVX vector registers, often used for + /// operations that produce double-width results. + pub struct HvxVectorPair(64 x i32); + + /// HVX vector predicate type (1024 bits / 128 bytes) + /// + /// This type represents a predicate vector used for conditional operations. + /// Each bit corresponds to a lane in the vector. + pub struct HvxVectorPred(32 x i32); +} + +// LLVM intrinsic declarations for 128-byte vector mode +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.hexagon.V6.extractw.128B"] + fn extractw(_: HvxVector, _: i32) -> i32; + #[link_name = "llvm.hexagon.V6.get.qfext.128B"] + fn get_qfext(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.hi.128B"] + fn hi(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lo.128B"] + fn lo(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplatb.128B"] + fn lvsplatb(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplath.128B"] + fn lvsplath(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplatw.128B"] + fn lvsplatw(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.and.128B"] + fn pred_and(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.and.n.128B"] + fn pred_and_n(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.not.128B"] + fn pred_not(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.or.128B"] + fn pred_or(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.or.n.128B"] + fn pred_or_n(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.scalar2.128B"] + fn pred_scalar2(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.scalar2v2.128B"] + fn pred_scalar2v2(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.xor.128B"] + fn pred_xor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.set.qfext.128B"] + fn set_qfext(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.shuffeqh.128B"] + fn shuffeqh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.shuffeqw.128B"] + fn shuffeqw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.v6mpyhubs10.128B"] + fn v6mpyhubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyhubs10.vxx.128B"] + fn v6mpyhubs10_vxx( + _: HvxVectorPair, + _: HvxVectorPair, + _: HvxVectorPair, + _: i32, + ) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyvubs10.128B"] + fn v6mpyvubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyvubs10.vxx.128B"] + fn v6mpyvubs10_vxx( + _: HvxVectorPair, + _: HvxVectorPair, + _: HvxVectorPair, + _: i32, + ) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vS32b.nqpred.ai.128B"] + fn vS32b_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.nt.nqpred.ai.128B"] + fn vS32b_nt_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.nt.qpred.ai.128B"] + fn vS32b_nt_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.qpred.ai.128B"] + fn vS32b_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vabs.f8.128B"] + fn vabs_f8(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabs.hf.128B"] + fn vabs_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabs.sf.128B"] + fn vabs_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsb.128B"] + fn vabsb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsb.sat.128B"] + fn vabsb_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffh.128B"] + fn vabsdiffh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffub.128B"] + fn vabsdiffub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffuh.128B"] + fn vabsdiffuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffw.128B"] + fn vabsdiffw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsh.128B"] + fn vabsh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsh.sat.128B"] + fn vabsh_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsw.128B"] + fn vabsw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsw.sat.128B"] + fn vabsw_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.hf.128B"] + fn vadd_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.hf.hf.128B"] + fn vadd_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf16.128B"] + fn vadd_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf16.mix.128B"] + fn vadd_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf32.128B"] + fn vadd_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf32.mix.128B"] + fn vadd_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.sf.128B"] + fn vadd_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.sf.hf.128B"] + fn vadd_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadd.sf.sf.128B"] + fn vadd_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddb.128B"] + fn vaddb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddb.dv.128B"] + fn vaddb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddbnq.128B"] + fn vaddbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbq.128B"] + fn vaddbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbsat.128B"] + fn vaddbsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbsat.dv.128B"] + fn vaddbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddcarrysat.128B"] + fn vaddcarrysat(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddclbh.128B"] + fn vaddclbh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddclbw.128B"] + fn vaddclbw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddh.128B"] + fn vaddh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddh.dv.128B"] + fn vaddh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhnq.128B"] + fn vaddhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhq.128B"] + fn vaddhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhsat.128B"] + fn vaddhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhsat.dv.128B"] + fn vaddhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhw.128B"] + fn vaddhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhw.acc.128B"] + fn vaddhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubh.128B"] + fn vaddubh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubh.acc.128B"] + fn vaddubh_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubsat.128B"] + fn vaddubsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddubsat.dv.128B"] + fn vaddubsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddububb.sat.128B"] + fn vaddububb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduhsat.128B"] + fn vadduhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduhsat.dv.128B"] + fn vadduhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduhw.128B"] + fn vadduhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduhw.acc.128B"] + fn vadduhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduwsat.128B"] + fn vadduwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduwsat.dv.128B"] + fn vadduwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddw.128B"] + fn vaddw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddw.dv.128B"] + fn vaddw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddwnq.128B"] + fn vaddwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwq.128B"] + fn vaddwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwsat.128B"] + fn vaddwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwsat.dv.128B"] + fn vaddwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.valignb.128B"] + fn valignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.valignbi.128B"] + fn valignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vand.128B"] + fn vand(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandnqrt.128B"] + fn vandnqrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandnqrt.acc.128B"] + fn vandnqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandqrt.128B"] + fn vandqrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandqrt.acc.128B"] + fn vandqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvnqv.128B"] + fn vandvnqv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvqv.128B"] + fn vandvqv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvrt.128B"] + fn vandvrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvrt.acc.128B"] + fn vandvrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslh.128B"] + fn vaslh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslh.acc.128B"] + fn vaslh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslhv.128B"] + fn vaslhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslw.128B"] + fn vaslw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslw.acc.128B"] + fn vaslw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslwv.128B"] + fn vaslwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasr.into.128B"] + fn vasr_into(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vasrh.128B"] + fn vasrh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrh.acc.128B"] + fn vasrh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhbrndsat.128B"] + fn vasrhbrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhbsat.128B"] + fn vasrhbsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhubrndsat.128B"] + fn vasrhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhubsat.128B"] + fn vasrhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhv.128B"] + fn vasrhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruhubrndsat.128B"] + fn vasruhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruhubsat.128B"] + fn vasruhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruwuhrndsat.128B"] + fn vasruwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruwuhsat.128B"] + fn vasruwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvuhubrndsat.128B"] + fn vasrvuhubrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvuhubsat.128B"] + fn vasrvuhubsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvwuhrndsat.128B"] + fn vasrvwuhrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvwuhsat.128B"] + fn vasrvwuhsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrw.128B"] + fn vasrw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrw.acc.128B"] + fn vasrw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwh.128B"] + fn vasrwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwhrndsat.128B"] + fn vasrwhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwhsat.128B"] + fn vasrwhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwuhrndsat.128B"] + fn vasrwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwuhsat.128B"] + fn vasrwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwv.128B"] + fn vasrwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassign.128B"] + fn vassign(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassign.fp.128B"] + fn vassign_fp(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassignp.128B"] + fn vassignp(_: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vavgb.128B"] + fn vavgb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgbrnd.128B"] + fn vavgbrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgh.128B"] + fn vavgh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavghrnd.128B"] + fn vavghrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgub.128B"] + fn vavgub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgubrnd.128B"] + fn vavgubrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguh.128B"] + fn vavguh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguhrnd.128B"] + fn vavguhrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguw.128B"] + fn vavguw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguwrnd.128B"] + fn vavguwrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgw.128B"] + fn vavgw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgwrnd.128B"] + fn vavgwrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcl0h.128B"] + fn vcl0h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcl0w.128B"] + fn vcl0w(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcombine.128B"] + fn vcombine(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vconv.h.hf.128B"] + fn vconv_h_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.h.128B"] + fn vconv_hf_h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.qf16.128B"] + fn vconv_hf_qf16(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.qf32.128B"] + fn vconv_hf_qf32(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.sf.qf32.128B"] + fn vconv_sf_qf32(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.sf.w.128B"] + fn vconv_sf_w(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.w.sf.128B"] + fn vconv_w_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt2.hf.b.128B"] + fn vcvt2_hf_b(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt2.hf.ub.128B"] + fn vcvt2_hf_ub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.b.hf.128B"] + fn vcvt_b_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.h.hf.128B"] + fn vcvt_h_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.b.128B"] + fn vcvt_hf_b(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.f8.128B"] + fn vcvt_hf_f8(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.h.128B"] + fn vcvt_hf_h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.sf.128B"] + fn vcvt_hf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.ub.128B"] + fn vcvt_hf_ub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.uh.128B"] + fn vcvt_hf_uh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.sf.hf.128B"] + fn vcvt_sf_hf(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.ub.hf.128B"] + fn vcvt_ub_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.uh.hf.128B"] + fn vcvt_uh_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vd0.128B"] + fn vd0() -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdd0.128B"] + fn vdd0() -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdealb.128B"] + fn vdealb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealb4w.128B"] + fn vdealb4w(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealh.128B"] + fn vdealh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealvdd.128B"] + fn vdealvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdelta.128B"] + fn vdelta(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.128B"] + fn vdmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.acc.128B"] + fn vdmpy_sf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.128B"] + fn vdmpybus(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.acc.128B"] + fn vdmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.dv.128B"] + fn vdmpybus_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpybus.dv.acc.128B"] + fn vdmpybus_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhb.128B"] + fn vdmpyhb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhb.acc.128B"] + fn vdmpyhb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.128B"] + fn vdmpyhb_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.acc.128B"] + fn vdmpyhb_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhisat.128B"] + fn vdmpyhisat(_: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhisat.acc.128B"] + fn vdmpyhisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsat.128B"] + fn vdmpyhsat(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsat.acc.128B"] + fn vdmpyhsat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.128B"] + fn vdmpyhsuisat(_: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.acc.128B"] + fn vdmpyhsuisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsusat.128B"] + fn vdmpyhsusat(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsusat.acc.128B"] + fn vdmpyhsusat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhvsat.128B"] + fn vdmpyhvsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhvsat.acc.128B"] + fn vdmpyhvsat_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdsaduh.128B"] + fn vdsaduh(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdsaduh.acc.128B"] + fn vdsaduh_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.veqb.128B"] + fn veqb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.and.128B"] + fn veqb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.or.128B"] + fn veqb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.xor.128B"] + fn veqb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.128B"] + fn veqh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.and.128B"] + fn veqh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.or.128B"] + fn veqh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.xor.128B"] + fn veqh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.128B"] + fn veqw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.and.128B"] + fn veqw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.or.128B"] + fn veqw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.xor.128B"] + fn veqw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.f8.128B"] + fn vfmax_f8(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.hf.128B"] + fn vfmax_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.sf.128B"] + fn vfmax_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.f8.128B"] + fn vfmin_f8(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.hf.128B"] + fn vfmin_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.sf.128B"] + fn vfmin_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.f8.128B"] + fn vfneg_f8(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.hf.128B"] + fn vfneg_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.sf.128B"] + fn vfneg_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgathermh.128B"] + fn vgathermh(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhq.128B"] + fn vgathermhq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhw.128B"] + fn vgathermhw(_: *mut HvxVector, _: i32, _: i32, _: HvxVectorPair) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhwq.128B"] + fn vgathermhwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVectorPair) -> (); + #[link_name = "llvm.hexagon.V6.vgathermw.128B"] + fn vgathermw(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermwq.128B"] + fn vgathermwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgtb.128B"] + fn vgtb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.and.128B"] + fn vgtb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.or.128B"] + fn vgtb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.xor.128B"] + fn vgtb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.128B"] + fn vgth(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.and.128B"] + fn vgth_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.or.128B"] + fn vgth_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.xor.128B"] + fn vgth_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.128B"] + fn vgthf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.and.128B"] + fn vgthf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.or.128B"] + fn vgthf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.xor.128B"] + fn vgthf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.128B"] + fn vgtsf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.and.128B"] + fn vgtsf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.or.128B"] + fn vgtsf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.xor.128B"] + fn vgtsf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.128B"] + fn vgtub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.and.128B"] + fn vgtub_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.or.128B"] + fn vgtub_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.xor.128B"] + fn vgtub_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.128B"] + fn vgtuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.and.128B"] + fn vgtuh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.or.128B"] + fn vgtuh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.xor.128B"] + fn vgtuh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.128B"] + fn vgtuw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.and.128B"] + fn vgtuw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.or.128B"] + fn vgtuw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.xor.128B"] + fn vgtuw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.128B"] + fn vgtw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.and.128B"] + fn vgtw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.or.128B"] + fn vgtw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.xor.128B"] + fn vgtw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vinsertwr.128B"] + fn vinsertwr(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlalignb.128B"] + fn vlalignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlalignbi.128B"] + fn vlalignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrb.128B"] + fn vlsrb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrh.128B"] + fn vlsrh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrhv.128B"] + fn vlsrhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrw.128B"] + fn vlsrw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrwv.128B"] + fn vlsrwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.128B"] + fn vlutvvb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.nm.128B"] + fn vlutvvb_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.oracc.128B"] + fn vlutvvb_oracc(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.oracci.128B"] + fn vlutvvb_oracci(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvbi.128B"] + fn vlutvvbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvwh.128B"] + fn vlutvwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.nm.128B"] + fn vlutvwh_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.oracc.128B"] + fn vlutvwh_oracc(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.oracci.128B"] + fn vlutvwh_oracci(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwhi.128B"] + fn vlutvwhi(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmax.hf.128B"] + fn vmax_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmax.sf.128B"] + fn vmax_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxb.128B"] + fn vmaxb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxh.128B"] + fn vmaxh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxub.128B"] + fn vmaxub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxuh.128B"] + fn vmaxuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxw.128B"] + fn vmaxw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmin.hf.128B"] + fn vmin_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmin.sf.128B"] + fn vmin_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminb.128B"] + fn vminb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminh.128B"] + fn vminh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminub.128B"] + fn vminub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminuh.128B"] + fn vminuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminw.128B"] + fn vminw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpabus.128B"] + fn vmpabus(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabus.acc.128B"] + fn vmpabus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabusv.128B"] + fn vmpabusv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuu.128B"] + fn vmpabuu(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuu.acc.128B"] + fn vmpabuu_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuuv.128B"] + fn vmpabuuv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpahb.128B"] + fn vmpahb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpahb.acc.128B"] + fn vmpahb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpauhb.128B"] + fn vmpauhb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpauhb.acc.128B"] + fn vmpauhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.128B"] + fn vmpy_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.acc.128B"] + fn vmpy_hf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.128B"] + fn vmpy_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.hf.128B"] + fn vmpy_qf16_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.mix.hf.128B"] + fn vmpy_qf16_mix_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.128B"] + fn vmpy_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.hf.128B"] + fn vmpy_qf32_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.mix.hf.128B"] + fn vmpy_qf32_mix_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.qf16.128B"] + fn vmpy_qf32_qf16(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.sf.128B"] + fn vmpy_qf32_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.128B"] + fn vmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.acc.128B"] + fn vmpy_sf_hf_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.sf.sf.128B"] + fn vmpy_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpybus.128B"] + fn vmpybus(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybus.acc.128B"] + fn vmpybus_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybusv.128B"] + fn vmpybusv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybusv.acc.128B"] + fn vmpybusv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybv.128B"] + fn vmpybv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybv.acc.128B"] + fn vmpybv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyewuh.128B"] + fn vmpyewuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyewuh.64.128B"] + fn vmpyewuh_64(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyh.128B"] + fn vmpyh(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyh.acc.128B"] + fn vmpyh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhsat.acc.128B"] + fn vmpyhsat_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhsrs.128B"] + fn vmpyhsrs(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyhss.128B"] + fn vmpyhss(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyhus.128B"] + fn vmpyhus(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhus.acc.128B"] + fn vmpyhus_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhv.128B"] + fn vmpyhv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhv.acc.128B"] + fn vmpyhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhvsrs.128B"] + fn vmpyhvsrs(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyieoh.128B"] + fn vmpyieoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewh.acc.128B"] + fn vmpyiewh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewuh.128B"] + fn vmpyiewuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewuh.acc.128B"] + fn vmpyiewuh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyih.128B"] + fn vmpyih(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyih.acc.128B"] + fn vmpyih_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyihb.128B"] + fn vmpyihb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyihb.acc.128B"] + fn vmpyihb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiowh.128B"] + fn vmpyiowh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwb.128B"] + fn vmpyiwb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwb.acc.128B"] + fn vmpyiwb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwh.128B"] + fn vmpyiwh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwh.acc.128B"] + fn vmpyiwh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwub.128B"] + fn vmpyiwub(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwub.acc.128B"] + fn vmpyiwub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.128B"] + fn vmpyowh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.64.acc.128B"] + fn vmpyowh_64_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.128B"] + fn vmpyowh_rnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.sacc.128B"] + fn vmpyowh_rnd_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.sacc.128B"] + fn vmpyowh_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyub.128B"] + fn vmpyub(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyub.acc.128B"] + fn vmpyub_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyubv.128B"] + fn vmpyubv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyubv.acc.128B"] + fn vmpyubv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuh.128B"] + fn vmpyuh(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuh.acc.128B"] + fn vmpyuh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhe.128B"] + fn vmpyuhe(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyuhe.acc.128B"] + fn vmpyuhe_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyuhv.128B"] + fn vmpyuhv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhv.acc.128B"] + fn vmpyuhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhvs.128B"] + fn vmpyuhvs(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmux.128B"] + fn vmux(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgb.128B"] + fn vnavgb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgh.128B"] + fn vnavgh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgub.128B"] + fn vnavgub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgw.128B"] + fn vnavgw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnormamth.128B"] + fn vnormamth(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnormamtw.128B"] + fn vnormamtw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnot.128B"] + fn vnot(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vor.128B"] + fn vor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackeb.128B"] + fn vpackeb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackeh.128B"] + fn vpackeh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackhb.sat.128B"] + fn vpackhb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackhub.sat.128B"] + fn vpackhub_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackob.128B"] + fn vpackob(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackoh.128B"] + fn vpackoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackwh.sat.128B"] + fn vpackwh_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackwuh.sat.128B"] + fn vpackwuh_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpopcounth.128B"] + fn vpopcounth(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqb.128B"] + fn vprefixqb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqh.128B"] + fn vprefixqh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqw.128B"] + fn vprefixqw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrdelta.128B"] + fn vrdelta(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybus.128B"] + fn vrmpybus(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybus.acc.128B"] + fn vrmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybusi.128B"] + fn vrmpybusi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpybusi.acc.128B"] + fn vrmpybusi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpybusv.128B"] + fn vrmpybusv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybusv.acc.128B"] + fn vrmpybusv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybv.128B"] + fn vrmpybv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybv.acc.128B"] + fn vrmpybv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyub.128B"] + fn vrmpyub(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyub.acc.128B"] + fn vrmpyub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyubi.128B"] + fn vrmpyubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpyubi.acc.128B"] + fn vrmpyubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpyubv.128B"] + fn vrmpyubv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyubv.acc.128B"] + fn vrmpyubv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vror.128B"] + fn vror(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrotr.128B"] + fn vrotr(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundhb.128B"] + fn vroundhb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundhub.128B"] + fn vroundhub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrounduhub.128B"] + fn vrounduhub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrounduwuh.128B"] + fn vrounduwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundwh.128B"] + fn vroundwh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundwuh.128B"] + fn vroundwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrsadubi.128B"] + fn vrsadubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrsadubi.acc.128B"] + fn vrsadubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsatdw.128B"] + fn vsatdw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsathub.128B"] + fn vsathub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsatuwuh.128B"] + fn vsatuwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsatwh.128B"] + fn vsatwh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsb.128B"] + fn vsb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vscattermh.128B"] + fn vscattermh(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermh.add.128B"] + fn vscattermh_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhq.128B"] + fn vscattermhq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhw.128B"] + fn vscattermhw(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhw.add.128B"] + fn vscattermhw_add(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhwq.128B"] + fn vscattermhwq(_: HvxVector, _: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermw.128B"] + fn vscattermw(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermw.add.128B"] + fn vscattermw_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermwq.128B"] + fn vscattermwq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vsh.128B"] + fn vsh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufeh.128B"] + fn vshufeh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffb.128B"] + fn vshuffb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffeb.128B"] + fn vshuffeb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffh.128B"] + fn vshuffh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffob.128B"] + fn vshuffob(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffvdd.128B"] + fn vshuffvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoeb.128B"] + fn vshufoeb(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoeh.128B"] + fn vshufoeh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoh.128B"] + fn vshufoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.hf.128B"] + fn vsub_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.hf.hf.128B"] + fn vsub_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf16.128B"] + fn vsub_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf16.mix.128B"] + fn vsub_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf32.128B"] + fn vsub_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf32.mix.128B"] + fn vsub_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.sf.128B"] + fn vsub_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.sf.hf.128B"] + fn vsub_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsub.sf.sf.128B"] + fn vsub_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubb.128B"] + fn vsubb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubb.dv.128B"] + fn vsubb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubbnq.128B"] + fn vsubbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbq.128B"] + fn vsubbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbsat.128B"] + fn vsubbsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbsat.dv.128B"] + fn vsubbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubh.128B"] + fn vsubh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubh.dv.128B"] + fn vsubh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubhnq.128B"] + fn vsubhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhq.128B"] + fn vsubhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhsat.128B"] + fn vsubhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhsat.dv.128B"] + fn vsubhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubhw.128B"] + fn vsubhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsububh.128B"] + fn vsububh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsububsat.128B"] + fn vsububsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsububsat.dv.128B"] + fn vsububsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubububb.sat.128B"] + fn vsubububb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuhsat.128B"] + fn vsubuhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuhsat.dv.128B"] + fn vsubuhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubuhw.128B"] + fn vsubuhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubuwsat.128B"] + fn vsubuwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuwsat.dv.128B"] + fn vsubuwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubw.128B"] + fn vsubw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubw.dv.128B"] + fn vsubw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubwnq.128B"] + fn vsubwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwq.128B"] + fn vsubwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwsat.128B"] + fn vsubwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwsat.dv.128B"] + fn vsubwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vswap.128B"] + fn vswap(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyb.128B"] + fn vtmpyb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyb.acc.128B"] + fn vtmpyb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpybus.128B"] + fn vtmpybus(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpybus.acc.128B"] + fn vtmpybus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyhb.128B"] + fn vtmpyhb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyhb.acc.128B"] + fn vtmpyhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackb.128B"] + fn vunpackb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackh.128B"] + fn vunpackh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackob.128B"] + fn vunpackob(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackoh.128B"] + fn vunpackoh(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackub.128B"] + fn vunpackub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackuh.128B"] + fn vunpackuh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vxor.128B"] + fn vxor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vzb.128B"] + fn vzb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vzh.128B"] + fn vzh(_: HvxVector) -> HvxVectorPair; +} + +/// `Rd32=vextract(Vu32,Rs32)` +/// +/// Instruction Type: LD +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(extractw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 { + extractw(vu, rs) +} + +/// `Vd32=hi(Vss32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(hi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector { + hi(vss) +} + +/// `Vd32=lo(Vss32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(lo))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector { + lo(vss) +} + +/// `Vd32=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(lvsplatw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector { + lvsplatw(rt) +} + +/// `Vd32.uh=vabsdiff(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffh(vu, vv) +} + +/// `Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffub(vu, vv) +} + +/// `Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffuh(vu, vv) +} + +/// `Vd32.uw=vabsdiff(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffw(vu, vv) +} + +/// `Vd32.h=vabs(Vu32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector { + vabsh(vu) +} + +/// `Vd32.h=vabs(Vu32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector { + vabsh_sat(vu) +} + +/// `Vd32.w=vabs(Vu32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector { + vabsw(vu) +} + +/// `Vd32.w=vabs(Vu32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsw_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector { + vabsw_sat(vu) +} + +/// `Vd32.b=vadd(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddb(vu, vv) +} + +/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddb_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddh(vu, vv) +} + +/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddh_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddh_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddhsat(vu, vv) +} + +/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vaddhw(vu, vv) +} + +/// `Vdd32.h=vadd(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vaddubh(vu, vv) +} + +/// `Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddubsat(vu, vv) +} + +/// `Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddubsat_dv(vuu, vvv) +} + +/// `Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadduhsat(vu, vv) +} + +/// `Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vadduhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vadd(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vadduhw(vu, vv) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_add(vu, vv) +} + +/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddw_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddw_dv(vuu, vvv) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddwsat(vu, vv) +} + +/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddwsat_dv(vuu, vvv) +} + +/// `Vd32=valign(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(valignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + valignb(vu, vv, rt) +} + +/// `Vd32=valign(Vu32,Vv32,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(valignbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + valignbi(vu, vv, iu3) +} + +/// `Vd32=vand(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vand))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_and(vu, vv) +} + +/// `Vd32.h=vasl(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector { + vaslh(vu, rt) +} + +/// `Vd32.h=vasl(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaslhv(vu, vv) +} + +/// `Vd32.w=vasl(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector { + vaslw(vu, rt) +} + +/// `Vx32.w+=vasl(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vaslw_acc(vx, vu, rt) +} + +/// `Vd32.w=vasl(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaslwv(vu, vv) +} + +/// `Vd32.h=vasr(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector { + vasrh(vu, rt) +} + +/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhbrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhbrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhubrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhubsat(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vasrhv(vu, vv) +} + +/// `Vd32.w=vasr(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector { + vasrw(vu, rt) +} + +/// `Vx32.w+=vasr(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vasrw_acc(vx, vu, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwh(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwhrndsat(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwhsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwuhsat(vu, vv, rt) +} + +/// `Vd32.w=vasr(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vasrwv(vu, vv) +} + +/// `Vd32=Vu32` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vassign))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector { + vassign(vu) +} + +/// `Vdd32=Vuu32` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vassignp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair { + vassignp(vuu) +} + +/// `Vd32.h=vavg(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgh(vu, vv) +} + +/// `Vd32.h=vavg(Vu32.h,Vv32.h):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavghrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavghrnd(vu, vv) +} + +/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgub(vu, vv) +} + +/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgubrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgubrnd(vu, vv) +} + +/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavguh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguh(vu, vv) +} + +/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavguhrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguhrnd(vu, vv) +} + +/// `Vd32.w=vavg(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgw(vu, vv) +} + +/// `Vd32.w=vavg(Vu32.w,Vv32.w):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgwrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgwrnd(vu, vv) +} + +/// `Vd32.uh=vcl0(Vu32.uh)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcl0h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector { + vcl0h(vu) +} + +/// `Vd32.uw=vcl0(Vu32.uw)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcl0w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector { + vcl0w(vu) +} + +/// `Vdd32=vcombine(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcombine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vcombine(vu, vv) +} + +/// `Vd32=#0` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vd0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vzero() -> HvxVector { + vd0() +} + +/// `Vd32.b=vdeal(Vu32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector { + vdealb(vu) +} + +/// `Vd32.b=vdeale(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealb4w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdealb4w(vu, vv) +} + +/// `Vd32.h=vdeal(Vu32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector { + vdealh(vu) +} + +/// `Vdd32=vdeal(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealvdd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vdealvdd(vu, vv, rt) +} + +/// `Vd32=vdelta(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdelta))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdelta(vu, vv) +} + +/// `Vd32.h=vdmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { + vdmpybus(vu, rt) +} + +/// `Vx32.h+=vdmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpybus_acc(vx, vu, rt) +} + +/// `Vdd32.h=vdmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdmpybus_dv(vuu, rt) +} + +/// `Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_dv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vdmpyacc_whwubrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdmpybus_dv_acc(vxx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhb(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhb_acc(vx, vu, rt) +} + +/// `Vdd32.w=vdmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdmpyhb_dv(vuu, rt) +} + +/// `Vxx32.w+=vdmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vdmpyacc_wwwhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdmpyhb_dv_acc(vxx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhisat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhisat(vuu, rt) +} + +/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhisat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhisat_acc(vx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsat(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsat_acc(vx, vu, rt) +} + +/// `Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsuisat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhsuisat(vuu, rt) +} + +/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhsuisat_acc(vx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsusat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsusat(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsusat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsusat_acc(vx, vu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhvsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpyhvsat(vu, vv) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhvsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpyhvsat_acc(vx, vu, vv) +} + +/// `Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdsaduh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdsaduh(vuu, rt) +} + +/// `Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdsaduh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdsaduh_acc(vxx, vuu, rt) +} + +/// `Vx32.w=vinsert(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vinsertwr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector { + vinsertwr(vx, rt) +} + +/// `Vd32=vlalign(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlalignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlalignb(vu, vv, rt) +} + +/// `Vd32=vlalign(Vu32,Vv32,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlalignbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + vlalignbi(vu, vv, iu3) +} + +/// `Vd32.uh=vlsr(Vu32.uh,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector { + vlsrh(vu, rt) +} + +/// `Vd32.h=vlsr(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vlsrhv(vu, vv) +} + +/// `Vd32.uw=vlsr(Vu32.uw,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector { + vlsrw(vu, rt) +} + +/// `Vd32.w=vlsr(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vlsrwv(vu, vv) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvvb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlutvvb(vu, vv, rt) +} + +/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvvb_oracc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32or_vbvbvbr( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, + rt: i32, +) -> HvxVector { + vlutvvb_oracc(vx, vu, vv, rt) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vlutvwh(vu, vv, rt) +} + +/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvwh_oracc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16or_whvbvhr( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, + rt: i32, +) -> HvxVectorPair { + vlutvwh_oracc(vxx, vu, vv, rt) +} + +/// `Vd32.h=vmax(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxh(vu, vv) +} + +/// `Vd32.ub=vmax(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxub(vu, vv) +} + +/// `Vd32.uh=vmax(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxuh(vu, vv) +} + +/// `Vd32.w=vmax(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxw(vu, vv) +} + +/// `Vd32.h=vmin(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminh(vu, vv) +} + +/// `Vd32.ub=vmin(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminub(vu, vv) +} + +/// `Vd32.uh=vmin(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminuh(vu, vv) +} + +/// `Vd32.w=vmin(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminw(vu, vv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpabus(vuu, rt) +} + +/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpaacc_whwubrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpabus_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vmpabusv(vuu, vvv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabuuv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vmpabuuv(vuu, vvv) +} + +/// `Vdd32.w=vmpa(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpahb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpahb(vuu, rt) +} + +/// `Vxx32.w+=vmpa(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpahb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpaacc_wwwhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpahb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpybus(vu, rt) +} + +/// `Vxx32.h+=vmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpybus_acc(vxx, vu, rt) +} + +/// `Vdd32.h=vmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpybusv(vu, vv) +} + +/// `Vxx32.h+=vmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybusv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpyacc_whvubvb( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpybusv_acc(vxx, vu, vv) +} + +/// `Vdd32.h=vmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpybv(vu, vv) +} + +/// `Vxx32.h+=vmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpyacc_whvbvb( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpybv_acc(vxx, vu, vv) +} + +/// `Vd32.w=vmpye(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyewuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyewuh(vu, vv) +} + +/// `Vdd32.w=vmpy(Vu32.h,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyh(vu, rt) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyhsat_acc(vxx, vu, rt) +} + +/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhsrs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { + vmpyhsrs(vu, rt) +} + +/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhss))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { + vmpyhss(vu, rt) +} + +/// `Vdd32.w=vmpy(Vu32.h,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyhus(vu, vv) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhvuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyhus_acc(vxx, vu, vv) +} + +/// `Vdd32.w=vmpy(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyhv(vu, vv) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhvh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyhv_acc(vxx, vu, vv) +} + +/// `Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhvsrs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyhvsrs(vu, vv) +} + +/// `Vd32.w=vmpyieo(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyieoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyieoh(vu, vv) +} + +/// `Vx32.w+=vmpyie(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewh_acc(vx, vu, vv) +} + +/// `Vd32.w=vmpyie(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewuh(vu, vv) +} + +/// `Vx32.w+=vmpyie(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewuh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewuh_acc(vx, vu, vv) +} + +/// `Vd32.h=vmpyi(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyih))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyih(vu, vv) +} + +/// `Vx32.h+=vmpyi(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyih_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyih_acc(vx, vu, vv) +} + +/// `Vd32.h=vmpyi(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyihb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector { + vmpyihb(vu, rt) +} + +/// `Vx32.h+=vmpyi(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyihb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyihb_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyio(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiowh(vu, vv) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwb(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwb_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwh(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwh_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyowh(vu, vv) +} + +/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_rnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyowh_rnd(vu, vv) +} + +/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, +) -> HvxVector { + vmpyowh_rnd_sacc(vx, vu, vv) +} + +/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_sacc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, +) -> HvxVector { + vmpyowh_sacc(vx, vu, vv) +} + +/// `Vdd32.uh=vmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyub(vu, rt) +} + +/// `Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpyacc_wuhvubrub( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyub_acc(vxx, vu, rt) +} + +/// `Vdd32.uh=vmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyubv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyubv(vu, vv) +} + +/// `Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyubv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpyacc_wuhvubvub( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyubv_acc(vxx, vu, vv) +} + +/// `Vdd32.uw=vmpy(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyuh(vu, rt) +} + +/// `Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyuh_acc(vxx, vu, rt) +} + +/// `Vdd32.uw=vmpy(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyuhv(vu, vv) +} + +/// `Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuhv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyuhv_acc(vxx, vu, vv) +} + +/// `Vd32.h=vnavg(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgh(vu, vv) +} + +/// `Vd32.b=vnavg(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgub(vu, vv) +} + +/// `Vd32.w=vnavg(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgw(vu, vv) +} + +/// `Vd32.h=vnormamt(Vu32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnormamth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector { + vnormamth(vu) +} + +/// `Vd32.w=vnormamt(Vu32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnormamtw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector { + vnormamtw(vu) +} + +/// `Vd32=vnot(Vu32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnot))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector { + vnot(vu) +} + +/// `Vd32=vor(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_or(vu, vv) +} + +/// `Vd32.b=vpacke(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackeb(vu, vv) +} + +/// `Vd32.h=vpacke(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackeh(vu, vv) +} + +/// `Vd32.b=vpack(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackhb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackhb_sat(vu, vv) +} + +/// `Vd32.ub=vpack(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackhub_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackhub_sat(vu, vv) +} + +/// `Vd32.b=vpacko(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackob(vu, vv) +} + +/// `Vd32.h=vpacko(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackoh(vu, vv) +} + +/// `Vd32.h=vpack(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackwh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackwh_sat(vu, vv) +} + +/// `Vd32.uh=vpack(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackwuh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackwuh_sat(vu, vv) +} + +/// `Vd32.h=vpopcount(Vu32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpopcounth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector { + vpopcounth(vu) +} + +/// `Vd32=vrdelta(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrdelta))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrdelta(vu, vv) +} + +/// `Vd32.w=vrmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { + vrmpybus(vu, rt) +} + +/// `Vx32.w+=vrmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vrmpybus_acc(vx, vu, rt) +} + +/// `Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrmpybusi(vuu, rt, iu1) +} + +/// `Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vrmpyacc_wwwubrbi( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrmpybusi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.w=vrmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybusv(vu, vv) +} + +/// `Vx32.w+=vrmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybusv_acc(vx, vu, vv) +} + +/// `Vd32.w=vrmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybv(vu, vv) +} + +/// `Vx32.w+=vrmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybv_acc(vx, vu, vv) +} + +/// `Vd32.uw=vrmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector { + vrmpyub(vu, rt) +} + +/// `Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vrmpyub_acc(vx, vu, rt) +} + +/// `Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrmpyubi(vuu, rt, iu1) +} + +/// `Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrmpyubi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.uw=vrmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpyubv(vu, vv) +} + +/// `Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpyubv_acc(vx, vu, vv) +} + +/// `Vd32=vror(Vu32,Rt32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vror))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector { + vror(vu, rt) +} + +/// `Vd32.b=vround(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundhb(vu, vv) +} + +/// `Vd32.ub=vround(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundhub(vu, vv) +} + +/// `Vd32.h=vround(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundwh(vu, vv) +} + +/// `Vd32.uh=vround(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundwuh(vu, vv) +} + +/// `Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrsadubi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrsadubi(vuu, rt, iu1) +} + +/// `Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrsadubi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrsadubi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.ub=vsat(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsathub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsathub(vu, vv) +} + +/// `Vd32.h=vsat(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsatwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatwh(vu, vv) +} + +/// `Vdd32.h=vsxt(Vu32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair { + vsb(vu) +} + +/// `Vdd32.w=vsxt(Vu32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair { + vsh(vu) +} + +/// `Vd32.h=vshuffe(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshufeh(vu, vv) +} + +/// `Vd32.b=vshuff(Vu32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector { + vshuffb(vu) +} + +/// `Vd32.b=vshuffe(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshuffeb(vu, vv) +} + +/// `Vd32.h=vshuff(Vu32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector { + vshuffh(vu) +} + +/// `Vd32.b=vshuffo(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshuffob(vu, vv) +} + +/// `Vdd32=vshuff(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffvdd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vshuffvdd(vu, vv, rt) +} + +/// `Vdd32.b=vshuffoe(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vshufoeb(vu, vv) +} + +/// `Vdd32.h=vshuffoe(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vshufoeh(vu, vv) +} + +/// `Vd32.h=vshuffo(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshufoh(vu, vv) +} + +/// `Vd32.b=vsub(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubb(vu, vv) +} + +/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubb_dv(vuu, vvv) +} + +/// `Vd32.h=vsub(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubh(vu, vv) +} + +/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubh_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubh_dv(vuu, vvv) +} + +/// `Vd32.h=vsub(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubhsat(vu, vv) +} + +/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vsub(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsubhw(vu, vv) +} + +/// `Vdd32.h=vsub(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsububh(vu, vv) +} + +/// `Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsububsat(vu, vv) +} + +/// `Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsububsat_dv(vuu, vvv) +} + +/// `Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubuhsat(vu, vv) +} + +/// `Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubuhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vsub(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsubuhw(vu, vv) +} + +/// `Vd32.w=vsub(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_sub(vu, vv) +} + +/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubw_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubw_dv(vuu, vvv) +} + +/// `Vd32.w=vsub(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubwsat(vu, vv) +} + +/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubwsat_dv(vuu, vvv) +} + +/// `Vdd32.h=vtmpy(Vuu32.b,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpyb(vuu, rt) +} + +/// `Vxx32.h+=vtmpy(Vuu32.b,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpyacc_whwbrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpyb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vtmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpybus(vuu, rt) +} + +/// `Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpyacc_whwubrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpybus_acc(vxx, vuu, rt) +} + +/// `Vdd32.w=vtmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpyhb(vuu, rt) +} + +/// `Vxx32.w+=vtmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vtmpyacc_wwwhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpyhb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vunpack(Vu32.b)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair { + vunpackb(vu) +} + +/// `Vdd32.w=vunpack(Vu32.h)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair { + vunpackh(vu) +} + +/// `Vxx32.h|=vunpacko(Vu32.b)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { + vunpackob(vxx, vu) +} + +/// `Vxx32.w|=vunpacko(Vu32.h)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { + vunpackoh(vxx, vu) +} + +/// `Vdd32.uh=vunpack(Vu32.ub)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair { + vunpackub(vu) +} + +/// `Vdd32.uw=vunpack(Vu32.uh)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair { + vunpackuh(vu) +} + +/// `Vd32=vxor(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vxor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_xor(vu, vv) +} + +/// `Vdd32.uh=vzxt(Vu32.ub)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vzb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair { + vzb(vu) +} + +/// `Vdd32.uw=vzxt(Vu32.uh)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vzh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair { + vzh(vu) +} + +/// `Vd32.b=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(lvsplatb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector { + lvsplatb(rt) +} + +/// `Vd32.h=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(lvsplath))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector { + lvsplath(rt) +} + +/// `Vd32.b=vadd(Vu32.b,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddbsat(vu, vv) +} + +/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddbsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddbsat_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(vclb(Vu32.h),Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddclbh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddclbh(vu, vv) +} + +/// `Vd32.w=vadd(vclb(Vu32.w),Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddclbw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddclbw(vu, vv) +} + +/// `Vxx32.w+=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddhw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vaddacc_wwvhvh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vaddhw_acc(vxx, vu, vv) +} + +/// `Vxx32.h+=vadd(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddubh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vaddacc_whvubvub( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vaddubh_acc(vxx, vu, vv) +} + +/// `Vd32.ub=vadd(Vu32.ub,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddububb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddububb_sat(vu, vv) +} + +/// `Vxx32.w+=vadd(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduhw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vaddacc_wwvuhvuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vadduhw_acc(vxx, vu, vv) +} + +/// `Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadduwsat(vu, vv) +} + +/// `Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vadduwsat_dv(vuu, vvv) +} + +/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasrhbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhbsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasruwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruwuhrndsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasrwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwuhrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vlsr(Vu32.ub,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlsrb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector { + vlsrb(vu, rt) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvb_nm))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlutvvb_nm(vu, vv, rt) +} + +/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvb_oracci))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32or_vbvbvbi( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, + iu3: i32, +) -> HvxVector { + vlutvvb_oracci(vx, vu, vv, iu3) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + vlutvvbi(vu, vv, iu3) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwh_nm))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vlutvwh_nm(vu, vv, rt) +} + +/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwh_oracci))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16or_whvbvhi( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, + iu3: i32, +) -> HvxVectorPair { + vlutvwh_oracci(vxx, vu, vv, iu3) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwhi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { + vlutvwhi(vu, vv, iu3) +} + +/// `Vd32.b=vmax(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmaxb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxb(vu, vv) +} + +/// `Vd32.b=vmin(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vminb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminb(vu, vv) +} + +/// `Vdd32.w=vmpa(Vuu32.uh,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpauhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpauhb(vuu, rt) +} + +/// `Vxx32.w+=vmpa(Vuu32.uh,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpauhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpaacc_wwwuhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpauhb_acc(vxx, vuu, rt) +} + +/// `Vdd32=vmpye(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyewuh_64))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyewuh_64(vu, vv) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyiwub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwub(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyiwub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwub_acc(vx, vu, rt) +} + +/// `Vxx32+=vmpyo(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyowh_64_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vmpyoacc_wvwvh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyowh_64_acc(vxx, vu, vv) +} + +/// `Vd32.ub=vround(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vrounduhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrounduhub(vu, vv) +} + +/// `Vd32.uh=vround(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vrounduwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrounduwuh(vu, vv) +} + +/// `Vd32.uh=vsat(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsatuwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatuwuh(vu, vv) +} + +/// `Vd32.b=vsub(Vu32.b,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubbsat(vu, vv) +} + +/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubbsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubbsat_dv(vuu, vvv) +} + +/// `Vd32.ub=vsub(Vu32.ub,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubububb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubububb_sat(vu, vv) +} + +/// `Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubuwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubuwsat(vu, vv) +} + +/// `Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubuwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubuwsat_dv(vuu, vvv) +} + +/// `Vd32.b=vabs(Vu32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vabsb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector { + vabsb(vu) +} + +/// `Vd32.b=vabs(Vu32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vabsb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector { + vabsb_sat(vu) +} + +/// `Vx32.h+=vasl(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vaslh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vaslh_acc(vx, vu, rt) +} + +/// `Vx32.h+=vasr(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasrh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vasrh_acc(vx, vu, rt) +} + +/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruhubrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruhubsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruwuhsat(vu, vv, rt) +} + +/// `Vd32.b=vavg(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavgb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgb(vu, vv) +} + +/// `Vd32.b=vavg(Vu32.b,Vv32.b):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavgbrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgbrnd(vu, vv) +} + +/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavguw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguw(vu, vv) +} + +/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavguwrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguwrnd(vu, vv) +} + +/// `Vdd32=#0` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vdd0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vzero() -> HvxVectorPair { + vdd0() +} + +/// `vtmp.h=vgather(Rt32,Mu2,Vv32.h).h` +/// +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { + vgathermh(rs, rt, mu, vv) +} + +/// `vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h` +/// +/// Instruction Type: CVI_GATHER_DV +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { + vgathermhw(rs, rt, mu, vvv) +} + +/// `vtmp.w=vgather(Rt32,Mu2,Vv32.w).w` +/// +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { + vgathermw(rs, rt, mu, vv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpabuu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpabuu(vuu, rt) +} + +/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpabuu_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpaacc_whwubrub( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpabuu_acc(vxx, vuu, rt) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyh_acc(vxx, vu, rt) +} + +/// `Vd32.uw=vmpye(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyuhe))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector { + vmpyuhe(vu, rt) +} + +/// `Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyuhe_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyuhe_acc(vx, vu, rt) +} + +/// `Vd32.b=vnavg(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vnavgb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgb(vu, vv) +} + +/// `vscatter(Rt32,Mu2,Vv32.h).h=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermh(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.h).h+=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermh_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermh_add(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vvv32.w).h=Vw32` +/// +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { + vscattermhw(rt, mu, vvv, vw) +} + +/// `vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32` +/// +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermhw_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { + vscattermhw_add(rt, mu, vvv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.w).w=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermw(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.w).w+=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermw_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermw_add(rt, mu, vv, vw) +} + +/// `Vxx32.w=vasrinto(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vasr_into))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vasrinto_wwvwvw( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vasr_into(vxx, vu, vv) +} + +/// `Vd32.uw=vrotr(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vrotr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrotr(vu, vv) +} + +/// `Vd32.w=vsatdw(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vsatdw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatdw(vu, vv) +} + +/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyhubs10))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpy_wubwbi_h( + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyhubs10(vuu, vvv, iu2) +} + +/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyhubs10_vxx(vxx, vuu, vvv, iu2) +} + +/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyvubs10))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpy_wubwbi_v( + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyvubs10(vuu, vvv, iu2) +} + +/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyvubs10_vxx(vxx, vuu, vvv, iu2) +} + +/// `Vd32.hf=vabs(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vabs_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector { + vabs_hf(vu) +} + +/// `Vd32.sf=vabs(Vu32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vabs_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector { + vabs_sf(vu) +} + +/// `Vd32.qf16=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_hf(vu, vv) +} + +/// `Vd32.hf=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_hf_hf(vu, vv) +} + +/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf16(vu, vv) +} + +/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf16_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf16_mix(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf32(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf32_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf32_mix(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_sf(vu, vv) +} + +/// `Vdd32.sf=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vadd_sf_hf(vu, vv) +} + +/// `Vd32.sf=vadd(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_sf_sf(vu, vv) +} + +/// `Vd32.w=vfmv(Vu32.w)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vassign_fp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector { + vassign_fp(vu) +} + +/// `Vd32.hf=Vu32.qf16` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_hf_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector { + vconv_hf_qf16(vu) +} + +/// `Vd32.hf=Vuu32.qf32` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_hf_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector { + vconv_hf_qf32(vuu) +} + +/// `Vd32.sf=Vu32.qf32` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_sf_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector { + vconv_sf_qf32(vu) +} + +/// `Vd32.b=vcvt(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_b_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_b_hf(vu, vv) +} + +/// `Vd32.h=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_h_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector { + vcvt_h_hf(vu) +} + +/// `Vdd32.hf=vcvt(Vu32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_b))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_b(vu) +} + +/// `Vd32.hf=vcvt(Vu32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector { + vcvt_hf_h(vu) +} + +/// `Vd32.hf=vcvt(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_hf_sf(vu, vv) +} + +/// `Vdd32.hf=vcvt(Vu32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_ub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_ub(vu) +} + +/// `Vd32.hf=vcvt(Vu32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_uh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector { + vcvt_hf_uh(vu) +} + +/// `Vdd32.sf=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair { + vcvt_sf_hf(vu) +} + +/// `Vd32.ub=vcvt(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_ub_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_ub_hf(vu, vv) +} + +/// `Vd32.uh=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_uh_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector { + vcvt_uh_hf(vu) +} + +/// `Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vdmpy_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpy_sf_hf(vu, vv) +} + +/// `Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpy_sf_hf_acc(vx, vu, vv) +} + +/// `Vd32.hf=vfmax(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmax_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_hf(vu, vv) +} + +/// `Vd32.sf=vfmax(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmax_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_sf(vu, vv) +} + +/// `Vd32.hf=vfmin(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmin_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_hf(vu, vv) +} + +/// `Vd32.sf=vfmin(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmin_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_sf(vu, vv) +} + +/// `Vd32.hf=vfneg(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfneg_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector { + vfneg_hf(vu) +} + +/// `Vd32.sf=vfneg(Vu32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfneg_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector { + vfneg_sf(vu) +} + +/// `Vd32.hf=vmax(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmax_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmax_hf(vu, vv) +} + +/// `Vd32.sf=vmax(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmax_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmax_sf(vu, vv) +} + +/// `Vd32.hf=vmin(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmin_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmin_hf(vu, vv) +} + +/// `Vd32.sf=vmin(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmin_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmin_sf(vu, vv) +} + +/// `Vd32.hf=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_hf_hf(vu, vv) +} + +/// `Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_hf_hf_acc(vx, vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16(vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16_hf(vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16_mix_hf(vu, vv) +} + +/// `Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf32(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_hf(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_mix_hf(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_qf16(vu, vv) +} + +/// `Vd32.qf32=vmpy(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf32_sf(vu, vv) +} + +/// `Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_sf_hf(vu, vv) +} + +/// `Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpy_sf_hf_acc(vxx, vu, vv) +} + +/// `Vd32.sf=vmpy(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_sf_sf(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_hf(vu, vv) +} + +/// `Vd32.hf=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_hf_hf(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf16(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf16_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf16_mix(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf32(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf32_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf32_mix(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_sf(vu, vv) +} + +/// `Vdd32.sf=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsub_sf_hf(vu, vv) +} + +/// `Vd32.sf=vsub(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_sf_sf(vu, vv) +} + +/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvuhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvuhubrndsat(vuu, vv) +} + +/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvuhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvuhubsat(vuu, vv) +} + +/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvwuhrndsat(vuu, vv) +} + +/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvwuhsat(vuu, vv) +} + +/// `Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vmpyuhvs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyuhvs(vu, vv) +} + +/// `Vd32.h=Vu32.hf` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_h_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector { + vconv_h_hf(vu) +} + +/// `Vd32.hf=Vu32.h` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_hf_h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector { + vconv_hf_h(vu) +} + +/// `Vd32.sf=Vu32.w` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_sf_w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector { + vconv_sf_w(vu) +} + +/// `Vd32.w=Vu32.sf` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_w_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector { + vconv_w_sf(vu) +} + +/// `Vd32=vgetqfext(Vu32.x,Rt32)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(get_qfext))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { + get_qfext(vu, rt) +} + +/// `Vd32.x=vsetqfext(Vu32,Rt32)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(set_qfext))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { + set_qfext(vu, rt) +} + +/// `Vd32.f8=vabs(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vabs_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector { + vabs_f8(vu) +} + +/// `Vdd32.hf=vcvt2(Vu32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt2_hf_b))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair { + vcvt2_hf_b(vu) +} + +/// `Vdd32.hf=vcvt2(Vu32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt2_hf_ub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair { + vcvt2_hf_ub(vu) +} + +/// `Vdd32.hf=vcvt(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt_hf_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_f8(vu) +} + +/// `Vd32.f8=vfmax(Vu32.f8,Vv32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfmax_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_f8(vu, vv) +} + +/// `Vd32.f8=vfmin(Vu32.f8,Vv32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfmin_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_f8(vu, vv) +} + +/// `Vd32.f8=vfneg(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfneg_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector { + vfneg_f8(vu) +} + +/// `Qd4=and(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_and( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=and(Qs4,!Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_and_n( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=not(Qs4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_not(vandvrt( + core::mem::transmute::(qs), + -1, + )), + -1, + )) +} + +/// `Qd4=or(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_or( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=or(Qs4,!Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_or_n( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=vsetq(Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(pred_scalar2(rt), -1)) +} + +/// `Qd4=xor(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_xor( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `if (!Qv4) vmem(Rt32+#s4)=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nqpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (!Qv4) vmem(Rt32+#s4):nt=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nt_nqpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (Qv4) vmem(Rt32+#s4):nt=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nt_qpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (Qv4) vmem(Rt32+#s4)=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_qpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (!Qv4) Vx32.b+=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddbnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.b+=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddbq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.h+=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddhnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.h+=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddhq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.w+=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddwnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.w+=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddwq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `Vd32=vand(Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector { + vandvrt(core::mem::transmute::(qu), rt) +} + +/// `Vx32|=vand(Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { + vandvrt_acc(vx, core::mem::transmute::(qu), rt) +} + +/// `Qd4=vand(Vu32,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vu, rt)) +} + +/// `Qx4|=vand(Vu32,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt_acc( + core::mem::transmute::(qx), + vu, + rt, + )) +} + +/// `Qd4=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqb(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqand_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqor_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqxacc_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqh(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqand_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqor_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqxacc_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqand_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqor_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqxacc_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtb(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgth(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtub(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvubvub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvubvub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvubvub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtuh(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvuhvuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvuhvuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtuw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvuwvuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvuwvuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Vd32=vmux(Qt4,Vu32,Vv32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmux( + vandvrt(core::mem::transmute::(qt), -1), + vu, + vv, + ) +} + +/// `if (!Qv4) Vx32.b-=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubbnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.b-=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubbq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.h-=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubhnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.h-=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubhq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.w-=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubwnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.w-=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubwq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `Vdd32=vswap(Qt4,Vu32,Vv32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vswap( + vandvrt(core::mem::transmute::(qt), -1), + vu, + vv, + ) +} + +/// `Qd4=vsetq2(Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(pred_scalar2v2(rt), -1)) +} + +/// `Qd4.b=vshuffe(Qs4.h,Qt4.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + shuffeqh( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4.h=vshuffe(Qs4.w,Qt4.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + shuffeqw( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Vd32=vand(!Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector { + vandnqrt( + vandvrt(core::mem::transmute::(qu), -1), + rt, + ) +} + +/// `Vx32|=vand(!Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { + vandnqrt_acc( + vx, + vandvrt(core::mem::transmute::(qu), -1), + rt, + ) +} + +/// `Vd32=vand(!Qv4,Vu32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { + vandvnqv( + vandvrt(core::mem::transmute::(qv), -1), + vu, + ) +} + +/// `Vd32=vand(Qv4,Vu32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { + vandvqv( + vandvrt(core::mem::transmute::(qv), -1), + vu, + ) +} + +/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_aqrmvh( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, +) { + vgathermhq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + ) +} + +/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER_DV +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_aqrmww( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vvv: HvxVectorPair, +) { + vgathermhwq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vvv, + ) +} + +/// `if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_aqrmvw( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, +) { + vgathermwq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + ) +} + +/// `Vd32.b=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector { + vprefixqb(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `Vd32.h=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector { + vprefixqh(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `Vd32.w=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector { + vprefixqw(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_qrmvhv( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, + vw: HvxVector, +) { + vscattermhq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + vw, + ) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_qrmwwv( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vvv: HvxVectorPair, + vw: HvxVector, +) { + vscattermhwq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vvv, + vw, + ) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_qrmvwv( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, + vw: HvxVector, +) { + vscattermwq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + vw, + ) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vwvwq_carry_sat( + vu: HvxVector, + vv: HvxVector, + qs: HvxVectorPred, +) -> HvxVector { + vaddcarrysat( + vu, + vv, + vandvrt(core::mem::transmute::(qs), -1), + ) +} + +/// `Qd4=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgthf(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvhfvhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvhfvhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtsf(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvsfvsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvsfvsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvsfvsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} diff --git a/stdarch/crates/core_arch/src/hexagon/v64.rs b/stdarch/crates/core_arch/src/hexagon/v64.rs new file mode 100644 index 0000000000000..023a8711d21f3 --- /dev/null +++ b/stdarch/crates/core_arch/src/hexagon/v64.rs @@ -0,0 +1,7489 @@ +//! Hexagon HVX 64-byte vector mode intrinsics +//! +//! This module provides intrinsics for the Hexagon Vector Extensions (HVX) +//! in 64-byte vector mode (512-bit vectors). +//! +//! HVX is a wide vector extension designed for high-performance signal processing. +//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61) +//! +//! ## Vector Types +//! +//! In 64-byte mode: +//! - `HvxVector` is 512 bits (64 bytes) containing 16 x 32-bit values +//! - `HvxVectorPair` is 1024 bits (128 bytes) +//! - `HvxVectorPred` is 512 bits (64 bytes) for predicate operations +//! +//! To use this module, compile with `-C target-feature=+hvx-length64b`. +//! +//! ## Architecture Versions +//! +//! Different intrinsics require different HVX architecture versions. Use the +//! appropriate target feature to enable the required version: +//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations) +//! - HVX v62: `-C target-feature=+hvxv62` +//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support) +//! - HVX v66: `-C target-feature=+hvxv66` +//! - HVX v68: `-C target-feature=+hvxv68` +//! - HVX v69: `-C target-feature=+hvxv69` +//! - HVX v73: `-C target-feature=+hvxv73` +//! - HVX v79: `-C target-feature=+hvxv79` +//! +//! Each version includes all features from previous versions. + +#![allow(non_camel_case_types)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use crate::intrinsics::simd::{simd_add, simd_and, simd_or, simd_sub, simd_xor}; + +// HVX type definitions for 64-byte vector mode +types! { + #![unstable(feature = "stdarch_hexagon", issue = "151523")] + + /// HVX vector type (512 bits / 64 bytes) + /// + /// This type represents a single HVX vector register containing 16 x 32-bit values. + pub struct HvxVector(16 x i32); + + /// HVX vector pair type (1024 bits / 128 bytes) + /// + /// This type represents a pair of HVX vector registers, often used for + /// operations that produce double-width results. + pub struct HvxVectorPair(32 x i32); + + /// HVX vector predicate type (512 bits / 64 bytes) + /// + /// This type represents a predicate vector used for conditional operations. + /// Each bit corresponds to a lane in the vector. + pub struct HvxVectorPred(16 x i32); +} + +// LLVM intrinsic declarations for 64-byte vector mode +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.hexagon.V6.extractw"] + fn extractw(_: HvxVector, _: i32) -> i32; + #[link_name = "llvm.hexagon.V6.get.qfext"] + fn get_qfext(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.hi"] + fn hi(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lo"] + fn lo(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplatb"] + fn lvsplatb(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplath"] + fn lvsplath(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplatw"] + fn lvsplatw(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.and"] + fn pred_and(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.and.n"] + fn pred_and_n(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.not"] + fn pred_not(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.or"] + fn pred_or(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.or.n"] + fn pred_or_n(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.scalar2"] + fn pred_scalar2(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.scalar2v2"] + fn pred_scalar2v2(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.xor"] + fn pred_xor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.set.qfext"] + fn set_qfext(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.shuffeqh"] + fn shuffeqh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.shuffeqw"] + fn shuffeqw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.v6mpyhubs10"] + fn v6mpyhubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyhubs10.vxx"] + fn v6mpyhubs10_vxx( + _: HvxVectorPair, + _: HvxVectorPair, + _: HvxVectorPair, + _: i32, + ) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyvubs10"] + fn v6mpyvubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyvubs10.vxx"] + fn v6mpyvubs10_vxx( + _: HvxVectorPair, + _: HvxVectorPair, + _: HvxVectorPair, + _: i32, + ) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vS32b.nqpred.ai"] + fn vS32b_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.nt.nqpred.ai"] + fn vS32b_nt_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.nt.qpred.ai"] + fn vS32b_nt_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.qpred.ai"] + fn vS32b_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vabs.f8"] + fn vabs_f8(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabs.hf"] + fn vabs_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabs.sf"] + fn vabs_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsb"] + fn vabsb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsb.sat"] + fn vabsb_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffh"] + fn vabsdiffh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffub"] + fn vabsdiffub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffuh"] + fn vabsdiffuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffw"] + fn vabsdiffw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsh"] + fn vabsh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsh.sat"] + fn vabsh_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsw"] + fn vabsw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsw.sat"] + fn vabsw_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.hf"] + fn vadd_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.hf.hf"] + fn vadd_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf16"] + fn vadd_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf16.mix"] + fn vadd_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf32"] + fn vadd_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf32.mix"] + fn vadd_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.sf"] + fn vadd_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.sf.hf"] + fn vadd_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadd.sf.sf"] + fn vadd_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddb"] + fn vaddb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddb.dv"] + fn vaddb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddbnq"] + fn vaddbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbq"] + fn vaddbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbsat"] + fn vaddbsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbsat.dv"] + fn vaddbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddcarrysat"] + fn vaddcarrysat(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddclbh"] + fn vaddclbh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddclbw"] + fn vaddclbw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddh"] + fn vaddh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddh.dv"] + fn vaddh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhnq"] + fn vaddhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhq"] + fn vaddhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhsat"] + fn vaddhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhsat.dv"] + fn vaddhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhw"] + fn vaddhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhw.acc"] + fn vaddhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubh"] + fn vaddubh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubh.acc"] + fn vaddubh_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubsat"] + fn vaddubsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddubsat.dv"] + fn vaddubsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddububb.sat"] + fn vaddububb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduhsat"] + fn vadduhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduhsat.dv"] + fn vadduhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduhw"] + fn vadduhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduhw.acc"] + fn vadduhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduwsat"] + fn vadduwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduwsat.dv"] + fn vadduwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddw"] + fn vaddw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddw.dv"] + fn vaddw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddwnq"] + fn vaddwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwq"] + fn vaddwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwsat"] + fn vaddwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwsat.dv"] + fn vaddwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.valignb"] + fn valignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.valignbi"] + fn valignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vand"] + fn vand(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandnqrt"] + fn vandnqrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandnqrt.acc"] + fn vandnqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandqrt"] + fn vandqrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandqrt.acc"] + fn vandqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvnqv"] + fn vandvnqv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvqv"] + fn vandvqv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvrt"] + fn vandvrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvrt.acc"] + fn vandvrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslh"] + fn vaslh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslh.acc"] + fn vaslh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslhv"] + fn vaslhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslw"] + fn vaslw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslw.acc"] + fn vaslw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslwv"] + fn vaslwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasr.into"] + fn vasr_into(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vasrh"] + fn vasrh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrh.acc"] + fn vasrh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhbrndsat"] + fn vasrhbrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhbsat"] + fn vasrhbsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhubrndsat"] + fn vasrhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhubsat"] + fn vasrhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhv"] + fn vasrhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruhubrndsat"] + fn vasruhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruhubsat"] + fn vasruhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruwuhrndsat"] + fn vasruwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruwuhsat"] + fn vasruwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvuhubrndsat"] + fn vasrvuhubrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvuhubsat"] + fn vasrvuhubsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvwuhrndsat"] + fn vasrvwuhrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvwuhsat"] + fn vasrvwuhsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrw"] + fn vasrw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrw.acc"] + fn vasrw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwh"] + fn vasrwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwhrndsat"] + fn vasrwhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwhsat"] + fn vasrwhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwuhrndsat"] + fn vasrwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwuhsat"] + fn vasrwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwv"] + fn vasrwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassign"] + fn vassign(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassign.fp"] + fn vassign_fp(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassignp"] + fn vassignp(_: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vavgb"] + fn vavgb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgbrnd"] + fn vavgbrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgh"] + fn vavgh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavghrnd"] + fn vavghrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgub"] + fn vavgub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgubrnd"] + fn vavgubrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguh"] + fn vavguh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguhrnd"] + fn vavguhrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguw"] + fn vavguw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguwrnd"] + fn vavguwrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgw"] + fn vavgw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgwrnd"] + fn vavgwrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcl0h"] + fn vcl0h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcl0w"] + fn vcl0w(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcombine"] + fn vcombine(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vconv.h.hf"] + fn vconv_h_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.h"] + fn vconv_hf_h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.qf16"] + fn vconv_hf_qf16(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.qf32"] + fn vconv_hf_qf32(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.sf.qf32"] + fn vconv_sf_qf32(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.sf.w"] + fn vconv_sf_w(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.w.sf"] + fn vconv_w_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt2.hf.b"] + fn vcvt2_hf_b(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt2.hf.ub"] + fn vcvt2_hf_ub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.b.hf"] + fn vcvt_b_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.h.hf"] + fn vcvt_h_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.b"] + fn vcvt_hf_b(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.f8"] + fn vcvt_hf_f8(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.h"] + fn vcvt_hf_h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.sf"] + fn vcvt_hf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.ub"] + fn vcvt_hf_ub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.uh"] + fn vcvt_hf_uh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.sf.hf"] + fn vcvt_sf_hf(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.ub.hf"] + fn vcvt_ub_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.uh.hf"] + fn vcvt_uh_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vd0"] + fn vd0() -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdd0"] + fn vdd0() -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdealb"] + fn vdealb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealb4w"] + fn vdealb4w(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealh"] + fn vdealh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealvdd"] + fn vdealvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdelta"] + fn vdelta(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf"] + fn vdmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.acc"] + fn vdmpy_sf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus"] + fn vdmpybus(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.acc"] + fn vdmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.dv"] + fn vdmpybus_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpybus.dv.acc"] + fn vdmpybus_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhb"] + fn vdmpyhb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhb.acc"] + fn vdmpyhb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhb.dv"] + fn vdmpyhb_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.acc"] + fn vdmpyhb_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhisat"] + fn vdmpyhisat(_: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhisat.acc"] + fn vdmpyhisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsat"] + fn vdmpyhsat(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsat.acc"] + fn vdmpyhsat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsuisat"] + fn vdmpyhsuisat(_: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.acc"] + fn vdmpyhsuisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsusat"] + fn vdmpyhsusat(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsusat.acc"] + fn vdmpyhsusat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhvsat"] + fn vdmpyhvsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhvsat.acc"] + fn vdmpyhvsat_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdsaduh"] + fn vdsaduh(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdsaduh.acc"] + fn vdsaduh_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.veqb"] + fn veqb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.and"] + fn veqb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.or"] + fn veqb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.xor"] + fn veqb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh"] + fn veqh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.and"] + fn veqh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.or"] + fn veqh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.xor"] + fn veqh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw"] + fn veqw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.and"] + fn veqw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.or"] + fn veqw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.xor"] + fn veqw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.f8"] + fn vfmax_f8(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.hf"] + fn vfmax_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.sf"] + fn vfmax_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.f8"] + fn vfmin_f8(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.hf"] + fn vfmin_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.sf"] + fn vfmin_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.f8"] + fn vfneg_f8(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.hf"] + fn vfneg_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.sf"] + fn vfneg_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgathermh"] + fn vgathermh(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhq"] + fn vgathermhq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhw"] + fn vgathermhw(_: *mut HvxVector, _: i32, _: i32, _: HvxVectorPair) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhwq"] + fn vgathermhwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVectorPair) -> (); + #[link_name = "llvm.hexagon.V6.vgathermw"] + fn vgathermw(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermwq"] + fn vgathermwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgtb"] + fn vgtb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.and"] + fn vgtb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.or"] + fn vgtb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.xor"] + fn vgtb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth"] + fn vgth(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.and"] + fn vgth_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.or"] + fn vgth_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.xor"] + fn vgth_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf"] + fn vgthf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.and"] + fn vgthf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.or"] + fn vgthf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.xor"] + fn vgthf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf"] + fn vgtsf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.and"] + fn vgtsf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.or"] + fn vgtsf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.xor"] + fn vgtsf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub"] + fn vgtub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.and"] + fn vgtub_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.or"] + fn vgtub_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.xor"] + fn vgtub_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh"] + fn vgtuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.and"] + fn vgtuh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.or"] + fn vgtuh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.xor"] + fn vgtuh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw"] + fn vgtuw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.and"] + fn vgtuw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.or"] + fn vgtuw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.xor"] + fn vgtuw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw"] + fn vgtw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.and"] + fn vgtw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.or"] + fn vgtw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.xor"] + fn vgtw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vinsertwr"] + fn vinsertwr(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlalignb"] + fn vlalignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlalignbi"] + fn vlalignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrb"] + fn vlsrb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrh"] + fn vlsrh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrhv"] + fn vlsrhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrw"] + fn vlsrw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrwv"] + fn vlsrwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb"] + fn vlutvvb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.nm"] + fn vlutvvb_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.oracc"] + fn vlutvvb_oracc(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.oracci"] + fn vlutvvb_oracci(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvbi"] + fn vlutvvbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvwh"] + fn vlutvwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.nm"] + fn vlutvwh_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.oracc"] + fn vlutvwh_oracc(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.oracci"] + fn vlutvwh_oracci(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwhi"] + fn vlutvwhi(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmax.hf"] + fn vmax_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmax.sf"] + fn vmax_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxb"] + fn vmaxb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxh"] + fn vmaxh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxub"] + fn vmaxub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxuh"] + fn vmaxuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxw"] + fn vmaxw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmin.hf"] + fn vmin_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmin.sf"] + fn vmin_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminb"] + fn vminb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminh"] + fn vminh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminub"] + fn vminub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminuh"] + fn vminuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminw"] + fn vminw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpabus"] + fn vmpabus(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabus.acc"] + fn vmpabus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabusv"] + fn vmpabusv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuu"] + fn vmpabuu(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuu.acc"] + fn vmpabuu_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuuv"] + fn vmpabuuv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpahb"] + fn vmpahb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpahb.acc"] + fn vmpahb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpauhb"] + fn vmpauhb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpauhb.acc"] + fn vmpauhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.hf.hf"] + fn vmpy_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.acc"] + fn vmpy_hf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16"] + fn vmpy_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.hf"] + fn vmpy_qf16_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.mix.hf"] + fn vmpy_qf16_mix_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf32"] + fn vmpy_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.hf"] + fn vmpy_qf32_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.mix.hf"] + fn vmpy_qf32_mix_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.qf16"] + fn vmpy_qf32_qf16(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.sf"] + fn vmpy_qf32_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.sf.hf"] + fn vmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.acc"] + fn vmpy_sf_hf_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.sf.sf"] + fn vmpy_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpybus"] + fn vmpybus(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybus.acc"] + fn vmpybus_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybusv"] + fn vmpybusv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybusv.acc"] + fn vmpybusv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybv"] + fn vmpybv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybv.acc"] + fn vmpybv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyewuh"] + fn vmpyewuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyewuh.64"] + fn vmpyewuh_64(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyh"] + fn vmpyh(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyh.acc"] + fn vmpyh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhsat.acc"] + fn vmpyhsat_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhsrs"] + fn vmpyhsrs(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyhss"] + fn vmpyhss(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyhus"] + fn vmpyhus(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhus.acc"] + fn vmpyhus_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhv"] + fn vmpyhv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhv.acc"] + fn vmpyhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhvsrs"] + fn vmpyhvsrs(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyieoh"] + fn vmpyieoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewh.acc"] + fn vmpyiewh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewuh"] + fn vmpyiewuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewuh.acc"] + fn vmpyiewuh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyih"] + fn vmpyih(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyih.acc"] + fn vmpyih_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyihb"] + fn vmpyihb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyihb.acc"] + fn vmpyihb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiowh"] + fn vmpyiowh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwb"] + fn vmpyiwb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwb.acc"] + fn vmpyiwb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwh"] + fn vmpyiwh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwh.acc"] + fn vmpyiwh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwub"] + fn vmpyiwub(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwub.acc"] + fn vmpyiwub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh"] + fn vmpyowh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.64.acc"] + fn vmpyowh_64_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyowh.rnd"] + fn vmpyowh_rnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.sacc"] + fn vmpyowh_rnd_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.sacc"] + fn vmpyowh_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyub"] + fn vmpyub(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyub.acc"] + fn vmpyub_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyubv"] + fn vmpyubv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyubv.acc"] + fn vmpyubv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuh"] + fn vmpyuh(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuh.acc"] + fn vmpyuh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhe"] + fn vmpyuhe(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyuhe.acc"] + fn vmpyuhe_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyuhv"] + fn vmpyuhv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhv.acc"] + fn vmpyuhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhvs"] + fn vmpyuhvs(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmux"] + fn vmux(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgb"] + fn vnavgb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgh"] + fn vnavgh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgub"] + fn vnavgub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgw"] + fn vnavgw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnormamth"] + fn vnormamth(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnormamtw"] + fn vnormamtw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnot"] + fn vnot(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vor"] + fn vor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackeb"] + fn vpackeb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackeh"] + fn vpackeh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackhb.sat"] + fn vpackhb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackhub.sat"] + fn vpackhub_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackob"] + fn vpackob(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackoh"] + fn vpackoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackwh.sat"] + fn vpackwh_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackwuh.sat"] + fn vpackwuh_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpopcounth"] + fn vpopcounth(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqb"] + fn vprefixqb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqh"] + fn vprefixqh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqw"] + fn vprefixqw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrdelta"] + fn vrdelta(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybus"] + fn vrmpybus(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybus.acc"] + fn vrmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybusi"] + fn vrmpybusi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpybusi.acc"] + fn vrmpybusi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpybusv"] + fn vrmpybusv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybusv.acc"] + fn vrmpybusv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybv"] + fn vrmpybv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybv.acc"] + fn vrmpybv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyub"] + fn vrmpyub(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyub.acc"] + fn vrmpyub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyubi"] + fn vrmpyubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpyubi.acc"] + fn vrmpyubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpyubv"] + fn vrmpyubv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyubv.acc"] + fn vrmpyubv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vror"] + fn vror(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrotr"] + fn vrotr(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundhb"] + fn vroundhb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundhub"] + fn vroundhub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrounduhub"] + fn vrounduhub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrounduwuh"] + fn vrounduwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundwh"] + fn vroundwh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundwuh"] + fn vroundwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrsadubi"] + fn vrsadubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrsadubi.acc"] + fn vrsadubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsatdw"] + fn vsatdw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsathub"] + fn vsathub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsatuwuh"] + fn vsatuwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsatwh"] + fn vsatwh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsb"] + fn vsb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vscattermh"] + fn vscattermh(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermh.add"] + fn vscattermh_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhq"] + fn vscattermhq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhw"] + fn vscattermhw(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhw.add"] + fn vscattermhw_add(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhwq"] + fn vscattermhwq(_: HvxVector, _: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermw"] + fn vscattermw(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermw.add"] + fn vscattermw_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermwq"] + fn vscattermwq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vsh"] + fn vsh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufeh"] + fn vshufeh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffb"] + fn vshuffb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffeb"] + fn vshuffeb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffh"] + fn vshuffh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffob"] + fn vshuffob(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffvdd"] + fn vshuffvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoeb"] + fn vshufoeb(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoeh"] + fn vshufoeh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoh"] + fn vshufoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.hf"] + fn vsub_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.hf.hf"] + fn vsub_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf16"] + fn vsub_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf16.mix"] + fn vsub_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf32"] + fn vsub_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf32.mix"] + fn vsub_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.sf"] + fn vsub_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.sf.hf"] + fn vsub_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsub.sf.sf"] + fn vsub_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubb"] + fn vsubb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubb.dv"] + fn vsubb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubbnq"] + fn vsubbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbq"] + fn vsubbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbsat"] + fn vsubbsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbsat.dv"] + fn vsubbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubh"] + fn vsubh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubh.dv"] + fn vsubh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubhnq"] + fn vsubhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhq"] + fn vsubhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhsat"] + fn vsubhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhsat.dv"] + fn vsubhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubhw"] + fn vsubhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsububh"] + fn vsububh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsububsat"] + fn vsububsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsububsat.dv"] + fn vsububsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubububb.sat"] + fn vsubububb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuhsat"] + fn vsubuhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuhsat.dv"] + fn vsubuhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubuhw"] + fn vsubuhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubuwsat"] + fn vsubuwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuwsat.dv"] + fn vsubuwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubw"] + fn vsubw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubw.dv"] + fn vsubw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubwnq"] + fn vsubwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwq"] + fn vsubwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwsat"] + fn vsubwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwsat.dv"] + fn vsubwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vswap"] + fn vswap(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyb"] + fn vtmpyb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyb.acc"] + fn vtmpyb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpybus"] + fn vtmpybus(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpybus.acc"] + fn vtmpybus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyhb"] + fn vtmpyhb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyhb.acc"] + fn vtmpyhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackb"] + fn vunpackb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackh"] + fn vunpackh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackob"] + fn vunpackob(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackoh"] + fn vunpackoh(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackub"] + fn vunpackub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackuh"] + fn vunpackuh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vxor"] + fn vxor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vzb"] + fn vzb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vzh"] + fn vzh(_: HvxVector) -> HvxVectorPair; +} + +/// `Rd32=vextract(Vu32,Rs32)` +/// +/// Instruction Type: LD +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(extractw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 { + extractw(vu, rs) +} + +/// `Vd32=hi(Vss32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(hi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector { + hi(vss) +} + +/// `Vd32=lo(Vss32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(lo))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector { + lo(vss) +} + +/// `Vd32=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(lvsplatw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector { + lvsplatw(rt) +} + +/// `Vd32.uh=vabsdiff(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffh(vu, vv) +} + +/// `Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffub(vu, vv) +} + +/// `Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffuh(vu, vv) +} + +/// `Vd32.uw=vabsdiff(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffw(vu, vv) +} + +/// `Vd32.h=vabs(Vu32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector { + vabsh(vu) +} + +/// `Vd32.h=vabs(Vu32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector { + vabsh_sat(vu) +} + +/// `Vd32.w=vabs(Vu32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector { + vabsw(vu) +} + +/// `Vd32.w=vabs(Vu32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsw_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector { + vabsw_sat(vu) +} + +/// `Vd32.b=vadd(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddb(vu, vv) +} + +/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddb_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddh(vu, vv) +} + +/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddh_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddh_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddhsat(vu, vv) +} + +/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vaddhw(vu, vv) +} + +/// `Vdd32.h=vadd(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vaddubh(vu, vv) +} + +/// `Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddubsat(vu, vv) +} + +/// `Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddubsat_dv(vuu, vvv) +} + +/// `Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadduhsat(vu, vv) +} + +/// `Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vadduhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vadd(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vadduhw(vu, vv) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_add(vu, vv) +} + +/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddw_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddw_dv(vuu, vvv) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddwsat(vu, vv) +} + +/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddwsat_dv(vuu, vvv) +} + +/// `Vd32=valign(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(valignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + valignb(vu, vv, rt) +} + +/// `Vd32=valign(Vu32,Vv32,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(valignbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + valignbi(vu, vv, iu3) +} + +/// `Vd32=vand(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vand))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_and(vu, vv) +} + +/// `Vd32.h=vasl(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector { + vaslh(vu, rt) +} + +/// `Vd32.h=vasl(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaslhv(vu, vv) +} + +/// `Vd32.w=vasl(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector { + vaslw(vu, rt) +} + +/// `Vx32.w+=vasl(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vaslw_acc(vx, vu, rt) +} + +/// `Vd32.w=vasl(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaslwv(vu, vv) +} + +/// `Vd32.h=vasr(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector { + vasrh(vu, rt) +} + +/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhbrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhbrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhubrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhubsat(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vasrhv(vu, vv) +} + +/// `Vd32.w=vasr(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector { + vasrw(vu, rt) +} + +/// `Vx32.w+=vasr(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vasrw_acc(vx, vu, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwh(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwhrndsat(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwhsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwuhsat(vu, vv, rt) +} + +/// `Vd32.w=vasr(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vasrwv(vu, vv) +} + +/// `Vd32=Vu32` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vassign))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector { + vassign(vu) +} + +/// `Vdd32=Vuu32` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vassignp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair { + vassignp(vuu) +} + +/// `Vd32.h=vavg(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgh(vu, vv) +} + +/// `Vd32.h=vavg(Vu32.h,Vv32.h):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavghrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavghrnd(vu, vv) +} + +/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgub(vu, vv) +} + +/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgubrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgubrnd(vu, vv) +} + +/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavguh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguh(vu, vv) +} + +/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavguhrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguhrnd(vu, vv) +} + +/// `Vd32.w=vavg(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgw(vu, vv) +} + +/// `Vd32.w=vavg(Vu32.w,Vv32.w):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgwrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgwrnd(vu, vv) +} + +/// `Vd32.uh=vcl0(Vu32.uh)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcl0h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector { + vcl0h(vu) +} + +/// `Vd32.uw=vcl0(Vu32.uw)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcl0w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector { + vcl0w(vu) +} + +/// `Vdd32=vcombine(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcombine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vcombine(vu, vv) +} + +/// `Vd32=#0` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vd0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vzero() -> HvxVector { + vd0() +} + +/// `Vd32.b=vdeal(Vu32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector { + vdealb(vu) +} + +/// `Vd32.b=vdeale(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealb4w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdealb4w(vu, vv) +} + +/// `Vd32.h=vdeal(Vu32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector { + vdealh(vu) +} + +/// `Vdd32=vdeal(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealvdd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vdealvdd(vu, vv, rt) +} + +/// `Vd32=vdelta(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdelta))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdelta(vu, vv) +} + +/// `Vd32.h=vdmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { + vdmpybus(vu, rt) +} + +/// `Vx32.h+=vdmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpybus_acc(vx, vu, rt) +} + +/// `Vdd32.h=vdmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdmpybus_dv(vuu, rt) +} + +/// `Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_dv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vdmpyacc_whwubrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdmpybus_dv_acc(vxx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhb(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhb_acc(vx, vu, rt) +} + +/// `Vdd32.w=vdmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdmpyhb_dv(vuu, rt) +} + +/// `Vxx32.w+=vdmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vdmpyacc_wwwhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdmpyhb_dv_acc(vxx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhisat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhisat(vuu, rt) +} + +/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhisat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhisat_acc(vx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsat(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsat_acc(vx, vu, rt) +} + +/// `Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsuisat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhsuisat(vuu, rt) +} + +/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhsuisat_acc(vx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsusat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsusat(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsusat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsusat_acc(vx, vu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhvsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpyhvsat(vu, vv) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhvsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpyhvsat_acc(vx, vu, vv) +} + +/// `Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdsaduh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdsaduh(vuu, rt) +} + +/// `Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdsaduh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdsaduh_acc(vxx, vuu, rt) +} + +/// `Vx32.w=vinsert(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vinsertwr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector { + vinsertwr(vx, rt) +} + +/// `Vd32=vlalign(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlalignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlalignb(vu, vv, rt) +} + +/// `Vd32=vlalign(Vu32,Vv32,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlalignbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + vlalignbi(vu, vv, iu3) +} + +/// `Vd32.uh=vlsr(Vu32.uh,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector { + vlsrh(vu, rt) +} + +/// `Vd32.h=vlsr(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vlsrhv(vu, vv) +} + +/// `Vd32.uw=vlsr(Vu32.uw,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector { + vlsrw(vu, rt) +} + +/// `Vd32.w=vlsr(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vlsrwv(vu, vv) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvvb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlutvvb(vu, vv, rt) +} + +/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvvb_oracc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32or_vbvbvbr( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, + rt: i32, +) -> HvxVector { + vlutvvb_oracc(vx, vu, vv, rt) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vlutvwh(vu, vv, rt) +} + +/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvwh_oracc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16or_whvbvhr( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, + rt: i32, +) -> HvxVectorPair { + vlutvwh_oracc(vxx, vu, vv, rt) +} + +/// `Vd32.h=vmax(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxh(vu, vv) +} + +/// `Vd32.ub=vmax(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxub(vu, vv) +} + +/// `Vd32.uh=vmax(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxuh(vu, vv) +} + +/// `Vd32.w=vmax(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxw(vu, vv) +} + +/// `Vd32.h=vmin(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminh(vu, vv) +} + +/// `Vd32.ub=vmin(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminub(vu, vv) +} + +/// `Vd32.uh=vmin(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminuh(vu, vv) +} + +/// `Vd32.w=vmin(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminw(vu, vv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpabus(vuu, rt) +} + +/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpaacc_whwubrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpabus_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vmpabusv(vuu, vvv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabuuv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vmpabuuv(vuu, vvv) +} + +/// `Vdd32.w=vmpa(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpahb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpahb(vuu, rt) +} + +/// `Vxx32.w+=vmpa(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpahb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpaacc_wwwhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpahb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpybus(vu, rt) +} + +/// `Vxx32.h+=vmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpybus_acc(vxx, vu, rt) +} + +/// `Vdd32.h=vmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpybusv(vu, vv) +} + +/// `Vxx32.h+=vmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybusv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpyacc_whvubvb( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpybusv_acc(vxx, vu, vv) +} + +/// `Vdd32.h=vmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpybv(vu, vv) +} + +/// `Vxx32.h+=vmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpyacc_whvbvb( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpybv_acc(vxx, vu, vv) +} + +/// `Vd32.w=vmpye(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyewuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyewuh(vu, vv) +} + +/// `Vdd32.w=vmpy(Vu32.h,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyh(vu, rt) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyhsat_acc(vxx, vu, rt) +} + +/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhsrs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { + vmpyhsrs(vu, rt) +} + +/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhss))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { + vmpyhss(vu, rt) +} + +/// `Vdd32.w=vmpy(Vu32.h,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyhus(vu, vv) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhvuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyhus_acc(vxx, vu, vv) +} + +/// `Vdd32.w=vmpy(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyhv(vu, vv) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhvh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyhv_acc(vxx, vu, vv) +} + +/// `Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhvsrs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyhvsrs(vu, vv) +} + +/// `Vd32.w=vmpyieo(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyieoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyieoh(vu, vv) +} + +/// `Vx32.w+=vmpyie(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewh_acc(vx, vu, vv) +} + +/// `Vd32.w=vmpyie(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewuh(vu, vv) +} + +/// `Vx32.w+=vmpyie(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewuh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewuh_acc(vx, vu, vv) +} + +/// `Vd32.h=vmpyi(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyih))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyih(vu, vv) +} + +/// `Vx32.h+=vmpyi(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyih_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyih_acc(vx, vu, vv) +} + +/// `Vd32.h=vmpyi(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyihb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector { + vmpyihb(vu, rt) +} + +/// `Vx32.h+=vmpyi(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyihb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyihb_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyio(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiowh(vu, vv) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwb(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwb_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwh(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwh_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyowh(vu, vv) +} + +/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_rnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyowh_rnd(vu, vv) +} + +/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, +) -> HvxVector { + vmpyowh_rnd_sacc(vx, vu, vv) +} + +/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_sacc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, +) -> HvxVector { + vmpyowh_sacc(vx, vu, vv) +} + +/// `Vdd32.uh=vmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyub(vu, rt) +} + +/// `Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpyacc_wuhvubrub( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyub_acc(vxx, vu, rt) +} + +/// `Vdd32.uh=vmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyubv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyubv(vu, vv) +} + +/// `Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyubv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpyacc_wuhvubvub( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyubv_acc(vxx, vu, vv) +} + +/// `Vdd32.uw=vmpy(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyuh(vu, rt) +} + +/// `Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyuh_acc(vxx, vu, rt) +} + +/// `Vdd32.uw=vmpy(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyuhv(vu, vv) +} + +/// `Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuhv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyuhv_acc(vxx, vu, vv) +} + +/// `Vd32.h=vnavg(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgh(vu, vv) +} + +/// `Vd32.b=vnavg(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgub(vu, vv) +} + +/// `Vd32.w=vnavg(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgw(vu, vv) +} + +/// `Vd32.h=vnormamt(Vu32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnormamth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector { + vnormamth(vu) +} + +/// `Vd32.w=vnormamt(Vu32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnormamtw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector { + vnormamtw(vu) +} + +/// `Vd32=vnot(Vu32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnot))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector { + vnot(vu) +} + +/// `Vd32=vor(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_or(vu, vv) +} + +/// `Vd32.b=vpacke(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackeb(vu, vv) +} + +/// `Vd32.h=vpacke(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackeh(vu, vv) +} + +/// `Vd32.b=vpack(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackhb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackhb_sat(vu, vv) +} + +/// `Vd32.ub=vpack(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackhub_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackhub_sat(vu, vv) +} + +/// `Vd32.b=vpacko(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackob(vu, vv) +} + +/// `Vd32.h=vpacko(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackoh(vu, vv) +} + +/// `Vd32.h=vpack(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackwh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackwh_sat(vu, vv) +} + +/// `Vd32.uh=vpack(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackwuh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackwuh_sat(vu, vv) +} + +/// `Vd32.h=vpopcount(Vu32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpopcounth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector { + vpopcounth(vu) +} + +/// `Vd32=vrdelta(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrdelta))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrdelta(vu, vv) +} + +/// `Vd32.w=vrmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { + vrmpybus(vu, rt) +} + +/// `Vx32.w+=vrmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vrmpybus_acc(vx, vu, rt) +} + +/// `Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrmpybusi(vuu, rt, iu1) +} + +/// `Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vrmpyacc_wwwubrbi( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrmpybusi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.w=vrmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybusv(vu, vv) +} + +/// `Vx32.w+=vrmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybusv_acc(vx, vu, vv) +} + +/// `Vd32.w=vrmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybv(vu, vv) +} + +/// `Vx32.w+=vrmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybv_acc(vx, vu, vv) +} + +/// `Vd32.uw=vrmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector { + vrmpyub(vu, rt) +} + +/// `Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vrmpyub_acc(vx, vu, rt) +} + +/// `Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrmpyubi(vuu, rt, iu1) +} + +/// `Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrmpyubi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.uw=vrmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpyubv(vu, vv) +} + +/// `Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpyubv_acc(vx, vu, vv) +} + +/// `Vd32=vror(Vu32,Rt32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vror))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector { + vror(vu, rt) +} + +/// `Vd32.b=vround(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundhb(vu, vv) +} + +/// `Vd32.ub=vround(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundhub(vu, vv) +} + +/// `Vd32.h=vround(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundwh(vu, vv) +} + +/// `Vd32.uh=vround(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundwuh(vu, vv) +} + +/// `Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrsadubi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrsadubi(vuu, rt, iu1) +} + +/// `Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrsadubi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrsadubi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.ub=vsat(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsathub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsathub(vu, vv) +} + +/// `Vd32.h=vsat(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsatwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatwh(vu, vv) +} + +/// `Vdd32.h=vsxt(Vu32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair { + vsb(vu) +} + +/// `Vdd32.w=vsxt(Vu32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair { + vsh(vu) +} + +/// `Vd32.h=vshuffe(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshufeh(vu, vv) +} + +/// `Vd32.b=vshuff(Vu32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector { + vshuffb(vu) +} + +/// `Vd32.b=vshuffe(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshuffeb(vu, vv) +} + +/// `Vd32.h=vshuff(Vu32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector { + vshuffh(vu) +} + +/// `Vd32.b=vshuffo(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshuffob(vu, vv) +} + +/// `Vdd32=vshuff(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffvdd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vshuffvdd(vu, vv, rt) +} + +/// `Vdd32.b=vshuffoe(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vshufoeb(vu, vv) +} + +/// `Vdd32.h=vshuffoe(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vshufoeh(vu, vv) +} + +/// `Vd32.h=vshuffo(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshufoh(vu, vv) +} + +/// `Vd32.b=vsub(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubb(vu, vv) +} + +/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubb_dv(vuu, vvv) +} + +/// `Vd32.h=vsub(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubh(vu, vv) +} + +/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubh_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubh_dv(vuu, vvv) +} + +/// `Vd32.h=vsub(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubhsat(vu, vv) +} + +/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vsub(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsubhw(vu, vv) +} + +/// `Vdd32.h=vsub(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsububh(vu, vv) +} + +/// `Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsububsat(vu, vv) +} + +/// `Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsububsat_dv(vuu, vvv) +} + +/// `Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubuhsat(vu, vv) +} + +/// `Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubuhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vsub(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsubuhw(vu, vv) +} + +/// `Vd32.w=vsub(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_sub(vu, vv) +} + +/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubw_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubw_dv(vuu, vvv) +} + +/// `Vd32.w=vsub(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubwsat(vu, vv) +} + +/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubwsat_dv(vuu, vvv) +} + +/// `Vdd32.h=vtmpy(Vuu32.b,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpyb(vuu, rt) +} + +/// `Vxx32.h+=vtmpy(Vuu32.b,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpyacc_whwbrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpyb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vtmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpybus(vuu, rt) +} + +/// `Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpyacc_whwubrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpybus_acc(vxx, vuu, rt) +} + +/// `Vdd32.w=vtmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpyhb(vuu, rt) +} + +/// `Vxx32.w+=vtmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vtmpyacc_wwwhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpyhb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vunpack(Vu32.b)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair { + vunpackb(vu) +} + +/// `Vdd32.w=vunpack(Vu32.h)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair { + vunpackh(vu) +} + +/// `Vxx32.h|=vunpacko(Vu32.b)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { + vunpackob(vxx, vu) +} + +/// `Vxx32.w|=vunpacko(Vu32.h)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { + vunpackoh(vxx, vu) +} + +/// `Vdd32.uh=vunpack(Vu32.ub)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair { + vunpackub(vu) +} + +/// `Vdd32.uw=vunpack(Vu32.uh)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair { + vunpackuh(vu) +} + +/// `Vd32=vxor(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vxor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_xor(vu, vv) +} + +/// `Vdd32.uh=vzxt(Vu32.ub)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vzb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair { + vzb(vu) +} + +/// `Vdd32.uw=vzxt(Vu32.uh)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vzh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair { + vzh(vu) +} + +/// `Vd32.b=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(lvsplatb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector { + lvsplatb(rt) +} + +/// `Vd32.h=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(lvsplath))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector { + lvsplath(rt) +} + +/// `Vd32.b=vadd(Vu32.b,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddbsat(vu, vv) +} + +/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddbsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddbsat_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(vclb(Vu32.h),Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddclbh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddclbh(vu, vv) +} + +/// `Vd32.w=vadd(vclb(Vu32.w),Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddclbw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddclbw(vu, vv) +} + +/// `Vxx32.w+=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddhw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vaddacc_wwvhvh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vaddhw_acc(vxx, vu, vv) +} + +/// `Vxx32.h+=vadd(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddubh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vaddacc_whvubvub( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vaddubh_acc(vxx, vu, vv) +} + +/// `Vd32.ub=vadd(Vu32.ub,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddububb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddububb_sat(vu, vv) +} + +/// `Vxx32.w+=vadd(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduhw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vaddacc_wwvuhvuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vadduhw_acc(vxx, vu, vv) +} + +/// `Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadduwsat(vu, vv) +} + +/// `Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vadduwsat_dv(vuu, vvv) +} + +/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasrhbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhbsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasruwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruwuhrndsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasrwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwuhrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vlsr(Vu32.ub,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlsrb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector { + vlsrb(vu, rt) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvb_nm))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlutvvb_nm(vu, vv, rt) +} + +/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvb_oracci))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32or_vbvbvbi( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, + iu3: i32, +) -> HvxVector { + vlutvvb_oracci(vx, vu, vv, iu3) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + vlutvvbi(vu, vv, iu3) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwh_nm))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vlutvwh_nm(vu, vv, rt) +} + +/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwh_oracci))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16or_whvbvhi( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, + iu3: i32, +) -> HvxVectorPair { + vlutvwh_oracci(vxx, vu, vv, iu3) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwhi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { + vlutvwhi(vu, vv, iu3) +} + +/// `Vd32.b=vmax(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmaxb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxb(vu, vv) +} + +/// `Vd32.b=vmin(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vminb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminb(vu, vv) +} + +/// `Vdd32.w=vmpa(Vuu32.uh,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpauhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpauhb(vuu, rt) +} + +/// `Vxx32.w+=vmpa(Vuu32.uh,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpauhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpaacc_wwwuhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpauhb_acc(vxx, vuu, rt) +} + +/// `Vdd32=vmpye(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyewuh_64))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyewuh_64(vu, vv) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyiwub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwub(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyiwub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwub_acc(vx, vu, rt) +} + +/// `Vxx32+=vmpyo(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyowh_64_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vmpyoacc_wvwvh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyowh_64_acc(vxx, vu, vv) +} + +/// `Vd32.ub=vround(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vrounduhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrounduhub(vu, vv) +} + +/// `Vd32.uh=vround(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vrounduwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrounduwuh(vu, vv) +} + +/// `Vd32.uh=vsat(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsatuwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatuwuh(vu, vv) +} + +/// `Vd32.b=vsub(Vu32.b,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubbsat(vu, vv) +} + +/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubbsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubbsat_dv(vuu, vvv) +} + +/// `Vd32.ub=vsub(Vu32.ub,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubububb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubububb_sat(vu, vv) +} + +/// `Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubuwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubuwsat(vu, vv) +} + +/// `Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubuwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubuwsat_dv(vuu, vvv) +} + +/// `Vd32.b=vabs(Vu32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vabsb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector { + vabsb(vu) +} + +/// `Vd32.b=vabs(Vu32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vabsb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector { + vabsb_sat(vu) +} + +/// `Vx32.h+=vasl(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vaslh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vaslh_acc(vx, vu, rt) +} + +/// `Vx32.h+=vasr(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasrh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vasrh_acc(vx, vu, rt) +} + +/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruhubrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruhubsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruwuhsat(vu, vv, rt) +} + +/// `Vd32.b=vavg(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavgb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgb(vu, vv) +} + +/// `Vd32.b=vavg(Vu32.b,Vv32.b):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavgbrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgbrnd(vu, vv) +} + +/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavguw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguw(vu, vv) +} + +/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavguwrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguwrnd(vu, vv) +} + +/// `Vdd32=#0` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vdd0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vzero() -> HvxVectorPair { + vdd0() +} + +/// `vtmp.h=vgather(Rt32,Mu2,Vv32.h).h` +/// +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { + vgathermh(rs, rt, mu, vv) +} + +/// `vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h` +/// +/// Instruction Type: CVI_GATHER_DV +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { + vgathermhw(rs, rt, mu, vvv) +} + +/// `vtmp.w=vgather(Rt32,Mu2,Vv32.w).w` +/// +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { + vgathermw(rs, rt, mu, vv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpabuu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpabuu(vuu, rt) +} + +/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpabuu_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpaacc_whwubrub( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpabuu_acc(vxx, vuu, rt) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyh_acc(vxx, vu, rt) +} + +/// `Vd32.uw=vmpye(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyuhe))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector { + vmpyuhe(vu, rt) +} + +/// `Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyuhe_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyuhe_acc(vx, vu, rt) +} + +/// `Vd32.b=vnavg(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vnavgb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgb(vu, vv) +} + +/// `vscatter(Rt32,Mu2,Vv32.h).h=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermh(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.h).h+=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermh_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermh_add(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vvv32.w).h=Vw32` +/// +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { + vscattermhw(rt, mu, vvv, vw) +} + +/// `vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32` +/// +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermhw_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { + vscattermhw_add(rt, mu, vvv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.w).w=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermw(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.w).w+=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermw_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermw_add(rt, mu, vv, vw) +} + +/// `Vxx32.w=vasrinto(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vasr_into))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vasrinto_wwvwvw( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vasr_into(vxx, vu, vv) +} + +/// `Vd32.uw=vrotr(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vrotr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrotr(vu, vv) +} + +/// `Vd32.w=vsatdw(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vsatdw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatdw(vu, vv) +} + +/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyhubs10))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpy_wubwbi_h( + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyhubs10(vuu, vvv, iu2) +} + +/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyhubs10_vxx(vxx, vuu, vvv, iu2) +} + +/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyvubs10))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpy_wubwbi_v( + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyvubs10(vuu, vvv, iu2) +} + +/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyvubs10_vxx(vxx, vuu, vvv, iu2) +} + +/// `Vd32.hf=vabs(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vabs_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector { + vabs_hf(vu) +} + +/// `Vd32.sf=vabs(Vu32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vabs_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector { + vabs_sf(vu) +} + +/// `Vd32.qf16=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_hf(vu, vv) +} + +/// `Vd32.hf=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_hf_hf(vu, vv) +} + +/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf16(vu, vv) +} + +/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf16_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf16_mix(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf32(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf32_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf32_mix(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_sf(vu, vv) +} + +/// `Vdd32.sf=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vadd_sf_hf(vu, vv) +} + +/// `Vd32.sf=vadd(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_sf_sf(vu, vv) +} + +/// `Vd32.w=vfmv(Vu32.w)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vassign_fp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector { + vassign_fp(vu) +} + +/// `Vd32.hf=Vu32.qf16` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_hf_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector { + vconv_hf_qf16(vu) +} + +/// `Vd32.hf=Vuu32.qf32` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_hf_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector { + vconv_hf_qf32(vuu) +} + +/// `Vd32.sf=Vu32.qf32` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_sf_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector { + vconv_sf_qf32(vu) +} + +/// `Vd32.b=vcvt(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_b_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_b_hf(vu, vv) +} + +/// `Vd32.h=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_h_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector { + vcvt_h_hf(vu) +} + +/// `Vdd32.hf=vcvt(Vu32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_b))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_b(vu) +} + +/// `Vd32.hf=vcvt(Vu32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector { + vcvt_hf_h(vu) +} + +/// `Vd32.hf=vcvt(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_hf_sf(vu, vv) +} + +/// `Vdd32.hf=vcvt(Vu32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_ub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_ub(vu) +} + +/// `Vd32.hf=vcvt(Vu32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_uh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector { + vcvt_hf_uh(vu) +} + +/// `Vdd32.sf=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair { + vcvt_sf_hf(vu) +} + +/// `Vd32.ub=vcvt(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_ub_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_ub_hf(vu, vv) +} + +/// `Vd32.uh=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_uh_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector { + vcvt_uh_hf(vu) +} + +/// `Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vdmpy_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpy_sf_hf(vu, vv) +} + +/// `Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpy_sf_hf_acc(vx, vu, vv) +} + +/// `Vd32.hf=vfmax(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmax_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_hf(vu, vv) +} + +/// `Vd32.sf=vfmax(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmax_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_sf(vu, vv) +} + +/// `Vd32.hf=vfmin(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmin_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_hf(vu, vv) +} + +/// `Vd32.sf=vfmin(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmin_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_sf(vu, vv) +} + +/// `Vd32.hf=vfneg(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfneg_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector { + vfneg_hf(vu) +} + +/// `Vd32.sf=vfneg(Vu32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfneg_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector { + vfneg_sf(vu) +} + +/// `Vd32.hf=vmax(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmax_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmax_hf(vu, vv) +} + +/// `Vd32.sf=vmax(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmax_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmax_sf(vu, vv) +} + +/// `Vd32.hf=vmin(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmin_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmin_hf(vu, vv) +} + +/// `Vd32.sf=vmin(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmin_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmin_sf(vu, vv) +} + +/// `Vd32.hf=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_hf_hf(vu, vv) +} + +/// `Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_hf_hf_acc(vx, vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16(vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16_hf(vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16_mix_hf(vu, vv) +} + +/// `Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf32(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_hf(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_mix_hf(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_qf16(vu, vv) +} + +/// `Vd32.qf32=vmpy(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf32_sf(vu, vv) +} + +/// `Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_sf_hf(vu, vv) +} + +/// `Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpy_sf_hf_acc(vxx, vu, vv) +} + +/// `Vd32.sf=vmpy(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_sf_sf(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_hf(vu, vv) +} + +/// `Vd32.hf=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_hf_hf(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf16(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf16_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf16_mix(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf32(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf32_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf32_mix(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_sf(vu, vv) +} + +/// `Vdd32.sf=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsub_sf_hf(vu, vv) +} + +/// `Vd32.sf=vsub(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_sf_sf(vu, vv) +} + +/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvuhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvuhubrndsat(vuu, vv) +} + +/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvuhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvuhubsat(vuu, vv) +} + +/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvwuhrndsat(vuu, vv) +} + +/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvwuhsat(vuu, vv) +} + +/// `Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vmpyuhvs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyuhvs(vu, vv) +} + +/// `Vd32.h=Vu32.hf` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_h_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector { + vconv_h_hf(vu) +} + +/// `Vd32.hf=Vu32.h` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_hf_h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector { + vconv_hf_h(vu) +} + +/// `Vd32.sf=Vu32.w` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_sf_w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector { + vconv_sf_w(vu) +} + +/// `Vd32.w=Vu32.sf` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_w_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector { + vconv_w_sf(vu) +} + +/// `Vd32=vgetqfext(Vu32.x,Rt32)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(get_qfext))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { + get_qfext(vu, rt) +} + +/// `Vd32.x=vsetqfext(Vu32,Rt32)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(set_qfext))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { + set_qfext(vu, rt) +} + +/// `Vd32.f8=vabs(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vabs_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector { + vabs_f8(vu) +} + +/// `Vdd32.hf=vcvt2(Vu32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt2_hf_b))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair { + vcvt2_hf_b(vu) +} + +/// `Vdd32.hf=vcvt2(Vu32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt2_hf_ub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair { + vcvt2_hf_ub(vu) +} + +/// `Vdd32.hf=vcvt(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt_hf_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_f8(vu) +} + +/// `Vd32.f8=vfmax(Vu32.f8,Vv32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfmax_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_f8(vu, vv) +} + +/// `Vd32.f8=vfmin(Vu32.f8,Vv32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfmin_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_f8(vu, vv) +} + +/// `Vd32.f8=vfneg(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfneg_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector { + vfneg_f8(vu) +} + +/// `Qd4=and(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_and( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=and(Qs4,!Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_and_n( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=not(Qs4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_not(vandvrt( + core::mem::transmute::(qs), + -1, + )), + -1, + )) +} + +/// `Qd4=or(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_or( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=or(Qs4,!Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_or_n( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=vsetq(Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(pred_scalar2(rt), -1)) +} + +/// `Qd4=xor(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_xor( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `if (!Qv4) vmem(Rt32+#s4)=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nqpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (!Qv4) vmem(Rt32+#s4):nt=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nt_nqpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (Qv4) vmem(Rt32+#s4):nt=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nt_qpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (Qv4) vmem(Rt32+#s4)=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_qpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (!Qv4) Vx32.b+=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddbnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.b+=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddbq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.h+=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddhnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.h+=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddhq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.w+=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddwnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.w+=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddwq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `Vd32=vand(Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector { + vandvrt(core::mem::transmute::(qu), rt) +} + +/// `Vx32|=vand(Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { + vandvrt_acc(vx, core::mem::transmute::(qu), rt) +} + +/// `Qd4=vand(Vu32,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vu, rt)) +} + +/// `Qx4|=vand(Vu32,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt_acc( + core::mem::transmute::(qx), + vu, + rt, + )) +} + +/// `Qd4=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqb(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqand_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqor_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqxacc_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqh(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqand_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqor_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqxacc_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqand_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqor_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqxacc_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtb(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgth(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtub(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvubvub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvubvub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvubvub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtuh(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvuhvuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvuhvuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtuw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvuwvuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvuwvuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Vd32=vmux(Qt4,Vu32,Vv32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmux( + vandvrt(core::mem::transmute::(qt), -1), + vu, + vv, + ) +} + +/// `if (!Qv4) Vx32.b-=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubbnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.b-=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubbq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.h-=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubhnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.h-=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubhq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.w-=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubwnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.w-=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubwq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `Vdd32=vswap(Qt4,Vu32,Vv32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vswap( + vandvrt(core::mem::transmute::(qt), -1), + vu, + vv, + ) +} + +/// `Qd4=vsetq2(Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(pred_scalar2v2(rt), -1)) +} + +/// `Qd4.b=vshuffe(Qs4.h,Qt4.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + shuffeqh( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4.h=vshuffe(Qs4.w,Qt4.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + shuffeqw( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Vd32=vand(!Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector { + vandnqrt( + vandvrt(core::mem::transmute::(qu), -1), + rt, + ) +} + +/// `Vx32|=vand(!Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { + vandnqrt_acc( + vx, + vandvrt(core::mem::transmute::(qu), -1), + rt, + ) +} + +/// `Vd32=vand(!Qv4,Vu32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { + vandvnqv( + vandvrt(core::mem::transmute::(qv), -1), + vu, + ) +} + +/// `Vd32=vand(Qv4,Vu32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { + vandvqv( + vandvrt(core::mem::transmute::(qv), -1), + vu, + ) +} + +/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_aqrmvh( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, +) { + vgathermhq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + ) +} + +/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER_DV +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_aqrmww( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vvv: HvxVectorPair, +) { + vgathermhwq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vvv, + ) +} + +/// `if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_aqrmvw( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, +) { + vgathermwq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + ) +} + +/// `Vd32.b=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector { + vprefixqb(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `Vd32.h=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector { + vprefixqh(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `Vd32.w=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector { + vprefixqw(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_qrmvhv( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, + vw: HvxVector, +) { + vscattermhq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + vw, + ) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_qrmwwv( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vvv: HvxVectorPair, + vw: HvxVector, +) { + vscattermhwq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vvv, + vw, + ) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_qrmvwv( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, + vw: HvxVector, +) { + vscattermwq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + vw, + ) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vwvwq_carry_sat( + vu: HvxVector, + vv: HvxVector, + qs: HvxVectorPred, +) -> HvxVector { + vaddcarrysat( + vu, + vv, + vandvrt(core::mem::transmute::(qs), -1), + ) +} + +/// `Qd4=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgthf(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvhfvhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvhfvhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtsf(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvsfvsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvsfvsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvsfvsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} diff --git a/stdarch/crates/core_arch/src/lib.rs b/stdarch/crates/core_arch/src/lib.rs index 039a4c4411f2e..9255994e5ee81 100644 --- a/stdarch/crates/core_arch/src/lib.rs +++ b/stdarch/crates/core_arch/src/lib.rs @@ -23,6 +23,7 @@ mips_target_feature, powerpc_target_feature, loongarch_target_feature, + hexagon_target_feature, wasm_target_feature, abi_unadjusted, rtm_target_feature, @@ -38,7 +39,8 @@ const_trait_impl, const_cmp, const_eval_select, - maybe_uninit_as_bytes + maybe_uninit_as_bytes, + movrs_target_feature )] #![cfg_attr(test, feature(test, abi_vectorcall, stdarch_internal))] #![deny(clippy::missing_inline_in_public_items)] diff --git a/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs b/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs index cda0ebec67799..1d9d4e8248e63 100644 --- a/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs +++ b/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs @@ -7,7 +7,7 @@ // ``` use crate::mem::transmute; -use super::types::*; +use super::super::*; #[allow(improper_ctypes)] unsafe extern "unadjusted" { @@ -980,7 +980,7 @@ unsafe extern "unadjusted" { #[link_name = "llvm.loongarch.lasx.xvssrln.w.d"] fn __lasx_xvssrln_w_d(a: __v4i64, b: __v4i64) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvorn.v"] - fn __lasx_xvorn_v(a: __v32i8, b: __v32i8) -> __v32i8; + fn __lasx_xvorn_v(a: __v32u8, b: __v32u8) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvldi"] fn __lasx_xvldi(a: i32) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvldx"] @@ -1491,6 +1491,42 @@ unsafe extern "unadjusted" { fn __lasx_xvrepli_h(a: i32) -> __v16i16; #[link_name = "llvm.loongarch.lasx.xvrepli.w"] fn __lasx_xvrepli_w(a: i32) -> __v8i32; + #[link_name = "llvm.loongarch.lasx.cast.128.s"] + fn __lasx_cast_128_s(a: __v4f32) -> __v8f32; + #[link_name = "llvm.loongarch.lasx.cast.128.d"] + fn __lasx_cast_128_d(a: __v2f64) -> __v4f64; + #[link_name = "llvm.loongarch.lasx.cast.128"] + fn __lasx_cast_128(a: __v2i64) -> __v4i64; + #[link_name = "llvm.loongarch.lasx.concat.128.s"] + fn __lasx_concat_128_s(a: __v4f32, b: __v4f32) -> __v8f32; + #[link_name = "llvm.loongarch.lasx.concat.128.d"] + fn __lasx_concat_128_d(a: __v2f64, b: __v2f64) -> __v4f64; + #[link_name = "llvm.loongarch.lasx.concat.128"] + fn __lasx_concat_128(a: __v2i64, b: __v2i64) -> __v4i64; + #[link_name = "llvm.loongarch.lasx.extract.128.lo.s"] + fn __lasx_extract_128_lo_s(a: __v8f32) -> __v4f32; + #[link_name = "llvm.loongarch.lasx.extract.128.hi.s"] + fn __lasx_extract_128_hi_s(a: __v8f32) -> __v4f32; + #[link_name = "llvm.loongarch.lasx.extract.128.lo.d"] + fn __lasx_extract_128_lo_d(a: __v4f64) -> __v2f64; + #[link_name = "llvm.loongarch.lasx.extract.128.hi.d"] + fn __lasx_extract_128_hi_d(a: __v4f64) -> __v2f64; + #[link_name = "llvm.loongarch.lasx.extract.128.lo"] + fn __lasx_extract_128_lo(a: __v4i64) -> __v2i64; + #[link_name = "llvm.loongarch.lasx.extract.128.hi"] + fn __lasx_extract_128_hi(a: __v4i64) -> __v2i64; + #[link_name = "llvm.loongarch.lasx.insert.128.lo.s"] + fn __lasx_insert_128_lo_s(a: __v8f32, b: __v4f32) -> __v8f32; + #[link_name = "llvm.loongarch.lasx.insert.128.hi.s"] + fn __lasx_insert_128_hi_s(a: __v8f32, b: __v4f32) -> __v8f32; + #[link_name = "llvm.loongarch.lasx.insert.128.lo.d"] + fn __lasx_insert_128_lo_d(a: __v4f64, b: __v2f64) -> __v4f64; + #[link_name = "llvm.loongarch.lasx.insert.128.hi.d"] + fn __lasx_insert_128_hi_d(a: __v4f64, b: __v2f64) -> __v4f64; + #[link_name = "llvm.loongarch.lasx.insert.128.lo"] + fn __lasx_insert_128_lo(a: __v4i64, b: __v2i64) -> __v4i64; + #[link_name = "llvm.loongarch.lasx.insert.128.hi"] + fn __lasx_insert_128_hi(a: __v4i64, b: __v2i64) -> __v4i64; } #[inline] @@ -7062,3 +7098,129 @@ pub fn lasx_xvrepli_w() -> m256i { static_assert_simm_bits!(IMM_S10, 10); unsafe { transmute(__lasx_xvrepli_w(IMM_S10)) } } + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_cast_128_s(a: m128) -> m256 { + unsafe { transmute(__lasx_cast_128_s(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_cast_128_d(a: m128d) -> m256d { + unsafe { transmute(__lasx_cast_128_d(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_cast_128(a: m128i) -> m256i { + unsafe { transmute(__lasx_cast_128(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_concat_128_s(a: m128, b: m128) -> m256 { + unsafe { transmute(__lasx_concat_128_s(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_concat_128_d(a: m128d, b: m128d) -> m256d { + unsafe { transmute(__lasx_concat_128_d(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_concat_128(a: m128i, b: m128i) -> m256i { + unsafe { transmute(__lasx_concat_128(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_lo_s(a: m256) -> m128 { + unsafe { transmute(__lasx_extract_128_lo_s(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_hi_s(a: m256) -> m128 { + unsafe { transmute(__lasx_extract_128_hi_s(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_lo_d(a: m256d) -> m128d { + unsafe { transmute(__lasx_extract_128_lo_d(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_hi_d(a: m256d) -> m128d { + unsafe { transmute(__lasx_extract_128_hi_d(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_lo(a: m256i) -> m128i { + unsafe { transmute(__lasx_extract_128_lo(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_hi(a: m256i) -> m128i { + unsafe { transmute(__lasx_extract_128_hi(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_lo_s(a: m256, b: m128) -> m256 { + unsafe { transmute(__lasx_insert_128_lo_s(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_hi_s(a: m256, b: m128) -> m256 { + unsafe { transmute(__lasx_insert_128_hi_s(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_lo_d(a: m256d, b: m128d) -> m256d { + unsafe { transmute(__lasx_insert_128_lo_d(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_hi_d(a: m256d, b: m128d) -> m256d { + unsafe { transmute(__lasx_insert_128_hi_d(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_lo(a: m256i, b: m128i) -> m256i { + unsafe { transmute(__lasx_insert_128_lo(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_hi(a: m256i, b: m128i) -> m256i { + unsafe { transmute(__lasx_insert_128_hi(transmute(a), transmute(b))) } +} diff --git a/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs b/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs index 54771d7b51109..319ce7cf98195 100644 --- a/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs +++ b/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs @@ -14756,3 +14756,284 @@ unsafe fn test_lasx_xvrepli_w() { assert_eq!(r, transmute(lasx_xvrepli_w::<-388>())); } + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_cast_128_s() { + let a = u32x4::new(1031165056, 1051966120, 1060984374, 1062536919); + let r = i64x4::new(4518160082931176576, 4563561318958585398, 1966080, 1966080); + + assert_eq!( + r.as_array()[0..2], + transmute::<_, i64x4>(lasx_cast_128_s(transmute(a))).as_array()[0..2] + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_cast_128_d() { + let a = u64x2::new(4604694967937271251, 4600904075476555984); + let r = i64x4::new( + 4604694967937271251, + 4600904075476555984, + 2910860781861170785, + 8314045306847701346, + ); + + assert_eq!( + r.as_array()[0..2], + transmute::<_, i64x4>(lasx_cast_128_d(transmute(a))).as_array()[0..2] + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_cast_128() { + let a = i64x2::new(-5333716211868108402, 2442107533729495827); + let r = i64x4::new( + -5333716211868108402, + 2442107533729495827, + -1115824375586394527, + 8314045306157170687, + ); + + assert_eq!( + r.as_array()[0..2], + transmute::<_, i64x4>(lasx_cast_128(transmute(a))).as_array()[0..2] + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_concat_128_s() { + let a = u32x4::new(1032255272, 1059413818, 1058434362, 1041454056); + let b = u32x4::new(1047296252, 1059191602, 1051282752, 1026847376); + let r = i64x4::new( + 4550147702272751400, + 4473011111864986938, + 4549193291835144444, + 4410275898954698048, + ); + + assert_eq!(r, transmute(lasx_concat_128_s(transmute(a), transmute(b)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_concat_128_d() { + let a = u64x2::new(4602341404117999960, 4599751584045405722); + let b = u64x2::new(4595947342927040984, 4600308396523102002); + let r = i64x4::new( + 4602341404117999960, + 4599751584045405722, + 4595947342927040984, + 4600308396523102002, + ); + + assert_eq!(r, transmute(lasx_concat_128_d(transmute(a), transmute(b)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_concat_128() { + let a = i64x2::new(3302609705743394573, 8438855426868306143); + let b = i64x2::new(8632034656150002181, 7751541408133090748); + let r = i64x4::new( + 3302609705743394573, + 8438855426868306143, + 8632034656150002181, + 7751541408133090748, + ); + + assert_eq!(r, transmute(lasx_concat_128(transmute(a), transmute(b)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_lo_s() { + let a = u32x8::new( + 1038279272, 1053426270, 1062315532, 1055361088, 1061380448, 1052007748, 1063816577, + 1061671114, + ); + let r = i64x2::new(4524431379435545192, 4532741359493293580); + + assert_eq!(r, transmute(lasx_extract_128_lo_s(transmute(a)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_hi_s() { + let a = u32x8::new( + 1059517342, 1052723820, 1053176244, 1060336354, 1058221022, 1064684502, 1061072013, + 1059238420, + ); + let r = i64x2::new(4572785117706267614, 4549394373627784333); + + assert_eq!(r, transmute(lasx_extract_128_hi_s(transmute(a)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_lo_d() { + let a = u64x4::new( + 4606487981487128637, + 4592443779247846248, + 4605637448543526041, + 4604126872543611047, + ); + let r = i64x2::new(4606487981487128637, 4592443779247846248); + + assert_eq!(r, transmute(lasx_extract_128_lo_d(transmute(a)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_hi_d() { + let a = u64x4::new( + 4595075050683709816, + 4603388454656549851, + 4603881047625519227, + 4604218419306666352, + ); + let r = i64x2::new(4603881047625519227, 4604218419306666352); + + assert_eq!(r, transmute(lasx_extract_128_hi_d(transmute(a)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_lo() { + let a = i64x4::new( + 1690990426210778543, + -1056924033489771427, + 1791197928200737608, + 2648792885519901423, + ); + let r = i64x2::new(1690990426210778543, -1056924033489771427); + + assert_eq!(r, transmute(lasx_extract_128_lo(transmute(a)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_hi() { + let a = i64x4::new( + 1400282616691463341, + 6677577875527300174, + -1903780563362068813, + -7449796170151383489, + ); + let r = i64x2::new(-1903780563362068813, -7449796170151383489); + + assert_eq!(r, transmute(lasx_extract_128_hi(transmute(a)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_lo_s() { + let a = u32x8::new( + 1063338913, 1017815328, 1065051130, 1040694156, 1059596680, 1048796526, 1058020845, + 1057822131, + ); + let b = u32x4::new(1052930766, 1021556992, 1050709482, 1059704809); + let r = i64x4::new( + 4387553872693064398, + 4551397499119635946, + 4504546780388010376, + 4543311458688048621, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_lo_s(transmute(a), transmute(b))) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_hi_s() { + let a = u32x8::new( + 1018863744, 1064221149, 1048659080, 1057450774, 1049935896, 1034170664, 1059759433, + 1057849762, + ); + let b = u32x4::new(1060332648, 1063149600, 1051087106, 1060582348); + let r = i64x4::new( + 4570795031685406848, + 4541716492508546184, + 4566192763815814248, + 4555166500425978114, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_hi_s(transmute(a), transmute(b))) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_lo_d() { + let a = u64x4::new( + 4601319519422109044, + 4601506273633970188, + 4605118087882201940, + 4605125059076454256, + ); + let b = u64x2::new(4587489919640425888, 4591909120489567808); + let r = i64x4::new( + 4587489919640425888, + 4591909120489567808, + 4605118087882201940, + 4605125059076454256, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_lo_d(transmute(a), transmute(b))) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_hi_d() { + let a = u64x4::new( + 4604690660177752777, + 4593824994203592700, + 4599958775071728504, + 4604125324674373728, + ); + let b = u64x2::new(4601718173474385938, 4591758028383494760); + let r = i64x4::new( + 4604690660177752777, + 4593824994203592700, + 4601718173474385938, + 4591758028383494760, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_hi_d(transmute(a), transmute(b))) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_lo() { + let a = i64x4::new( + 8159968186698006293, + 5648210958959948409, + 603295919044368378, + -4396186135186039276, + ); + let b = i64x2::new(-6258666140812668387, 5822982556977506382); + let r = i64x4::new( + -6258666140812668387, + 5822982556977506382, + 603295919044368378, + -4396186135186039276, + ); + + assert_eq!(r, transmute(lasx_insert_128_lo(transmute(a), transmute(b)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_hi() { + let a = i64x4::new( + 2981835982487038158, + 5258378092714202875, + 5115371338527125146, + -6993491475145500537, + ); + let b = i64x2::new(1176776599938765863, -7502655081590988207); + let r = i64x4::new( + 2981835982487038158, + 5258378092714202875, + 1176776599938765863, + -7502655081590988207, + ); + + assert_eq!(r, transmute(lasx_insert_128_hi(transmute(a), transmute(b)))); +} diff --git a/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs b/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs index 764e69ca05444..25efaadb42880 100644 --- a/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs +++ b/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs @@ -7,7 +7,7 @@ // ``` use crate::mem::transmute; -use super::types::*; +use super::super::*; #[allow(improper_ctypes)] unsafe extern "unadjusted" { @@ -1324,7 +1324,7 @@ unsafe extern "unadjusted" { #[link_name = "llvm.loongarch.lsx.vssrln.w.d"] fn __lsx_vssrln_w_d(a: __v2i64, b: __v2i64) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vorn.v"] - fn __lsx_vorn_v(a: __v16i8, b: __v16i8) -> __v16i8; + fn __lsx_vorn_v(a: __v16u8, b: __v16u8) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vldi"] fn __lsx_vldi(a: i32) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vshuf.b"] diff --git a/stdarch/crates/core_arch/src/macros.rs b/stdarch/crates/core_arch/src/macros.rs index 353829633f018..00e92428b3e7e 100644 --- a/stdarch/crates/core_arch/src/macros.rs +++ b/stdarch/crates/core_arch/src/macros.rs @@ -186,3 +186,176 @@ macro_rules! simd_masked_store { $crate::intrinsics::simd::simd_masked_store::<_, _, _, { $align }>($mask, $ptr, $default) }; } + +/// The first N indices `[0, 1, 2, ...]`. +pub(crate) const fn identity() -> [u32; N] { + let mut out = [0u32; N]; + let mut i = 0usize; + while i < N { + out[i] = i as u32; + i += 1; + } + out +} + +/// The first N even indices `[0, 2, 4, ...]`. +pub(crate) const fn even() -> [u32; N] { + let mut out = [0u32; N]; + let mut i = 0usize; + while i < N { + out[i] = (2 * i) as u32; + i += 1; + } + out +} + +/// The first N odd indices `[1, 3, 5, ...]`. +pub(crate) const fn odd() -> [u32; N] { + let mut out = [0u32; N]; + let mut i = 0usize; + while i < N { + out[i] = (2 * i + 1) as u32; + i += 1; + } + out +} + +/// Multiples of N offset by K `[K, K+N, K+2N, ...]`. +pub(crate) const fn deinterleave_mask() +-> [u32; LANES] { + let mut out = [0u32; LANES]; + let mut i = 0usize; + while i < LANES { + out[i] = (i * N + K) as u32; + i += 1; + } + out +} + +#[allow(unused)] +macro_rules! deinterleaving_load { + ($elem:ty, $lanes:literal, 2, $ptr:expr) => {{ + use $crate::core_arch::macros::deinterleave_mask; + use $crate::core_arch::simd::Simd; + use $crate::mem::transmute; + + type V = Simd<$elem, $lanes>; + type W = Simd<$elem, { $lanes * 2 }>; + + let w: W = $crate::ptr::read_unaligned($ptr as *const W); + + let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 2, 0>()); + let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 2, 1>()); + + transmute((v0, v1)) + }}; + + ($elem:ty, $lanes:literal, 3, $ptr:expr) => {{ + use $crate::core_arch::macros::deinterleave_mask; + use $crate::core_arch::simd::Simd; + use $crate::mem::{MaybeUninit, transmute}; + + type V = Simd<$elem, $lanes>; + type W = Simd<$elem, { $lanes * 3 }>; + + // NOTE: repr(simd) adds padding to make the total size a power of two. + // Hence reading W from ptr might read out of bounds. + let mut mem = MaybeUninit::::uninit(); + $crate::ptr::copy_nonoverlapping( + $ptr.cast::<$elem>(), + mem.as_mut_ptr().cast::<$elem>(), + $lanes * 3, + ); + let w = mem.assume_init(); + + let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 0>()); + let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 1>()); + let v2: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 2>()); + + transmute((v0, v1, v2)) + }}; + + ($elem:ty, $lanes:literal, 4, $ptr:expr) => {{ + use $crate::core_arch::macros::deinterleave_mask; + use $crate::core_arch::simd::Simd; + use $crate::mem::transmute; + + type V = Simd<$elem, $lanes>; + type W = Simd<$elem, { $lanes * 4 }>; + + let w: W = $crate::ptr::read_unaligned($ptr as *const W); + + let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 0>()); + let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 1>()); + let v2: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 2>()); + let v3: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 3>()); + + transmute((v0, v1, v2, v3)) + }}; +} + +#[allow(unused)] +pub(crate) use deinterleaving_load; + +pub(crate) const fn interleave_mask() +-> [u32; LANES] { + let mut out = [0u32; LANES]; + let mut j = 0usize; + while j < LANES { + out[j] = ((j % K) * N + j / K) as u32; + j += 1; + } + out +} + +#[allow(unused)] +macro_rules! interleaving_store { + ($elem:ty, $lanes:literal, 2, $ptr:expr, $v:expr) => {{ + use $crate::core_arch::macros::interleave_mask; + use $crate::core_arch::simd::Simd; + + type W = Simd<$elem, { $lanes * 2 }>; + let w: W = simd_shuffle!($v.0, $v.1, interleave_mask::<{ $lanes * 2 }, $lanes, 2>()); + $crate::ptr::write_unaligned($ptr as *mut W, w); + }}; + + // N = 3 + ($elem:ty, $lanes:literal, 3, $ptr:expr, $v:expr) => {{ + use $crate::core_arch::macros::{identity, interleave_mask}; + use $crate::core_arch::simd::Simd; + + let v0v1: Simd<$elem, { $lanes * 2 }> = + simd_shuffle!($v.0, $v.1, identity::<{ $lanes * 2 }>()); + let v2v2: Simd<$elem, { $lanes * 2 }> = + simd_shuffle!($v.2, $v.2, identity::<{ $lanes * 2 }>()); + + type W = Simd<$elem, { $lanes * 3 }>; + + // NOTE: repr(simd) adds padding to make the total size a power of two. + // Hence writing W to ptr might write out of bounds. + let w: W = simd_shuffle!(v0v1, v2v2, interleave_mask::<{ $lanes * 3 }, $lanes, 3>()); + $crate::ptr::copy_nonoverlapping( + (&w as *const W).cast::<$elem>(), + $ptr.cast::<$elem>(), + $lanes * 3, + ); + }}; + + // N = 4 + ($elem:ty, $lanes:literal, 4, $ptr:expr, $v:expr) => {{ + use $crate::core_arch::macros::{identity, interleave_mask}; + use $crate::core_arch::simd::Simd; + + let v0v1: Simd<$elem, { $lanes * 2 }> = + simd_shuffle!($v.0, $v.1, identity::<{ $lanes * 2 }>()); + let v2v3: Simd<$elem, { $lanes * 2 }> = + simd_shuffle!($v.2, $v.3, identity::<{ $lanes * 2 }>()); + + type W = Simd<$elem, { $lanes * 4 }>; + let w: W = simd_shuffle!(v0v1, v2v3, interleave_mask::<{ $lanes * 4 }, $lanes, 4>()); + $crate::ptr::write_unaligned($ptr as *mut W, w); + }}; +} + +#[allow(unused)] +pub(crate) use interleaving_store; diff --git a/stdarch/crates/core_arch/src/mips/msa.rs b/stdarch/crates/core_arch/src/mips/msa.rs index 563e121a7badb..6246433da5585 100644 --- a/stdarch/crates/core_arch/src/mips/msa.rs +++ b/stdarch/crates/core_arch/src/mips/msa.rs @@ -9187,7 +9187,6 @@ mod tests { core_arch::{mips::msa::*, simd::*}, mem, }; - use std::{f32, f64}; use stdarch_test::simd_test; #[simd_test(enable = "msa")] diff --git a/stdarch/crates/core_arch/src/mod.rs b/stdarch/crates/core_arch/src/mod.rs index 3577175ae31c7..2483d07b230f9 100644 --- a/stdarch/crates/core_arch/src/mod.rs +++ b/stdarch/crates/core_arch/src/mod.rs @@ -320,6 +320,19 @@ pub mod arch { pub mod s390x { pub use crate::core_arch::s390x::*; } + + /// Platform-specific intrinsics for the `hexagon` platform. + /// + /// This module provides intrinsics for the Qualcomm Hexagon DSP architecture, + /// including the Hexagon Vector Extensions (HVX). + /// + /// See the [module documentation](../index.html) for more details. + #[cfg(any(target_arch = "hexagon", doc))] + #[doc(cfg(target_arch = "hexagon"))] + #[unstable(feature = "stdarch_hexagon", issue = "151523")] + pub mod hexagon { + pub use crate::core_arch::hexagon::*; + } } #[cfg(any(target_arch = "x86", target_arch = "x86_64", doc))] @@ -379,3 +392,7 @@ mod loongarch64; #[cfg(any(target_arch = "s390x", doc))] #[doc(cfg(target_arch = "s390x"))] mod s390x; + +#[cfg(any(target_arch = "hexagon", doc))] +#[doc(cfg(target_arch = "hexagon"))] +mod hexagon; diff --git a/stdarch/crates/core_arch/src/nvptx/packed.rs b/stdarch/crates/core_arch/src/nvptx/packed.rs index 856aeea4b686c..1c7e81268fc99 100644 --- a/stdarch/crates/core_arch/src/nvptx/packed.rs +++ b/stdarch/crates/core_arch/src/nvptx/packed.rs @@ -99,7 +99,7 @@ pub unsafe fn f16x2_neg(a: f16x2) -> f16x2 { #[cfg_attr(test, assert_instr(min.f16x2))] #[unstable(feature = "stdarch_nvptx", issue = "111199")] pub unsafe fn f16x2_min(a: f16x2, b: f16x2) -> f16x2 { - simd_fmin(a, b) + simd_minimum_number_nsz(a, b) } /// Find the minimum of two values, NaNs pass through. @@ -123,7 +123,7 @@ pub unsafe fn f16x2_min_nan(a: f16x2, b: f16x2) -> f16x2 { #[cfg_attr(test, assert_instr(max.f16x2))] #[unstable(feature = "stdarch_nvptx", issue = "111199")] pub unsafe fn f16x2_max(a: f16x2, b: f16x2) -> f16x2 { - simd_fmax(a, b) + simd_maximum_number_nsz(a, b) } /// Find the maximum of two values, NaNs pass through. diff --git a/stdarch/crates/core_arch/src/powerpc/altivec.rs b/stdarch/crates/core_arch/src/powerpc/altivec.rs index fb1a9d8ed9e2c..f68121ad31716 100644 --- a/stdarch/crates/core_arch/src/powerpc/altivec.rs +++ b/stdarch/crates/core_arch/src/powerpc/altivec.rs @@ -47,6 +47,54 @@ types! { pub struct vector_float(4 x f32); } +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for vector_bool_char { + #[inline] + fn from(value: m8x16) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for m8x16 { + #[inline] + fn from(value: vector_bool_char) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for vector_bool_short { + #[inline] + fn from(value: m16x8) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for m16x8 { + #[inline] + fn from(value: vector_bool_short) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for vector_bool_int { + #[inline] + fn from(value: m32x4) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for m32x4 { + #[inline] + fn from(value: vector_bool_int) -> Self { + unsafe { transmute(value) } + } +} + #[allow(improper_ctypes)] unsafe extern "C" { #[link_name = "llvm.ppc.altivec.lvx"] @@ -129,8 +177,6 @@ unsafe extern "C" { b: vector_signed_short, c: vector_signed_int, ) -> vector_signed_int; - #[link_name = "llvm.ppc.altivec.vnmsubfp"] - fn vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float; #[link_name = "llvm.ppc.altivec.vsum2sws"] fn vsum2sws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int; #[link_name = "llvm.ppc.altivec.vsum4ubs"] @@ -1881,9 +1927,9 @@ mod sealed { #[inline] #[target_feature(enable = "altivec")] - #[cfg_attr(test, assert_instr(vnmsubfp))] - unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float { - vnmsubfp(a, b, c) + #[cfg_attr(test, assert_instr(xvnmsubasp))] + pub unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float { + simd_neg(simd_fma(a, b, simd_neg(c))) } #[inline] @@ -3249,7 +3295,7 @@ mod sealed { unsafe fn vec_round(self) -> Self; } - test_impl! { vec_vrfin(a: vector_float) -> vector_float [vrfin, xvrspic] } + test_impl! { vec_vrfin(a: vector_float) -> vector_float [vrfin, vrfin] } #[unstable(feature = "stdarch_powerpc", issue = "111145")] impl VectorRound for vector_float { @@ -4281,7 +4327,7 @@ pub unsafe fn vec_madd(a: vector_float, b: vector_float, c: vector_float) -> vec #[target_feature(enable = "altivec")] #[unstable(feature = "stdarch_powerpc", issue = "111145")] pub unsafe fn vec_nmsub(a: vector_float, b: vector_float, c: vector_float) -> vector_float { - vnmsubfp(a, b, c) + sealed::vec_vnmsubfp(a, b, c) } /// Vector Select @@ -4653,22 +4699,22 @@ mod tests { }; { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); + let b: s_t_l!($ty) = $ty::new($($b),+).into(); let d = $ty_out::new($($d),+); - let r : $ty_out = transmute($fn(a, b)); + let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!(d, r); } }; { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); + let b: s_t_l!($ty) = $ty::new($($b),+).into(); - let r : $ty_out = transmute($fn(a, b)); + let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!($d, r); } } @@ -4677,11 +4723,11 @@ mod tests { macro_rules! test_vec_1 { { $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: vector_float = transmute(f32x4::new($($a),+)); + fn $name() { + let a = vector_float::from(f32x4::new($($a),+)); - let d: vector_float = transmute(f32x4::new($($d),+)); - let r = transmute(vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON))); + let d = vector_float::from(f32x4::new($($d),+)); + let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)) }); let e = m32x4::new(true, true, true, true); assert_eq!(e, r); } @@ -4691,18 +4737,18 @@ mod tests { }; { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); let d = $ty_out::new($($d),+); - let r : $ty_out = transmute($fn(a)); + let r = $ty_out::from(unsafe { $fn(a) }); assert_eq!(d, r); } } } #[simd_test(enable = "altivec")] - unsafe fn test_vec_ld() { + fn test_vec_ld() { let pat = [ u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), u8x16::new( @@ -4711,14 +4757,14 @@ mod tests { ]; for off in 0..16 { - let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off))); + let v = u8x16::from(unsafe { vec_ld(0, (pat.as_ptr() as *const u8).offset(off)) }); assert_eq!( v, u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) ); } for off in 16..32 { - let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off))); + let v = u8x16::from(unsafe { vec_ld(0, (pat.as_ptr() as *const u8).offset(off)) }); assert_eq!( v, u8x16::new( @@ -4729,7 +4775,7 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_xl() { + fn test_vec_xl() { let pat = [ u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), u8x16::new( @@ -4738,7 +4784,7 @@ mod tests { ]; for off in 0..16 { - let val: u8x16 = transmute(vec_xl(0, (pat.as_ptr() as *const u8).offset(off))); + let val = u8x16::from(unsafe { vec_xl(0, (pat.as_ptr() as *const u8).offset(off)) }); for i in 0..16 { let v = val.extract_dyn(i); assert_eq!(off as usize + i, v as usize); @@ -4747,14 +4793,16 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_xst() { - let v: vector_unsigned_char = transmute(u8x16::new( + fn test_vec_xst() { + let v = vector_unsigned_char::from(u8x16::new( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, )); for off in 0..16 { let mut buf = [0u8; 32]; - vec_xst(v, 0, (buf.as_mut_ptr() as *mut u8).offset(off)); + unsafe { + vec_xst(v, 0, (buf.as_mut_ptr() as *mut u8).offset(off)); + } for i in 0..16 { assert_eq!(i as u8, buf[off as usize..][i]); } @@ -4762,7 +4810,7 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_ldl() { + fn test_vec_ldl() { let pat = [ u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), u8x16::new( @@ -4771,14 +4819,14 @@ mod tests { ]; for off in 0..16 { - let v: u8x16 = transmute(vec_ldl(0, (pat.as_ptr() as *const u8).offset(off))); + let v = u8x16::from(unsafe { vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)) }); assert_eq!( v, u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) ); } for off in 16..32 { - let v: u8x16 = transmute(vec_ldl(0, (pat.as_ptr() as *const u8).offset(off))); + let v = u8x16::from(unsafe { vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)) }); assert_eq!( v, u8x16::new( @@ -4789,30 +4837,30 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_lde_u8() { + fn test_vec_lde_u8() { let pat = [u8x16::new( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, )]; for off in 0..16 { - let v: u8x16 = transmute(vec_lde(off, pat.as_ptr() as *const u8)); + let v = u8x16::from(unsafe { vec_lde(off, pat.as_ptr() as *const u8) }); assert_eq!(off as u8, v.extract_dyn(off as _)); } } #[simd_test(enable = "altivec")] - unsafe fn test_vec_lde_u16() { + fn test_vec_lde_u16() { let pat = [u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)]; for off in 0..8 { - let v: u16x8 = transmute(vec_lde(off * 2, pat.as_ptr() as *const u16)); + let v = u16x8::from(unsafe { vec_lde(off * 2, pat.as_ptr() as *const u16) }); assert_eq!(off as u16, v.extract_dyn(off as _)); } } #[simd_test(enable = "altivec")] - unsafe fn test_vec_lde_u32() { + fn test_vec_lde_u32() { let pat = [u32x4::new(0, 1, 2, 3)]; for off in 0..4 { - let v: u32x4 = transmute(vec_lde(off * 4, pat.as_ptr() as *const u32)); + let v = u32x4::from(unsafe { vec_lde(off * 4, pat.as_ptr() as *const u32) }); assert_eq!(off as u32, v.extract_dyn(off as _)); } } @@ -5818,9 +5866,9 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_cmpb() { - let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9)); - let b: vector_float = transmute(f32x4::new(-0.1, 0.5, -0.6, 0.9)); + fn test_vec_cmpb() { + let a = vector_float::from(f32x4::new(0.1, 0.5, 0.6, 0.9)); + let b = vector_float::from(f32x4::new(-0.1, 0.5, -0.6, 0.9)); let d = i32x4::new( -0b10000000000000000000000000000000, 0, @@ -5828,15 +5876,15 @@ mod tests { 0, ); - assert_eq!(d, transmute(vec_cmpb(a, b))); + assert_eq!(d, i32x4::from(unsafe { vec_cmpb(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_ceil() { - let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9)); + fn test_vec_ceil() { + let a = vector_float::from(f32x4::new(0.1, 0.5, 0.6, 0.9)); let d = f32x4::new(1.0, 1.0, 1.0, 1.0); - assert_eq!(d, transmute(vec_ceil(a))); + assert_eq!(d, f32x4::from(unsafe { vec_ceil(a) })); } test_vec_2! { test_vec_andc, vec_andc, i32x4, @@ -5926,11 +5974,11 @@ mod tests { macro_rules! test_vec_abs { { $name: ident, $ty: ident, $a: expr, $d: expr } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a = vec_splats($a); - let a: s_t_l!($ty) = vec_abs(a); + fn $name() { + let a = unsafe { vec_splats($a) }; + let a: s_t_l!($ty) = unsafe { vec_abs(a) }; let d = $ty::splat($d); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -5943,11 +5991,11 @@ mod tests { macro_rules! test_vec_abss { { $name: ident, $ty: ident, $a: expr, $d: expr } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a = vec_splats($a); - let a: s_t_l!($ty) = vec_abss(a); + fn $name() { + let a = unsafe { vec_splats($a) }; + let a: s_t_l!($ty) = unsafe { vec_abss(a) }; let d = $ty::splat($d); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -5959,10 +6007,10 @@ mod tests { macro_rules! test_vec_splats { { $name: ident, $ty: ident, $a: expr } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = vec_splats($a); + fn $name() { + let a: s_t_l!($ty) = unsafe { vec_splats($a) }; let d = $ty::splat($a); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -5978,10 +6026,10 @@ mod tests { macro_rules! test_vec_splat { { $name: ident, $fun: ident, $ty: ident, $a: expr, $b: expr} => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a = $fun::<$a>(); + fn $name() { + let a = unsafe { $fun::<$a>() }; let d = $ty::splat($b); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -6073,12 +6121,12 @@ mod tests { macro_rules! test_vec_min { { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); + let b: s_t_l!($ty) = $ty::new($($b),+).into(); let d = $ty::new($($d),+); - let r : $ty = transmute(vec_min(a, b)); + let r = $ty::from(unsafe { vec_min(a, b) }); assert_eq!(d, r); } } @@ -6117,12 +6165,12 @@ mod tests { macro_rules! test_vec_max { { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); + let b: s_t_l!($ty) = $ty::new($($b),+).into(); let d = $ty::new($($d),+); - let r : $ty = transmute(vec_max(a, b)); + let r = $ty::from(unsafe { vec_max(a, b) }); assert_eq!(d, r); } } @@ -6163,13 +6211,13 @@ mod tests { $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: $longtype = transmute($shorttype::new($($a),+)); - let b: $longtype = transmute($shorttype::new($($b),+)); - let c: vector_unsigned_char = transmute(u8x16::new($($c),+)); + fn $name() { + let a = $longtype::from($shorttype::new($($a),+)); + let b = $longtype::from($shorttype::new($($b),+)); + let c = vector_unsigned_char::from(u8x16::new($($c),+)); let d = $shorttype::new($($d),+); - let r: $shorttype = transmute(vec_perm(a, b, c)); + let r = $shorttype::from(unsafe { vec_perm(a, b, c) }); assert_eq!(d, r); } } @@ -6249,8 +6297,8 @@ mod tests { [0.0, 1.0, 1.0, 1.1]} #[simd_test(enable = "altivec")] - unsafe fn test_vec_madds() { - let a: vector_signed_short = transmute(i16x8::new( + fn test_vec_madds() { + let a = vector_signed_short::from(i16x8::new( 0 * 256, 1 * 256, 2 * 256, @@ -6260,19 +6308,19 @@ mod tests { 6 * 256, 7 * 256, )); - let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, 21); - assert_eq!(d, transmute(vec_madds(a, b, c))); + assert_eq!(d, i16x8::from(unsafe { vec_madds(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_madd_float() { - let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); - let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); - let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); + fn test_vec_madd_float() { + let a = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); + let b = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); + let c = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); let d = f32x4::new( 0.1 * 0.1 + 0.1, 0.2 * 0.2 + 0.2, @@ -6280,26 +6328,26 @@ mod tests { 0.4 * 0.4 + 0.4, ); - assert_eq!(d, transmute(vec_madd(a, b, c))); + assert_eq!(d, f32x4::from(unsafe { vec_madd(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_nmsub_float() { - let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); - let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); - let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); + fn test_vec_nmsub_float() { + let a = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); + let b = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); + let c = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); let d = f32x4::new( -(0.1 * 0.1 - 0.1), -(0.2 * 0.2 - 0.2), -(0.3 * 0.3 - 0.3), -(0.4 * 0.4 - 0.4), ); - assert_eq!(d, transmute(vec_nmsub(a, b, c))); + assert_eq!(d, f32x4::from(unsafe { vec_nmsub(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mradds() { - let a: vector_signed_short = transmute(i16x8::new( + fn test_vec_mradds() { + let a = vector_signed_short::from(i16x8::new( 0 * 256, 1 * 256, 2 * 256, @@ -6309,25 +6357,25 @@ mod tests { 6 * 256, 7 * 256, )); - let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1)); + let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1)); let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, i16::MAX); - assert_eq!(d, transmute(vec_mradds(a, b, c))); + assert_eq!(d, i16x8::from(unsafe { vec_mradds(a, b, c) })); } macro_rules! test_vec_mladd { {$name:ident, $sa:ident, $la:ident, $sbc:ident, $lbc:ident, $sd:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: $la = transmute($sa::new($($a),+)); - let b: $lbc = transmute($sbc::new($($b),+)); - let c = transmute($sbc::new($($c),+)); + fn $name() { + let a = $la::from($sa::new($($a),+)); + let b = $lbc::from($sbc::new($($b),+)); + let c = $sbc::new($($c),+).into(); let d = $sd::new($($d),+); - assert_eq!(d, transmute(vec_mladd(a, b, c))); + assert_eq!(d, $sd::from(unsafe { vec_mladd(a, b, c) })); } } } @@ -6335,24 +6383,24 @@ mod tests { test_vec_mladd! { test_vec_mladd_u16x8_u16x8, u16x8, vector_unsigned_short, u16x8, vector_unsigned_short, u16x8, [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56] } - test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_unsigned_short, i16x8, + test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_signed_short, i16x8, [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56] } test_vec_mladd! { test_vec_mladd_i16x8_u16x8, i16x8, vector_signed_short, u16x8, vector_unsigned_short, i16x8, [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56] } - test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_unsigned_short, i16x8, + test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_signed_short, i16x8, [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56] } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msum_unsigned_char() { - let a: vector_unsigned_char = - transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); - let b: vector_unsigned_char = transmute(u8x16::new( + fn test_vec_msum_unsigned_char() { + let a = + vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_unsigned_char::from(u8x16::new( 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, )); - let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3)); + let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3)); let d = u32x4::new( (0 + 1 + 2 + 3) * 255 + 0, (4 + 5 + 6 + 7) * 255 + 1, @@ -6360,17 +6408,17 @@ mod tests { (4 + 5 + 6 + 7) * 255 + 3, ); - assert_eq!(d, transmute(vec_msum(a, b, c))); + assert_eq!(d, u32x4::from(unsafe { vec_msum(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msum_signed_char() { - let a: vector_signed_char = transmute(i8x16::new( + fn test_vec_msum_signed_char() { + let a = vector_signed_char::from(i8x16::new( 0, -1, 2, -3, 1, -1, 1, -1, 0, 1, 2, 3, 4, -5, -6, -7, )); - let b: vector_unsigned_char = - transmute(i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)); - let c: vector_signed_int = transmute(u32x4::new(0, 1, 2, 3)); + let b = + vector_unsigned_char::from(u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)); + let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new( (0 - 1 + 2 - 3) + 0, (0) + 1, @@ -6378,11 +6426,12 @@ mod tests { (4 - 5 - 6 - 7) + 3, ); - assert_eq!(d, transmute(vec_msum(a, b, c))); + assert_eq!(d, i32x4::from(unsafe { vec_msum(a, b, c) })); } + #[simd_test(enable = "altivec")] - unsafe fn test_vec_msum_unsigned_short() { - let a: vector_unsigned_short = transmute(u16x8::new( + fn test_vec_msum_unsigned_short() { + let a = vector_unsigned_short::from(u16x8::new( 0 * 256, 1 * 256, 2 * 256, @@ -6392,9 +6441,8 @@ mod tests { 6 * 256, 7 * 256, )); - let b: vector_unsigned_short = - transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3)); + let b = vector_unsigned_short::from(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3)); let d = u32x4::new( (0 + 1) * 256 * 256 + 0, (2 + 3) * 256 * 256 + 1, @@ -6402,12 +6450,12 @@ mod tests { (6 + 7) * 256 * 256 + 3, ); - assert_eq!(d, transmute(vec_msum(a, b, c))); + assert_eq!(d, u32x4::from(unsafe { vec_msum(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msum_signed_short() { - let a: vector_signed_short = transmute(i16x8::new( + fn test_vec_msum_signed_short() { + let a = vector_signed_short::from(i16x8::new( 0 * 256, -1 * 256, 2 * 256, @@ -6417,8 +6465,8 @@ mod tests { 6 * 256, -7 * 256, )); - let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new( (0 - 1) * 256 * 256 + 0, (2 - 3) * 256 * 256 + 1, @@ -6426,12 +6474,12 @@ mod tests { (6 - 7) * 256 * 256 + 3, ); - assert_eq!(d, transmute(vec_msum(a, b, c))); + assert_eq!(d, i32x4::from(unsafe { vec_msum(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msums_unsigned() { - let a: vector_unsigned_short = transmute(u16x8::new( + fn test_vec_msums_unsigned() { + let a = vector_unsigned_short::from(u16x8::new( 0 * 256, 1 * 256, 2 * 256, @@ -6441,9 +6489,8 @@ mod tests { 6 * 256, 7 * 256, )); - let b: vector_unsigned_short = - transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3)); + let b = vector_unsigned_short::from(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3)); let d = u32x4::new( (0 + 1) * 256 * 256 + 0, (2 + 3) * 256 * 256 + 1, @@ -6451,12 +6498,12 @@ mod tests { (6 + 7) * 256 * 256 + 3, ); - assert_eq!(d, transmute(vec_msums(a, b, c))); + assert_eq!(d, u32x4::from(unsafe { vec_msums(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msums_signed() { - let a: vector_signed_short = transmute(i16x8::new( + fn test_vec_msums_signed() { + let a = vector_signed_short::from(i16x8::new( 0 * 256, -1 * 256, 2 * 256, @@ -6466,8 +6513,8 @@ mod tests { 6 * 256, -7 * 256, )); - let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new( (0 - 1) * 256 * 256 + 0, (2 - 3) * 256 * 256 + 1, @@ -6475,23 +6522,23 @@ mod tests { (6 - 7) * 256 * 256 + 3, ); - assert_eq!(d, transmute(vec_msums(a, b, c))); + assert_eq!(d, i32x4::from(unsafe { vec_msums(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_sum2s() { - let a: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); - let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + fn test_vec_sum2s() { + let a = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); + let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new(0, 0 + 1 + 1, 0, 2 + 3 + 3); - assert_eq!(d, transmute(vec_sum2s(a, b))); + assert_eq!(d, i32x4::from(unsafe { vec_sum2s(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_sum4s_unsigned_char() { - let a: vector_unsigned_char = - transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); - let b: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3)); + fn test_vec_sum4s_unsigned_char() { + let a = + vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3)); let d = u32x4::new( 0 + 1 + 2 + 3 + 0, 4 + 5 + 6 + 7 + 1, @@ -6499,13 +6546,13 @@ mod tests { 4 + 5 + 6 + 7 + 3, ); - assert_eq!(d, transmute(vec_sum4s(a, b))); + assert_eq!(d, u32x4::from(unsafe { vec_sum4s(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_sum4s_signed_char() { - let a: vector_signed_char = - transmute(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); - let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + fn test_vec_sum4s_signed_char() { + let a = + vector_signed_char::from(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new( 0 + 1 + 2 + 3 + 0, 4 + 5 + 6 + 7 + 1, @@ -6513,109 +6560,110 @@ mod tests { 4 + 5 + 6 + 7 + 3, ); - assert_eq!(d, transmute(vec_sum4s(a, b))); + assert_eq!(d, i32x4::from(unsafe { vec_sum4s(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_sum4s_signed_short() { - let a: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); - let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + fn test_vec_sum4s_signed_short() { + let a = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new(0 + 1 + 0, 2 + 3 + 1, 4 + 5 + 2, 6 + 7 + 3); - assert_eq!(d, transmute(vec_sum4s(a, b))); + assert_eq!(d, i32x4::from(unsafe { vec_sum4s(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mule_unsigned_char() { - let a: vector_unsigned_char = - transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + fn test_vec_mule_unsigned_char() { + let a = + vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); let d = u16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6); - assert_eq!(d, transmute(vec_mule(a, a))); + assert_eq!(d, u16x8::from(unsafe { vec_mule(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mule_signed_char() { - let a: vector_signed_char = transmute(i8x16::new( + fn test_vec_mule_signed_char() { + let a = vector_signed_char::from(i8x16::new( 0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7, )); let d = i16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6); - assert_eq!(d, transmute(vec_mule(a, a))); + assert_eq!(d, i16x8::from(unsafe { vec_mule(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mule_unsigned_short() { - let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); + fn test_vec_mule_unsigned_short() { + let a = vector_unsigned_short::from(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); let d = u32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6); - assert_eq!(d, transmute(vec_mule(a, a))); + assert_eq!(d, u32x4::from(unsafe { vec_mule(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mule_signed_short() { - let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7)); + fn test_vec_mule_signed_short() { + let a = vector_signed_short::from(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7)); let d = i32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6); - assert_eq!(d, transmute(vec_mule(a, a))); + assert_eq!(d, i32x4::from(unsafe { vec_mule(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mulo_unsigned_char() { - let a: vector_unsigned_char = - transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + fn test_vec_mulo_unsigned_char() { + let a = + vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); let d = u16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7); - assert_eq!(d, transmute(vec_mulo(a, a))); + assert_eq!(d, u16x8::from(unsafe { vec_mulo(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mulo_signed_char() { - let a: vector_signed_char = transmute(i8x16::new( + fn test_vec_mulo_signed_char() { + let a = vector_signed_char::from(i8x16::new( 0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7, )); let d = i16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7); - assert_eq!(d, transmute(vec_mulo(a, a))); + assert_eq!(d, i16x8::from(unsafe { vec_mulo(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mulo_unsigned_short() { - let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); + fn test_vec_mulo_unsigned_short() { + let a = vector_unsigned_short::from(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); let d = u32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7); - assert_eq!(d, transmute(vec_mulo(a, a))); + assert_eq!(d, u32x4::from(unsafe { vec_mulo(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mulo_signed_short() { - let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7)); + fn test_vec_mulo_signed_short() { + let a = vector_signed_short::from(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7)); let d = i32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7); - assert_eq!(d, transmute(vec_mulo(a, a))); + assert_eq!(d, i32x4::from(unsafe { vec_mulo(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn vec_add_i32x4_i32x4() { + fn vec_add_i32x4_i32x4() { let x = i32x4::new(1, 2, 3, 4); let y = i32x4::new(4, 3, 2, 1); - let x: vector_signed_int = transmute(x); - let y: vector_signed_int = transmute(y); - let z = vec_add(x, y); - assert_eq!(i32x4::splat(5), transmute(z)); + let x = vector_signed_int::from(x); + let y = vector_signed_int::from(y); + let z = unsafe { vec_add(x, y) }; + assert_eq!(i32x4::splat(5), i32x4::from(z)); } #[simd_test(enable = "altivec")] - unsafe fn vec_ctf_u32() { - let v: vector_unsigned_int = transmute(u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42)); - let v2 = vec_ctf::<1, _>(v); - let r2: vector_float = transmute(f32x4::new(0.0, 2147483600.0, 2147483600.0, 21.0)); - let v4 = vec_ctf::<2, _>(v); - let r4: vector_float = transmute(f32x4::new(0.0, 1073741800.0, 1073741800.0, 10.5)); - let v8 = vec_ctf::<3, _>(v); - let r8: vector_float = transmute(f32x4::new(0.0, 536870900.0, 536870900.0, 5.25)); + fn vec_ctf_u32() { + let v = vector_unsigned_int::from(u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42)); + let v2 = unsafe { vec_ctf::<1, _>(v) }; + let r2 = vector_float::from(f32x4::new(0.0, 2147483600.0, 2147483600.0, 21.0)); + let v4 = unsafe { vec_ctf::<2, _>(v) }; + let r4 = vector_float::from(f32x4::new(0.0, 1073741800.0, 1073741800.0, 10.5)); + let v8 = unsafe { vec_ctf::<3, _>(v) }; + let r8 = vector_float::from(f32x4::new(0.0, 536870900.0, 536870900.0, 5.25)); let check = |a, b| { - let r = transmute(vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON))); + let r = + m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) }); let e = m32x4::new(true, true, true, true); assert_eq!(e, r); }; @@ -6626,26 +6674,32 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_ctu() { + fn test_vec_ctu() { let v = u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42); - let v2: u32x4 = transmute(vec_ctu::<1>(transmute(f32x4::new( - 0.0, - 2147483600.0, - 2147483600.0, - 21.0, - )))); - let v4: u32x4 = transmute(vec_ctu::<2>(transmute(f32x4::new( - 0.0, - 1073741800.0, - 1073741800.0, - 10.5, - )))); - let v8: u32x4 = transmute(vec_ctu::<3>(transmute(f32x4::new( - 0.0, - 536870900.0, - 536870900.0, - 5.25, - )))); + let v2 = u32x4::from(unsafe { + vec_ctu::<1>(vector_float::from(f32x4::new( + 0.0, + 2147483600.0, + 2147483600.0, + 21.0, + ))) + }); + let v4 = u32x4::from(unsafe { + vec_ctu::<2>(vector_float::from(f32x4::new( + 0.0, + 1073741800.0, + 1073741800.0, + 10.5, + ))) + }); + let v8 = u32x4::from(unsafe { + vec_ctu::<3>(vector_float::from(f32x4::new( + 0.0, + 536870900.0, + 536870900.0, + 5.25, + ))) + }); assert_eq!(v2, v); assert_eq!(v4, v); @@ -6653,18 +6707,18 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn vec_ctf_i32() { - let v: vector_signed_int = transmute(i32x4::new(i32::MIN, i32::MAX, i32::MAX - 42, 42)); - let v2 = vec_ctf::<1, _>(v); - let r2: vector_float = - transmute(f32x4::new(-1073741800.0, 1073741800.0, 1073741800.0, 21.0)); - let v4 = vec_ctf::<2, _>(v); - let r4: vector_float = transmute(f32x4::new(-536870900.0, 536870900.0, 536870900.0, 10.5)); - let v8 = vec_ctf::<3, _>(v); - let r8: vector_float = transmute(f32x4::new(-268435460.0, 268435460.0, 268435460.0, 5.25)); + fn vec_ctf_i32() { + let v = vector_signed_int::from(i32x4::new(i32::MIN, i32::MAX, i32::MAX - 42, 42)); + let v2 = unsafe { vec_ctf::<1, _>(v) }; + let r2 = vector_float::from(f32x4::new(-1073741800.0, 1073741800.0, 1073741800.0, 21.0)); + let v4 = unsafe { vec_ctf::<2, _>(v) }; + let r4 = vector_float::from(f32x4::new(-536870900.0, 536870900.0, 536870900.0, 10.5)); + let v8 = unsafe { vec_ctf::<3, _>(v) }; + let r8 = vector_float::from(f32x4::new(-268435460.0, 268435460.0, 268435460.0, 5.25)); let check = |a, b| { - let r = transmute(vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON))); + let r = + m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) }); println!("{:?} {:?}", a, b); let e = m32x4::new(true, true, true, true); assert_eq!(e, r); @@ -6676,26 +6730,32 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_cts() { + fn test_vec_cts() { let v = i32x4::new(i32::MIN, i32::MAX, i32::MAX, 42); - let v2: i32x4 = transmute(vec_cts::<1>(transmute(f32x4::new( - -1073741800.0, - 1073741800.0, - 1073741800.0, - 21.0, - )))); - let v4: i32x4 = transmute(vec_cts::<2>(transmute(f32x4::new( - -536870900.0, - 536870900.0, - 536870900.0, - 10.5, - )))); - let v8: i32x4 = transmute(vec_cts::<3>(transmute(f32x4::new( - -268435460.0, - 268435460.0, - 268435460.0, - 5.25, - )))); + let v2 = i32x4::from(unsafe { + vec_cts::<1>(transmute(f32x4::new( + -1073741800.0, + 1073741800.0, + 1073741800.0, + 21.0, + ))) + }); + let v4 = i32x4::from(unsafe { + vec_cts::<2>(transmute(f32x4::new( + -536870900.0, + 536870900.0, + 536870900.0, + 10.5, + ))) + }); + let v8 = i32x4::from(unsafe { + vec_cts::<3>(transmute(f32x4::new( + -268435460.0, + 268435460.0, + 268435460.0, + 5.25, + ))) + }); assert_eq!(v2, v); assert_eq!(v4, v); diff --git a/stdarch/crates/core_arch/src/powerpc/vsx.rs b/stdarch/crates/core_arch/src/powerpc/vsx.rs index ca9fcaabe8b22..0aac236173401 100644 --- a/stdarch/crates/core_arch/src/powerpc/vsx.rs +++ b/stdarch/crates/core_arch/src/powerpc/vsx.rs @@ -9,6 +9,7 @@ #![allow(non_camel_case_types)] use crate::core_arch::powerpc::*; +use crate::core_arch::simd::*; #[cfg(test)] use stdarch_test::assert_instr; @@ -34,6 +35,22 @@ types! { // pub struct vector_unsigned___int128 = i128x1; } +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for vector_bool_long { + #[inline] + fn from(value: m64x2) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for m64x2 { + #[inline] + fn from(value: vector_bool_long) -> Self { + unsafe { transmute(value) } + } +} + #[allow(improper_ctypes)] unsafe extern "C" { #[link_name = "llvm.ppc.altivec.vperm"] @@ -46,7 +63,6 @@ unsafe extern "C" { mod sealed { use super::*; - use crate::core_arch::simd::*; #[unstable(feature = "stdarch_powerpc", issue = "111145")] pub trait VectorPermDI { @@ -221,14 +237,16 @@ mod tests { macro_rules! test_vec_xxpermdi { {$name:ident, $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "vsx")] - unsafe fn $name() { - let a: $longtype = transmute($shorttype::new($($a),+, $($b),+)); - let b = transmute($shorttype::new($($c),+, $($d),+)); - - assert_eq!($shorttype::new($($a),+, $($c),+), transmute(vec_xxpermdi::<_, 0>(a, b))); - assert_eq!($shorttype::new($($b),+, $($c),+), transmute(vec_xxpermdi::<_, 1>(a, b))); - assert_eq!($shorttype::new($($a),+, $($d),+), transmute(vec_xxpermdi::<_, 2>(a, b))); - assert_eq!($shorttype::new($($b),+, $($d),+), transmute(vec_xxpermdi::<_, 3>(a, b))); + fn $name() { + let a = $longtype::from($shorttype::new($($a),+, $($b),+)); + let b = $longtype::from($shorttype::new($($c),+, $($d),+)); + + unsafe { + assert_eq!($shorttype::new($($a),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 0>(a, b))); + assert_eq!($shorttype::new($($b),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 1>(a, b))); + assert_eq!($shorttype::new($($a),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 2>(a, b))); + assert_eq!($shorttype::new($($b),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 3>(a, b))); + } } } } diff --git a/stdarch/crates/core_arch/src/s390x/mod.rs b/stdarch/crates/core_arch/src/s390x/mod.rs index 7d3b3f2d99aae..5b85020072d87 100644 --- a/stdarch/crates/core_arch/src/s390x/mod.rs +++ b/stdarch/crates/core_arch/src/s390x/mod.rs @@ -2,6 +2,11 @@ pub(crate) mod macros; +/// the float and vector registers overlap therefore we cannot use any vector +/// extensions if softfloat is enabled. + +#[cfg(not(target_abi = "softfloat"))] mod vector; +#[cfg(not(target_abi = "softfloat"))] #[unstable(feature = "stdarch_s390x", issue = "130869")] pub use self::vector::*; diff --git a/stdarch/crates/core_arch/src/s390x/vector.rs b/stdarch/crates/core_arch/src/s390x/vector.rs index e1f841030c000..376c912c04090 100644 --- a/stdarch/crates/core_arch/src/s390x/vector.rs +++ b/stdarch/crates/core_arch/src/s390x/vector.rs @@ -51,6 +51,54 @@ types! { pub struct vector_double(2 x f64); } +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for vector_bool_char { + #[inline] + fn from(value: m8x16) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for m8x16 { + #[inline] + fn from(value: vector_bool_char) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for vector_bool_short { + #[inline] + fn from(value: m16x8) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for m16x8 { + #[inline] + fn from(value: vector_bool_short) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for vector_bool_int { + #[inline] + fn from(value: m32x4) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for m32x4 { + #[inline] + fn from(value: vector_bool_int) -> Self { + unsafe { transmute(value) } + } +} + #[repr(C, packed)] struct PackedTuple { x: T, @@ -287,6 +335,20 @@ unsafe extern "unadjusted" { #[link_name = "llvm.s390.vcfn"] fn vcfn(a: vector_signed_short, immarg: i32) -> vector_signed_short; #[link_name = "llvm.s390.vcnf"] fn vcnf(a: vector_signed_short, immarg: i32) -> vector_signed_short; #[link_name = "llvm.s390.vcrnfs"] fn vcrnfs(a: vector_float, b: vector_float, immarg: i32) -> vector_signed_short; + + // These are the intrinsics we'd like to use (with mode 0). However, they require + // "vector-enhancements-1" and don't have a fallback, whereas `vec_min`/`vec_max` should be + // available with just "vector". Therefore, we cannot use them. + // #[link_name = "llvm.s390.vfmaxsb"] fn vfmaxsb(a: vector_float, b: vector_float, mode: i32) -> vector_float; + // #[link_name = "llvm.s390.vfmaxdb"] fn vfmaxdb(a: vector_double, b: vector_double, mode: i32) -> vector_double; + // #[link_name = "llvm.s390.vfminsb"] fn vfminsb(a: vector_float, b: vector_float, mode: i32) -> vector_float; + // #[link_name = "llvm.s390.vfmindb"] fn vfmindb(a: vector_double, b: vector_double, mode: i32) -> vector_double; + // Instead, we use "portable" LLVM intrinsics -- even though those have the wrong semantics + // (https://github.com/rust-lang/stdarch/issues/2060), they usually do the right thing. + #[link_name = "llvm.minnum.v4f32"] fn minnum_v4f32(a: vector_float, b: vector_float) -> vector_float; + #[link_name = "llvm.minnum.v2f64"] fn minnum_v2f64(a: vector_double, b: vector_double) -> vector_double; + #[link_name = "llvm.maxnum.v4f32"] fn maxnum_v4f32(a: vector_float, b: vector_float) -> vector_float; + #[link_name = "llvm.maxnum.v2f64"] fn maxnum_v2f64(a: vector_double, b: vector_double) -> vector_double; } #[repr(simd)] @@ -732,8 +794,8 @@ mod sealed { impl_max!(vec_vmxslg, vector_unsigned_long_long, vmxlg); } - test_impl! { vec_vfmaxsb (a: vector_float, b: vector_float) -> vector_float [simd_fmax, "vector-enhancements-1" vfmaxsb ] } - test_impl! { vec_vfmaxdb (a: vector_double, b: vector_double) -> vector_double [simd_fmax, "vector-enhancements-1" vfmaxdb] } + test_impl! { vec_vfmaxsb (a: vector_float, b: vector_float) -> vector_float [maxnum_v4f32, "vector-enhancements-1" vfmaxsb] } + test_impl! { vec_vfmaxdb (a: vector_double, b: vector_double) -> vector_double [maxnum_v2f64, "vector-enhancements-1" vfmaxdb] } impl_vec_trait!([VectorMax vec_max] vec_vfmaxsb (vector_float, vector_float) -> vector_float); impl_vec_trait!([VectorMax vec_max] vec_vfmaxdb (vector_double, vector_double) -> vector_double); @@ -779,8 +841,8 @@ mod sealed { impl_min!(vec_vmnslg, vector_unsigned_long_long, vmnlg); } - test_impl! { vec_vfminsb (a: vector_float, b: vector_float) -> vector_float [simd_fmin, "vector-enhancements-1" vfminsb] } - test_impl! { vec_vfmindb (a: vector_double, b: vector_double) -> vector_double [simd_fmin, "vector-enhancements-1" vfmindb] } + test_impl! { vec_vfminsb (a: vector_float, b: vector_float) -> vector_float [minnum_v4f32, "vector-enhancements-1" vfminsb] } + test_impl! { vec_vfmindb (a: vector_double, b: vector_double) -> vector_double [minnum_v2f64, "vector-enhancements-1" vfmindb] } impl_vec_trait!([VectorMin vec_min] vec_vfminsb (vector_float, vector_float) -> vector_float); impl_vec_trait!([VectorMin vec_min] vec_vfmindb (vector_double, vector_double) -> vector_double); @@ -6051,27 +6113,16 @@ mod tests { } macro_rules! test_vec_1 { - { $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => { - #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: vector_float = transmute(f32x4::new($($a),+)); - - let d: vector_float = transmute(f32x4::new($($d),+)); - let r = transmute(vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON))); - let e = m32x4::new(true, true, true, true); - assert_eq!(e, r); - } - }; { $name: ident, $fn:ident, $ty: ident, [$($a:expr),+], [$($d:expr),+] } => { test_vec_1! { $name, $fn, $ty -> $ty, [$($a),+], [$($d),+] } }; { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); let d = $ty_out::new($($d),+); - let r : $ty_out = transmute($fn(a)); + let r = $ty_out::from(unsafe { $fn(a) }); assert_eq!(d, r); } } @@ -6086,35 +6137,23 @@ mod tests { }; { $name: ident, $fn:ident, $ty1: ident, $ty2: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: s_t_l!($ty1) = transmute($ty1::new($($a),+)); - let b: s_t_l!($ty2) = transmute($ty2::new($($b),+)); + fn $name() { + let a: s_t_l!($ty1) = $ty1::new($($a),+).into(); + let b: s_t_l!($ty2) = $ty2::new($($b),+).into(); let d = $ty_out::new($($d),+); - let r : $ty_out = transmute($fn(a, b)); + let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!(d, r); } }; - { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => { - #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); - - let r : $ty_out = transmute($fn(a, b)); - assert_eq!($d, r); - } - } } #[simd_test(enable = "vector")] - unsafe fn vec_add_i32x4_i32x4() { - let x = i32x4::new(1, 2, 3, 4); - let y = i32x4::new(4, 3, 2, 1); - let x: vector_signed_int = transmute(x); - let y: vector_signed_int = transmute(y); - let z = vec_add(x, y); - assert_eq!(i32x4::splat(5), transmute(z)); + fn vec_add_i32x4_i32x4() { + let x = vector_signed_int::from(i32x4::new(1, 2, 3, 4)); + let y = vector_signed_int::from(i32x4::new(4, 3, 2, 1)); + let z = unsafe { vec_add(x, y) }; + assert_eq!(i32x4::splat(5), i32x4::from(z)); } macro_rules! test_vec_sub { @@ -6232,11 +6271,11 @@ mod tests { macro_rules! test_vec_abs { { $name: ident, $ty: ident, $a: expr, $d: expr } => { #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: s_t_l!($ty) = vec_splats($a); - let a: s_t_l!($ty) = vec_abs(a); + fn $name() { + let a: s_t_l!($ty) = unsafe { vec_splats($a) }; + let a: s_t_l!($ty) = unsafe { vec_abs(a) }; let d = $ty::splat($d); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -6386,7 +6425,7 @@ mod tests { [0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 16], [4, 2, 1, 8] } - test_vec_2! { test_vec_sral_pos, vec_sral, u32x4, u8x16 -> i32x4, + test_vec_2! { test_vec_sral_pos, vec_sral, u32x4, u8x16 -> u32x4, [0b1000, 0b1000, 0b1000, 0b1000], [0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 16], [4, 2, 1, 8] } @@ -6423,13 +6462,13 @@ mod tests { $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: $longtype = transmute($shorttype::new($($a),+)); - let b: $longtype = transmute($shorttype::new($($b),+)); - let c: vector_unsigned_char = transmute(u8x16::new($($c),+)); + fn $name() { + let a = $longtype::from($shorttype::new($($a),+)); + let b = $longtype::from($shorttype::new($($b),+)); + let c = vector_unsigned_char::from(u8x16::new($($c),+)); let d = $shorttype::new($($d),+); - let r: $shorttype = transmute(vec_perm(a, b, c)); + let r = $shorttype::from(unsafe { vec_perm(a, b, c) }); assert_eq!(d, r); } } @@ -6512,46 +6551,46 @@ mod tests { [core::f32::consts::PI, 1.0, 25.0, 2.0], [core::f32::consts::PI.sqrt(), 1.0, 5.0, core::f32::consts::SQRT_2] } - test_vec_2! { test_vec_find_any_eq, vec_find_any_eq, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_eq, vec_find_any_eq, i32x4, i32x4 -> i32x4, [1, -2, 3, -4], [-5, 3, -7, 8], - [0, 0, 0xFFFFFFFF, 0] + [0, 0, !0, 0] } - test_vec_2! { test_vec_find_any_ne, vec_find_any_ne, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_ne, vec_find_any_ne, i32x4, i32x4 -> i32x4, [1, -2, 3, -4], [-5, 3, -7, 8], - [0xFFFFFFFF, 0xFFFFFFFF, 0, 0xFFFFFFFF] + [!0, !0, 0, !0] } - test_vec_2! { test_vec_find_any_eq_idx_1, vec_find_any_eq_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_eq_idx_1, vec_find_any_eq_idx, i32x4, i32x4 -> i32x4, [1, 2, 3, 4], [5, 3, 7, 8], [0, 8, 0, 0] } - test_vec_2! { test_vec_find_any_eq_idx_2, vec_find_any_eq_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_eq_idx_2, vec_find_any_eq_idx, i32x4, i32x4 -> i32x4, [1, 2, 3, 4], [5, 6, 7, 8], [0, 16, 0, 0] } - test_vec_2! { test_vec_find_any_ne_idx_1, vec_find_any_ne_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_ne_idx_1, vec_find_any_ne_idx, i32x4, i32x4 -> i32x4, [1, 2, 3, 4], [1, 5, 3, 4], [0, 4, 0, 0] } - test_vec_2! { test_vec_find_any_ne_idx_2, vec_find_any_ne_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_ne_idx_2, vec_find_any_ne_idx, i32x4, i32x4 -> i32x4, [1, 2, 3, 4], [1, 2, 3, 4], [0, 16, 0, 0] } - test_vec_2! { test_vec_find_any_eq_or_0_idx_1, vec_find_any_eq_or_0_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_eq_or_0_idx_1, vec_find_any_eq_or_0_idx, i32x4, i32x4 -> i32x4, [1, 2, 0, 4], [5, 6, 7, 8], [0, 8, 0, 0] } - test_vec_2! { test_vec_find_any_ne_or_0_idx_1, vec_find_any_ne_or_0_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_ne_or_0_idx_1, vec_find_any_ne_or_0_idx, i32x4, i32x4 -> i32x4, [1, 2, 0, 4], [1, 2, 3, 4], [0, 8, 0, 0] @@ -7452,6 +7491,30 @@ mod tests { [0, !0, !0, !0] } + test_vec_2! { test_vec_max_f32, vec_max, f32x4, f32x4 -> f32x4, + [1.0, f32::NAN, f32::INFINITY, 2.0], + [-10.0, -10.0, 5.0, f32::NAN], + [1.0, -10.0, f32::INFINITY, 2.0] + } + + test_vec_2! { test_vec_min_f32, vec_min, f32x4, f32x4 -> f32x4, + [1.0, f32::NAN, f32::INFINITY, 2.0], + [-10.0, -10.0, 5.0, f32::NAN], + [-10.0, -10.0, 5.0, 2.0] + } + + test_vec_2! { test_vec_max_f64, vec_max, f64x2, f64x2 -> f64x2, + [f64::NAN, 2.0], + [-10.0, f64::NAN], + [-10.0, 2.0] + } + + test_vec_2! { test_vec_min_f64, vec_min, f64x2, f64x2 -> f64x2, + [f64::NAN, 2.0], + [-10.0, f64::NAN], + [-10.0, 2.0] + } + #[simd_test(enable = "vector")] fn test_vec_meadd() { let a = vector_unsigned_short([1, 0, 2, 0, 3, 0, 4, 0]); diff --git a/stdarch/crates/core_arch/src/wasm32/simd128.rs b/stdarch/crates/core_arch/src/wasm32/simd128.rs index c864d6a516e08..e1a3754965907 100644 --- a/stdarch/crates/core_arch/src/wasm32/simd128.rs +++ b/stdarch/crates/core_arch/src/wasm32/simd128.rs @@ -86,10 +86,6 @@ unsafe extern "unadjusted" { fn llvm_i8x16_all_true(x: simd::i8x16) -> i32; #[link_name = "llvm.wasm.bitmask.v16i8"] fn llvm_bitmask_i8x16(a: simd::i8x16) -> i32; - #[link_name = "llvm.wasm.narrow.signed.v16i8.v8i16"] - fn llvm_narrow_i8x16_s(a: simd::i16x8, b: simd::i16x8) -> simd::i8x16; - #[link_name = "llvm.wasm.narrow.unsigned.v16i8.v8i16"] - fn llvm_narrow_i8x16_u(a: simd::i16x8, b: simd::i16x8) -> simd::i8x16; #[link_name = "llvm.wasm.avgr.unsigned.v16i8"] fn llvm_avgr_u_i8x16(a: simd::i8x16, b: simd::i8x16) -> simd::i8x16; @@ -103,10 +99,6 @@ unsafe extern "unadjusted" { fn llvm_i16x8_all_true(x: simd::i16x8) -> i32; #[link_name = "llvm.wasm.bitmask.v8i16"] fn llvm_bitmask_i16x8(a: simd::i16x8) -> i32; - #[link_name = "llvm.wasm.narrow.signed.v8i16.v4i32"] - fn llvm_narrow_i16x8_s(a: simd::i32x4, b: simd::i32x4) -> simd::i16x8; - #[link_name = "llvm.wasm.narrow.unsigned.v8i16.v4i32"] - fn llvm_narrow_i16x8_u(a: simd::i32x4, b: simd::i32x4) -> simd::i16x8; #[link_name = "llvm.wasm.avgr.unsigned.v8i16"] fn llvm_avgr_u_i16x8(a: simd::i16x8, b: simd::i16x8) -> simd::i16x8; @@ -2281,7 +2273,23 @@ pub use i8x16_bitmask as u8x16_bitmask; #[doc(alias("i8x16.narrow_i16x8_s"))] #[stable(feature = "wasm_simd", since = "1.54.0")] pub fn i8x16_narrow_i16x8(a: v128, b: v128) -> v128 { - unsafe { llvm_narrow_i8x16_s(a.as_i16x8(), b.as_i16x8()).v128() } + unsafe { + let v: simd::i16x16 = simd_shuffle!( + a.as_i16x8(), + b.as_i16x8(), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ); + + let max = simd_splat(i16::from(i8::MAX)); + let min = simd_splat(i16::from(i8::MIN)); + + let v = simd_select(simd_gt::<_, simd::i16x16>(v, max), max, v); + let v = simd_select(simd_lt::<_, simd::i16x16>(v, min), min, v); + + let v: simd::i8x16 = simd_cast(v); + + v.v128() + } } /// Converts two input vectors into a smaller lane vector by narrowing each @@ -2295,7 +2303,23 @@ pub fn i8x16_narrow_i16x8(a: v128, b: v128) -> v128 { #[doc(alias("i8x16.narrow_i16x8_u"))] #[stable(feature = "wasm_simd", since = "1.54.0")] pub fn u8x16_narrow_i16x8(a: v128, b: v128) -> v128 { - unsafe { llvm_narrow_i8x16_u(a.as_i16x8(), b.as_i16x8()).v128() } + unsafe { + let v: simd::i16x16 = simd_shuffle!( + a.as_i16x8(), + b.as_i16x8(), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ); + + let max = simd_splat(i16::from(u8::MAX)); + let min = simd_splat(i16::from(u8::MIN)); + + let v = simd_select(simd_gt::<_, simd::i16x16>(v, max), max, v); + let v = simd_select(simd_lt::<_, simd::i16x16>(v, min), min, v); + + let v: simd::u8x16 = simd_cast(v); + + v.v128() + } } /// Shifts each lane to the left by the specified number of bits. @@ -2593,7 +2617,19 @@ pub use i16x8_bitmask as u16x8_bitmask; #[doc(alias("i16x8.narrow_i32x4_s"))] #[stable(feature = "wasm_simd", since = "1.54.0")] pub fn i16x8_narrow_i32x4(a: v128, b: v128) -> v128 { - unsafe { llvm_narrow_i16x8_s(a.as_i32x4(), b.as_i32x4()).v128() } + unsafe { + let v: simd::i32x8 = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); + + let max = simd_splat(i32::from(i16::MAX)); + let min = simd_splat(i32::from(i16::MIN)); + + let v = simd_select(simd_gt::<_, simd::i32x8>(v, max), max, v); + let v = simd_select(simd_lt::<_, simd::i32x8>(v, min), min, v); + + let v: simd::i16x8 = simd_cast(v); + + v.v128() + } } /// Converts two input vectors into a smaller lane vector by narrowing each @@ -2607,7 +2643,19 @@ pub fn i16x8_narrow_i32x4(a: v128, b: v128) -> v128 { #[doc(alias("i16x8.narrow_i32x4_u"))] #[stable(feature = "wasm_simd", since = "1.54.0")] pub fn u16x8_narrow_i32x4(a: v128, b: v128) -> v128 { - unsafe { llvm_narrow_i16x8_u(a.as_i32x4(), b.as_i32x4()).v128() } + unsafe { + let v: simd::i32x8 = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); + + let max = simd_splat(i32::from(u16::MAX)); + let min = simd_splat(i32::from(u16::MIN)); + + let v = simd_select(simd_gt::<_, simd::i32x8>(v, max), max, v); + let v = simd_select(simd_lt::<_, simd::i32x8>(v, min), min, v); + + let v: simd::u16x8 = simd_cast(v); + + v.v128() + } } /// Converts low half of the smaller lane vector to a larger lane diff --git a/stdarch/crates/core_arch/src/x86/avx.rs b/stdarch/crates/core_arch/src/x86/avx.rs index 7b4b210bacf4c..74fc2db13dcdc 100644 --- a/stdarch/crates/core_arch/src/x86/avx.rs +++ b/stdarch/crates/core_arch/src/x86/avx.rs @@ -2426,7 +2426,6 @@ pub const fn _mm256_setzero_si256() -> __m256i { #[inline] #[target_feature(enable = "avx")] // This intrinsic has no corresponding instruction. -#[cfg_attr(test, assert_instr(vinsertf128))] #[stable(feature = "simd_x86", since = "1.27.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_set_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d { diff --git a/stdarch/crates/core_arch/src/x86/avx2.rs b/stdarch/crates/core_arch/src/x86/avx2.rs index 6a39a0aaf8feb..b49ad9522a412 100644 --- a/stdarch/crates/core_arch/src/x86/avx2.rs +++ b/stdarch/crates/core_arch/src/x86/avx2.rs @@ -991,7 +991,21 @@ pub const fn _mm256_hadd_epi32(a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vphaddsw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm256_hadds_epi16(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(phaddsw(a.as_i16x16(), b.as_i16x16())) } + let a = a.as_i16x16(); + let b = b.as_i16x16(); + unsafe { + let even: i16x16 = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 16, 18, 20, 22, 8, 10, 12, 14, 24, 26, 28, 30] + ); + let odd: i16x16 = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 17, 19, 21, 23, 9, 11, 13, 15, 25, 27, 29, 31] + ); + simd_saturating_add(even, odd).as_m256i() + } } /// Horizontally subtract adjacent pairs of 16-bit integers in `a` and `b`. @@ -1047,7 +1061,21 @@ pub const fn _mm256_hsub_epi32(a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vphsubsw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm256_hsubs_epi16(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(phsubsw(a.as_i16x16(), b.as_i16x16())) } + let a = a.as_i16x16(); + let b = b.as_i16x16(); + unsafe { + let even: i16x16 = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 16, 18, 20, 22, 8, 10, 12, 14, 24, 26, 28, 30] + ); + let odd: i16x16 = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 17, 19, 21, 23, 9, 11, 13, 15, 25, 27, 29, 31] + ); + simd_saturating_sub(even, odd).as_m256i() + } } /// Returns values from `slice` at offsets determined by `offsets * scale`, @@ -2287,7 +2315,7 @@ pub const fn _mm256_or_si256(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(simd_or(a.as_i32x8(), b.as_i32x8())) } } -/// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers +/// Converts packed signed 16-bit integers from `a` and `b` to packed 8-bit integers /// using signed saturation /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packs_epi16) @@ -2295,11 +2323,33 @@ pub const fn _mm256_or_si256(a: __m256i, b: __m256i) -> __m256i { #[target_feature(enable = "avx2")] #[cfg_attr(test, assert_instr(vpacksswb))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(packsswb(a.as_i16x16(), b.as_i16x16())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i { + unsafe { + let max = simd_splat(i8::MAX as i16); + let min = simd_splat(i8::MIN as i16); + + let clamped_a = simd_imax(simd_imin(a.as_i16x16(), max), min) + .as_m256i() + .as_i8x32(); + let clamped_b = simd_imax(simd_imin(b.as_i16x16(), max), min) + .as_m256i() + .as_i8x32(); + + #[rustfmt::skip] + const IDXS: [u32; 32] = [ + 00, 02, 04, 06, 08, 10, 12, 14, // a-lo i16 to i8 conversions + 32, 34, 36, 38, 40, 42, 44, 46, // b-lo + 16, 18, 20, 22, 24, 26, 28, 30, // a-hi + 48, 50, 52, 54, 56, 58, 60, 62, // b-hi + ]; + let result: i8x32 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m256i() + } } -/// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers +/// Converts packed signed 32-bit integers from `a` and `b` to packed 16-bit integers /// using signed saturation /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packs_epi32) @@ -2307,11 +2357,33 @@ pub fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i { #[target_feature(enable = "avx2")] #[cfg_attr(test, assert_instr(vpackssdw))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(packssdw(a.as_i32x8(), b.as_i32x8())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i { + unsafe { + let max = simd_splat(i16::MAX as i32); + let min = simd_splat(i16::MIN as i32); + + let clamped_a = simd_imax(simd_imin(a.as_i32x8(), max), min) + .as_m256i() + .as_i16x16(); + let clamped_b = simd_imax(simd_imin(b.as_i32x8(), max), min) + .as_m256i() + .as_i16x16(); + + #[rustfmt::skip] + const IDXS: [u32; 16] = [ + 00, 02, 04, 06, // a-lo i32 to i16 conversions + 16, 18, 20, 22, // b-lo + 08, 10, 12, 14, // a-hi + 24, 26, 28, 30, // b-hi + ]; + let result: i16x16 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m256i() + } } -/// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers +/// Converts packed signed 16-bit integers from `a` and `b` to packed 8-bit integers /// using unsigned saturation /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packus_epi16) @@ -2319,11 +2391,33 @@ pub fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i { #[target_feature(enable = "avx2")] #[cfg_attr(test, assert_instr(vpackuswb))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(packuswb(a.as_i16x16(), b.as_i16x16())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i { + unsafe { + let max = simd_splat(u8::MAX as i16); + let min = simd_splat(u8::MIN as i16); + + let clamped_a = simd_imax(simd_imin(a.as_i16x16(), max), min) + .as_m256i() + .as_i8x32(); + let clamped_b = simd_imax(simd_imin(b.as_i16x16(), max), min) + .as_m256i() + .as_i8x32(); + + #[rustfmt::skip] + const IDXS: [u32; 32] = [ + 00, 02, 04, 06, 08, 10, 12, 14, // a-lo i16 to u8 conversions + 32, 34, 36, 38, 40, 42, 44, 46, // b-lo + 16, 18, 20, 22, 24, 26, 28, 30, // a-hi + 48, 50, 52, 54, 56, 58, 60, 62, // b-hi + ]; + let result: i8x32 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m256i() + } } -/// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers +/// Converts packed signed 32-bit integers from `a` and `b` to packed 16-bit integers /// using unsigned saturation /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packus_epi32) @@ -2331,8 +2425,30 @@ pub fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i { #[target_feature(enable = "avx2")] #[cfg_attr(test, assert_instr(vpackusdw))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm256_packus_epi32(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(packusdw(a.as_i32x8(), b.as_i32x8())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_packus_epi32(a: __m256i, b: __m256i) -> __m256i { + unsafe { + let max = simd_splat(u16::MAX as i32); + let min = simd_splat(u16::MIN as i32); + + let clamped_a = simd_imax(simd_imin(a.as_i32x8(), max), min) + .as_m256i() + .as_i16x16(); + let clamped_b = simd_imax(simd_imin(b.as_i32x8(), max), min) + .as_m256i() + .as_i16x16(); + + #[rustfmt::skip] + const IDXS: [u32; 16] = [ + 00, 02, 04, 06, // a-lo i32 to u16 conversions + 16, 18, 20, 22, // b-lo + 08, 10, 12, 14, // a-hi + 24, 26, 28, 30, // b-hi + ]; + let result: i16x16 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m256i() + } } /// Permutes packed 32-bit integers from `a` according to the content of `b`. @@ -3791,10 +3907,6 @@ pub const fn _mm256_extract_epi16(a: __m256i) -> i32 { #[allow(improper_ctypes)] unsafe extern "C" { - #[link_name = "llvm.x86.avx2.phadd.sw"] - fn phaddsw(a: i16x16, b: i16x16) -> i16x16; - #[link_name = "llvm.x86.avx2.phsub.sw"] - fn phsubsw(a: i16x16, b: i16x16) -> i16x16; #[link_name = "llvm.x86.avx2.pmadd.wd"] fn pmaddwd(a: i16x16, b: i16x16) -> i32x8; #[link_name = "llvm.x86.avx2.pmadd.ub.sw"] @@ -3803,14 +3915,6 @@ unsafe extern "C" { fn mpsadbw(a: u8x32, b: u8x32, imm8: i8) -> u16x16; #[link_name = "llvm.x86.avx2.pmul.hr.sw"] fn pmulhrsw(a: i16x16, b: i16x16) -> i16x16; - #[link_name = "llvm.x86.avx2.packsswb"] - fn packsswb(a: i16x16, b: i16x16) -> i8x32; - #[link_name = "llvm.x86.avx2.packssdw"] - fn packssdw(a: i32x8, b: i32x8) -> i16x16; - #[link_name = "llvm.x86.avx2.packuswb"] - fn packuswb(a: i16x16, b: i16x16) -> u8x32; - #[link_name = "llvm.x86.avx2.packusdw"] - fn packusdw(a: i32x8, b: i32x8) -> u16x16; #[link_name = "llvm.x86.avx2.psad.bw"] fn psadbw(a: u8x32, b: u8x32) -> u64x4; #[link_name = "llvm.x86.avx2.psign.b"] @@ -4653,6 +4757,26 @@ mod tests { assert_eq_m256i(r, e); } + #[target_feature(enable = "avx2")] + #[cfg_attr(test, assert_instr(vpmaddwd))] + unsafe fn test_mm256_madd_epi16_mul_one(v: __m256i) -> __m256i { + // This is a trick used in the adler32 algorithm to get a widening addition. The + // multiplication by 1 is trivial, but must not be optimized out because then the vpmaddwd + // instruction is no longer selected. The assert_instr verifies that this is the case. + let one_v = _mm256_set1_epi16(1); + _mm256_madd_epi16(v, one_v) + } + + #[target_feature(enable = "avx2")] + #[cfg_attr(test, assert_instr(vpmaddwd))] + unsafe fn test_mm256_madd_epi16_shl(v: __m256i) -> __m256i { + // This is a trick used in the base64 algorithm to get a widening addition. Instead of a + // multiplication, a vector shl is used. In LLVM 22 that breaks the pattern recognition + // for the automatic optimization to vpmaddwd. + let shift_value = _mm256_set1_epi32(12i32); + _mm256_madd_epi16(v, shift_value) + } + #[simd_test(enable = "avx2")] const fn test_mm256_inserti128_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); @@ -4944,7 +5068,7 @@ mod tests { } #[simd_test(enable = "avx2")] - fn test_mm256_packs_epi16() { + const fn test_mm256_packs_epi16() { let a = _mm256_set1_epi16(2); let b = _mm256_set1_epi16(4); let r = _mm256_packs_epi16(a, b); @@ -4960,7 +5084,7 @@ mod tests { } #[simd_test(enable = "avx2")] - fn test_mm256_packs_epi32() { + const fn test_mm256_packs_epi32() { let a = _mm256_set1_epi32(2); let b = _mm256_set1_epi32(4); let r = _mm256_packs_epi32(a, b); @@ -4970,7 +5094,7 @@ mod tests { } #[simd_test(enable = "avx2")] - fn test_mm256_packus_epi16() { + const fn test_mm256_packus_epi16() { let a = _mm256_set1_epi16(2); let b = _mm256_set1_epi16(4); let r = _mm256_packus_epi16(a, b); @@ -4986,7 +5110,7 @@ mod tests { } #[simd_test(enable = "avx2")] - fn test_mm256_packus_epi32() { + const fn test_mm256_packus_epi32() { let a = _mm256_set1_epi32(2); let b = _mm256_set1_epi32(4); let r = _mm256_packus_epi32(a, b); diff --git a/stdarch/crates/core_arch/src/x86/avx512bw.rs b/stdarch/crates/core_arch/src/x86/avx512bw.rs index 8e074fdcfa486..659d6c3be88e7 100644 --- a/stdarch/crates/core_arch/src/x86/avx512bw.rs +++ b/stdarch/crates/core_arch/src/x86/avx512bw.rs @@ -6523,8 +6523,34 @@ pub fn _mm_maskz_maddubs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] -pub fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpackssdw(a.as_i32x16(), b.as_i32x16())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i { + unsafe { + let max = simd_splat(i16::MAX as i32); + let min = simd_splat(i16::MIN as i32); + + let clamped_a = simd_imax(simd_imin(a.as_i32x16(), max), min) + .as_m512i() + .as_i16x32(); + let clamped_b = simd_imax(simd_imin(b.as_i32x16(), max), min) + .as_m512i() + .as_i16x32(); + + #[rustfmt::skip] + const IDXS: [u32; 32] = [ + 00, 02, 04, 06, + 32, 34, 36, 38, + 08, 10, 12, 14, + 40, 42, 44, 46, + 16, 18, 20, 22, + 48, 50, 52, 54, + 24, 26, 28, 30, + 56, 58, 60, 62, + ]; + let result: i16x32 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m512i() + } } /// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -6534,7 +6560,13 @@ pub fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] -pub fn _mm512_mask_packs_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_mask_packs_epi32( + src: __m512i, + k: __mmask32, + a: __m512i, + b: __m512i, +) -> __m512i { unsafe { let pack = _mm512_packs_epi32(a, b).as_i16x32(); transmute(simd_select_bitmask(k, pack, src.as_i16x32())) @@ -6548,7 +6580,8 @@ pub fn _mm512_mask_packs_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m512 #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] -pub fn _mm512_maskz_packs_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_maskz_packs_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { let pack = _mm512_packs_epi32(a, b).as_i16x32(); transmute(simd_select_bitmask(k, pack, i16x32::ZERO)) @@ -6562,7 +6595,13 @@ pub fn _mm512_maskz_packs_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] -pub fn _mm256_mask_packs_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_mask_packs_epi32( + src: __m256i, + k: __mmask16, + a: __m256i, + b: __m256i, +) -> __m256i { unsafe { let pack = _mm256_packs_epi32(a, b).as_i16x16(); transmute(simd_select_bitmask(k, pack, src.as_i16x16())) @@ -6590,7 +6629,8 @@ pub fn _mm256_maskz_packs_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] -pub fn _mm_mask_packs_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_mask_packs_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packs_epi32(a, b).as_i16x8(); transmute(simd_select_bitmask(k, pack, src.as_i16x8())) @@ -6604,7 +6644,8 @@ pub fn _mm_mask_packs_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) - #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] -pub fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packs_epi32(a, b).as_i16x8(); transmute(simd_select_bitmask(k, pack, i16x8::ZERO)) @@ -6618,8 +6659,34 @@ pub fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpacksswb(a.as_i16x32(), b.as_i16x32())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i { + unsafe { + let max = simd_splat(i8::MAX as i16); + let min = simd_splat(i8::MIN as i16); + + let clamped_a = simd_imax(simd_imin(a.as_i16x32(), max), min) + .as_m512i() + .as_i8x64(); + let clamped_b = simd_imax(simd_imin(b.as_i16x32(), max), min) + .as_m512i() + .as_i8x64(); + + #[rustfmt::skip] + const IDXS: [u32; 64] = [ + 000, 002, 004, 006, 008, 010, 012, 014, + 064, 066, 068, 070, 072, 074, 076, 078, + 016, 018, 020, 022, 024, 026, 028, 030, + 080, 082, 084, 086, 088, 090, 092, 094, + 032, 034, 036, 038, 040, 042, 044, 046, + 096, 098, 100, 102, 104, 106, 108, 110, + 048, 050, 052, 054, 056, 058, 060, 062, + 112, 114, 116, 118, 120, 122, 124, 126, + ]; + let result: i8x64 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m512i() + } } /// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -6629,7 +6696,13 @@ pub fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm512_mask_packs_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_mask_packs_epi16( + src: __m512i, + k: __mmask64, + a: __m512i, + b: __m512i, +) -> __m512i { unsafe { let pack = _mm512_packs_epi16(a, b).as_i8x64(); transmute(simd_select_bitmask(k, pack, src.as_i8x64())) @@ -6643,7 +6716,8 @@ pub fn _mm512_mask_packs_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m512 #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm512_maskz_packs_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_maskz_packs_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { let pack = _mm512_packs_epi16(a, b).as_i8x64(); transmute(simd_select_bitmask(k, pack, i8x64::ZERO)) @@ -6657,7 +6731,13 @@ pub fn _mm512_maskz_packs_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm256_mask_packs_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_mask_packs_epi16( + src: __m256i, + k: __mmask32, + a: __m256i, + b: __m256i, +) -> __m256i { unsafe { let pack = _mm256_packs_epi16(a, b).as_i8x32(); transmute(simd_select_bitmask(k, pack, src.as_i8x32())) @@ -6671,7 +6751,8 @@ pub fn _mm256_mask_packs_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m256 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm256_maskz_packs_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_maskz_packs_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { let pack = _mm256_packs_epi16(a, b).as_i8x32(); transmute(simd_select_bitmask(k, pack, i8x32::ZERO)) @@ -6685,7 +6766,8 @@ pub fn _mm256_maskz_packs_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm_mask_packs_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_mask_packs_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packs_epi16(a, b).as_i8x16(); transmute(simd_select_bitmask(k, pack, src.as_i8x16())) @@ -6699,7 +6781,8 @@ pub fn _mm_mask_packs_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] -pub fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packs_epi16(a, b).as_i8x16(); transmute(simd_select_bitmask(k, pack, i8x16::ZERO)) @@ -6713,8 +6796,34 @@ pub fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpackusdw(a.as_i32x16(), b.as_i32x16())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i { + unsafe { + let max = simd_splat(u16::MAX as i32); + let min = simd_splat(u16::MIN as i32); + + let clamped_a = simd_imax(simd_imin(a.as_i32x16(), max), min) + .as_m512i() + .as_i16x32(); + let clamped_b = simd_imax(simd_imin(b.as_i32x16(), max), min) + .as_m512i() + .as_i16x32(); + + #[rustfmt::skip] + const IDXS: [u32; 32] = [ + 00, 02, 04, 06, + 32, 34, 36, 38, + 08, 10, 12, 14, + 40, 42, 44, 46, + 16, 18, 20, 22, + 48, 50, 52, 54, + 24, 26, 28, 30, + 56, 58, 60, 62, + ]; + let result: i16x32 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m512i() + } } /// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -6724,7 +6833,13 @@ pub fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm512_mask_packus_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_mask_packus_epi32( + src: __m512i, + k: __mmask32, + a: __m512i, + b: __m512i, +) -> __m512i { unsafe { let pack = _mm512_packus_epi32(a, b).as_i16x32(); transmute(simd_select_bitmask(k, pack, src.as_i16x32())) @@ -6738,7 +6853,8 @@ pub fn _mm512_mask_packus_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m51 #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm512_maskz_packus_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_maskz_packus_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { let pack = _mm512_packus_epi32(a, b).as_i16x32(); transmute(simd_select_bitmask(k, pack, i16x32::ZERO)) @@ -6752,7 +6868,13 @@ pub fn _mm512_maskz_packus_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm256_mask_packus_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_mask_packus_epi32( + src: __m256i, + k: __mmask16, + a: __m256i, + b: __m256i, +) -> __m256i { unsafe { let pack = _mm256_packus_epi32(a, b).as_i16x16(); transmute(simd_select_bitmask(k, pack, src.as_i16x16())) @@ -6766,7 +6888,8 @@ pub fn _mm256_mask_packus_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m25 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm256_maskz_packus_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_maskz_packus_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { let pack = _mm256_packus_epi32(a, b).as_i16x16(); transmute(simd_select_bitmask(k, pack, i16x16::ZERO)) @@ -6780,7 +6903,8 @@ pub fn _mm256_maskz_packus_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm_mask_packus_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_mask_packus_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packus_epi32(a, b).as_i16x8(); transmute(simd_select_bitmask(k, pack, src.as_i16x8())) @@ -6794,7 +6918,8 @@ pub fn _mm_mask_packus_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] -pub fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packus_epi32(a, b).as_i16x8(); transmute(simd_select_bitmask(k, pack, i16x8::ZERO)) @@ -6808,8 +6933,34 @@ pub fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpackuswb(a.as_i16x32(), b.as_i16x32())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i { + unsafe { + let max = simd_splat(u8::MAX as i16); + let min = simd_splat(u8::MIN as i16); + + let clamped_a = simd_imax(simd_imin(a.as_i16x32(), max), min) + .as_m512i() + .as_i8x64(); + let clamped_b = simd_imax(simd_imin(b.as_i16x32(), max), min) + .as_m512i() + .as_i8x64(); + + #[rustfmt::skip] + const IDXS: [u32; 64] = [ + 000, 002, 004, 006, 008, 010, 012, 014, + 064, 066, 068, 070, 072, 074, 076, 078, + 016, 018, 020, 022, 024, 026, 028, 030, + 080, 082, 084, 086, 088, 090, 092, 094, + 032, 034, 036, 038, 040, 042, 044, 046, + 096, 098, 100, 102, 104, 106, 108, 110, + 048, 050, 052, 054, 056, 058, 060, 062, + 112, 114, 116, 118, 120, 122, 124, 126, + ]; + let result: i8x64 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m512i() + } } /// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -6819,7 +6970,13 @@ pub fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm512_mask_packus_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_mask_packus_epi16( + src: __m512i, + k: __mmask64, + a: __m512i, + b: __m512i, +) -> __m512i { unsafe { let pack = _mm512_packus_epi16(a, b).as_i8x64(); transmute(simd_select_bitmask(k, pack, src.as_i8x64())) @@ -6833,7 +6990,8 @@ pub fn _mm512_mask_packus_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m51 #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm512_maskz_packus_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm512_maskz_packus_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { let pack = _mm512_packus_epi16(a, b).as_i8x64(); transmute(simd_select_bitmask(k, pack, i8x64::ZERO)) @@ -6847,7 +7005,13 @@ pub fn _mm512_maskz_packus_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm256_mask_packus_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_mask_packus_epi16( + src: __m256i, + k: __mmask32, + a: __m256i, + b: __m256i, +) -> __m256i { unsafe { let pack = _mm256_packus_epi16(a, b).as_i8x32(); transmute(simd_select_bitmask(k, pack, src.as_i8x32())) @@ -6861,7 +7025,8 @@ pub fn _mm256_mask_packus_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m25 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm256_maskz_packus_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm256_maskz_packus_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { let pack = _mm256_packus_epi16(a, b).as_i8x32(); transmute(simd_select_bitmask(k, pack, i8x32::ZERO)) @@ -6875,7 +7040,8 @@ pub fn _mm256_maskz_packus_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256 #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm_mask_packus_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_mask_packus_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packus_epi16(a, b).as_i8x16(); transmute(simd_select_bitmask(k, pack, src.as_i8x16())) @@ -6889,7 +7055,8 @@ pub fn _mm_mask_packus_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] -pub fn _mm_maskz_packus_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_maskz_packus_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { let pack = _mm_packus_epi16(a, b).as_i8x16(); transmute(simd_select_bitmask(k, pack, i8x16::ZERO)) @@ -11586,7 +11753,7 @@ pub const fn _mm_maskz_cvtepi16_epi8(k: __mmask8, a: __m128i) -> __m128i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i { unsafe { simd_cast::<_, i8x32>(simd_imax( @@ -11604,7 +11771,7 @@ pub const fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i { unsafe { simd_select_bitmask(k, _mm512_cvtsepi16_epi8(a).as_i8x32(), src.as_i8x32()).as_m256i() @@ -11618,7 +11785,7 @@ pub const fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { unsafe { simd_select_bitmask(k, _mm512_cvtsepi16_epi8(a).as_i8x32(), i8x32::ZERO).as_m256i() } } @@ -11630,7 +11797,7 @@ pub const fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i { unsafe { simd_cast::<_, i8x16>(simd_imax( @@ -11648,7 +11815,7 @@ pub const fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i { #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i { unsafe { simd_select_bitmask(k, _mm256_cvtsepi16_epi8(a).as_i8x16(), src.as_i8x16()).as_m128i() @@ -11662,7 +11829,7 @@ pub const fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_cvtsepi16_epi8(k: __mmask16, a: __m256i) -> __m128i { unsafe { simd_select_bitmask(k, _mm256_cvtsepi16_epi8(a).as_i8x16(), i8x16::ZERO).as_m128i() } } @@ -11707,7 +11874,7 @@ pub fn _mm_maskz_cvtsepi16_epi8(k: __mmask8, a: __m128i) -> __m128i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i { unsafe { simd_cast::<_, u8x32>(simd_imin(a.as_u16x32(), u16x32::splat(u8::MAX as _))).as_m256i() @@ -11721,7 +11888,7 @@ pub const fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i { #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i { unsafe { simd_select_bitmask(k, _mm512_cvtusepi16_epi8(a).as_u8x32(), src.as_u8x32()).as_m256i() @@ -11735,7 +11902,7 @@ pub const fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { unsafe { simd_select_bitmask(k, _mm512_cvtusepi16_epi8(a).as_u8x32(), u8x32::ZERO).as_m256i() } } @@ -11747,7 +11914,7 @@ pub const fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i { unsafe { simd_cast::<_, u8x16>(simd_imin(a.as_u16x16(), u16x16::splat(u8::MAX as _))).as_m128i() @@ -11761,7 +11928,7 @@ pub const fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i { #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i { unsafe { simd_select_bitmask(k, _mm256_cvtusepi16_epi8(a).as_u8x16(), src.as_u8x16()).as_m128i() @@ -11775,7 +11942,7 @@ pub const fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_cvtusepi16_epi8(k: __mmask16, a: __m256i) -> __m128i { unsafe { simd_select_bitmask(k, _mm256_cvtusepi16_epi8(a).as_u8x16(), u8x16::ZERO).as_m128i() } } @@ -12476,7 +12643,14 @@ pub unsafe fn _mm512_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub unsafe fn _mm256_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) { - vpmovswbmem256(mem_addr, a.as_i16x16(), k); + let mask = simd_select_bitmask(k, i16x16::splat(!0), i16x16::ZERO); + + let max = simd_splat(i16::from(i8::MAX)); + let min = simd_splat(i16::from(i8::MIN)); + + let v = simd_imax(simd_imin(a.as_i16x16(), max), min); + let truncated: i8x16 = simd_cast(v); + simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated); } /// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr. @@ -12487,7 +12661,14 @@ pub unsafe fn _mm256_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub unsafe fn _mm_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { - vpmovswbmem128(mem_addr, a.as_i16x8(), k); + let mask = simd_select_bitmask(k, i16x8::splat(!0), i16x8::ZERO); + + let max = simd_splat(i16::from(i8::MAX)); + let min = simd_splat(i16::from(i8::MIN)); + + let v = simd_imax(simd_imin(a.as_i16x8(), max), min); + let truncated: i8x8 = simd_cast(v); + simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated); } /// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr. @@ -12497,7 +12678,7 @@ pub unsafe fn _mm_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: #[target_feature(enable = "avx512bw")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, a: __m512i) { let result = _mm512_cvtepi16_epi8(a).as_i8x32(); let mask = simd_select_bitmask(k, i8x32::splat(!0), i8x32::ZERO); @@ -12511,7 +12692,7 @@ pub const unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mma #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) { let result = _mm256_cvtepi16_epi8(a).as_i8x16(); let mask = simd_select_bitmask(k, i8x16::splat(!0), i8x16::ZERO); @@ -12525,7 +12706,7 @@ pub const unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mma #[target_feature(enable = "avx512bw,avx512vl")] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] -#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")] +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const unsafe fn _mm_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { let result: i8x8 = simd_shuffle!( _mm_cvtepi16_epi8(a).as_i8x16(), @@ -12555,7 +12736,12 @@ pub unsafe fn _mm512_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub unsafe fn _mm256_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) { - vpmovuswbmem256(mem_addr, a.as_i16x16(), k); + let mask = simd_select_bitmask(k, i16x16::splat(!0), i16x16::ZERO); + let mem_addr = mem_addr.cast::(); + let max = simd_splat(u16::from(u8::MAX)); + + let truncated: u8x16 = simd_cast(simd_imin(a.as_u16x16(), max)); + simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated); } /// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr. @@ -12566,7 +12752,15 @@ pub unsafe fn _mm256_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub unsafe fn _mm_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { - vpmovuswbmem128(mem_addr, a.as_i16x8(), k); + let mask = simd_select_bitmask(k, i16x8::splat(!0), i16x8::ZERO); + let mem_addr = mem_addr.cast::(); + let max = simd_splat(u16::from(u8::MAX)); + + let v = a.as_u16x8(); + let v = simd_imin(v, max); + + let truncated: u8x8 = simd_cast(v); + simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated); } #[allow(improper_ctypes)] @@ -12579,15 +12773,6 @@ unsafe extern "C" { #[link_name = "llvm.x86.avx512.pmaddubs.w.512"] fn vpmaddubsw(a: u8x64, b: i8x64) -> i16x32; - #[link_name = "llvm.x86.avx512.packssdw.512"] - fn vpackssdw(a: i32x16, b: i32x16) -> i16x32; - #[link_name = "llvm.x86.avx512.packsswb.512"] - fn vpacksswb(a: i16x32, b: i16x32) -> i8x64; - #[link_name = "llvm.x86.avx512.packusdw.512"] - fn vpackusdw(a: i32x16, b: i32x16) -> u16x32; - #[link_name = "llvm.x86.avx512.packuswb.512"] - fn vpackuswb(a: i16x32, b: i16x32) -> u8x64; - #[link_name = "llvm.x86.avx512.psll.w.512"] fn vpsllw(a: i16x32, count: i16x8) -> i16x32; @@ -12632,17 +12817,9 @@ unsafe extern "C" { #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.512"] fn vpmovswbmem(mem_addr: *mut i8, a: i16x32, mask: u32); - #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.256"] - fn vpmovswbmem256(mem_addr: *mut i8, a: i16x16, mask: u16); - #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.128"] - fn vpmovswbmem128(mem_addr: *mut i8, a: i16x8, mask: u8); #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.512"] fn vpmovuswbmem(mem_addr: *mut i8, a: i16x32, mask: u32); - #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.256"] - fn vpmovuswbmem256(mem_addr: *mut i8, a: i16x16, mask: u16); - #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.128"] - fn vpmovuswbmem128(mem_addr: *mut i8, a: i16x8, mask: u8); } #[cfg(test)] @@ -17683,7 +17860,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_packs_epi32() { + const fn test_mm512_packs_epi32() { let a = _mm512_set1_epi32(i32::MAX); let b = _mm512_set1_epi32(1); let r = _mm512_packs_epi32(a, b); @@ -17694,7 +17871,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_mask_packs_epi32() { + const fn test_mm512_mask_packs_epi32() { let a = _mm512_set1_epi32(i32::MAX); let b = _mm512_set1_epi32(1 << 16 | 1); let r = _mm512_mask_packs_epi32(a, 0, a, b); @@ -17707,7 +17884,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_maskz_packs_epi32() { + const fn test_mm512_maskz_packs_epi32() { let a = _mm512_set1_epi32(i32::MAX); let b = _mm512_set1_epi32(1); let r = _mm512_maskz_packs_epi32(0, a, b); @@ -17720,7 +17897,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_mask_packs_epi32() { + const fn test_mm256_mask_packs_epi32() { let a = _mm256_set1_epi32(i32::MAX); let b = _mm256_set1_epi32(1 << 16 | 1); let r = _mm256_mask_packs_epi32(a, 0, a, b); @@ -17744,7 +17921,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_mask_packs_epi32() { + const fn test_mm_mask_packs_epi32() { let a = _mm_set1_epi32(i32::MAX); let b = _mm_set1_epi32(1 << 16 | 1); let r = _mm_mask_packs_epi32(a, 0, a, b); @@ -17755,7 +17932,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_maskz_packs_epi32() { + const fn test_mm_maskz_packs_epi32() { let a = _mm_set1_epi32(i32::MAX); let b = _mm_set1_epi32(1); let r = _mm_maskz_packs_epi32(0, a, b); @@ -17766,7 +17943,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_packs_epi16() { + const fn test_mm512_packs_epi16() { let a = _mm512_set1_epi16(i16::MAX); let b = _mm512_set1_epi16(1); let r = _mm512_packs_epi16(a, b); @@ -17779,7 +17956,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_mask_packs_epi16() { + const fn test_mm512_mask_packs_epi16() { let a = _mm512_set1_epi16(i16::MAX); let b = _mm512_set1_epi16(1 << 8 | 1); let r = _mm512_mask_packs_epi16(a, 0, a, b); @@ -17799,7 +17976,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_maskz_packs_epi16() { + const fn test_mm512_maskz_packs_epi16() { let a = _mm512_set1_epi16(i16::MAX); let b = _mm512_set1_epi16(1); let r = _mm512_maskz_packs_epi16(0, a, b); @@ -17818,7 +17995,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_mask_packs_epi16() { + const fn test_mm256_mask_packs_epi16() { let a = _mm256_set1_epi16(i16::MAX); let b = _mm256_set1_epi16(1 << 8 | 1); let r = _mm256_mask_packs_epi16(a, 0, a, b); @@ -17831,7 +18008,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_maskz_packs_epi16() { + const fn test_mm256_maskz_packs_epi16() { let a = _mm256_set1_epi16(i16::MAX); let b = _mm256_set1_epi16(1); let r = _mm256_maskz_packs_epi16(0, a, b); @@ -17844,7 +18021,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_mask_packs_epi16() { + const fn test_mm_mask_packs_epi16() { let a = _mm_set1_epi16(i16::MAX); let b = _mm_set1_epi16(1 << 8 | 1); let r = _mm_mask_packs_epi16(a, 0, a, b); @@ -17856,7 +18033,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_maskz_packs_epi16() { + const fn test_mm_maskz_packs_epi16() { let a = _mm_set1_epi16(i16::MAX); let b = _mm_set1_epi16(1); let r = _mm_maskz_packs_epi16(0, a, b); @@ -17868,7 +18045,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_packus_epi32() { + const fn test_mm512_packus_epi32() { let a = _mm512_set1_epi32(-1); let b = _mm512_set1_epi32(1); let r = _mm512_packus_epi32(a, b); @@ -17879,7 +18056,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_mask_packus_epi32() { + const fn test_mm512_mask_packus_epi32() { let a = _mm512_set1_epi32(-1); let b = _mm512_set1_epi32(1 << 16 | 1); let r = _mm512_mask_packus_epi32(a, 0, a, b); @@ -17892,7 +18069,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_maskz_packus_epi32() { + const fn test_mm512_maskz_packus_epi32() { let a = _mm512_set1_epi32(-1); let b = _mm512_set1_epi32(1); let r = _mm512_maskz_packus_epi32(0, a, b); @@ -17905,7 +18082,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_mask_packus_epi32() { + const fn test_mm256_mask_packus_epi32() { let a = _mm256_set1_epi32(-1); let b = _mm256_set1_epi32(1 << 16 | 1); let r = _mm256_mask_packus_epi32(a, 0, a, b); @@ -17916,7 +18093,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_maskz_packus_epi32() { + const fn test_mm256_maskz_packus_epi32() { let a = _mm256_set1_epi32(-1); let b = _mm256_set1_epi32(1); let r = _mm256_maskz_packus_epi32(0, a, b); @@ -17927,7 +18104,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_mask_packus_epi32() { + const fn test_mm_mask_packus_epi32() { let a = _mm_set1_epi32(-1); let b = _mm_set1_epi32(1 << 16 | 1); let r = _mm_mask_packus_epi32(a, 0, a, b); @@ -17938,7 +18115,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_maskz_packus_epi32() { + const fn test_mm_maskz_packus_epi32() { let a = _mm_set1_epi32(-1); let b = _mm_set1_epi32(1); let r = _mm_maskz_packus_epi32(0, a, b); @@ -17949,7 +18126,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_packus_epi16() { + const fn test_mm512_packus_epi16() { let a = _mm512_set1_epi16(-1); let b = _mm512_set1_epi16(1); let r = _mm512_packus_epi16(a, b); @@ -17962,7 +18139,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_mask_packus_epi16() { + const fn test_mm512_mask_packus_epi16() { let a = _mm512_set1_epi16(-1); let b = _mm512_set1_epi16(1 << 8 | 1); let r = _mm512_mask_packus_epi16(a, 0, a, b); @@ -17982,7 +18159,7 @@ mod tests { } #[simd_test(enable = "avx512bw")] - fn test_mm512_maskz_packus_epi16() { + const fn test_mm512_maskz_packus_epi16() { let a = _mm512_set1_epi16(-1); let b = _mm512_set1_epi16(1); let r = _mm512_maskz_packus_epi16(0, a, b); @@ -18001,7 +18178,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_mask_packus_epi16() { + const fn test_mm256_mask_packus_epi16() { let a = _mm256_set1_epi16(-1); let b = _mm256_set1_epi16(1 << 8 | 1); let r = _mm256_mask_packus_epi16(a, 0, a, b); @@ -18014,7 +18191,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm256_maskz_packus_epi16() { + const fn test_mm256_maskz_packus_epi16() { let a = _mm256_set1_epi16(-1); let b = _mm256_set1_epi16(1); let r = _mm256_maskz_packus_epi16(0, a, b); @@ -18027,7 +18204,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_mask_packus_epi16() { + const fn test_mm_mask_packus_epi16() { let a = _mm_set1_epi16(-1); let b = _mm_set1_epi16(1 << 8 | 1); let r = _mm_mask_packus_epi16(a, 0, a, b); @@ -18038,7 +18215,7 @@ mod tests { } #[simd_test(enable = "avx512bw,avx512vl")] - fn test_mm_maskz_packus_epi16() { + const fn test_mm_maskz_packus_epi16() { let a = _mm_set1_epi16(-1); let b = _mm_set1_epi16(1); let r = _mm_maskz_packus_epi16(0, a, b); diff --git a/stdarch/crates/core_arch/src/x86/avx512fp16.rs b/stdarch/crates/core_arch/src/x86/avx512fp16.rs index 27f06691c5500..8ddc3d29a3a11 100644 --- a/stdarch/crates/core_arch/src/x86/avx512fp16.rs +++ b/stdarch/crates/core_arch/src/x86/avx512fp16.rs @@ -247,7 +247,7 @@ pub const fn _mm512_setr_ph( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setzero_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_setzero_ph() -> __m128h { unsafe { transmute(f16x8::ZERO) } @@ -258,7 +258,7 @@ pub const fn _mm_setzero_ph() -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setzero_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_setzero_ph() -> __m256h { f16x16::ZERO.as_m256h() @@ -269,7 +269,7 @@ pub const fn _mm256_setzero_ph() -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_setzero_ph() -> __m512h { f16x32::ZERO.as_m512h() @@ -283,7 +283,7 @@ pub const fn _mm512_setzero_ph() -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_undefined_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_undefined_ph() -> __m128h { f16x8::ZERO.as_m128h() @@ -297,7 +297,7 @@ pub const fn _mm_undefined_ph() -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_undefined_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_undefined_ph() -> __m256h { f16x16::ZERO.as_m256h() @@ -311,7 +311,7 @@ pub const fn _mm256_undefined_ph() -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_undefined_ph() -> __m512h { f16x32::ZERO.as_m512h() @@ -323,7 +323,7 @@ pub const fn _mm512_undefined_ph() -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castpd_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castpd_ph(a: __m128d) -> __m128h { unsafe { transmute(a) } @@ -335,7 +335,7 @@ pub const fn _mm_castpd_ph(a: __m128d) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castpd_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castpd_ph(a: __m256d) -> __m256h { unsafe { transmute(a) } @@ -347,7 +347,7 @@ pub const fn _mm256_castpd_ph(a: __m256d) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castpd_ph(a: __m512d) -> __m512h { unsafe { transmute(a) } @@ -359,7 +359,7 @@ pub const fn _mm512_castpd_ph(a: __m512d) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_pd) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castph_pd(a: __m128h) -> __m128d { unsafe { transmute(a) } @@ -371,7 +371,7 @@ pub const fn _mm_castph_pd(a: __m128h) -> __m128d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_pd) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph_pd(a: __m256h) -> __m256d { unsafe { transmute(a) } @@ -383,7 +383,7 @@ pub const fn _mm256_castph_pd(a: __m256h) -> __m256d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_pd) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph_pd(a: __m512h) -> __m512d { unsafe { transmute(a) } @@ -395,7 +395,7 @@ pub const fn _mm512_castph_pd(a: __m512h) -> __m512d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castps_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castps_ph(a: __m128) -> __m128h { unsafe { transmute(a) } @@ -407,7 +407,7 @@ pub const fn _mm_castps_ph(a: __m128) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castps_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castps_ph(a: __m256) -> __m256h { unsafe { transmute(a) } @@ -419,7 +419,7 @@ pub const fn _mm256_castps_ph(a: __m256) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castps_ph(a: __m512) -> __m512h { unsafe { transmute(a) } @@ -431,7 +431,7 @@ pub const fn _mm512_castps_ph(a: __m512) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_ps) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castph_ps(a: __m128h) -> __m128 { unsafe { transmute(a) } @@ -443,7 +443,7 @@ pub const fn _mm_castph_ps(a: __m128h) -> __m128 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_ps) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph_ps(a: __m256h) -> __m256 { unsafe { transmute(a) } @@ -455,7 +455,7 @@ pub const fn _mm256_castph_ps(a: __m256h) -> __m256 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_ps) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph_ps(a: __m512h) -> __m512 { unsafe { transmute(a) } @@ -467,7 +467,7 @@ pub const fn _mm512_castph_ps(a: __m512h) -> __m512 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castsi128_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castsi128_ph(a: __m128i) -> __m128h { unsafe { transmute(a) } @@ -479,7 +479,7 @@ pub const fn _mm_castsi128_ph(a: __m128i) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castsi256_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castsi256_ph(a: __m256i) -> __m256h { unsafe { transmute(a) } @@ -491,7 +491,7 @@ pub const fn _mm256_castsi256_ph(a: __m256i) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castsi512_ph(a: __m512i) -> __m512h { unsafe { transmute(a) } @@ -503,7 +503,7 @@ pub const fn _mm512_castsi512_ph(a: __m512i) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_si128) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castph_si128(a: __m128h) -> __m128i { unsafe { transmute(a) } @@ -515,7 +515,7 @@ pub const fn _mm_castph_si128(a: __m128h) -> __m128i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_si256) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph_si256(a: __m256h) -> __m256i { unsafe { transmute(a) } @@ -527,7 +527,7 @@ pub const fn _mm256_castph_si256(a: __m256h) -> __m256i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_si512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph_si512(a: __m512h) -> __m512i { unsafe { transmute(a) } @@ -539,7 +539,7 @@ pub const fn _mm512_castph_si512(a: __m512h) -> __m512i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph256_ph128) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph256_ph128(a: __m256h) -> __m128h { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } @@ -551,7 +551,7 @@ pub const fn _mm256_castph256_ph128(a: __m256h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph512_ph128) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph512_ph128(a: __m512h) -> __m128h { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } @@ -563,7 +563,7 @@ pub const fn _mm512_castph512_ph128(a: __m512h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph512_ph256) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph512_ph256(a: __m512h) -> __m256h { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } @@ -576,7 +576,7 @@ pub const fn _mm512_castph512_ph256(a: __m512h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph128_ph256) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph128_ph256(a: __m128h) -> __m256h { unsafe { @@ -595,7 +595,7 @@ pub const fn _mm256_castph128_ph256(a: __m128h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph128_ph512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph128_ph512(a: __m128h) -> __m512h { unsafe { @@ -617,7 +617,7 @@ pub const fn _mm512_castph128_ph512(a: __m128h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph256_ph512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph256_ph512(a: __m256h) -> __m512h { unsafe { @@ -639,7 +639,7 @@ pub const fn _mm512_castph256_ph512(a: __m256h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zextph128_ph256) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_zextph128_ph256(a: __m128h) -> __m256h { unsafe { @@ -658,7 +658,7 @@ pub const fn _mm256_zextph128_ph256(a: __m128h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextph256_ph512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_zextph256_ph512(a: __m256h) -> __m512h { unsafe { @@ -680,7 +680,7 @@ pub const fn _mm512_zextph256_ph512(a: __m256h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextph128_ph512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_zextph128_ph512(a: __m128h) -> __m512h { unsafe { @@ -730,7 +730,7 @@ macro_rules! cmp_asm { // FIXME: use LLVM intrinsics #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmp_ph_mask(a: __m128h, b: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM5, 5); @@ -746,7 +746,7 @@ pub fn _mm_cmp_ph_mask(a: __m128h, b: __m128h) -> __mmask8 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmp_ph_mask(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM5, 5); @@ -761,7 +761,7 @@ pub fn _mm_mask_cmp_ph_mask(k1: __mmask8, a: __m128h, b: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cmp_ph_mask(a: __m256h, b: __m256h) -> __mmask16 { unsafe { static_assert_uimm_bits!(IMM5, 5); @@ -777,7 +777,7 @@ pub fn _mm256_cmp_ph_mask(a: __m256h, b: __m256h) -> __mmask16 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cmp_ph_mask( k1: __mmask16, a: __m256h, @@ -796,7 +796,7 @@ pub fn _mm256_mask_cmp_ph_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmp_ph_mask(a: __m512h, b: __m512h) -> __mmask32 { unsafe { static_assert_uimm_bits!(IMM5, 5); @@ -812,7 +812,7 @@ pub fn _mm512_cmp_ph_mask(a: __m512h, b: __m512h) -> __mmask32 #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cmp_ph_mask( k1: __mmask32, a: __m512h, @@ -833,7 +833,7 @@ pub fn _mm512_mask_cmp_ph_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmp_round_ph_mask( a: __m512h, b: __m512h, @@ -868,7 +868,7 @@ pub fn _mm512_cmp_round_ph_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cmp_round_ph_mask( k1: __mmask32, a: __m512h, @@ -903,7 +903,7 @@ pub fn _mm512_mask_cmp_round_ph_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmp_round_sh_mask(a: __m128h, b: __m128h) -> __mmask8 { static_assert_uimm_bits!(IMM5, 5); static_assert_sae!(SAE); @@ -918,7 +918,7 @@ pub fn _mm_cmp_round_sh_mask(a: __m128h, b: __m #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmp_round_sh_mask( k1: __mmask8, a: __m128h, @@ -938,7 +938,7 @@ pub fn _mm_mask_cmp_round_sh_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmp_sh_mask(a: __m128h, b: __m128h) -> __mmask8 { static_assert_uimm_bits!(IMM5, 5); _mm_cmp_round_sh_mask::(a, b) @@ -951,7 +951,7 @@ pub fn _mm_cmp_sh_mask(a: __m128h, b: __m128h) -> __mmask8 { #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmp_sh_mask(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 { static_assert_uimm_bits!(IMM5, 5); _mm_mask_cmp_round_sh_mask::(k1, a, b) @@ -965,7 +965,7 @@ pub fn _mm_mask_cmp_sh_mask(k1: __mmask8, a: __m128h, b: __m128 #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comi_round_sh(a: __m128h, b: __m128h) -> i32 { unsafe { static_assert_uimm_bits!(IMM5, 5); @@ -981,7 +981,7 @@ pub fn _mm_comi_round_sh(a: __m128h, b: __m128h #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comi_sh(a: __m128h, b: __m128h) -> i32 { static_assert_uimm_bits!(IMM5, 5); _mm_comi_round_sh::(a, b) @@ -993,7 +993,7 @@ pub fn _mm_comi_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comieq_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comieq_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_EQ_OS>(a, b) } @@ -1004,7 +1004,7 @@ pub fn _mm_comieq_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comige_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comige_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_GE_OS>(a, b) } @@ -1015,7 +1015,7 @@ pub fn _mm_comige_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comigt_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comigt_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_GT_OS>(a, b) } @@ -1026,7 +1026,7 @@ pub fn _mm_comigt_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comile_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comile_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_LE_OS>(a, b) } @@ -1037,7 +1037,7 @@ pub fn _mm_comile_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comilt_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comilt_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_LT_OS>(a, b) } @@ -1048,7 +1048,7 @@ pub fn _mm_comilt_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comineq_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comineq_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_NEQ_US>(a, b) } @@ -1059,7 +1059,7 @@ pub fn _mm_comineq_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomieq_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomieq_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_EQ_OQ>(a, b) } @@ -1070,7 +1070,7 @@ pub fn _mm_ucomieq_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomige_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomige_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_GE_OQ>(a, b) } @@ -1081,7 +1081,7 @@ pub fn _mm_ucomige_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomigt_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomigt_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_GT_OQ>(a, b) } @@ -1092,7 +1092,7 @@ pub fn _mm_ucomigt_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomile_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomile_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_LE_OQ>(a, b) } @@ -1103,7 +1103,7 @@ pub fn _mm_ucomile_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomilt_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomilt_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_LT_OQ>(a, b) } @@ -1114,7 +1114,7 @@ pub fn _mm_ucomilt_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomineq_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomineq_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_NEQ_UQ>(a, b) } @@ -1248,7 +1248,7 @@ pub const unsafe fn _mm512_loadu_ph(mem_addr: *const f16) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_move_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1267,7 +1267,7 @@ pub const fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_move_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1285,7 +1285,7 @@ pub const fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_move_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_move_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1399,7 +1399,7 @@ pub const unsafe fn _mm512_storeu_ph(mem_addr: *mut f16, a: __m512h) { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_add(a, b) } @@ -1412,7 +1412,7 @@ pub const fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1428,7 +1428,7 @@ pub const fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1443,7 +1443,7 @@ pub const fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { simd_add(a, b) } @@ -1456,7 +1456,7 @@ pub const fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -1472,7 +1472,7 @@ pub const fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -1487,7 +1487,7 @@ pub const fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { simd_add(a, b) } @@ -1500,7 +1500,7 @@ pub const fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -1516,7 +1516,7 @@ pub const fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -1539,7 +1539,7 @@ pub const fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_add_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -1562,7 +1562,7 @@ pub fn _mm512_add_round_ph(a: __m512h, b: __m512h) -> __m51 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_add_round_ph( src: __m512h, k: __mmask32, @@ -1590,7 +1590,7 @@ pub fn _mm512_mask_add_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_add_round_ph( k: __mmask32, a: __m512h, @@ -1618,7 +1618,7 @@ pub fn _mm512_maskz_add_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_add_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_add_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -1640,7 +1640,7 @@ pub fn _mm_add_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_add_round_sh( src: __m128h, k: __mmask8, @@ -1669,7 +1669,7 @@ pub fn _mm_mask_add_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_add_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_add_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -1682,7 +1682,7 @@ pub fn _mm_maskz_add_round_sh(k: __mmask8, a: __m128h, b: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) + _mm_cvtsh_h(b)) } @@ -1696,7 +1696,7 @@ pub const fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1719,7 +1719,7 @@ pub const fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1739,7 +1739,7 @@ pub const fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_sub(a, b) } @@ -1752,7 +1752,7 @@ pub const fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1768,7 +1768,7 @@ pub const fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1783,7 +1783,7 @@ pub const fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { simd_sub(a, b) } @@ -1796,7 +1796,7 @@ pub const fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -1812,7 +1812,7 @@ pub const fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -1827,7 +1827,7 @@ pub const fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { simd_sub(a, b) } @@ -1840,7 +1840,7 @@ pub const fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -1856,7 +1856,7 @@ pub const fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -1879,7 +1879,7 @@ pub const fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_sub_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -1902,7 +1902,7 @@ pub fn _mm512_sub_round_ph(a: __m512h, b: __m512h) -> __m51 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_sub_round_ph( src: __m512h, k: __mmask32, @@ -1931,7 +1931,7 @@ pub fn _mm512_mask_sub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_sub_round_ph( k: __mmask32, a: __m512h, @@ -1959,7 +1959,7 @@ pub fn _mm512_maskz_sub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_sub_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_sub_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -1981,7 +1981,7 @@ pub fn _mm_sub_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_sub_round_sh( src: __m128h, k: __mmask8, @@ -2010,7 +2010,7 @@ pub fn _mm_mask_sub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_sub_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_sub_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -2023,7 +2023,7 @@ pub fn _mm_maskz_sub_round_sh(k: __mmask8, a: __m128h, b: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) - _mm_cvtsh_h(b)) } @@ -2037,7 +2037,7 @@ pub const fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2060,7 +2060,7 @@ pub const fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2080,7 +2080,7 @@ pub const fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_mul(a, b) } @@ -2093,7 +2093,7 @@ pub const fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2109,7 +2109,7 @@ pub const fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2124,7 +2124,7 @@ pub const fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { simd_mul(a, b) } @@ -2137,7 +2137,7 @@ pub const fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -2153,7 +2153,7 @@ pub const fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -2168,7 +2168,7 @@ pub const fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { simd_mul(a, b) } @@ -2181,7 +2181,7 @@ pub const fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -2197,7 +2197,7 @@ pub const fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -2220,7 +2220,7 @@ pub const fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mul_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -2243,7 +2243,7 @@ pub fn _mm512_mul_round_ph(a: __m512h, b: __m512h) -> __m51 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_mul_round_ph( src: __m512h, k: __mmask32, @@ -2272,7 +2272,7 @@ pub fn _mm512_mask_mul_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_mul_round_ph( k: __mmask32, a: __m512h, @@ -2300,7 +2300,7 @@ pub fn _mm512_maskz_mul_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mul_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_mul_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -2322,7 +2322,7 @@ pub fn _mm_mul_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_mul_round_sh( src: __m128h, k: __mmask8, @@ -2351,7 +2351,7 @@ pub fn _mm_mask_mul_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_mul_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_mul_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -2364,7 +2364,7 @@ pub fn _mm_maskz_mul_round_sh(k: __mmask8, a: __m128h, b: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) * _mm_cvtsh_h(b)) } @@ -2378,7 +2378,7 @@ pub const fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2401,7 +2401,7 @@ pub const fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2421,7 +2421,7 @@ pub const fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_div(a, b) } @@ -2434,7 +2434,7 @@ pub const fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2450,7 +2450,7 @@ pub const fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2465,7 +2465,7 @@ pub const fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { simd_div(a, b) } @@ -2478,7 +2478,7 @@ pub const fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -2494,7 +2494,7 @@ pub const fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -2509,7 +2509,7 @@ pub const fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { simd_div(a, b) } @@ -2522,7 +2522,7 @@ pub const fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -2538,7 +2538,7 @@ pub const fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -2561,7 +2561,7 @@ pub const fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_div_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -2584,7 +2584,7 @@ pub fn _mm512_div_round_ph(a: __m512h, b: __m512h) -> __m51 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_div_round_ph( src: __m512h, k: __mmask32, @@ -2613,7 +2613,7 @@ pub fn _mm512_mask_div_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_div_round_ph( k: __mmask32, a: __m512h, @@ -2641,7 +2641,7 @@ pub fn _mm512_maskz_div_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_div_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_div_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -2663,7 +2663,7 @@ pub fn _mm_div_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_div_round_sh( src: __m128h, k: __mmask8, @@ -2692,7 +2692,7 @@ pub fn _mm_mask_div_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_div_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_div_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -2705,7 +2705,7 @@ pub fn _mm_maskz_div_round_sh(k: __mmask8, a: __m128h, b: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) / _mm_cvtsh_h(b)) } @@ -2719,7 +2719,7 @@ pub const fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2742,7 +2742,7 @@ pub const fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2764,7 +2764,7 @@ pub const fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mul_pch(a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_pch(_mm_undefined_ph(), 0xff, a, b) } @@ -2777,7 +2777,7 @@ pub fn _mm_mul_pch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_mul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { transmute(vfmulcph_128(transmute(a), transmute(b), transmute(src), k)) } } @@ -2790,7 +2790,7 @@ pub fn _mm_mask_mul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_mul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_pch(_mm_setzero_ph(), k, a, b) } @@ -2803,7 +2803,7 @@ pub fn _mm_maskz_mul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mul_pch(a: __m256h, b: __m256h) -> __m256h { _mm256_mask_mul_pch(_mm256_undefined_ph(), 0xff, a, b) } @@ -2816,7 +2816,7 @@ pub fn _mm256_mul_pch(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_mul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h { unsafe { transmute(vfmulcph_256(transmute(a), transmute(b), transmute(src), k)) } } @@ -2829,7 +2829,7 @@ pub fn _mm256_mask_mul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_mul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_mul_pch(_mm256_setzero_ph(), k, a, b) } @@ -2842,7 +2842,7 @@ pub fn _mm256_maskz_mul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mul_pch(a: __m512h, b: __m512h) -> __m512h { _mm512_mask_mul_pch(_mm512_undefined_ph(), 0xffff, a, b) } @@ -2855,7 +2855,7 @@ pub fn _mm512_mul_pch(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_mul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_mul_round_pch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -2868,7 +2868,7 @@ pub fn _mm512_mask_mul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) - #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_mul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_mul_pch(_mm512_setzero_ph(), k, a, b) } @@ -2890,7 +2890,7 @@ pub fn _mm512_maskz_mul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mul_round_pch(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_mul_round_pch::(_mm512_undefined_ph(), 0xffff, a, b) @@ -2913,7 +2913,7 @@ pub fn _mm512_mul_round_pch(a: __m512h, b: __m512h) -> __m5 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_mul_round_pch( src: __m512h, k: __mmask16, @@ -2949,7 +2949,7 @@ pub fn _mm512_mask_mul_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_mul_round_pch( k: __mmask16, a: __m512h, @@ -2968,7 +2968,7 @@ pub fn _mm512_maskz_mul_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mul_sch(a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_sch(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -2982,7 +2982,7 @@ pub fn _mm_mul_sch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_mul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_round_sch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -2996,7 +2996,7 @@ pub fn _mm_mask_mul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_mul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_sch(f16x8::ZERO.as_m128h(), k, a, b) } @@ -3019,7 +3019,7 @@ pub fn _mm_maskz_mul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mul_round_sch(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_mul_round_sch::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -3043,7 +3043,7 @@ pub fn _mm_mul_round_sch(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_mul_round_sch( src: __m128h, k: __mmask8, @@ -3080,7 +3080,7 @@ pub fn _mm_mask_mul_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_mul_round_sch( k: __mmask8, a: __m128h, @@ -3098,7 +3098,7 @@ pub fn _mm_maskz_mul_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmul_pch(a: __m128h, b: __m128h) -> __m128h { _mm_mul_pch(a, b) } @@ -3111,7 +3111,7 @@ pub fn _mm_fmul_pch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_pch(src, k, a, b) } @@ -3124,7 +3124,7 @@ pub fn _mm_mask_fmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_maskz_mul_pch(k, a, b) } @@ -3137,7 +3137,7 @@ pub fn _mm_maskz_fmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fmul_pch(a: __m256h, b: __m256h) -> __m256h { _mm256_mul_pch(a, b) } @@ -3150,7 +3150,7 @@ pub fn _mm256_fmul_pch(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_mul_pch(src, k, a, b) } @@ -3163,7 +3163,7 @@ pub fn _mm256_mask_fmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) - #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_fmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_maskz_mul_pch(k, a, b) } @@ -3175,7 +3175,7 @@ pub fn _mm256_maskz_fmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmul_pch(a: __m512h, b: __m512h) -> __m512h { _mm512_mul_pch(a, b) } @@ -3188,7 +3188,7 @@ pub fn _mm512_fmul_pch(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_mul_pch(src, k, a, b) } @@ -3201,7 +3201,7 @@ pub fn _mm512_mask_fmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_maskz_mul_pch(k, a, b) } @@ -3221,7 +3221,7 @@ pub fn _mm512_maskz_fmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmul_round_pch(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mul_round_pch::(a, b) @@ -3243,7 +3243,7 @@ pub fn _mm512_fmul_round_pch(a: __m512h, b: __m512h) -> __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmul_round_pch( src: __m512h, k: __mmask16, @@ -3270,7 +3270,7 @@ pub fn _mm512_mask_fmul_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmul_round_pch( k: __mmask16, a: __m512h, @@ -3288,7 +3288,7 @@ pub fn _mm512_maskz_fmul_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmul_sch(a: __m128h, b: __m128h) -> __m128h { _mm_mul_sch(a, b) } @@ -3301,7 +3301,7 @@ pub fn _mm_fmul_sch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_sch(src, k, a, b) } @@ -3314,7 +3314,7 @@ pub fn _mm_mask_fmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_maskz_mul_sch(k, a, b) } @@ -3335,7 +3335,7 @@ pub fn _mm_maskz_fmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmul_round_sch(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mul_round_sch::(a, b) @@ -3358,7 +3358,7 @@ pub fn _mm_fmul_round_sch(a: __m128h, b: __m128h) -> __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmul_round_sch( src: __m128h, k: __mmask8, @@ -3386,7 +3386,7 @@ pub fn _mm_mask_fmul_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmul_round_sch( k: __mmask8, a: __m128h, @@ -3405,7 +3405,7 @@ pub fn _mm_maskz_fmul_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmul_pch(a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_pch(_mm_undefined_ph(), 0xff, a, b) } @@ -3419,7 +3419,7 @@ pub fn _mm_cmul_pch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { transmute(vfcmulcph_128(transmute(a), transmute(b), transmute(src), k)) } } @@ -3433,7 +3433,7 @@ pub fn _mm_mask_cmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_pch(_mm_setzero_ph(), k, a, b) } @@ -3447,7 +3447,7 @@ pub fn _mm_maskz_cmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cmul_pch(a: __m256h, b: __m256h) -> __m256h { _mm256_mask_cmul_pch(_mm256_undefined_ph(), 0xff, a, b) } @@ -3461,7 +3461,7 @@ pub fn _mm256_cmul_pch(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h { unsafe { transmute(vfcmulcph_256(transmute(a), transmute(b), transmute(src), k)) } } @@ -3475,7 +3475,7 @@ pub fn _mm256_mask_cmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) - #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_cmul_pch(_mm256_setzero_ph(), k, a, b) } @@ -3489,7 +3489,7 @@ pub fn _mm256_maskz_cmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmul_pch(a: __m512h, b: __m512h) -> __m512h { _mm512_mask_cmul_pch(_mm512_undefined_ph(), 0xffff, a, b) } @@ -3503,7 +3503,7 @@ pub fn _mm512_cmul_pch(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_cmul_round_pch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -3517,7 +3517,7 @@ pub fn _mm512_mask_cmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_cmul_pch(_mm512_setzero_ph(), k, a, b) } @@ -3540,7 +3540,7 @@ pub fn _mm512_maskz_cmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmul_round_pch(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_cmul_round_pch::(_mm512_undefined_ph(), 0xffff, a, b) @@ -3564,7 +3564,7 @@ pub fn _mm512_cmul_round_pch(a: __m512h, b: __m512h) -> __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cmul_round_pch( src: __m512h, k: __mmask16, @@ -3601,7 +3601,7 @@ pub fn _mm512_mask_cmul_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cmul_round_pch( k: __mmask16, a: __m512h, @@ -3619,7 +3619,7 @@ pub fn _mm512_maskz_cmul_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmul_sch(a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_sch(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -3633,7 +3633,7 @@ pub fn _mm_cmul_sch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_round_sch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -3647,7 +3647,7 @@ pub fn _mm_mask_cmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_sch(f16x8::ZERO.as_m128h(), k, a, b) } @@ -3669,7 +3669,7 @@ pub fn _mm_maskz_cmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmul_round_sch(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_cmul_round_sch::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -3693,7 +3693,7 @@ pub fn _mm_cmul_round_sch(a: __m128h, b: __m128h) -> __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmul_round_sch( src: __m128h, k: __mmask8, @@ -3730,7 +3730,7 @@ pub fn _mm_mask_cmul_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cmul_round_sch( k: __mmask8, a: __m128h, @@ -3749,7 +3749,7 @@ pub fn _mm_maskz_cmul_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmul_pch(a: __m128h, b: __m128h) -> __m128h { _mm_cmul_pch(a, b) } @@ -3763,7 +3763,7 @@ pub fn _mm_fcmul_pch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_pch(src, k, a, b) } @@ -3777,7 +3777,7 @@ pub fn _mm_mask_fcmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_maskz_cmul_pch(k, a, b) } @@ -3791,7 +3791,7 @@ pub fn _mm_maskz_fcmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fcmul_pch(a: __m256h, b: __m256h) -> __m256h { _mm256_cmul_pch(a, b) } @@ -3805,7 +3805,7 @@ pub fn _mm256_fcmul_pch(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fcmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_cmul_pch(src, k, a, b) } @@ -3819,7 +3819,7 @@ pub fn _mm256_mask_fcmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_fcmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_maskz_cmul_pch(k, a, b) } @@ -3833,7 +3833,7 @@ pub fn _mm256_maskz_fcmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fcmul_pch(a: __m512h, b: __m512h) -> __m512h { _mm512_cmul_pch(a, b) } @@ -3847,7 +3847,7 @@ pub fn _mm512_fcmul_pch(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fcmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_cmul_pch(src, k, a, b) } @@ -3861,7 +3861,7 @@ pub fn _mm512_mask_fcmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fcmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_maskz_cmul_pch(k, a, b) } @@ -3883,7 +3883,7 @@ pub fn _mm512_maskz_fcmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fcmul_round_pch(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_cmul_round_pch::(a, b) @@ -3907,7 +3907,7 @@ pub fn _mm512_fcmul_round_pch(a: __m512h, b: __m512h) -> __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fcmul_round_pch( src: __m512h, k: __mmask16, @@ -3936,7 +3936,7 @@ pub fn _mm512_mask_fcmul_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fcmul_round_pch( k: __mmask16, a: __m512h, @@ -3955,7 +3955,7 @@ pub fn _mm512_maskz_fcmul_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmul_sch(a: __m128h, b: __m128h) -> __m128h { _mm_cmul_sch(a, b) } @@ -3969,7 +3969,7 @@ pub fn _mm_fcmul_sch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_sch(src, k, a, b) } @@ -3983,7 +3983,7 @@ pub fn _mm_mask_fcmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_maskz_cmul_sch(k, a, b) } @@ -4005,7 +4005,7 @@ pub fn _mm_maskz_fcmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmul_round_sch(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_cmul_round_sch::(a, b) @@ -4029,7 +4029,7 @@ pub fn _mm_fcmul_round_sch(a: __m128h, b: __m128h) -> __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmul_round_sch( src: __m128h, k: __mmask8, @@ -4058,7 +4058,7 @@ pub fn _mm_mask_fcmul_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmul_round_sch( k: __mmask8, a: __m128h, @@ -4074,7 +4074,7 @@ pub fn _mm_maskz_fcmul_round_sch( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_abs_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_abs_ph(v2: __m128h) -> __m128h { unsafe { transmute(_mm_and_si128(transmute(v2), _mm_set1_epi16(i16::MAX))) } @@ -4086,7 +4086,7 @@ pub const fn _mm_abs_ph(v2: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_abs_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_abs_ph(v2: __m256h) -> __m256h { unsafe { transmute(_mm256_and_si256(transmute(v2), _mm256_set1_epi16(i16::MAX))) } @@ -4098,7 +4098,7 @@ pub const fn _mm256_abs_ph(v2: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_abs_ph(v2: __m512h) -> __m512h { unsafe { transmute(_mm512_and_si512(transmute(v2), _mm512_set1_epi16(i16::MAX))) } @@ -4112,7 +4112,7 @@ pub const fn _mm512_abs_ph(v2: __m512h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_conj_pch(a: __m128h) -> __m128h { unsafe { transmute(_mm_xor_si128(transmute(a), _mm_set1_epi32(i32::MIN))) } @@ -4126,7 +4126,7 @@ pub const fn _mm_conj_pch(a: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { @@ -4143,7 +4143,7 @@ pub const fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h { _mm_mask_conj_pch(_mm_setzero_ph(), k, a) @@ -4156,7 +4156,7 @@ pub const fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_conj_pch(a: __m256h) -> __m256h { unsafe { transmute(_mm256_xor_si256(transmute(a), _mm256_set1_epi32(i32::MIN))) } @@ -4170,7 +4170,7 @@ pub const fn _mm256_conj_pch(a: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m256h { unsafe { @@ -4187,7 +4187,7 @@ pub const fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m2 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h { _mm256_mask_conj_pch(_mm256_setzero_ph(), k, a) @@ -4200,7 +4200,7 @@ pub const fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_conj_pch) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_conj_pch(a: __m512h) -> __m512h { unsafe { transmute(_mm512_xor_si512(transmute(a), _mm512_set1_epi32(i32::MIN))) } @@ -4214,7 +4214,7 @@ pub const fn _mm512_conj_pch(a: __m512h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_conj_pch) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m512h { unsafe { @@ -4231,7 +4231,7 @@ pub const fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_conj_pch) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h { _mm512_mask_conj_pch(_mm512_setzero_ph(), k, a) @@ -4245,7 +4245,7 @@ pub const fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_mask3_fmadd_pch(a, b, c, 0xff) } @@ -4259,7 +4259,7 @@ pub fn _mm_fmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { let r: __m128 = transmute(_mm_mask3_fmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does @@ -4276,7 +4276,7 @@ pub fn _mm_mask_fmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { transmute(vfmaddcph_mask3_128( @@ -4297,7 +4297,7 @@ pub fn _mm_mask3_fmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { transmute(vfmaddcph_maskz_128( @@ -4317,7 +4317,7 @@ pub fn _mm_maskz_fmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h { _mm256_mask3_fmadd_pch(a, b, c, 0xff) } @@ -4331,7 +4331,7 @@ pub fn _mm256_fmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> __m256h { unsafe { let r: __m256 = transmute(_mm256_mask3_fmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does @@ -4348,7 +4348,7 @@ pub fn _mm256_mask_fmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask3_fmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -> __m256h { unsafe { transmute(vfmaddcph_mask3_256( @@ -4369,7 +4369,7 @@ pub fn _mm256_mask3_fmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) - #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_fmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { transmute(vfmaddcph_maskz_256( @@ -4389,7 +4389,7 @@ pub fn _mm256_maskz_fmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) - #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c) } @@ -4403,7 +4403,7 @@ pub fn _mm512_fmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -> __m512h { _mm512_mask_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c) } @@ -4417,7 +4417,7 @@ pub fn _mm512_mask_fmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) - #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) -> __m512h { _mm512_mask3_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k) } @@ -4431,7 +4431,7 @@ pub fn _mm512_mask3_fmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_maskz_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c) } @@ -4453,7 +4453,7 @@ pub fn _mm512_maskz_fmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmadd_round_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask3_fmadd_round_pch::(a, b, c, 0xffff) @@ -4477,7 +4477,7 @@ pub fn _mm512_fmadd_round_pch(a: __m512h, b: __m512h, c: __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmadd_round_pch( a: __m512h, k: __mmask16, @@ -4509,7 +4509,7 @@ pub fn _mm512_mask_fmadd_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmadd_round_pch( a: __m512h, b: __m512h, @@ -4546,7 +4546,7 @@ pub fn _mm512_mask3_fmadd_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmadd_round_pch( k: __mmask16, a: __m512h, @@ -4574,7 +4574,7 @@ pub fn _mm512_maskz_fmadd_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c) } @@ -4589,7 +4589,7 @@ pub fn _mm_fmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { _mm_mask_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c) } @@ -4604,7 +4604,7 @@ pub fn _mm_mask_fmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { _mm_mask3_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k) } @@ -4619,7 +4619,7 @@ pub fn _mm_mask3_fmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_maskz_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c) } @@ -4641,7 +4641,7 @@ pub fn _mm_maskz_fmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmadd_round_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -4674,7 +4674,7 @@ pub fn _mm_fmadd_round_sch(a: __m128h, b: __m128h, c: __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmadd_round_sch( a: __m128h, k: __mmask8, @@ -4708,7 +4708,7 @@ pub fn _mm_mask_fmadd_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmadd_round_sch( a: __m128h, b: __m128h, @@ -4742,7 +4742,7 @@ pub fn _mm_mask3_fmadd_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmadd_round_sch( k: __mmask8, a: __m128h, @@ -4770,7 +4770,7 @@ pub fn _mm_maskz_fmadd_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_mask3_fcmadd_pch(a, b, c, 0xff) } @@ -4785,7 +4785,7 @@ pub fn _mm_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { let r: __m128 = transmute(_mm_mask3_fcmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does @@ -4803,7 +4803,7 @@ pub fn _mm_mask_fcmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { transmute(vfcmaddcph_mask3_128( @@ -4825,7 +4825,7 @@ pub fn _mm_mask3_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { transmute(vfcmaddcph_maskz_128( @@ -4846,7 +4846,7 @@ pub fn _mm_maskz_fcmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h { _mm256_mask3_fcmadd_pch(a, b, c, 0xff) } @@ -4861,7 +4861,7 @@ pub fn _mm256_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fcmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> __m256h { unsafe { let r: __m256 = transmute(_mm256_mask3_fcmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does @@ -4879,7 +4879,7 @@ pub fn _mm256_mask_fcmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) - #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask3_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -> __m256h { unsafe { transmute(vfcmaddcph_mask3_256( @@ -4901,7 +4901,7 @@ pub fn _mm256_mask3_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_fcmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { transmute(vfcmaddcph_maskz_256( @@ -4922,7 +4922,7 @@ pub fn _mm256_maskz_fcmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c) } @@ -4937,7 +4937,7 @@ pub fn _mm512_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fcmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -> __m512h { _mm512_mask_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c) } @@ -4952,7 +4952,7 @@ pub fn _mm512_mask_fcmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) -> __m512h { _mm512_mask3_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k) } @@ -4967,7 +4967,7 @@ pub fn _mm512_mask3_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fcmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_maskz_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c) } @@ -4990,7 +4990,7 @@ pub fn _mm512_maskz_fcmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fcmadd_round_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask3_fcmadd_round_pch::(a, b, c, 0xffff) @@ -5015,7 +5015,7 @@ pub fn _mm512_fcmadd_round_pch(a: __m512h, b: __m512h, c: _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fcmadd_round_pch( a: __m512h, k: __mmask16, @@ -5048,7 +5048,7 @@ pub fn _mm512_mask_fcmadd_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fcmadd_round_pch( a: __m512h, b: __m512h, @@ -5086,7 +5086,7 @@ pub fn _mm512_mask3_fcmadd_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fcmadd_round_pch( k: __mmask16, a: __m512h, @@ -5115,7 +5115,7 @@ pub fn _mm512_maskz_fcmadd_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c) } @@ -5131,7 +5131,7 @@ pub fn _mm_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { _mm_mask_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c) } @@ -5147,7 +5147,7 @@ pub fn _mm_mask_fcmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { _mm_mask3_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k) } @@ -5163,7 +5163,7 @@ pub fn _mm_mask3_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_maskz_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c) } @@ -5187,7 +5187,7 @@ pub fn _mm_maskz_fcmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmadd_round_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -5221,7 +5221,7 @@ pub fn _mm_fcmadd_round_sch(a: __m128h, b: __m128h, c: __m1 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmadd_round_sch( a: __m128h, k: __mmask8, @@ -5256,7 +5256,7 @@ pub fn _mm_mask_fcmadd_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fcmadd_round_sch( a: __m128h, b: __m128h, @@ -5291,7 +5291,7 @@ pub fn _mm_mask3_fcmadd_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmadd_round_sch( k: __mmask8, a: __m128h, @@ -5317,7 +5317,7 @@ pub fn _mm_maskz_fcmadd_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_fma(a, b, c) } @@ -5331,7 +5331,7 @@ pub const fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), a) } @@ -5345,7 +5345,7 @@ pub const fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), c) } @@ -5359,7 +5359,7 @@ pub const fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), _mm_setzero_ph()) } @@ -5372,7 +5372,7 @@ pub const fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_fma(a, b, c) } @@ -5386,7 +5386,7 @@ pub const fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), a) } @@ -5400,7 +5400,7 @@ pub const fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), c) } @@ -5414,7 +5414,7 @@ pub const fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), _mm256_setzero_ph()) } @@ -5427,7 +5427,7 @@ pub const fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m2 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_fma(a, b, c) } @@ -5441,7 +5441,7 @@ pub const fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), a) } @@ -5455,7 +5455,7 @@ pub const fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), c) } @@ -5469,7 +5469,7 @@ pub const fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), _mm512_setzero_ph()) } @@ -5491,7 +5491,7 @@ pub const fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m5 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmadd_round_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -5516,7 +5516,7 @@ pub fn _mm512_fmadd_round_ph(a: __m512h, b: __m512h, c: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmadd_round_ph( a: __m512h, k: __mmask32, @@ -5546,7 +5546,7 @@ pub fn _mm512_mask_fmadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmadd_round_ph( a: __m512h, b: __m512h, @@ -5576,7 +5576,7 @@ pub fn _mm512_mask3_fmadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmadd_round_ph( k: __mmask32, a: __m512h, @@ -5601,7 +5601,7 @@ pub fn _mm512_maskz_fmadd_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -5622,7 +5622,7 @@ pub const fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -5645,7 +5645,7 @@ pub const fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { @@ -5668,7 +5668,7 @@ pub const fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -5700,7 +5700,7 @@ pub const fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmadd_round_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -5730,7 +5730,7 @@ pub fn _mm_fmadd_round_sh(a: __m128h, b: __m128h, c: __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmadd_round_sh( a: __m128h, k: __mmask8, @@ -5767,7 +5767,7 @@ pub fn _mm_mask_fmadd_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmadd_round_sh( a: __m128h, b: __m128h, @@ -5804,7 +5804,7 @@ pub fn _mm_mask3_fmadd_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmadd_round_sh( k: __mmask8, a: __m128h, @@ -5832,7 +5832,7 @@ pub fn _mm_maskz_fmadd_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_fma(a, b, simd_neg(c)) } @@ -5846,7 +5846,7 @@ pub const fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), a) } @@ -5860,7 +5860,7 @@ pub const fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), c) } @@ -5874,7 +5874,7 @@ pub const fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), _mm_setzero_ph()) } @@ -5887,7 +5887,7 @@ pub const fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_fma(a, b, simd_neg(c)) } @@ -5901,7 +5901,7 @@ pub const fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), a) } @@ -5915,7 +5915,7 @@ pub const fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), c) } @@ -5929,7 +5929,7 @@ pub const fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), _mm256_setzero_ph()) } @@ -5942,7 +5942,7 @@ pub const fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m2 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_fma(a, b, simd_neg(c)) } @@ -5956,7 +5956,7 @@ pub const fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), a) } @@ -5970,7 +5970,7 @@ pub const fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), c) } @@ -5984,7 +5984,7 @@ pub const fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), _mm512_setzero_ph()) } @@ -6006,7 +6006,7 @@ pub const fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m5 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmsub_round_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -6031,7 +6031,7 @@ pub fn _mm512_fmsub_round_ph(a: __m512h, b: __m512h, c: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmsub_round_ph( a: __m512h, k: __mmask32, @@ -6061,7 +6061,7 @@ pub fn _mm512_mask_fmsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmsub_round_ph( a: __m512h, b: __m512h, @@ -6091,7 +6091,7 @@ pub fn _mm512_mask3_fmsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmsub_round_ph( k: __mmask32, a: __m512h, @@ -6116,7 +6116,7 @@ pub fn _mm512_maskz_fmsub_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6137,7 +6137,7 @@ pub const fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6160,7 +6160,7 @@ pub const fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { @@ -6183,7 +6183,7 @@ pub const fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6215,7 +6215,7 @@ pub const fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmsub_round_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -6245,7 +6245,7 @@ pub fn _mm_fmsub_round_sh(a: __m128h, b: __m128h, c: __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmsub_round_sh( a: __m128h, k: __mmask8, @@ -6282,7 +6282,7 @@ pub fn _mm_mask_fmsub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmsub_round_sh( a: __m128h, b: __m128h, @@ -6311,7 +6311,7 @@ pub fn _mm_mask3_fmsub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmsub_round_sh( k: __mmask8, a: __m128h, @@ -6338,7 +6338,7 @@ pub fn _mm_maskz_fmsub_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_fma(simd_neg(a), b, c) } @@ -6352,7 +6352,7 @@ pub const fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), a) } @@ -6366,7 +6366,7 @@ pub const fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), c) } @@ -6380,7 +6380,7 @@ pub const fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), _mm_setzero_ph()) } @@ -6393,7 +6393,7 @@ pub const fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_fma(simd_neg(a), b, c) } @@ -6407,7 +6407,7 @@ pub const fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), a) } @@ -6421,7 +6421,7 @@ pub const fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m2 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), c) } @@ -6435,7 +6435,7 @@ pub const fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mma #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), _mm256_setzero_ph()) } @@ -6448,7 +6448,7 @@ pub const fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_fma(simd_neg(a), b, c) } @@ -6462,7 +6462,7 @@ pub const fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), a) } @@ -6476,7 +6476,7 @@ pub const fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m5 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), c) } @@ -6490,7 +6490,7 @@ pub const fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mma #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), _mm512_setzero_ph()) } @@ -6512,7 +6512,7 @@ pub const fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fnmadd_round_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -6537,7 +6537,7 @@ pub fn _mm512_fnmadd_round_ph(a: __m512h, b: __m512h, c: __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fnmadd_round_ph( a: __m512h, k: __mmask32, @@ -6567,7 +6567,7 @@ pub fn _mm512_mask_fnmadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fnmadd_round_ph( a: __m512h, b: __m512h, @@ -6597,7 +6597,7 @@ pub fn _mm512_mask3_fnmadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fnmadd_round_ph( k: __mmask32, a: __m512h, @@ -6622,7 +6622,7 @@ pub fn _mm512_maskz_fnmadd_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6643,7 +6643,7 @@ pub const fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6666,7 +6666,7 @@ pub const fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { @@ -6689,7 +6689,7 @@ pub const fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6721,7 +6721,7 @@ pub const fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fnmadd_round_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -6751,7 +6751,7 @@ pub fn _mm_fnmadd_round_sh(a: __m128h, b: __m128h, c: __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fnmadd_round_sh( a: __m128h, k: __mmask8, @@ -6788,7 +6788,7 @@ pub fn _mm_mask_fnmadd_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fnmadd_round_sh( a: __m128h, b: __m128h, @@ -6825,7 +6825,7 @@ pub fn _mm_mask3_fnmadd_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fnmadd_round_sh( k: __mmask8, a: __m128h, @@ -6852,7 +6852,7 @@ pub fn _mm_maskz_fnmadd_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) } @@ -6866,7 +6866,7 @@ pub const fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), a) } @@ -6880,7 +6880,7 @@ pub const fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), c) } @@ -6894,7 +6894,7 @@ pub const fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), _mm_setzero_ph()) } @@ -6907,7 +6907,7 @@ pub const fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) } @@ -6921,7 +6921,7 @@ pub const fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), a) } @@ -6935,7 +6935,7 @@ pub const fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m2 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), c) } @@ -6949,7 +6949,7 @@ pub const fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mma #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), _mm256_setzero_ph()) } @@ -6962,7 +6962,7 @@ pub const fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) } @@ -6976,7 +6976,7 @@ pub const fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), a) } @@ -6990,7 +6990,7 @@ pub const fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m5 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), c) } @@ -7004,7 +7004,7 @@ pub const fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mma #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), _mm512_setzero_ph()) } @@ -7026,7 +7026,7 @@ pub const fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fnmsub_round_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -7051,7 +7051,7 @@ pub fn _mm512_fnmsub_round_ph(a: __m512h, b: __m512h, c: __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fnmsub_round_ph( a: __m512h, k: __mmask32, @@ -7081,7 +7081,7 @@ pub fn _mm512_mask_fnmsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fnmsub_round_ph( a: __m512h, b: __m512h, @@ -7111,7 +7111,7 @@ pub fn _mm512_mask3_fnmsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fnmsub_round_ph( k: __mmask32, a: __m512h, @@ -7136,7 +7136,7 @@ pub fn _mm512_maskz_fnmsub_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -7157,7 +7157,7 @@ pub const fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -7180,7 +7180,7 @@ pub const fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { @@ -7203,7 +7203,7 @@ pub const fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -7235,7 +7235,7 @@ pub const fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fnmsub_round_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -7265,7 +7265,7 @@ pub fn _mm_fnmsub_round_sh(a: __m128h, b: __m128h, c: __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fnmsub_round_sh( a: __m128h, k: __mmask8, @@ -7302,7 +7302,7 @@ pub fn _mm_mask_fnmsub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fnmsub_round_sh( a: __m128h, b: __m128h, @@ -7339,7 +7339,7 @@ pub fn _mm_mask3_fnmsub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fnmsub_round_sh( k: __mmask8, a: __m128h, @@ -7366,7 +7366,7 @@ pub fn _mm_maskz_fnmsub_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -7384,7 +7384,7 @@ pub const fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), a) } @@ -7398,7 +7398,7 @@ pub const fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), c) } @@ -7412,7 +7412,7 @@ pub const fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), _mm_setzero_ph()) } @@ -7425,7 +7425,7 @@ pub const fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { @@ -7447,7 +7447,7 @@ pub const fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), a) } @@ -7461,7 +7461,7 @@ pub const fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), c) } @@ -7475,7 +7475,7 @@ pub const fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), _mm256_setzero_ph()) } @@ -7488,7 +7488,7 @@ pub const fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { @@ -7513,7 +7513,7 @@ pub const fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), a) } @@ -7527,7 +7527,7 @@ pub const fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), c) } @@ -7541,7 +7541,7 @@ pub const fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), _mm512_setzero_ph()) } @@ -7563,7 +7563,7 @@ pub const fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmaddsub_round_ph( a: __m512h, b: __m512h, @@ -7592,7 +7592,7 @@ pub fn _mm512_fmaddsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmaddsub_round_ph( a: __m512h, k: __mmask32, @@ -7622,7 +7622,7 @@ pub fn _mm512_mask_fmaddsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmaddsub_round_ph( a: __m512h, b: __m512h, @@ -7652,7 +7652,7 @@ pub fn _mm512_mask3_fmaddsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmaddsub_round_ph( k: __mmask32, a: __m512h, @@ -7676,7 +7676,7 @@ pub fn _mm512_maskz_fmaddsub_round_ph( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_fmaddsub_ph(a, b, unsafe { simd_neg(c) }) @@ -7690,7 +7690,7 @@ pub const fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), a) } @@ -7704,7 +7704,7 @@ pub const fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), c) } @@ -7718,7 +7718,7 @@ pub const fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), _mm_setzero_ph()) } @@ -7731,7 +7731,7 @@ pub const fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { _mm256_fmaddsub_ph(a, b, unsafe { simd_neg(c) }) @@ -7745,7 +7745,7 @@ pub const fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), a) } @@ -7759,7 +7759,7 @@ pub const fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), c) } @@ -7773,7 +7773,7 @@ pub const fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), _mm256_setzero_ph()) } @@ -7786,7 +7786,7 @@ pub const fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_fmaddsub_ph(a, b, unsafe { simd_neg(c) }) @@ -7800,7 +7800,7 @@ pub const fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), a) } @@ -7814,7 +7814,7 @@ pub const fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), c) } @@ -7828,7 +7828,7 @@ pub const fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), _mm512_setzero_ph()) } @@ -7850,7 +7850,7 @@ pub const fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmsubadd_round_ph( a: __m512h, b: __m512h, @@ -7879,7 +7879,7 @@ pub fn _mm512_fmsubadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmsubadd_round_ph( a: __m512h, k: __mmask32, @@ -7909,7 +7909,7 @@ pub fn _mm512_mask_fmsubadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmsubadd_round_ph( a: __m512h, b: __m512h, @@ -7939,7 +7939,7 @@ pub fn _mm512_mask3_fmsubadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmsubadd_round_ph( k: __mmask32, a: __m512h, @@ -7963,7 +7963,7 @@ pub fn _mm512_maskz_fmsubadd_round_ph( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_rcp_ph(a: __m128h) -> __m128h { _mm_mask_rcp_ph(_mm_undefined_ph(), 0xff, a) } @@ -7976,7 +7976,7 @@ pub fn _mm_rcp_ph(a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_rcp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { vrcpph_128(a, src, k) } } @@ -7989,7 +7989,7 @@ pub fn _mm_mask_rcp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_rcp_ph(k: __mmask8, a: __m128h) -> __m128h { _mm_mask_rcp_ph(_mm_setzero_ph(), k, a) } @@ -8001,7 +8001,7 @@ pub fn _mm_maskz_rcp_ph(k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_rcp_ph(a: __m256h) -> __m256h { _mm256_mask_rcp_ph(_mm256_undefined_ph(), 0xffff, a) } @@ -8014,7 +8014,7 @@ pub fn _mm256_rcp_ph(a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_rcp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { vrcpph_256(a, src, k) } } @@ -8027,7 +8027,7 @@ pub fn _mm256_mask_rcp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_rcp_ph(k: __mmask16, a: __m256h) -> __m256h { _mm256_mask_rcp_ph(_mm256_setzero_ph(), k, a) } @@ -8039,7 +8039,7 @@ pub fn _mm256_maskz_rcp_ph(k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_rcp_ph(a: __m512h) -> __m512h { _mm512_mask_rcp_ph(_mm512_undefined_ph(), 0xffffffff, a) } @@ -8052,7 +8052,7 @@ pub fn _mm512_rcp_ph(a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_rcp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { unsafe { vrcpph_512(a, src, k) } } @@ -8065,7 +8065,7 @@ pub fn _mm512_mask_rcp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_rcp_ph(k: __mmask32, a: __m512h) -> __m512h { _mm512_mask_rcp_ph(_mm512_setzero_ph(), k, a) } @@ -8079,7 +8079,7 @@ pub fn _mm512_maskz_rcp_ph(k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_rcp_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_rcp_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -8093,7 +8093,7 @@ pub fn _mm_rcp_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_rcp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { vrcpsh(a, b, src, k) } } @@ -8107,7 +8107,7 @@ pub fn _mm_mask_rcp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_rcp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_rcp_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -8120,7 +8120,7 @@ pub fn _mm_maskz_rcp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_rsqrt_ph(a: __m128h) -> __m128h { _mm_mask_rsqrt_ph(_mm_undefined_ph(), 0xff, a) } @@ -8134,7 +8134,7 @@ pub fn _mm_rsqrt_ph(a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_rsqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { vrsqrtph_128(a, src, k) } } @@ -8148,7 +8148,7 @@ pub fn _mm_mask_rsqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_rsqrt_ph(k: __mmask8, a: __m128h) -> __m128h { _mm_mask_rsqrt_ph(_mm_setzero_ph(), k, a) } @@ -8161,7 +8161,7 @@ pub fn _mm_maskz_rsqrt_ph(k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_rsqrt_ph(a: __m256h) -> __m256h { _mm256_mask_rsqrt_ph(_mm256_undefined_ph(), 0xffff, a) } @@ -8175,7 +8175,7 @@ pub fn _mm256_rsqrt_ph(a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_rsqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { vrsqrtph_256(a, src, k) } } @@ -8189,7 +8189,7 @@ pub fn _mm256_mask_rsqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_rsqrt_ph(k: __mmask16, a: __m256h) -> __m256h { _mm256_mask_rsqrt_ph(_mm256_setzero_ph(), k, a) } @@ -8202,7 +8202,7 @@ pub fn _mm256_maskz_rsqrt_ph(k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_rsqrt_ph(a: __m512h) -> __m512h { _mm512_mask_rsqrt_ph(_mm512_undefined_ph(), 0xffffffff, a) } @@ -8216,7 +8216,7 @@ pub fn _mm512_rsqrt_ph(a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_rsqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { unsafe { vrsqrtph_512(a, src, k) } } @@ -8230,7 +8230,7 @@ pub fn _mm512_mask_rsqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_rsqrt_ph(k: __mmask32, a: __m512h) -> __m512h { _mm512_mask_rsqrt_ph(_mm512_setzero_ph(), k, a) } @@ -8244,7 +8244,7 @@ pub fn _mm512_maskz_rsqrt_ph(k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_rsqrt_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_rsqrt_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -8258,7 +8258,7 @@ pub fn _mm_rsqrt_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_rsqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { vrsqrtsh(a, b, src, k) } } @@ -8272,7 +8272,7 @@ pub fn _mm_mask_rsqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_rsqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_rsqrt_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -8284,7 +8284,7 @@ pub fn _mm_maskz_rsqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_sqrt_ph(a: __m128h) -> __m128h { unsafe { simd_fsqrt(a) } } @@ -8296,7 +8296,7 @@ pub fn _mm_sqrt_ph(a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_sqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_sqrt_ph(a), src) } } @@ -8308,7 +8308,7 @@ pub fn _mm_mask_sqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_sqrt_ph(k: __mmask8, a: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_sqrt_ph(a), _mm_setzero_ph()) } } @@ -8320,7 +8320,7 @@ pub fn _mm_maskz_sqrt_ph(k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_sqrt_ph(a: __m256h) -> __m256h { unsafe { simd_fsqrt(a) } } @@ -8332,7 +8332,7 @@ pub fn _mm256_sqrt_ph(a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_sqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_sqrt_ph(a), src) } } @@ -8344,7 +8344,7 @@ pub fn _mm256_mask_sqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_sqrt_ph(k: __mmask16, a: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_sqrt_ph(a), _mm256_setzero_ph()) } } @@ -8356,7 +8356,7 @@ pub fn _mm256_maskz_sqrt_ph(k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_sqrt_ph(a: __m512h) -> __m512h { unsafe { simd_fsqrt(a) } } @@ -8368,7 +8368,7 @@ pub fn _mm512_sqrt_ph(a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_sqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_sqrt_ph(a), src) } } @@ -8380,7 +8380,7 @@ pub fn _mm512_mask_sqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_sqrt_ph(k: __mmask32, a: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_sqrt_ph(a), _mm512_setzero_ph()) } } @@ -8400,7 +8400,7 @@ pub fn _mm512_maskz_sqrt_ph(k: __mmask32, a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_sqrt_round_ph(a: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -8423,7 +8423,7 @@ pub fn _mm512_sqrt_round_ph(a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_sqrt_round_ph( src: __m512h, k: __mmask32, @@ -8450,7 +8450,7 @@ pub fn _mm512_mask_sqrt_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_sqrt_round_ph(k: __mmask32, a: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -8466,7 +8466,7 @@ pub fn _mm512_maskz_sqrt_round_ph(k: __mmask32, a: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_sqrt_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_sqrt_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -8479,7 +8479,7 @@ pub fn _mm_sqrt_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_sqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_sqrt_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -8492,7 +8492,7 @@ pub fn _mm_mask_sqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_sqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_sqrt_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -8513,7 +8513,7 @@ pub fn _mm_maskz_sqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_sqrt_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_sqrt_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -8535,7 +8535,7 @@ pub fn _mm_sqrt_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_sqrt_round_sh( src: __m128h, k: __mmask8, @@ -8564,7 +8564,7 @@ pub fn _mm_mask_sqrt_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_sqrt_round_sh( k: __mmask8, a: __m128h, @@ -8582,7 +8582,7 @@ pub fn _mm_maskz_sqrt_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_max_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { vmaxph_128(a, b) } } @@ -8596,7 +8596,7 @@ pub fn _mm_max_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_max_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_max_ph(a, b), src) } } @@ -8610,7 +8610,7 @@ pub fn _mm_mask_max_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_max_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_max_ph(a, b), _mm_setzero_ph()) } } @@ -8623,7 +8623,7 @@ pub fn _mm_maskz_max_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_max_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { vmaxph_256(a, b) } } @@ -8637,7 +8637,7 @@ pub fn _mm256_max_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_max_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_max_ph(a, b), src) } } @@ -8651,7 +8651,7 @@ pub fn _mm256_mask_max_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_max_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_max_ph(a, b), _mm256_setzero_ph()) } } @@ -8664,7 +8664,7 @@ pub fn _mm256_maskz_max_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_max_ph(a: __m512h, b: __m512h) -> __m512h { _mm512_max_round_ph::<_MM_FROUND_CUR_DIRECTION>(a, b) } @@ -8678,7 +8678,7 @@ pub fn _mm512_max_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_max_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_max_ph(a, b), src) } } @@ -8692,7 +8692,7 @@ pub fn _mm512_mask_max_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_max_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_max_ph(a, b), _mm512_setzero_ph()) } } @@ -8707,7 +8707,7 @@ pub fn _mm512_maskz_max_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_max_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_sae!(SAE); @@ -8725,7 +8725,7 @@ pub fn _mm512_max_round_ph(a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_max_round_ph( src: __m512h, k: __mmask32, @@ -8748,7 +8748,7 @@ pub fn _mm512_mask_max_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_max_round_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_sae!(SAE); @@ -8765,7 +8765,7 @@ pub fn _mm512_maskz_max_round_ph(k: __mmask32, a: __m512h, b: __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_max_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_max_sh(_mm_undefined_ph(), 0xff, a, b) } @@ -8779,7 +8779,7 @@ pub fn _mm_max_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_max_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_max_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -8793,7 +8793,7 @@ pub fn _mm_mask_max_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_max_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_max_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -8808,7 +8808,7 @@ pub fn _mm_maskz_max_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_max_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_max_round_sh::(_mm_undefined_ph(), 0xff, a, b) @@ -8825,7 +8825,7 @@ pub fn _mm_max_round_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_max_round_sh( src: __m128h, k: __mmask8, @@ -8849,7 +8849,7 @@ pub fn _mm_mask_max_round_sh( #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_max_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_max_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -8863,7 +8863,7 @@ pub fn _mm_maskz_max_round_sh(k: __mmask8, a: __m128h, b: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_min_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { vminph_128(a, b) } } @@ -8877,7 +8877,7 @@ pub fn _mm_min_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_min_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_min_ph(a, b), src) } } @@ -8891,7 +8891,7 @@ pub fn _mm_mask_min_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_min_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_min_ph(a, b), _mm_setzero_ph()) } } @@ -8904,7 +8904,7 @@ pub fn _mm_maskz_min_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_min_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { vminph_256(a, b) } } @@ -8918,7 +8918,7 @@ pub fn _mm256_min_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_min_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_min_ph(a, b), src) } } @@ -8932,7 +8932,7 @@ pub fn _mm256_mask_min_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_min_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_min_ph(a, b), _mm256_setzero_ph()) } } @@ -8945,7 +8945,7 @@ pub fn _mm256_maskz_min_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_min_ph(a: __m512h, b: __m512h) -> __m512h { _mm512_min_round_ph::<_MM_FROUND_CUR_DIRECTION>(a, b) } @@ -8959,7 +8959,7 @@ pub fn _mm512_min_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_min_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_min_ph(a, b), src) } } @@ -8973,7 +8973,7 @@ pub fn _mm512_mask_min_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_min_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_min_ph(a, b), _mm512_setzero_ph()) } } @@ -8987,7 +8987,7 @@ pub fn _mm512_maskz_min_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_min_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_sae!(SAE); @@ -9005,7 +9005,7 @@ pub fn _mm512_min_round_ph(a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_min_round_ph( src: __m512h, k: __mmask32, @@ -9028,7 +9028,7 @@ pub fn _mm512_mask_min_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_min_round_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_sae!(SAE); @@ -9045,7 +9045,7 @@ pub fn _mm512_maskz_min_round_ph(k: __mmask32, a: __m512h, b: __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_min_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_min_sh(_mm_undefined_ph(), 0xff, a, b) } @@ -9059,7 +9059,7 @@ pub fn _mm_min_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_min_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_min_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -9073,7 +9073,7 @@ pub fn _mm_mask_min_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_min_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_min_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -9088,7 +9088,7 @@ pub fn _mm_maskz_min_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_min_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_min_round_sh::(_mm_undefined_ph(), 0xff, a, b) @@ -9105,7 +9105,7 @@ pub fn _mm_min_round_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_min_round_sh( src: __m128h, k: __mmask8, @@ -9129,7 +9129,7 @@ pub fn _mm_mask_min_round_sh( #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_min_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_min_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -9143,7 +9143,7 @@ pub fn _mm_maskz_min_round_sh(k: __mmask8, a: __m128h, b: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_getexp_ph(a: __m128h) -> __m128h { _mm_mask_getexp_ph(_mm_undefined_ph(), 0xff, a) } @@ -9157,7 +9157,7 @@ pub fn _mm_getexp_ph(a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_getexp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { vgetexpph_128(a, src, k) } } @@ -9171,7 +9171,7 @@ pub fn _mm_mask_getexp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_getexp_ph(k: __mmask8, a: __m128h) -> __m128h { _mm_mask_getexp_ph(_mm_setzero_ph(), k, a) } @@ -9184,7 +9184,7 @@ pub fn _mm_maskz_getexp_ph(k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_getexp_ph(a: __m256h) -> __m256h { _mm256_mask_getexp_ph(_mm256_undefined_ph(), 0xffff, a) } @@ -9198,7 +9198,7 @@ pub fn _mm256_getexp_ph(a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_getexp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { vgetexpph_256(a, src, k) } } @@ -9212,7 +9212,7 @@ pub fn _mm256_mask_getexp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_getexp_ph(k: __mmask16, a: __m256h) -> __m256h { _mm256_mask_getexp_ph(_mm256_setzero_ph(), k, a) } @@ -9225,7 +9225,7 @@ pub fn _mm256_maskz_getexp_ph(k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_getexp_ph(a: __m512h) -> __m512h { _mm512_mask_getexp_ph(_mm512_undefined_ph(), 0xffffffff, a) } @@ -9239,7 +9239,7 @@ pub fn _mm512_getexp_ph(a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_getexp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { _mm512_mask_getexp_round_ph::<_MM_FROUND_CUR_DIRECTION>(src, k, a) } @@ -9253,7 +9253,7 @@ pub fn _mm512_mask_getexp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_getexp_ph(k: __mmask32, a: __m512h) -> __m512h { _mm512_mask_getexp_ph(_mm512_setzero_ph(), k, a) } @@ -9268,7 +9268,7 @@ pub fn _mm512_maskz_getexp_ph(k: __mmask32, a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_getexp_round_ph(a: __m512h) -> __m512h { static_assert_sae!(SAE); _mm512_mask_getexp_round_ph::(_mm512_undefined_ph(), 0xffffffff, a) @@ -9284,7 +9284,7 @@ pub fn _mm512_getexp_round_ph(a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_getexp_round_ph( src: __m512h, k: __mmask32, @@ -9306,7 +9306,7 @@ pub fn _mm512_mask_getexp_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_getexp_round_ph(k: __mmask32, a: __m512h) -> __m512h { static_assert_sae!(SAE); _mm512_mask_getexp_round_ph::(_mm512_setzero_ph(), k, a) @@ -9321,7 +9321,7 @@ pub fn _mm512_maskz_getexp_round_ph(k: __mmask32, a: __m512h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_getexp_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_getexp_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -9336,7 +9336,7 @@ pub fn _mm_getexp_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_getexp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_getexp_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -9351,7 +9351,7 @@ pub fn _mm_mask_getexp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_getexp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_getexp_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -9367,7 +9367,7 @@ pub fn _mm_maskz_getexp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_getexp_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_getexp_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -9384,7 +9384,7 @@ pub fn _mm_getexp_round_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_getexp_round_sh( src: __m128h, k: __mmask8, @@ -9408,7 +9408,7 @@ pub fn _mm_mask_getexp_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_getexp_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_getexp_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -9436,7 +9436,7 @@ pub fn _mm_maskz_getexp_round_sh(k: __mmask8, a: __m128h, b: __m #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))] #[rustc_legacy_const_generics(1, 2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_getmant_ph( a: __m128h, ) -> __m128h { @@ -9468,7 +9468,7 @@ pub fn _mm_getmant_ph( a: __m256h, ) -> __m256h { @@ -9574,7 +9574,7 @@ pub fn _mm256_getmant_ph( a: __m512h, ) -> __m512h { @@ -9680,7 +9680,7 @@ pub fn _mm512_getmant_ph( a: __m128h, b: __m128h, @@ -9911,7 +9911,7 @@ pub fn _mm_getmant_sh(a: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_roundscale_ph::(_mm_undefined_ph(), 0xff, a) @@ -10131,7 +10131,7 @@ pub fn _mm_roundscale_ph(a: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_roundscale_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -10156,7 +10156,7 @@ pub fn _mm_mask_roundscale_ph(src: __m128h, k: __mmask8, a: __m #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_roundscale_ph(k: __mmask8, a: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_roundscale_ph::(_mm_setzero_ph(), k, a) @@ -10178,7 +10178,7 @@ pub fn _mm_maskz_roundscale_ph(k: __mmask8, a: __m128h) -> __m1 #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_roundscale_ph(a: __m256h) -> __m256h { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_roundscale_ph::(_mm256_undefined_ph(), 0xffff, a) @@ -10201,7 +10201,7 @@ pub fn _mm256_roundscale_ph(a: __m256h) -> __m256h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_roundscale_ph( src: __m256h, k: __mmask16, @@ -10230,7 +10230,7 @@ pub fn _mm256_mask_roundscale_ph( #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_roundscale_ph(k: __mmask16, a: __m256h) -> __m256h { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_roundscale_ph::(_mm256_setzero_ph(), k, a) @@ -10252,7 +10252,7 @@ pub fn _mm256_maskz_roundscale_ph(k: __mmask16, a: __m256h) -> #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_roundscale_ph(a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_roundscale_ph::(_mm512_undefined_ph(), 0xffffffff, a) @@ -10275,7 +10275,7 @@ pub fn _mm512_roundscale_ph(a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_roundscale_ph( src: __m512h, k: __mmask32, @@ -10302,7 +10302,7 @@ pub fn _mm512_mask_roundscale_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_roundscale_ph(k: __mmask32, a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_roundscale_ph::(_mm512_setzero_ph(), k, a) @@ -10325,7 +10325,7 @@ pub fn _mm512_maskz_roundscale_ph(k: __mmask32, a: __m512h) -> #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(1, 2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_roundscale_round_ph(a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -10350,7 +10350,7 @@ pub fn _mm512_roundscale_round_ph(a: __m512h) - #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_roundscale_round_ph( src: __m512h, k: __mmask32, @@ -10380,7 +10380,7 @@ pub fn _mm512_mask_roundscale_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_roundscale_round_ph( k: __mmask32, a: __m512h, @@ -10407,7 +10407,7 @@ pub fn _mm512_maskz_roundscale_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_roundscale_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_roundscale_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -10430,7 +10430,7 @@ pub fn _mm_roundscale_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_roundscale_sh( src: __m128h, k: __mmask8, @@ -10458,7 +10458,7 @@ pub fn _mm_mask_roundscale_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_roundscale_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_roundscale_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -10483,7 +10483,7 @@ pub fn _mm_maskz_roundscale_sh(k: __mmask8, a: __m128h, b: __m1 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_roundscale_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -10509,7 +10509,7 @@ pub fn _mm_roundscale_round_sh(a: __m128h, b: _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_roundscale_round_sh( src: __m128h, k: __mmask8, @@ -10542,7 +10542,7 @@ pub fn _mm_mask_roundscale_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_roundscale_round_sh( k: __mmask8, a: __m128h, @@ -10560,7 +10560,7 @@ pub fn _mm_maskz_roundscale_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_scalef_ph(a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_ph(_mm_undefined_ph(), 0xff, a, b) } @@ -10572,7 +10572,7 @@ pub fn _mm_scalef_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_scalef_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { vscalefph_128(a, b, src, k) } } @@ -10584,7 +10584,7 @@ pub fn _mm_mask_scalef_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_scalef_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_ph(_mm_setzero_ph(), k, a, b) } @@ -10596,7 +10596,7 @@ pub fn _mm_maskz_scalef_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_scalef_ph(a: __m256h, b: __m256h) -> __m256h { _mm256_mask_scalef_ph(_mm256_undefined_ph(), 0xffff, a, b) } @@ -10608,7 +10608,7 @@ pub fn _mm256_scalef_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_scalef_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { vscalefph_256(a, b, src, k) } } @@ -10620,7 +10620,7 @@ pub fn _mm256_mask_scalef_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_scalef_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_scalef_ph(_mm256_setzero_ph(), k, a, b) } @@ -10632,7 +10632,7 @@ pub fn _mm256_maskz_scalef_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_scalef_ph(a: __m512h, b: __m512h) -> __m512h { _mm512_mask_scalef_ph(_mm512_undefined_ph(), 0xffffffff, a, b) } @@ -10644,7 +10644,7 @@ pub fn _mm512_scalef_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_scalef_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_scalef_round_ph::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -10656,7 +10656,7 @@ pub fn _mm512_mask_scalef_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_scalef_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_scalef_ph(_mm512_setzero_ph(), k, a, b) } @@ -10677,7 +10677,7 @@ pub fn _mm512_maskz_scalef_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_scalef_round_ph(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_scalef_round_ph::(_mm512_undefined_ph(), 0xffffffff, a, b) @@ -10699,7 +10699,7 @@ pub fn _mm512_scalef_round_ph(a: __m512h, b: __m512h) -> __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_scalef_round_ph( src: __m512h, k: __mmask32, @@ -10728,7 +10728,7 @@ pub fn _mm512_mask_scalef_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_scalef_round_ph( k: __mmask32, a: __m512h, @@ -10746,7 +10746,7 @@ pub fn _mm512_maskz_scalef_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_scalef_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -10759,7 +10759,7 @@ pub fn _mm_scalef_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_scalef_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -10772,7 +10772,7 @@ pub fn _mm_mask_scalef_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_scalef_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -10794,7 +10794,7 @@ pub fn _mm_maskz_scalef_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_scalef_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_scalef_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -10817,7 +10817,7 @@ pub fn _mm_scalef_round_sh(a: __m128h, b: __m128h) -> __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_scalef_round_sh( src: __m128h, k: __mmask8, @@ -10847,7 +10847,7 @@ pub fn _mm_mask_scalef_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_scalef_round_sh( k: __mmask8, a: __m128h, @@ -10873,7 +10873,7 @@ pub fn _mm_maskz_scalef_round_sh( #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_reduce_ph(a: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_ph::(_mm_undefined_ph(), 0xff, a) @@ -10896,7 +10896,7 @@ pub fn _mm_reduce_ph(a: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_reduce_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -10921,7 +10921,7 @@ pub fn _mm_mask_reduce_ph(src: __m128h, k: __mmask8, a: __m128h #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_reduce_ph(k: __mmask8, a: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_ph::(_mm_setzero_ph(), k, a) @@ -10943,7 +10943,7 @@ pub fn _mm_maskz_reduce_ph(k: __mmask8, a: __m128h) -> __m128h #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_reduce_ph(a: __m256h) -> __m256h { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_reduce_ph::(_mm256_undefined_ph(), 0xffff, a) @@ -10966,7 +10966,7 @@ pub fn _mm256_reduce_ph(a: __m256h) -> __m256h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_reduce_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -10991,7 +10991,7 @@ pub fn _mm256_mask_reduce_ph(src: __m256h, k: __mmask16, a: __m #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_reduce_ph(k: __mmask16, a: __m256h) -> __m256h { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_reduce_ph::(_mm256_setzero_ph(), k, a) @@ -11013,7 +11013,7 @@ pub fn _mm256_maskz_reduce_ph(k: __mmask16, a: __m256h) -> __m2 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_reduce_ph(a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_ph::(_mm512_undefined_ph(), 0xffffffff, a) @@ -11036,7 +11036,7 @@ pub fn _mm512_reduce_ph(a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_reduce_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_round_ph::(src, k, a) @@ -11059,7 +11059,7 @@ pub fn _mm512_mask_reduce_ph(src: __m512h, k: __mmask32, a: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_reduce_ph(k: __mmask32, a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_ph::(_mm512_setzero_ph(), k, a) @@ -11083,7 +11083,7 @@ pub fn _mm512_maskz_reduce_ph(k: __mmask32, a: __m512h) -> __m5 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(1, 2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_reduce_round_ph(a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -11109,7 +11109,7 @@ pub fn _mm512_reduce_round_ph(a: __m512h) -> __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_reduce_round_ph( src: __m512h, k: __mmask32, @@ -11141,7 +11141,7 @@ pub fn _mm512_mask_reduce_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_reduce_round_ph( k: __mmask32, a: __m512h, @@ -11168,7 +11168,7 @@ pub fn _mm512_maskz_reduce_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_reduce_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -11192,7 +11192,7 @@ pub fn _mm_reduce_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_reduce_sh( src: __m128h, k: __mmask8, @@ -11221,7 +11221,7 @@ pub fn _mm_mask_reduce_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_reduce_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -11246,7 +11246,7 @@ pub fn _mm_maskz_reduce_sh(k: __mmask8, a: __m128h, b: __m128h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_reduce_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -11273,7 +11273,7 @@ pub fn _mm_reduce_round_sh(a: __m128h, b: __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_reduce_round_sh( src: __m128h, k: __mmask8, @@ -11307,7 +11307,7 @@ pub fn _mm_mask_reduce_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_reduce_round_sh( k: __mmask8, a: __m128h, @@ -11582,7 +11582,7 @@ macro_rules! fpclass_asm { // FIXME: use LLVM intrinsics #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fpclass_ph_mask(a: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11609,7 +11609,7 @@ pub fn _mm_fpclass_ph_mask(a: __m128h) -> __mmask8 { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fpclass_ph_mask(k1: __mmask8, a: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11635,7 +11635,7 @@ pub fn _mm_mask_fpclass_ph_mask(k1: __mmask8, a: __m128h) -> __ #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fpclass_ph_mask(a: __m256h) -> __mmask16 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11662,7 +11662,7 @@ pub fn _mm256_fpclass_ph_mask(a: __m256h) -> __mmask16 { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fpclass_ph_mask(k1: __mmask16, a: __m256h) -> __mmask16 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11688,7 +11688,7 @@ pub fn _mm256_mask_fpclass_ph_mask(k1: __mmask16, a: __m256h) - #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fpclass_ph_mask(a: __m512h) -> __mmask32 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11715,7 +11715,7 @@ pub fn _mm512_fpclass_ph_mask(a: __m512h) -> __mmask32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fpclass_ph_mask(k1: __mmask32, a: __m512h) -> __mmask32 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11741,7 +11741,7 @@ pub fn _mm512_mask_fpclass_ph_mask(k1: __mmask32, a: __m512h) - #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfpclasssh, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fpclass_sh_mask(a: __m128h) -> __mmask8 { _mm_mask_fpclass_sh_mask::(0xff, a) } @@ -11765,7 +11765,7 @@ pub fn _mm_fpclass_sh_mask(a: __m128h) -> __mmask8 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfpclasssh, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fpclass_sh_mask(k1: __mmask8, a: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11779,7 +11779,7 @@ pub fn _mm_mask_fpclass_sh_mask(k1: __mmask8, a: __m128h) -> __ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_blend_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, b, a) } @@ -11791,7 +11791,7 @@ pub const fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_blend_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, b, a) } @@ -11803,7 +11803,7 @@ pub const fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m25 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, b, a) } @@ -11815,7 +11815,7 @@ pub const fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m51 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutex2var_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_permutex2var_ph(a: __m128h, idx: __m128i, b: __m128h) -> __m128h { _mm_castsi128_ph(_mm_permutex2var_epi16( _mm_castph_si128(a), @@ -11830,7 +11830,7 @@ pub fn _mm_permutex2var_ph(a: __m128h, idx: __m128i, b: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutex2var_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_permutex2var_ph(a: __m256h, idx: __m256i, b: __m256h) -> __m256h { _mm256_castsi256_ph(_mm256_permutex2var_epi16( _mm256_castph_si256(a), @@ -11845,7 +11845,7 @@ pub fn _mm256_permutex2var_ph(a: __m256h, idx: __m256i, b: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex2var_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_permutex2var_ph(a: __m512h, idx: __m512i, b: __m512h) -> __m512h { _mm512_castsi512_ph(_mm512_permutex2var_epi16( _mm512_castph_si512(a), @@ -11860,7 +11860,7 @@ pub fn _mm512_permutex2var_ph(a: __m512h, idx: __m512i, b: __m512h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutexvar_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_permutexvar_ph(idx: __m128i, a: __m128h) -> __m128h { _mm_castsi128_ph(_mm_permutexvar_epi16(idx, _mm_castph_si128(a))) } @@ -11871,7 +11871,7 @@ pub fn _mm_permutexvar_ph(idx: __m128i, a: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutexvar_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_permutexvar_ph(idx: __m256i, a: __m256h) -> __m256h { _mm256_castsi256_ph(_mm256_permutexvar_epi16(idx, _mm256_castph_si256(a))) } @@ -11882,7 +11882,7 @@ pub fn _mm256_permutexvar_ph(idx: __m256i, a: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutexvar_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_permutexvar_ph(idx: __m512i, a: __m512h) -> __m512h { _mm512_castsi512_ph(_mm512_permutexvar_epi16(idx, _mm512_castph_si512(a))) } @@ -11894,7 +11894,7 @@ pub fn _mm512_permutexvar_ph(idx: __m512i, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepi16_ph(a: __m128i) -> __m128h { unsafe { vcvtw2ph_128(a.as_i16x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -11907,7 +11907,7 @@ pub fn _mm_cvtepi16_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepi16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { simd_select_bitmask(k, _mm_cvtepi16_ph(a), src) } } @@ -11919,7 +11919,7 @@ pub fn _mm_mask_cvtepi16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepi16_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepi16_ph(_mm_setzero_ph(), k, a) } @@ -11931,7 +11931,7 @@ pub fn _mm_maskz_cvtepi16_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepi16_ph(a: __m256i) -> __m256h { unsafe { vcvtw2ph_256(a.as_i16x16(), _MM_FROUND_CUR_DIRECTION) } } @@ -11944,7 +11944,7 @@ pub fn _mm256_cvtepi16_ph(a: __m256i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepi16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_cvtepi16_ph(a), src) } } @@ -11956,7 +11956,7 @@ pub fn _mm256_mask_cvtepi16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepi16_ph(k: __mmask16, a: __m256i) -> __m256h { _mm256_mask_cvtepi16_ph(_mm256_setzero_ph(), k, a) } @@ -11968,7 +11968,7 @@ pub fn _mm256_maskz_cvtepi16_ph(k: __mmask16, a: __m256i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepi16_ph(a: __m512i) -> __m512h { unsafe { vcvtw2ph_512(a.as_i16x32(), _MM_FROUND_CUR_DIRECTION) } } @@ -11981,7 +11981,7 @@ pub fn _mm512_cvtepi16_ph(a: __m512i) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepi16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_cvtepi16_ph(a), src) } } @@ -11993,7 +11993,7 @@ pub fn _mm512_mask_cvtepi16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepi16_ph(k: __mmask32, a: __m512i) -> __m512h { _mm512_mask_cvtepi16_ph(_mm512_setzero_ph(), k, a) } @@ -12014,7 +12014,7 @@ pub fn _mm512_maskz_cvtepi16_ph(k: __mmask32, a: __m512i) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepi16_ph(a: __m512i) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -12039,7 +12039,7 @@ pub fn _mm512_cvt_roundepi16_ph(a: __m512i) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepi16_ph( src: __m512h, k: __mmask32, @@ -12067,7 +12067,7 @@ pub fn _mm512_mask_cvt_roundepi16_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepi16_ph(k: __mmask32, a: __m512i) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepi16_ph::(_mm512_setzero_ph(), k, a) @@ -12080,7 +12080,7 @@ pub fn _mm512_maskz_cvt_roundepi16_ph(k: __mmask32, a: __m5 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepu16_ph(a: __m128i) -> __m128h { unsafe { vcvtuw2ph_128(a.as_u16x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12093,7 +12093,7 @@ pub fn _mm_cvtepu16_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepu16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { simd_select_bitmask(k, _mm_cvtepu16_ph(a), src) } } @@ -12105,7 +12105,7 @@ pub fn _mm_mask_cvtepu16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepu16_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepu16_ph(_mm_setzero_ph(), k, a) } @@ -12117,7 +12117,7 @@ pub fn _mm_maskz_cvtepu16_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepu16_ph(a: __m256i) -> __m256h { unsafe { vcvtuw2ph_256(a.as_u16x16(), _MM_FROUND_CUR_DIRECTION) } } @@ -12130,7 +12130,7 @@ pub fn _mm256_cvtepu16_ph(a: __m256i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepu16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_cvtepu16_ph(a), src) } } @@ -12142,7 +12142,7 @@ pub fn _mm256_mask_cvtepu16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepu16_ph(k: __mmask16, a: __m256i) -> __m256h { _mm256_mask_cvtepu16_ph(_mm256_setzero_ph(), k, a) } @@ -12154,7 +12154,7 @@ pub fn _mm256_maskz_cvtepu16_ph(k: __mmask16, a: __m256i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepu16_ph(a: __m512i) -> __m512h { unsafe { vcvtuw2ph_512(a.as_u16x32(), _MM_FROUND_CUR_DIRECTION) } } @@ -12167,7 +12167,7 @@ pub fn _mm512_cvtepu16_ph(a: __m512i) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepu16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_cvtepu16_ph(a), src) } } @@ -12179,7 +12179,7 @@ pub fn _mm512_mask_cvtepu16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepu16_ph(k: __mmask32, a: __m512i) -> __m512h { _mm512_mask_cvtepu16_ph(_mm512_setzero_ph(), k, a) } @@ -12200,7 +12200,7 @@ pub fn _mm512_maskz_cvtepu16_ph(k: __mmask32, a: __m512i) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepu16_ph(a: __m512i) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -12225,7 +12225,7 @@ pub fn _mm512_cvt_roundepu16_ph(a: __m512i) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepu16_ph( src: __m512h, k: __mmask32, @@ -12253,7 +12253,7 @@ pub fn _mm512_mask_cvt_roundepu16_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepu16_ph(k: __mmask32, a: __m512i) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepu16_ph::(_mm512_setzero_ph(), k, a) @@ -12266,7 +12266,7 @@ pub fn _mm512_maskz_cvt_roundepu16_ph(k: __mmask32, a: __m5 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepi32_ph(a: __m128i) -> __m128h { _mm_mask_cvtepi32_ph(_mm_setzero_ph(), 0xff, a) } @@ -12279,7 +12279,7 @@ pub fn _mm_cvtepi32_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { vcvtdq2ph_128(a.as_i32x4(), src, k) } } @@ -12292,7 +12292,7 @@ pub fn _mm_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepi32_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepi32_ph(_mm_setzero_ph(), k, a) } @@ -12304,7 +12304,7 @@ pub fn _mm_maskz_cvtepi32_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepi32_ph(a: __m256i) -> __m128h { unsafe { vcvtdq2ph_256(a.as_i32x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12317,7 +12317,7 @@ pub fn _mm256_cvtepi32_ph(a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h { unsafe { simd_select_bitmask(k, _mm256_cvtepi32_ph(a), src) } } @@ -12329,7 +12329,7 @@ pub fn _mm256_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepi32_ph(k: __mmask8, a: __m256i) -> __m128h { _mm256_mask_cvtepi32_ph(_mm_setzero_ph(), k, a) } @@ -12341,7 +12341,7 @@ pub fn _mm256_maskz_cvtepi32_ph(k: __mmask8, a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepi32_ph(a: __m512i) -> __m256h { unsafe { vcvtdq2ph_512(a.as_i32x16(), _MM_FROUND_CUR_DIRECTION) } } @@ -12354,7 +12354,7 @@ pub fn _mm512_cvtepi32_ph(a: __m512i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepi32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256h { unsafe { simd_select_bitmask(k, _mm512_cvtepi32_ph(a), src) } } @@ -12366,7 +12366,7 @@ pub fn _mm512_mask_cvtepi32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepi32_ph(k: __mmask16, a: __m512i) -> __m256h { _mm512_mask_cvtepi32_ph(f16x16::ZERO.as_m256h(), k, a) } @@ -12387,7 +12387,7 @@ pub fn _mm512_maskz_cvtepi32_ph(k: __mmask16, a: __m512i) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepi32_ph(a: __m512i) -> __m256h { unsafe { static_assert_rounding!(ROUNDING); @@ -12412,7 +12412,7 @@ pub fn _mm512_cvt_roundepi32_ph(a: __m512i) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepi32_ph( src: __m256h, k: __mmask16, @@ -12440,7 +12440,7 @@ pub fn _mm512_mask_cvt_roundepi32_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepi32_ph(k: __mmask16, a: __m512i) -> __m256h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepi32_ph::(f16x16::ZERO.as_m256h(), k, a) @@ -12454,7 +12454,7 @@ pub fn _mm512_maskz_cvt_roundepi32_ph(k: __mmask16, a: __m5 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsi2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvti32_sh(a: __m128h, b: i32) -> __m128h { unsafe { vcvtsi2sh(a, b, _MM_FROUND_CUR_DIRECTION) } } @@ -12476,7 +12476,7 @@ pub fn _mm_cvti32_sh(a: __m128h, b: i32) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsi2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundi32_sh(a: __m128h, b: i32) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -12491,7 +12491,7 @@ pub fn _mm_cvt_roundi32_sh(a: __m128h, b: i32) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepu32_ph(a: __m128i) -> __m128h { _mm_mask_cvtepu32_ph(_mm_setzero_ph(), 0xff, a) } @@ -12504,7 +12504,7 @@ pub fn _mm_cvtepu32_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { vcvtudq2ph_128(a.as_u32x4(), src, k) } } @@ -12517,7 +12517,7 @@ pub fn _mm_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepu32_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepu32_ph(_mm_setzero_ph(), k, a) } @@ -12529,7 +12529,7 @@ pub fn _mm_maskz_cvtepu32_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepu32_ph(a: __m256i) -> __m128h { unsafe { vcvtudq2ph_256(a.as_u32x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12542,7 +12542,7 @@ pub fn _mm256_cvtepu32_ph(a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h { unsafe { simd_select_bitmask(k, _mm256_cvtepu32_ph(a), src) } } @@ -12554,7 +12554,7 @@ pub fn _mm256_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepu32_ph(k: __mmask8, a: __m256i) -> __m128h { _mm256_mask_cvtepu32_ph(_mm_setzero_ph(), k, a) } @@ -12566,7 +12566,7 @@ pub fn _mm256_maskz_cvtepu32_ph(k: __mmask8, a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepu32_ph(a: __m512i) -> __m256h { unsafe { vcvtudq2ph_512(a.as_u32x16(), _MM_FROUND_CUR_DIRECTION) } } @@ -12579,7 +12579,7 @@ pub fn _mm512_cvtepu32_ph(a: __m512i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepu32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256h { unsafe { simd_select_bitmask(k, _mm512_cvtepu32_ph(a), src) } } @@ -12591,7 +12591,7 @@ pub fn _mm512_mask_cvtepu32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepu32_ph(k: __mmask16, a: __m512i) -> __m256h { _mm512_mask_cvtepu32_ph(f16x16::ZERO.as_m256h(), k, a) } @@ -12612,7 +12612,7 @@ pub fn _mm512_maskz_cvtepu32_ph(k: __mmask16, a: __m512i) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepu32_ph(a: __m512i) -> __m256h { unsafe { static_assert_rounding!(ROUNDING); @@ -12637,7 +12637,7 @@ pub fn _mm512_cvt_roundepu32_ph(a: __m512i) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepu32_ph( src: __m256h, k: __mmask16, @@ -12665,7 +12665,7 @@ pub fn _mm512_mask_cvt_roundepu32_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepu32_ph(k: __mmask16, a: __m512i) -> __m256h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepu32_ph::(f16x16::ZERO.as_m256h(), k, a) @@ -12679,7 +12679,7 @@ pub fn _mm512_maskz_cvt_roundepu32_ph(k: __mmask16, a: __m5 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtusi2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtu32_sh(a: __m128h, b: u32) -> __m128h { unsafe { vcvtusi2sh(a, b, _MM_FROUND_CUR_DIRECTION) } } @@ -12701,7 +12701,7 @@ pub fn _mm_cvtu32_sh(a: __m128h, b: u32) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtusi2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundu32_sh(a: __m128h, b: u32) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -12716,7 +12716,7 @@ pub fn _mm_cvt_roundu32_sh(a: __m128h, b: u32) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepi64_ph(a: __m128i) -> __m128h { _mm_mask_cvtepi64_ph(_mm_setzero_ph(), 0xff, a) } @@ -12729,7 +12729,7 @@ pub fn _mm_cvtepi64_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { vcvtqq2ph_128(a.as_i64x2(), src, k) } } @@ -12742,7 +12742,7 @@ pub fn _mm_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepi64_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepi64_ph(_mm_setzero_ph(), k, a) } @@ -12754,7 +12754,7 @@ pub fn _mm_maskz_cvtepi64_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepi64_ph(a: __m256i) -> __m128h { _mm256_mask_cvtepi64_ph(_mm_setzero_ph(), 0xff, a) } @@ -12767,7 +12767,7 @@ pub fn _mm256_cvtepi64_ph(a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h { unsafe { vcvtqq2ph_256(a.as_i64x4(), src, k) } } @@ -12780,7 +12780,7 @@ pub fn _mm256_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepi64_ph(k: __mmask8, a: __m256i) -> __m128h { _mm256_mask_cvtepi64_ph(_mm_setzero_ph(), k, a) } @@ -12792,7 +12792,7 @@ pub fn _mm256_maskz_cvtepi64_ph(k: __mmask8, a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepi64_ph(a: __m512i) -> __m128h { unsafe { vcvtqq2ph_512(a.as_i64x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12805,7 +12805,7 @@ pub fn _mm512_cvtepi64_ph(a: __m512i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h { unsafe { simd_select_bitmask(k, _mm512_cvtepi64_ph(a), src) } } @@ -12817,7 +12817,7 @@ pub fn _mm512_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepi64_ph(k: __mmask8, a: __m512i) -> __m128h { _mm512_mask_cvtepi64_ph(f16x8::ZERO.as_m128h(), k, a) } @@ -12838,7 +12838,7 @@ pub fn _mm512_maskz_cvtepi64_ph(k: __mmask8, a: __m512i) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepi64_ph(a: __m512i) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -12863,7 +12863,7 @@ pub fn _mm512_cvt_roundepi64_ph(a: __m512i) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepi64_ph( src: __m128h, k: __mmask8, @@ -12891,7 +12891,7 @@ pub fn _mm512_mask_cvt_roundepi64_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepi64_ph(k: __mmask8, a: __m512i) -> __m128h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepi64_ph::(f16x8::ZERO.as_m128h(), k, a) @@ -12904,7 +12904,7 @@ pub fn _mm512_maskz_cvt_roundepi64_ph(k: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepu64_ph(a: __m128i) -> __m128h { _mm_mask_cvtepu64_ph(_mm_setzero_ph(), 0xff, a) } @@ -12917,7 +12917,7 @@ pub fn _mm_cvtepu64_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { vcvtuqq2ph_128(a.as_u64x2(), src, k) } } @@ -12930,7 +12930,7 @@ pub fn _mm_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepu64_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepu64_ph(_mm_setzero_ph(), k, a) } @@ -12942,7 +12942,7 @@ pub fn _mm_maskz_cvtepu64_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepu64_ph(a: __m256i) -> __m128h { _mm256_mask_cvtepu64_ph(_mm_setzero_ph(), 0xff, a) } @@ -12955,7 +12955,7 @@ pub fn _mm256_cvtepu64_ph(a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h { unsafe { vcvtuqq2ph_256(a.as_u64x4(), src, k) } } @@ -12968,7 +12968,7 @@ pub fn _mm256_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepu64_ph(k: __mmask8, a: __m256i) -> __m128h { _mm256_mask_cvtepu64_ph(_mm_setzero_ph(), k, a) } @@ -12980,7 +12980,7 @@ pub fn _mm256_maskz_cvtepu64_ph(k: __mmask8, a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepu64_ph(a: __m512i) -> __m128h { unsafe { vcvtuqq2ph_512(a.as_u64x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12993,7 +12993,7 @@ pub fn _mm512_cvtepu64_ph(a: __m512i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h { unsafe { simd_select_bitmask(k, _mm512_cvtepu64_ph(a), src) } } @@ -13005,7 +13005,7 @@ pub fn _mm512_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepu64_ph(k: __mmask8, a: __m512i) -> __m128h { _mm512_mask_cvtepu64_ph(f16x8::ZERO.as_m128h(), k, a) } @@ -13026,7 +13026,7 @@ pub fn _mm512_maskz_cvtepu64_ph(k: __mmask8, a: __m512i) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepu64_ph(a: __m512i) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -13051,7 +13051,7 @@ pub fn _mm512_cvt_roundepu64_ph(a: __m512i) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepu64_ph( src: __m128h, k: __mmask8, @@ -13079,7 +13079,7 @@ pub fn _mm512_mask_cvt_roundepu64_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepu64_ph(k: __mmask8, a: __m512i) -> __m128h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepu64_ph::(f16x8::ZERO.as_m128h(), k, a) @@ -13092,7 +13092,7 @@ pub fn _mm512_maskz_cvt_roundepu64_ph(k: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtxps_ph(a: __m128) -> __m128h { _mm_mask_cvtxps_ph(_mm_setzero_ph(), 0xff, a) } @@ -13105,7 +13105,7 @@ pub fn _mm_cvtxps_ph(a: __m128) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m128) -> __m128h { unsafe { vcvtps2phx_128(a, src, k) } } @@ -13118,7 +13118,7 @@ pub fn _mm_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m128) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtxps_ph(k: __mmask8, a: __m128) -> __m128h { _mm_mask_cvtxps_ph(_mm_setzero_ph(), k, a) } @@ -13130,7 +13130,7 @@ pub fn _mm_maskz_cvtxps_ph(k: __mmask8, a: __m128) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtxps_ph(a: __m256) -> __m128h { _mm256_mask_cvtxps_ph(_mm_setzero_ph(), 0xff, a) } @@ -13143,7 +13143,7 @@ pub fn _mm256_cvtxps_ph(a: __m256) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m256) -> __m128h { unsafe { vcvtps2phx_256(a, src, k) } } @@ -13156,7 +13156,7 @@ pub fn _mm256_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m256) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtxps_ph(k: __mmask8, a: __m256) -> __m128h { _mm256_mask_cvtxps_ph(_mm_setzero_ph(), k, a) } @@ -13168,7 +13168,7 @@ pub fn _mm256_maskz_cvtxps_ph(k: __mmask8, a: __m256) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtxps_ph(a: __m512) -> __m256h { _mm512_mask_cvtxps_ph(f16x16::ZERO.as_m256h(), 0xffff, a) } @@ -13181,7 +13181,7 @@ pub fn _mm512_cvtxps_ph(a: __m512) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtxps_ph(src: __m256h, k: __mmask16, a: __m512) -> __m256h { unsafe { vcvtps2phx_512(a, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -13194,7 +13194,7 @@ pub fn _mm512_mask_cvtxps_ph(src: __m256h, k: __mmask16, a: __m512) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtxps_ph(k: __mmask16, a: __m512) -> __m256h { _mm512_mask_cvtxps_ph(f16x16::ZERO.as_m256h(), k, a) } @@ -13215,7 +13215,7 @@ pub fn _mm512_maskz_cvtxps_ph(k: __mmask16, a: __m512) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtx_roundps_ph(a: __m512) -> __m256h { static_assert_rounding!(ROUNDING); _mm512_mask_cvtx_roundps_ph::(f16x16::ZERO.as_m256h(), 0xffff, a) @@ -13238,7 +13238,7 @@ pub fn _mm512_cvtx_roundps_ph(a: __m512) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtx_roundps_ph( src: __m256h, k: __mmask16, @@ -13267,7 +13267,7 @@ pub fn _mm512_mask_cvtx_roundps_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtx_roundps_ph(k: __mmask16, a: __m512) -> __m256h { static_assert_rounding!(ROUNDING); _mm512_mask_cvtx_roundps_ph::(f16x16::ZERO.as_m256h(), k, a) @@ -13281,7 +13281,7 @@ pub fn _mm512_maskz_cvtx_roundps_ph(k: __mmask16, a: __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtss_sh(a: __m128h, b: __m128) -> __m128h { _mm_mask_cvtss_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -13295,7 +13295,7 @@ pub fn _mm_cvtss_sh(a: __m128h, b: __m128) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtss_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128) -> __m128h { unsafe { vcvtss2sh(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -13309,7 +13309,7 @@ pub fn _mm_mask_cvtss_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128) -> __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtss_sh(k: __mmask8, a: __m128h, b: __m128) -> __m128h { _mm_mask_cvtss_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -13331,7 +13331,7 @@ pub fn _mm_maskz_cvtss_sh(k: __mmask8, a: __m128h, b: __m128) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundss_sh(a: __m128h, b: __m128) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_cvt_roundss_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -13355,7 +13355,7 @@ pub fn _mm_cvt_roundss_sh(a: __m128h, b: __m128) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvt_roundss_sh( src: __m128h, k: __mmask8, @@ -13386,7 +13386,7 @@ pub fn _mm_mask_cvt_roundss_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvt_roundss_sh( k: __mmask8, a: __m128h, @@ -13403,7 +13403,7 @@ pub fn _mm_maskz_cvt_roundss_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtpd_ph(a: __m128d) -> __m128h { _mm_mask_cvtpd_ph(_mm_setzero_ph(), 0xff, a) } @@ -13416,7 +13416,7 @@ pub fn _mm_cvtpd_ph(a: __m128d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m128d) -> __m128h { unsafe { vcvtpd2ph_128(a, src, k) } } @@ -13429,7 +13429,7 @@ pub fn _mm_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m128d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtpd_ph(k: __mmask8, a: __m128d) -> __m128h { _mm_mask_cvtpd_ph(_mm_setzero_ph(), k, a) } @@ -13441,7 +13441,7 @@ pub fn _mm_maskz_cvtpd_ph(k: __mmask8, a: __m128d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtpd_ph(a: __m256d) -> __m128h { _mm256_mask_cvtpd_ph(_mm_setzero_ph(), 0xff, a) } @@ -13454,7 +13454,7 @@ pub fn _mm256_cvtpd_ph(a: __m256d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m256d) -> __m128h { unsafe { vcvtpd2ph_256(a, src, k) } } @@ -13467,7 +13467,7 @@ pub fn _mm256_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m256d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtpd_ph(k: __mmask8, a: __m256d) -> __m128h { _mm256_mask_cvtpd_ph(_mm_setzero_ph(), k, a) } @@ -13479,7 +13479,7 @@ pub fn _mm256_maskz_cvtpd_ph(k: __mmask8, a: __m256d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtpd_ph(a: __m512d) -> __m128h { _mm512_mask_cvtpd_ph(f16x8::ZERO.as_m128h(), 0xff, a) } @@ -13492,7 +13492,7 @@ pub fn _mm512_cvtpd_ph(a: __m512d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m512d) -> __m128h { unsafe { vcvtpd2ph_512(a, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -13505,7 +13505,7 @@ pub fn _mm512_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m512d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtpd_ph(k: __mmask8, a: __m512d) -> __m128h { _mm512_mask_cvtpd_ph(f16x8::ZERO.as_m128h(), k, a) } @@ -13526,7 +13526,7 @@ pub fn _mm512_maskz_cvtpd_ph(k: __mmask8, a: __m512d) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundpd_ph(a: __m512d) -> __m128h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundpd_ph::(f16x8::ZERO.as_m128h(), 0xff, a) @@ -13549,7 +13549,7 @@ pub fn _mm512_cvt_roundpd_ph(a: __m512d) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundpd_ph( src: __m128h, k: __mmask8, @@ -13578,7 +13578,7 @@ pub fn _mm512_mask_cvt_roundpd_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundpd_ph(k: __mmask8, a: __m512d) -> __m128h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundpd_ph::(f16x8::ZERO.as_m128h(), k, a) @@ -13592,7 +13592,7 @@ pub fn _mm512_maskz_cvt_roundpd_ph(k: __mmask8, a: __m512d) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsd_sh(a: __m128h, b: __m128d) -> __m128h { _mm_mask_cvtsd_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -13606,7 +13606,7 @@ pub fn _mm_cvtsd_sh(a: __m128h, b: __m128d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtsd_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128d) -> __m128h { unsafe { vcvtsd2sh(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -13620,7 +13620,7 @@ pub fn _mm_mask_cvtsd_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128d) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtsd_sh(k: __mmask8, a: __m128h, b: __m128d) -> __m128h { _mm_mask_cvtsd_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -13642,7 +13642,7 @@ pub fn _mm_maskz_cvtsd_sh(k: __mmask8, a: __m128h, b: __m128d) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsd_sh(a: __m128h, b: __m128d) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_cvt_roundsd_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -13666,7 +13666,7 @@ pub fn _mm_cvt_roundsd_sh(a: __m128h, b: __m128d) -> __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvt_roundsd_sh( src: __m128h, k: __mmask8, @@ -13697,7 +13697,7 @@ pub fn _mm_mask_cvt_roundsd_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvt_roundsd_sh( k: __mmask8, a: __m128h, @@ -13714,7 +13714,7 @@ pub fn _mm_maskz_cvt_roundsd_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epi16(a: __m128h) -> __m128i { _mm_mask_cvtph_epi16(_mm_undefined_si128(), 0xff, a) } @@ -13727,7 +13727,7 @@ pub fn _mm_cvtph_epi16(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2w_128(a, src.as_i16x8(), k)) } } @@ -13739,7 +13739,7 @@ pub fn _mm_mask_cvtph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epi16(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epi16(_mm_setzero_si128(), k, a) } @@ -13751,7 +13751,7 @@ pub fn _mm_maskz_cvtph_epi16(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epi16(a: __m256h) -> __m256i { _mm256_mask_cvtph_epi16(_mm256_undefined_si256(), 0xffff, a) } @@ -13764,7 +13764,7 @@ pub fn _mm256_cvtph_epi16(a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i { unsafe { transmute(vcvtph2w_256(a, src.as_i16x16(), k)) } } @@ -13776,7 +13776,7 @@ pub fn _mm256_mask_cvtph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epi16(k: __mmask16, a: __m256h) -> __m256i { _mm256_mask_cvtph_epi16(_mm256_setzero_si256(), k, a) } @@ -13788,7 +13788,7 @@ pub fn _mm256_maskz_cvtph_epi16(k: __mmask16, a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epi16(a: __m512h) -> __m512i { _mm512_mask_cvtph_epi16(_mm512_undefined_epi32(), 0xffffffff, a) } @@ -13801,7 +13801,7 @@ pub fn _mm512_cvtph_epi16(a: __m512h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i { unsafe { transmute(vcvtph2w_512( @@ -13820,7 +13820,7 @@ pub fn _mm512_mask_cvtph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epi16(k: __mmask32, a: __m512h) -> __m512i { _mm512_mask_cvtph_epi16(_mm512_setzero_si512(), k, a) } @@ -13841,7 +13841,7 @@ pub fn _mm512_maskz_cvtph_epi16(k: __mmask32, a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epi16(a: __m512h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi16::(_mm512_undefined_epi32(), 0xffffffff, a) @@ -13864,7 +13864,7 @@ pub fn _mm512_cvt_roundph_epi16(a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epi16( src: __m512i, k: __mmask32, @@ -13892,7 +13892,7 @@ pub fn _mm512_mask_cvt_roundph_epi16( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epi16(k: __mmask32, a: __m512h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi16::(_mm512_setzero_si512(), k, a) @@ -13905,7 +13905,7 @@ pub fn _mm512_maskz_cvt_roundph_epi16(k: __mmask32, a: __m5 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epu16(a: __m128h) -> __m128i { _mm_mask_cvtph_epu16(_mm_undefined_si128(), 0xff, a) } @@ -13918,7 +13918,7 @@ pub fn _mm_cvtph_epu16(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2uw_128(a, src.as_u16x8(), k)) } } @@ -13930,7 +13930,7 @@ pub fn _mm_mask_cvtph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epu16(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epu16(_mm_setzero_si128(), k, a) } @@ -13942,7 +13942,7 @@ pub fn _mm_maskz_cvtph_epu16(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epu16(a: __m256h) -> __m256i { _mm256_mask_cvtph_epu16(_mm256_undefined_si256(), 0xffff, a) } @@ -13955,7 +13955,7 @@ pub fn _mm256_cvtph_epu16(a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i { unsafe { transmute(vcvtph2uw_256(a, src.as_u16x16(), k)) } } @@ -13967,7 +13967,7 @@ pub fn _mm256_mask_cvtph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epu16(k: __mmask16, a: __m256h) -> __m256i { _mm256_mask_cvtph_epu16(_mm256_setzero_si256(), k, a) } @@ -13979,7 +13979,7 @@ pub fn _mm256_maskz_cvtph_epu16(k: __mmask16, a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epu16(a: __m512h) -> __m512i { _mm512_mask_cvtph_epu16(_mm512_undefined_epi32(), 0xffffffff, a) } @@ -13992,7 +13992,7 @@ pub fn _mm512_cvtph_epu16(a: __m512h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i { unsafe { transmute(vcvtph2uw_512( @@ -14011,7 +14011,7 @@ pub fn _mm512_mask_cvtph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epu16(k: __mmask32, a: __m512h) -> __m512i { _mm512_mask_cvtph_epu16(_mm512_setzero_si512(), k, a) } @@ -14026,7 +14026,7 @@ pub fn _mm512_maskz_cvtph_epu16(k: __mmask32, a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epu16(a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvt_roundph_epu16::(_mm512_undefined_epi32(), 0xffffffff, a) @@ -14043,7 +14043,7 @@ pub fn _mm512_cvt_roundph_epu16(a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epu16( src: __m512i, k: __mmask32, @@ -14065,7 +14065,7 @@ pub fn _mm512_mask_cvt_roundph_epu16( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epu16(k: __mmask32, a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvt_roundph_epu16::(_mm512_setzero_si512(), k, a) @@ -14078,7 +14078,7 @@ pub fn _mm512_maskz_cvt_roundph_epu16(k: __mmask32, a: __m512h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epi16(a: __m128h) -> __m128i { _mm_mask_cvttph_epi16(_mm_undefined_si128(), 0xff, a) } @@ -14091,7 +14091,7 @@ pub fn _mm_cvttph_epi16(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2w_128(a, src.as_i16x8(), k)) } } @@ -14104,7 +14104,7 @@ pub fn _mm_mask_cvttph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epi16(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epi16(_mm_setzero_si128(), k, a) } @@ -14116,7 +14116,7 @@ pub fn _mm_maskz_cvttph_epi16(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epi16(a: __m256h) -> __m256i { _mm256_mask_cvttph_epi16(_mm256_undefined_si256(), 0xffff, a) } @@ -14129,7 +14129,7 @@ pub fn _mm256_cvttph_epi16(a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i { unsafe { transmute(vcvttph2w_256(a, src.as_i16x16(), k)) } } @@ -14142,7 +14142,7 @@ pub fn _mm256_mask_cvttph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epi16(k: __mmask16, a: __m256h) -> __m256i { _mm256_mask_cvttph_epi16(_mm256_setzero_si256(), k, a) } @@ -14154,7 +14154,7 @@ pub fn _mm256_maskz_cvttph_epi16(k: __mmask16, a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epi16(a: __m512h) -> __m512i { _mm512_mask_cvttph_epi16(_mm512_undefined_epi32(), 0xffffffff, a) } @@ -14167,7 +14167,7 @@ pub fn _mm512_cvttph_epi16(a: __m512h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i { unsafe { transmute(vcvttph2w_512( @@ -14187,7 +14187,7 @@ pub fn _mm512_mask_cvttph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epi16(k: __mmask32, a: __m512h) -> __m512i { _mm512_mask_cvttph_epi16(_mm512_setzero_si512(), k, a) } @@ -14202,7 +14202,7 @@ pub fn _mm512_maskz_cvttph_epi16(k: __mmask32, a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epi16(a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi16::(_mm512_undefined_epi32(), 0xffffffff, a) @@ -14219,7 +14219,7 @@ pub fn _mm512_cvtt_roundph_epi16(a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epi16( src: __m512i, k: __mmask32, @@ -14242,7 +14242,7 @@ pub fn _mm512_mask_cvtt_roundph_epi16( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epi16(k: __mmask32, a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi16::(_mm512_setzero_si512(), k, a) @@ -14255,7 +14255,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi16(k: __mmask32, a: __m512h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epu16(a: __m128h) -> __m128i { _mm_mask_cvttph_epu16(_mm_undefined_si128(), 0xff, a) } @@ -14268,7 +14268,7 @@ pub fn _mm_cvttph_epu16(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2uw_128(a, src.as_u16x8(), k)) } } @@ -14281,7 +14281,7 @@ pub fn _mm_mask_cvttph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epu16(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epu16(_mm_setzero_si128(), k, a) } @@ -14293,7 +14293,7 @@ pub fn _mm_maskz_cvttph_epu16(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epu16(a: __m256h) -> __m256i { _mm256_mask_cvttph_epu16(_mm256_undefined_si256(), 0xffff, a) } @@ -14306,7 +14306,7 @@ pub fn _mm256_cvttph_epu16(a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i { unsafe { transmute(vcvttph2uw_256(a, src.as_u16x16(), k)) } } @@ -14319,7 +14319,7 @@ pub fn _mm256_mask_cvttph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epu16(k: __mmask16, a: __m256h) -> __m256i { _mm256_mask_cvttph_epu16(_mm256_setzero_si256(), k, a) } @@ -14331,7 +14331,7 @@ pub fn _mm256_maskz_cvttph_epu16(k: __mmask16, a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epu16(a: __m512h) -> __m512i { _mm512_mask_cvttph_epu16(_mm512_undefined_epi32(), 0xffffffff, a) } @@ -14344,7 +14344,7 @@ pub fn _mm512_cvttph_epu16(a: __m512h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i { unsafe { transmute(vcvttph2uw_512( @@ -14364,7 +14364,7 @@ pub fn _mm512_mask_cvttph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epu16(k: __mmask32, a: __m512h) -> __m512i { _mm512_mask_cvttph_epu16(_mm512_setzero_si512(), k, a) } @@ -14379,7 +14379,7 @@ pub fn _mm512_maskz_cvttph_epu16(k: __mmask32, a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epu16(a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu16::(_mm512_undefined_epi32(), 0xffffffff, a) @@ -14396,7 +14396,7 @@ pub fn _mm512_cvtt_roundph_epu16(a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epu16( src: __m512i, k: __mmask32, @@ -14419,7 +14419,7 @@ pub fn _mm512_mask_cvtt_roundph_epu16( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epu16(k: __mmask32, a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu16::(_mm512_setzero_si512(), k, a) @@ -14432,7 +14432,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu16(k: __mmask32, a: __m512h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epi32(a: __m128h) -> __m128i { _mm_mask_cvtph_epi32(_mm_undefined_si128(), 0xff, a) } @@ -14444,7 +14444,7 @@ pub fn _mm_cvtph_epi32(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2dq_128(a, src.as_i32x4(), k)) } } @@ -14456,7 +14456,7 @@ pub fn _mm_mask_cvtph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epi32(_mm_setzero_si128(), k, a) } @@ -14468,7 +14468,7 @@ pub fn _mm_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epi32(a: __m128h) -> __m256i { _mm256_mask_cvtph_epi32(_mm256_undefined_si256(), 0xff, a) } @@ -14480,7 +14480,7 @@ pub fn _mm256_cvtph_epi32(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvtph2dq_256(a, src.as_i32x8(), k)) } } @@ -14492,7 +14492,7 @@ pub fn _mm256_mask_cvtph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvtph_epi32(_mm256_setzero_si256(), k, a) } @@ -14504,7 +14504,7 @@ pub fn _mm256_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epi32(a: __m256h) -> __m512i { _mm512_mask_cvtph_epi32(_mm512_undefined_epi32(), 0xffff, a) } @@ -14516,7 +14516,7 @@ pub fn _mm512_cvtph_epi32(a: __m256h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i { unsafe { transmute(vcvtph2dq_512( @@ -14535,7 +14535,7 @@ pub fn _mm512_mask_cvtph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epi32(k: __mmask16, a: __m256h) -> __m512i { _mm512_mask_cvtph_epi32(_mm512_setzero_si512(), k, a) } @@ -14556,7 +14556,7 @@ pub fn _mm512_maskz_cvtph_epi32(k: __mmask16, a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epi32(a: __m256h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi32::(_mm512_undefined_epi32(), 0xffff, a) @@ -14578,7 +14578,7 @@ pub fn _mm512_cvt_roundph_epi32(a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epi32( src: __m512i, k: __mmask16, @@ -14606,7 +14606,7 @@ pub fn _mm512_mask_cvt_roundph_epi32( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epi32(k: __mmask16, a: __m256h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi32::(_mm512_setzero_si512(), k, a) @@ -14619,7 +14619,7 @@ pub fn _mm512_maskz_cvt_roundph_epi32(k: __mmask16, a: __m2 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2si))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_i32(a: __m128h) -> i32 { unsafe { vcvtsh2si32(a, _MM_FROUND_CUR_DIRECTION) } } @@ -14640,7 +14640,7 @@ pub fn _mm_cvtsh_i32(a: __m128h) -> i32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_i32(a: __m128h) -> i32 { unsafe { static_assert_rounding!(ROUNDING); @@ -14655,7 +14655,7 @@ pub fn _mm_cvt_roundsh_i32(a: __m128h) -> i32 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epu32(a: __m128h) -> __m128i { _mm_mask_cvtph_epu32(_mm_undefined_si128(), 0xff, a) } @@ -14667,7 +14667,7 @@ pub fn _mm_cvtph_epu32(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2udq_128(a, src.as_u32x4(), k)) } } @@ -14679,7 +14679,7 @@ pub fn _mm_mask_cvtph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epu32(_mm_setzero_si128(), k, a) } @@ -14691,7 +14691,7 @@ pub fn _mm_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epu32(a: __m128h) -> __m256i { _mm256_mask_cvtph_epu32(_mm256_undefined_si256(), 0xff, a) } @@ -14703,7 +14703,7 @@ pub fn _mm256_cvtph_epu32(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvtph2udq_256(a, src.as_u32x8(), k)) } } @@ -14715,7 +14715,7 @@ pub fn _mm256_mask_cvtph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvtph_epu32(_mm256_setzero_si256(), k, a) } @@ -14727,7 +14727,7 @@ pub fn _mm256_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epu32(a: __m256h) -> __m512i { _mm512_mask_cvtph_epu32(_mm512_undefined_epi32(), 0xffff, a) } @@ -14739,7 +14739,7 @@ pub fn _mm512_cvtph_epu32(a: __m256h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i { unsafe { transmute(vcvtph2udq_512( @@ -14758,7 +14758,7 @@ pub fn _mm512_mask_cvtph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epu32(k: __mmask16, a: __m256h) -> __m512i { _mm512_mask_cvtph_epu32(_mm512_setzero_si512(), k, a) } @@ -14779,7 +14779,7 @@ pub fn _mm512_maskz_cvtph_epu32(k: __mmask16, a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epu32(a: __m256h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epu32::(_mm512_undefined_epi32(), 0xffff, a) @@ -14801,7 +14801,7 @@ pub fn _mm512_cvt_roundph_epu32(a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epu32( src: __m512i, k: __mmask16, @@ -14829,7 +14829,7 @@ pub fn _mm512_mask_cvt_roundph_epu32( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epu32(k: __mmask16, a: __m256h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epu32::(_mm512_setzero_si512(), k, a) @@ -14842,7 +14842,7 @@ pub fn _mm512_maskz_cvt_roundph_epu32(k: __mmask16, a: __m2 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2usi))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_u32(a: __m128h) -> u32 { unsafe { vcvtsh2usi32(a, _MM_FROUND_CUR_DIRECTION) } } @@ -14857,7 +14857,7 @@ pub fn _mm_cvtsh_u32(a: __m128h) -> u32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_u32(a: __m128h) -> u32 { unsafe { static_assert_rounding!(SAE); @@ -14872,7 +14872,7 @@ pub fn _mm_cvt_roundsh_u32(a: __m128h) -> u32 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epi32(a: __m128h) -> __m128i { _mm_mask_cvttph_epi32(_mm_undefined_si128(), 0xff, a) } @@ -14884,7 +14884,7 @@ pub fn _mm_cvttph_epi32(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2dq_128(a, src.as_i32x4(), k)) } } @@ -14896,7 +14896,7 @@ pub fn _mm_mask_cvttph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epi32(_mm_setzero_si128(), k, a) } @@ -14908,7 +14908,7 @@ pub fn _mm_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epi32(a: __m128h) -> __m256i { _mm256_mask_cvttph_epi32(_mm256_undefined_si256(), 0xff, a) } @@ -14920,7 +14920,7 @@ pub fn _mm256_cvttph_epi32(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvttph2dq_256(a, src.as_i32x8(), k)) } } @@ -14932,7 +14932,7 @@ pub fn _mm256_mask_cvttph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvttph_epi32(_mm256_setzero_si256(), k, a) } @@ -14944,7 +14944,7 @@ pub fn _mm256_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epi32(a: __m256h) -> __m512i { _mm512_mask_cvttph_epi32(_mm512_undefined_epi32(), 0xffff, a) } @@ -14956,7 +14956,7 @@ pub fn _mm512_cvttph_epi32(a: __m256h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i { unsafe { transmute(vcvttph2dq_512( @@ -14975,7 +14975,7 @@ pub fn _mm512_mask_cvttph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epi32(k: __mmask16, a: __m256h) -> __m512i { _mm512_mask_cvttph_epi32(_mm512_setzero_si512(), k, a) } @@ -14990,7 +14990,7 @@ pub fn _mm512_maskz_cvttph_epi32(k: __mmask16, a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epi32(a: __m256h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi32::(_mm512_undefined_epi32(), 0xffff, a) @@ -15006,7 +15006,7 @@ pub fn _mm512_cvtt_roundph_epi32(a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epi32( src: __m512i, k: __mmask16, @@ -15028,7 +15028,7 @@ pub fn _mm512_mask_cvtt_roundph_epi32( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epi32(k: __mmask16, a: __m256h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi32::(_mm512_setzero_si512(), k, a) @@ -15041,7 +15041,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi32(k: __mmask16, a: __m256h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2si))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttsh_i32(a: __m128h) -> i32 { unsafe { vcvttsh2si32(a, _MM_FROUND_CUR_DIRECTION) } } @@ -15056,7 +15056,7 @@ pub fn _mm_cvttsh_i32(a: __m128h) -> i32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2si, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtt_roundsh_i32(a: __m128h) -> i32 { unsafe { static_assert_sae!(SAE); @@ -15071,7 +15071,7 @@ pub fn _mm_cvtt_roundsh_i32(a: __m128h) -> i32 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epu32(a: __m128h) -> __m128i { _mm_mask_cvttph_epu32(_mm_undefined_si128(), 0xff, a) } @@ -15083,7 +15083,7 @@ pub fn _mm_cvttph_epu32(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2udq_128(a, src.as_u32x4(), k)) } } @@ -15095,7 +15095,7 @@ pub fn _mm_mask_cvttph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epu32(_mm_setzero_si128(), k, a) } @@ -15107,7 +15107,7 @@ pub fn _mm_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epu32(a: __m128h) -> __m256i { _mm256_mask_cvttph_epu32(_mm256_undefined_si256(), 0xff, a) } @@ -15119,7 +15119,7 @@ pub fn _mm256_cvttph_epu32(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvttph2udq_256(a, src.as_u32x8(), k)) } } @@ -15131,7 +15131,7 @@ pub fn _mm256_mask_cvttph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvttph_epu32(_mm256_setzero_si256(), k, a) } @@ -15143,7 +15143,7 @@ pub fn _mm256_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epu32(a: __m256h) -> __m512i { _mm512_mask_cvttph_epu32(_mm512_undefined_epi32(), 0xffff, a) } @@ -15155,7 +15155,7 @@ pub fn _mm512_cvttph_epu32(a: __m256h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i { unsafe { transmute(vcvttph2udq_512( @@ -15174,7 +15174,7 @@ pub fn _mm512_mask_cvttph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epu32(k: __mmask16, a: __m256h) -> __m512i { _mm512_mask_cvttph_epu32(_mm512_setzero_si512(), k, a) } @@ -15189,7 +15189,7 @@ pub fn _mm512_maskz_cvttph_epu32(k: __mmask16, a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epu32(a: __m256h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu32::(_mm512_undefined_epi32(), 0xffff, a) @@ -15205,7 +15205,7 @@ pub fn _mm512_cvtt_roundph_epu32(a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epu32( src: __m512i, k: __mmask16, @@ -15227,7 +15227,7 @@ pub fn _mm512_mask_cvtt_roundph_epu32( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epu32(k: __mmask16, a: __m256h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu32::(_mm512_setzero_si512(), k, a) @@ -15240,7 +15240,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu32(k: __mmask16, a: __m256h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2usi))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttsh_u32(a: __m128h) -> u32 { unsafe { vcvttsh2usi32(a, _MM_FROUND_CUR_DIRECTION) } } @@ -15255,7 +15255,7 @@ pub fn _mm_cvttsh_u32(a: __m128h) -> u32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtt_roundsh_u32(a: __m128h) -> u32 { unsafe { static_assert_sae!(SAE); @@ -15270,7 +15270,7 @@ pub fn _mm_cvtt_roundsh_u32(a: __m128h) -> u32 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epi64(a: __m128h) -> __m128i { _mm_mask_cvtph_epi64(_mm_undefined_si128(), 0xff, a) } @@ -15282,7 +15282,7 @@ pub fn _mm_cvtph_epi64(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2qq_128(a, src.as_i64x2(), k)) } } @@ -15294,7 +15294,7 @@ pub fn _mm_mask_cvtph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epi64(_mm_setzero_si128(), k, a) } @@ -15306,7 +15306,7 @@ pub fn _mm_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epi64(a: __m128h) -> __m256i { _mm256_mask_cvtph_epi64(_mm256_undefined_si256(), 0xff, a) } @@ -15318,7 +15318,7 @@ pub fn _mm256_cvtph_epi64(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvtph2qq_256(a, src.as_i64x4(), k)) } } @@ -15330,7 +15330,7 @@ pub fn _mm256_mask_cvtph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvtph_epi64(_mm256_setzero_si256(), k, a) } @@ -15342,7 +15342,7 @@ pub fn _mm256_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epi64(a: __m128h) -> __m512i { _mm512_mask_cvtph_epi64(_mm512_undefined_epi32(), 0xff, a) } @@ -15354,7 +15354,7 @@ pub fn _mm512_cvtph_epi64(a: __m128h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i { unsafe { transmute(vcvtph2qq_512( @@ -15373,7 +15373,7 @@ pub fn _mm512_mask_cvtph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m512i { _mm512_mask_cvtph_epi64(_mm512_setzero_si512(), k, a) } @@ -15394,7 +15394,7 @@ pub fn _mm512_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epi64(a: __m128h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi64::(_mm512_undefined_epi32(), 0xff, a) @@ -15416,7 +15416,7 @@ pub fn _mm512_cvt_roundph_epi64(a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epi64( src: __m512i, k: __mmask8, @@ -15444,7 +15444,7 @@ pub fn _mm512_mask_cvt_roundph_epi64( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epi64(k: __mmask8, a: __m128h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi64::(_mm512_setzero_si512(), k, a) @@ -15457,7 +15457,7 @@ pub fn _mm512_maskz_cvt_roundph_epi64(k: __mmask8, a: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epu64(a: __m128h) -> __m128i { _mm_mask_cvtph_epu64(_mm_undefined_si128(), 0xff, a) } @@ -15469,7 +15469,7 @@ pub fn _mm_cvtph_epu64(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2uqq_128(a, src.as_u64x2(), k)) } } @@ -15481,7 +15481,7 @@ pub fn _mm_mask_cvtph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epu64(_mm_setzero_si128(), k, a) } @@ -15493,7 +15493,7 @@ pub fn _mm_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epu64(a: __m128h) -> __m256i { _mm256_mask_cvtph_epu64(_mm256_undefined_si256(), 0xff, a) } @@ -15505,7 +15505,7 @@ pub fn _mm256_cvtph_epu64(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvtph2uqq_256(a, src.as_u64x4(), k)) } } @@ -15517,7 +15517,7 @@ pub fn _mm256_mask_cvtph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvtph_epu64(_mm256_setzero_si256(), k, a) } @@ -15529,7 +15529,7 @@ pub fn _mm256_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epu64(a: __m128h) -> __m512i { _mm512_mask_cvtph_epu64(_mm512_undefined_epi32(), 0xff, a) } @@ -15541,7 +15541,7 @@ pub fn _mm512_cvtph_epu64(a: __m128h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i { unsafe { transmute(vcvtph2uqq_512( @@ -15560,7 +15560,7 @@ pub fn _mm512_mask_cvtph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m512i { _mm512_mask_cvtph_epu64(_mm512_setzero_si512(), k, a) } @@ -15581,7 +15581,7 @@ pub fn _mm512_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epu64(a: __m128h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epu64::(_mm512_undefined_epi32(), 0xff, a) @@ -15603,7 +15603,7 @@ pub fn _mm512_cvt_roundph_epu64(a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epu64( src: __m512i, k: __mmask8, @@ -15631,7 +15631,7 @@ pub fn _mm512_mask_cvt_roundph_epu64( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epu64(k: __mmask8, a: __m128h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epu64::(_mm512_setzero_si512(), k, a) @@ -15644,7 +15644,7 @@ pub fn _mm512_maskz_cvt_roundph_epu64(k: __mmask8, a: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epi64(a: __m128h) -> __m128i { _mm_mask_cvttph_epi64(_mm_undefined_si128(), 0xff, a) } @@ -15656,7 +15656,7 @@ pub fn _mm_cvttph_epi64(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2qq_128(a, src.as_i64x2(), k)) } } @@ -15668,7 +15668,7 @@ pub fn _mm_mask_cvttph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epi64(_mm_setzero_si128(), k, a) } @@ -15680,7 +15680,7 @@ pub fn _mm_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epi64(a: __m128h) -> __m256i { _mm256_mask_cvttph_epi64(_mm256_undefined_si256(), 0xff, a) } @@ -15692,7 +15692,7 @@ pub fn _mm256_cvttph_epi64(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvttph2qq_256(a, src.as_i64x4(), k)) } } @@ -15704,7 +15704,7 @@ pub fn _mm256_mask_cvttph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvttph_epi64(_mm256_setzero_si256(), k, a) } @@ -15716,7 +15716,7 @@ pub fn _mm256_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epi64(a: __m128h) -> __m512i { _mm512_mask_cvttph_epi64(_mm512_undefined_epi32(), 0xff, a) } @@ -15728,7 +15728,7 @@ pub fn _mm512_cvttph_epi64(a: __m128h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i { unsafe { transmute(vcvttph2qq_512( @@ -15747,7 +15747,7 @@ pub fn _mm512_mask_cvttph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m512i { _mm512_mask_cvttph_epi64(_mm512_setzero_si512(), k, a) } @@ -15762,7 +15762,7 @@ pub fn _mm512_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epi64(a: __m128h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi64::(_mm512_undefined_epi32(), 0xff, a) @@ -15778,7 +15778,7 @@ pub fn _mm512_cvtt_roundph_epi64(a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epi64( src: __m512i, k: __mmask8, @@ -15800,7 +15800,7 @@ pub fn _mm512_mask_cvtt_roundph_epi64( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epi64(k: __mmask8, a: __m128h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi64::(_mm512_setzero_si512(), k, a) @@ -15813,7 +15813,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi64(k: __mmask8, a: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epu64(a: __m128h) -> __m128i { _mm_mask_cvttph_epu64(_mm_undefined_si128(), 0xff, a) } @@ -15825,7 +15825,7 @@ pub fn _mm_cvttph_epu64(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2uqq_128(a, src.as_u64x2(), k)) } } @@ -15837,7 +15837,7 @@ pub fn _mm_mask_cvttph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epu64(_mm_setzero_si128(), k, a) } @@ -15849,7 +15849,7 @@ pub fn _mm_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epu64(a: __m128h) -> __m256i { _mm256_mask_cvttph_epu64(_mm256_undefined_si256(), 0xff, a) } @@ -15861,7 +15861,7 @@ pub fn _mm256_cvttph_epu64(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvttph2uqq_256(a, src.as_u64x4(), k)) } } @@ -15873,7 +15873,7 @@ pub fn _mm256_mask_cvttph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvttph_epu64(_mm256_setzero_si256(), k, a) } @@ -15885,7 +15885,7 @@ pub fn _mm256_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epu64(a: __m128h) -> __m512i { _mm512_mask_cvttph_epu64(_mm512_undefined_epi32(), 0xff, a) } @@ -15897,7 +15897,7 @@ pub fn _mm512_cvttph_epu64(a: __m128h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i { unsafe { transmute(vcvttph2uqq_512( @@ -15916,7 +15916,7 @@ pub fn _mm512_mask_cvttph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m512i { _mm512_mask_cvttph_epu64(_mm512_setzero_si512(), k, a) } @@ -15931,7 +15931,7 @@ pub fn _mm512_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epu64(a: __m128h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu64::(_mm512_undefined_epi32(), 0xff, a) @@ -15947,7 +15947,7 @@ pub fn _mm512_cvtt_roundph_epu64(a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epu64( src: __m512i, k: __mmask8, @@ -15969,7 +15969,7 @@ pub fn _mm512_mask_cvtt_roundph_epu64( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epu64(k: __mmask8, a: __m128h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu64::(_mm512_setzero_si512(), k, a) @@ -15982,7 +15982,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu64(k: __mmask8, a: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtxph_ps(a: __m128h) -> __m128 { _mm_mask_cvtxph_ps(_mm_setzero_ps(), 0xff, a) } @@ -15995,7 +15995,7 @@ pub fn _mm_cvtxph_ps(a: __m128h) -> __m128 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtxph_ps(src: __m128, k: __mmask8, a: __m128h) -> __m128 { unsafe { vcvtph2psx_128(a, src, k) } } @@ -16008,7 +16008,7 @@ pub fn _mm_mask_cvtxph_ps(src: __m128, k: __mmask8, a: __m128h) -> __m128 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m128 { _mm_mask_cvtxph_ps(_mm_setzero_ps(), k, a) } @@ -16020,7 +16020,7 @@ pub fn _mm_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m128 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtxph_ps(a: __m128h) -> __m256 { _mm256_mask_cvtxph_ps(_mm256_setzero_ps(), 0xff, a) } @@ -16033,7 +16033,7 @@ pub fn _mm256_cvtxph_ps(a: __m128h) -> __m256 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtxph_ps(src: __m256, k: __mmask8, a: __m128h) -> __m256 { unsafe { vcvtph2psx_256(a, src, k) } } @@ -16046,7 +16046,7 @@ pub fn _mm256_mask_cvtxph_ps(src: __m256, k: __mmask8, a: __m128h) -> __m256 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m256 { _mm256_mask_cvtxph_ps(_mm256_setzero_ps(), k, a) } @@ -16058,7 +16058,7 @@ pub fn _mm256_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m256 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtxph_ps(a: __m256h) -> __m512 { _mm512_mask_cvtxph_ps(_mm512_setzero_ps(), 0xffff, a) } @@ -16071,7 +16071,7 @@ pub fn _mm512_cvtxph_ps(a: __m256h) -> __m512 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtxph_ps(src: __m512, k: __mmask16, a: __m256h) -> __m512 { unsafe { vcvtph2psx_512(a, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -16084,7 +16084,7 @@ pub fn _mm512_mask_cvtxph_ps(src: __m512, k: __mmask16, a: __m256h) -> __m512 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtxph_ps(k: __mmask16, a: __m256h) -> __m512 { _mm512_mask_cvtxph_ps(_mm512_setzero_ps(), k, a) } @@ -16099,7 +16099,7 @@ pub fn _mm512_maskz_cvtxph_ps(k: __mmask16, a: __m256h) -> __m512 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtx_roundph_ps(a: __m256h) -> __m512 { static_assert_sae!(SAE); _mm512_mask_cvtx_roundph_ps::(_mm512_setzero_ps(), 0xffff, a) @@ -16116,7 +16116,7 @@ pub fn _mm512_cvtx_roundph_ps(a: __m256h) -> __m512 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtx_roundph_ps( src: __m512, k: __mmask16, @@ -16139,7 +16139,7 @@ pub fn _mm512_mask_cvtx_roundph_ps( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtx_roundph_ps(k: __mmask16, a: __m256h) -> __m512 { static_assert_sae!(SAE); _mm512_mask_cvtx_roundph_ps::(_mm512_setzero_ps(), k, a) @@ -16153,7 +16153,7 @@ pub fn _mm512_maskz_cvtx_roundph_ps(k: __mmask16, a: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_ss(a: __m128, b: __m128h) -> __m128 { _mm_mask_cvtsh_ss(a, 0xff, a, b) } @@ -16167,7 +16167,7 @@ pub fn _mm_cvtsh_ss(a: __m128, b: __m128h) -> __m128 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtsh_ss(src: __m128, k: __mmask8, a: __m128, b: __m128h) -> __m128 { unsafe { vcvtsh2ss(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -16181,7 +16181,7 @@ pub fn _mm_mask_cvtsh_ss(src: __m128, k: __mmask8, a: __m128, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 { _mm_mask_cvtsh_ss(_mm_set_ss(0.0), k, a, b) } @@ -16197,7 +16197,7 @@ pub fn _mm_maskz_cvtsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_ss(a: __m128, b: __m128h) -> __m128 { static_assert_sae!(SAE); _mm_mask_cvt_roundsh_ss::(_mm_undefined_ps(), 0xff, a, b) @@ -16215,7 +16215,7 @@ pub fn _mm_cvt_roundsh_ss(a: __m128, b: __m128h) -> __m128 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvt_roundsh_ss( src: __m128, k: __mmask8, @@ -16240,7 +16240,7 @@ pub fn _mm_mask_cvt_roundsh_ss( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvt_roundsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 { static_assert_sae!(SAE); _mm_mask_cvt_roundsh_ss::(_mm_set_ss(0.0), k, a, b) @@ -16253,7 +16253,7 @@ pub fn _mm_maskz_cvt_roundsh_ss(k: __mmask8, a: __m128, b: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_pd(a: __m128h) -> __m128d { _mm_mask_cvtph_pd(_mm_setzero_pd(), 0xff, a) } @@ -16266,7 +16266,7 @@ pub fn _mm_cvtph_pd(a: __m128h) -> __m128d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_pd(src: __m128d, k: __mmask8, a: __m128h) -> __m128d { unsafe { vcvtph2pd_128(a, src, k) } } @@ -16279,7 +16279,7 @@ pub fn _mm_mask_cvtph_pd(src: __m128d, k: __mmask8, a: __m128h) -> __m128d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m128d { _mm_mask_cvtph_pd(_mm_setzero_pd(), k, a) } @@ -16291,7 +16291,7 @@ pub fn _mm_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m128d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_pd(a: __m128h) -> __m256d { _mm256_mask_cvtph_pd(_mm256_setzero_pd(), 0xff, a) } @@ -16304,7 +16304,7 @@ pub fn _mm256_cvtph_pd(a: __m128h) -> __m256d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_pd(src: __m256d, k: __mmask8, a: __m128h) -> __m256d { unsafe { vcvtph2pd_256(a, src, k) } } @@ -16317,7 +16317,7 @@ pub fn _mm256_mask_cvtph_pd(src: __m256d, k: __mmask8, a: __m128h) -> __m256d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m256d { _mm256_mask_cvtph_pd(_mm256_setzero_pd(), k, a) } @@ -16329,7 +16329,7 @@ pub fn _mm256_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m256d { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_pd(a: __m128h) -> __m512d { _mm512_mask_cvtph_pd(_mm512_setzero_pd(), 0xff, a) } @@ -16342,7 +16342,7 @@ pub fn _mm512_cvtph_pd(a: __m128h) -> __m512d { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_pd(src: __m512d, k: __mmask8, a: __m128h) -> __m512d { unsafe { vcvtph2pd_512(a, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -16355,7 +16355,7 @@ pub fn _mm512_mask_cvtph_pd(src: __m512d, k: __mmask8, a: __m128h) -> __m512d { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m512d { _mm512_mask_cvtph_pd(_mm512_setzero_pd(), k, a) } @@ -16370,7 +16370,7 @@ pub fn _mm512_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m512d { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_pd(a: __m128h) -> __m512d { static_assert_sae!(SAE); _mm512_mask_cvt_roundph_pd::(_mm512_setzero_pd(), 0xff, a) @@ -16387,7 +16387,7 @@ pub fn _mm512_cvt_roundph_pd(a: __m128h) -> __m512d { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_pd( src: __m512d, k: __mmask8, @@ -16410,7 +16410,7 @@ pub fn _mm512_mask_cvt_roundph_pd( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_pd(k: __mmask8, a: __m128h) -> __m512d { static_assert_sae!(SAE); _mm512_mask_cvt_roundph_pd::(_mm512_setzero_pd(), k, a) @@ -16424,7 +16424,7 @@ pub fn _mm512_maskz_cvt_roundph_pd(k: __mmask8, a: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_sd(a: __m128d, b: __m128h) -> __m128d { _mm_mask_cvtsh_sd(a, 0xff, a, b) } @@ -16438,7 +16438,7 @@ pub fn _mm_cvtsh_sd(a: __m128d, b: __m128h) -> __m128d { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtsh_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128h) -> __m128d { unsafe { vcvtsh2sd(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -16451,7 +16451,7 @@ pub fn _mm_mask_cvtsh_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d { _mm_mask_cvtsh_sd(_mm_set_sd(0.0), k, a, b) } @@ -16467,7 +16467,7 @@ pub fn _mm_maskz_cvtsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_sd(a: __m128d, b: __m128h) -> __m128d { static_assert_sae!(SAE); _mm_mask_cvt_roundsh_sd::(a, 0xff, a, b) @@ -16485,7 +16485,7 @@ pub fn _mm_cvt_roundsh_sd(a: __m128d, b: __m128h) -> __m128d { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvt_roundsh_sd( src: __m128d, k: __mmask8, @@ -16509,7 +16509,7 @@ pub fn _mm_mask_cvt_roundsh_sd( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvt_roundsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d { static_assert_sae!(SAE); _mm_mask_cvt_roundsh_sd::(_mm_set_sd(0.0), k, a, b) @@ -16553,7 +16553,7 @@ pub const fn _mm512_cvtsh_h(a: __m512h) -> f16 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi128_si16) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_cvtsi128_si16(a: __m128i) -> i16 { unsafe { simd_extract!(a.as_i16x8(), 0) } @@ -16564,7 +16564,7 @@ pub const fn _mm_cvtsi128_si16(a: __m128i) -> i16 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi16_si128) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_cvtsi16_si128(a: i16) -> __m128i { unsafe { transmute(simd_insert!(i16x8::ZERO, 0, a)) } diff --git a/stdarch/crates/core_arch/src/x86/avx512vnni.rs b/stdarch/crates/core_arch/src/x86/avx512vnni.rs index 49b790b151049..8cd8764f24868 100644 --- a/stdarch/crates/core_arch/src/x86/avx512vnni.rs +++ b/stdarch/crates/core_arch/src/x86/avx512vnni.rs @@ -12,7 +12,7 @@ use stdarch_test::assert_instr; #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm512_dpwssd_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpdpwssd(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) } + unsafe { transmute(vpdpwssd(src.as_i32x16(), a.as_i16x32(), b.as_i16x32())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -51,7 +51,7 @@ pub fn _mm512_maskz_dpwssd_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m5 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm256_dpwssd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i16x16(), b.as_i16x16())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst. @@ -62,7 +62,7 @@ pub fn _mm256_dpwssd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm256_dpwssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i16x16(), b.as_i16x16())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -101,7 +101,7 @@ pub fn _mm256_maskz_dpwssd_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m25 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm_dpwssd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i16x8(), b.as_i16x8())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst. @@ -112,7 +112,7 @@ pub fn _mm_dpwssd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm_dpwssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i16x8(), b.as_i16x8())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -151,7 +151,7 @@ pub fn _mm_maskz_dpwssd_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i) #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm512_dpwssds_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpdpwssds(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) } + unsafe { transmute(vpdpwssds(src.as_i32x16(), a.as_i16x32(), b.as_i16x32())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -190,7 +190,7 @@ pub fn _mm512_maskz_dpwssds_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm256_dpwssds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i16x16(), b.as_i16x16())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst. @@ -201,7 +201,7 @@ pub fn _mm256_dpwssds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm256_dpwssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i16x16(), b.as_i16x16())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -240,7 +240,7 @@ pub fn _mm256_maskz_dpwssds_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m2 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm_dpwssds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i16x8(), b.as_i16x8())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst. @@ -251,7 +251,7 @@ pub fn _mm_dpwssds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm_dpwssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i16x8(), b.as_i16x8())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding 16-bit integers in b, producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -290,7 +290,7 @@ pub fn _mm_maskz_dpwssds_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm512_dpbusd_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpdpbusd(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) } + unsafe { transmute(vpdpbusd(src.as_i32x16(), a.as_u8x64(), b.as_i8x64())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -329,7 +329,7 @@ pub fn _mm512_maskz_dpbusd_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m5 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm256_dpbusd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_u8x32(), b.as_i8x32())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst. @@ -340,7 +340,7 @@ pub fn _mm256_dpbusd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm256_dpbusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_u8x32(), b.as_i8x32())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -379,7 +379,7 @@ pub fn _mm256_maskz_dpbusd_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m25 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm_dpbusd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_u8x16(), b.as_i8x16())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst. @@ -390,7 +390,7 @@ pub fn _mm_dpbusd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm_dpbusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_u8x16(), b.as_i8x16())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -429,7 +429,7 @@ pub fn _mm_maskz_dpbusd_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i) #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm512_dpbusds_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { - unsafe { transmute(vpdpbusds(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) } + unsafe { transmute(vpdpbusds(src.as_i32x16(), a.as_u8x64(), b.as_i8x64())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -468,7 +468,7 @@ pub fn _mm512_maskz_dpbusds_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm256_dpbusds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_u8x32(), b.as_i8x32())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst. @@ -479,7 +479,7 @@ pub fn _mm256_dpbusds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm256_dpbusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_u8x32(), b.as_i8x32())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -518,7 +518,7 @@ pub fn _mm256_maskz_dpbusds_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m2 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm_dpbusds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_u8x16(), b.as_i8x16())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst. @@ -529,7 +529,7 @@ pub fn _mm_dpbusds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm_dpbusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_u8x16(), b.as_i8x16())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding signed 8-bit integers in b, producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in src using signed saturation, and store the packed 32-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -570,7 +570,7 @@ pub fn _mm_maskz_dpbusds_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i #[cfg_attr(test, assert_instr(vpdpbssd))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbssd_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbssd_128(src.as_i32x4(), a.as_i8x16(), b.as_i8x16())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding signed 8-bit @@ -583,7 +583,7 @@ pub fn _mm_dpbssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpbssd))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbssd_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbssd_256(src.as_i32x8(), a.as_i8x32(), b.as_i8x32())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding signed 8-bit @@ -596,7 +596,7 @@ pub fn _mm256_dpbssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpbssds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbssds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbssds_128(src.as_i32x4(), a.as_i8x16(), b.as_i8x16())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding signed 8-bit @@ -609,7 +609,7 @@ pub fn _mm_dpbssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpbssds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbssds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbssds_256(src.as_i32x8(), a.as_i8x32(), b.as_i8x32())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding unsigned 8-bit @@ -622,7 +622,7 @@ pub fn _mm256_dpbssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpbsud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbsud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbsud_128(src.as_i32x4(), a.as_i8x16(), b.as_u8x16())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding unsigned 8-bit @@ -635,7 +635,7 @@ pub fn _mm_dpbsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpbsud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbsud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbsud_256(src.as_i32x8(), a.as_i8x32(), b.as_u8x32())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding unsigned 8-bit @@ -648,7 +648,7 @@ pub fn _mm256_dpbsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpbsuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbsuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbsuds_128(src.as_i32x4(), a.as_i8x16(), b.as_u8x16())) } } /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in a with corresponding unsigned 8-bit @@ -661,7 +661,7 @@ pub fn _mm_dpbsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpbsuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbsuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbsuds_256(src.as_i32x8(), a.as_i8x32(), b.as_u8x32())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding unsigned 8-bit @@ -674,7 +674,7 @@ pub fn _mm256_dpbsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpbuud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbuud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbuud_128(src.as_i32x4(), a.as_u8x16(), b.as_u8x16())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding unsigned 8-bit @@ -687,7 +687,7 @@ pub fn _mm_dpbuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpbuud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbuud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbuud_256(src.as_i32x8(), a.as_u8x32(), b.as_u8x32())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding unsigned 8-bit @@ -700,7 +700,7 @@ pub fn _mm256_dpbuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpbuuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpbuuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpbuuds_128(src.as_i32x4(), a.as_u8x16(), b.as_u8x16())) } } /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in a with corresponding unsigned 8-bit @@ -713,7 +713,7 @@ pub fn _mm_dpbuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpbuuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpbuuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpbuuds_256(src.as_i32x8(), a.as_u8x32(), b.as_u8x32())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding unsigned 16-bit @@ -726,7 +726,7 @@ pub fn _mm256_dpbuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpwsud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwsud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwsud_128(src.as_i32x4(), a.as_i16x8(), b.as_u16x8())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding unsigned 16-bit @@ -739,7 +739,7 @@ pub fn _mm_dpwsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpwsud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwsud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwsud_256(src.as_i32x8(), a.as_i16x16(), b.as_u16x16())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding unsigned 16-bit @@ -752,7 +752,7 @@ pub fn _mm256_dpwsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpwsuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwsuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwsuds_128(src.as_i32x4(), a.as_i16x8(), b.as_u16x8())) } } /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in a with corresponding unsigned 16-bit @@ -765,7 +765,7 @@ pub fn _mm_dpwsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpwsuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwsuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwsuds_256(src.as_i32x8(), a.as_i16x16(), b.as_u16x16())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding signed 16-bit @@ -778,7 +778,7 @@ pub fn _mm256_dpwsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpwusd))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwusd_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwusd_128(src.as_i32x4(), a.as_u16x8(), b.as_i16x8())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding signed 16-bit @@ -791,7 +791,7 @@ pub fn _mm_dpwusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpwusd))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwusd_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwusd_256(src.as_i32x8(), a.as_u16x16(), b.as_i16x16())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding signed 16-bit @@ -804,7 +804,7 @@ pub fn _mm256_dpwusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpwusds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwusds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwusds_128(src.as_i32x4(), a.as_u16x8(), b.as_i16x8())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding signed 16-bit @@ -817,7 +817,7 @@ pub fn _mm_dpwusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpwusds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwusds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwusds_256(src.as_i32x8(), a.as_u16x16(), b.as_i16x16())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding unsigned 16-bit @@ -830,7 +830,7 @@ pub fn _mm256_dpwusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpwuud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwuud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwuud_128(src.as_i32x4(), a.as_u16x8(), b.as_u16x8())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding unsigned 16-bit @@ -843,7 +843,7 @@ pub fn _mm_dpwuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpwuud))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwuud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwuud_256(src.as_i32x8(), a.as_u16x16(), b.as_u16x16())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding unsigned 16-bit @@ -856,7 +856,7 @@ pub fn _mm256_dpwuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vpdpwuuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(vpdpwuuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } + unsafe { transmute(vpdpwuuds_128(src.as_i32x4(), a.as_u16x8(), b.as_u16x8())) } } /// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in a with corresponding unsigned 16-bit @@ -869,98 +869,98 @@ pub fn _mm_dpwuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(vpdpwuuds))] #[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(vpdpwuuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } + unsafe { transmute(vpdpwuuds_256(src.as_i32x8(), a.as_u16x16(), b.as_u16x16())) } } #[allow(improper_ctypes)] unsafe extern "C" { #[link_name = "llvm.x86.avx512.vpdpwssd.512"] - fn vpdpwssd(src: i32x16, a: i32x16, b: i32x16) -> i32x16; + fn vpdpwssd(src: i32x16, a: i16x32, b: i16x32) -> i32x16; #[link_name = "llvm.x86.avx512.vpdpwssd.256"] - fn vpdpwssd256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwssd256(src: i32x8, a: i16x16, b: i16x16) -> i32x8; #[link_name = "llvm.x86.avx512.vpdpwssd.128"] - fn vpdpwssd128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwssd128(src: i32x4, a: i16x8, b: i16x8) -> i32x4; #[link_name = "llvm.x86.avx512.vpdpwssds.512"] - fn vpdpwssds(src: i32x16, a: i32x16, b: i32x16) -> i32x16; + fn vpdpwssds(src: i32x16, a: i16x32, b: i16x32) -> i32x16; #[link_name = "llvm.x86.avx512.vpdpwssds.256"] - fn vpdpwssds256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwssds256(src: i32x8, a: i16x16, b: i16x16) -> i32x8; #[link_name = "llvm.x86.avx512.vpdpwssds.128"] - fn vpdpwssds128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwssds128(src: i32x4, a: i16x8, b: i16x8) -> i32x4; #[link_name = "llvm.x86.avx512.vpdpbusd.512"] - fn vpdpbusd(src: i32x16, a: i32x16, b: i32x16) -> i32x16; + fn vpdpbusd(src: i32x16, a: u8x64, b: i8x64) -> i32x16; #[link_name = "llvm.x86.avx512.vpdpbusd.256"] - fn vpdpbusd256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbusd256(src: i32x8, a: u8x32, b: i8x32) -> i32x8; #[link_name = "llvm.x86.avx512.vpdpbusd.128"] - fn vpdpbusd128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbusd128(src: i32x4, a: u8x16, b: i8x16) -> i32x4; #[link_name = "llvm.x86.avx512.vpdpbusds.512"] - fn vpdpbusds(src: i32x16, a: i32x16, b: i32x16) -> i32x16; + fn vpdpbusds(src: i32x16, a: u8x64, b: i8x64) -> i32x16; #[link_name = "llvm.x86.avx512.vpdpbusds.256"] - fn vpdpbusds256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbusds256(src: i32x8, a: u8x32, b: i8x32) -> i32x8; #[link_name = "llvm.x86.avx512.vpdpbusds.128"] - fn vpdpbusds128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbusds128(src: i32x4, a: u8x16, b: i8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbssd.128"] - fn vpdpbssd_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbssd_128(src: i32x4, a: i8x16, b: i8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbssd.256"] - fn vpdpbssd_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbssd_256(src: i32x8, a: i8x32, b: i8x32) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpbssds.128"] - fn vpdpbssds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbssds_128(src: i32x4, a: i8x16, b: i8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbssds.256"] - fn vpdpbssds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbssds_256(src: i32x8, a: i8x32, b: i8x32) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpbsud.128"] - fn vpdpbsud_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbsud_128(src: i32x4, a: i8x16, b: u8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbsud.256"] - fn vpdpbsud_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbsud_256(src: i32x8, a: i8x32, b: u8x32) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpbsuds.128"] - fn vpdpbsuds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbsuds_128(src: i32x4, a: i8x16, b: u8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbsuds.256"] - fn vpdpbsuds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbsuds_256(src: i32x8, a: i8x32, b: u8x32) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpbuud.128"] - fn vpdpbuud_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbuud_128(src: i32x4, a: u8x16, b: u8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbuud.256"] - fn vpdpbuud_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbuud_256(src: i32x8, a: u8x32, b: u8x32) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpbuuds.128"] - fn vpdpbuuds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpbuuds_128(src: i32x4, a: u8x16, b: u8x16) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpbuuds.256"] - fn vpdpbuuds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpbuuds_256(src: i32x8, a: u8x32, b: u8x32) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpwsud.128"] - fn vpdpwsud_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwsud_128(src: i32x4, a: i16x8, b: u16x8) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpwsud.256"] - fn vpdpwsud_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwsud_256(src: i32x8, a: i16x16, b: u16x16) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpwsuds.128"] - fn vpdpwsuds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwsuds_128(src: i32x4, a: i16x8, b: u16x8) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpwsuds.256"] - fn vpdpwsuds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwsuds_256(src: i32x8, a: i16x16, b: u16x16) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpwusd.128"] - fn vpdpwusd_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwusd_128(src: i32x4, a: u16x8, b: i16x8) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpwusd.256"] - fn vpdpwusd_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwusd_256(src: i32x8, a: u16x16, b: i16x16) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpwusds.128"] - fn vpdpwusds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwusds_128(src: i32x4, a: u16x8, b: i16x8) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpwusds.256"] - fn vpdpwusds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwusds_256(src: i32x8, a: u16x16, b: i16x16) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpwuud.128"] - fn vpdpwuud_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwuud_128(src: i32x4, a: u16x8, b: u16x8) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpwuud.256"] - fn vpdpwuud_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwuud_256(src: i32x8, a: u16x16, b: u16x16) -> i32x8; #[link_name = "llvm.x86.avx2.vpdpwuuds.128"] - fn vpdpwuuds_128(src: i32x4, a: i32x4, b: i32x4) -> i32x4; + fn vpdpwuuds_128(src: i32x4, a: u16x8, b: u16x8) -> i32x4; #[link_name = "llvm.x86.avx2.vpdpwuuds.256"] - fn vpdpwuuds_256(src: i32x8, a: i32x8, b: i32x8) -> i32x8; + fn vpdpwuuds_256(src: i32x8, a: u16x16, b: u16x16) -> i32x8; } #[cfg(test)] diff --git a/stdarch/crates/core_arch/src/x86/avxneconvert.rs b/stdarch/crates/core_arch/src/x86/avxneconvert.rs index 91b6be2b09d78..b8a3b9473af9e 100644 --- a/stdarch/crates/core_arch/src/x86/avxneconvert.rs +++ b/stdarch/crates/core_arch/src/x86/avxneconvert.rs @@ -87,7 +87,7 @@ pub unsafe fn _mm256_cvtneebf16_ps(a: *const __m256bh) -> __m256 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneeph2ps))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub unsafe fn _mm_cvtneeph_ps(a: *const __m128h) -> __m128 { transmute(cvtneeph2ps_128(a)) } @@ -99,7 +99,7 @@ pub unsafe fn _mm_cvtneeph_ps(a: *const __m128h) -> __m128 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneeph2ps))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub unsafe fn _mm256_cvtneeph_ps(a: *const __m256h) -> __m256 { transmute(cvtneeph2ps_256(a)) } @@ -135,7 +135,7 @@ pub unsafe fn _mm256_cvtneobf16_ps(a: *const __m256bh) -> __m256 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneoph2ps))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub unsafe fn _mm_cvtneoph_ps(a: *const __m128h) -> __m128 { transmute(cvtneoph2ps_128(a)) } @@ -147,7 +147,7 @@ pub unsafe fn _mm_cvtneoph_ps(a: *const __m128h) -> __m128 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneoph2ps))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub unsafe fn _mm256_cvtneoph_ps(a: *const __m256h) -> __m256 { transmute(cvtneoph2ps_256(a)) } diff --git a/stdarch/crates/core_arch/src/x86/mod.rs b/stdarch/crates/core_arch/src/x86/mod.rs index c40fbd3ca3178..68a963f65b7d4 100644 --- a/stdarch/crates/core_arch/src/x86/mod.rs +++ b/stdarch/crates/core_arch/src/x86/mod.rs @@ -401,7 +401,7 @@ types! { } types! { - #![stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] + #![stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] /// 128-bit wide set of 8 `f16` types, x86-specific /// @@ -768,9 +768,13 @@ mod avxneconvert; pub use self::avxneconvert::*; mod avx512fp16; -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub use self::avx512fp16::*; mod kl; #[stable(feature = "keylocker_x86", since = "1.89.0")] pub use self::kl::*; + +mod movrs; +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub use self::movrs::*; diff --git a/stdarch/crates/core_arch/src/x86/movrs.rs b/stdarch/crates/core_arch/src/x86/movrs.rs new file mode 100644 index 0000000000000..d5f4d146c44aa --- /dev/null +++ b/stdarch/crates/core_arch/src/x86/movrs.rs @@ -0,0 +1,23 @@ +//! Read-shared move intrinsics + +#[cfg(test)] +use stdarch_test::assert_instr; + +unsafe extern "unadjusted" { + #[link_name = "llvm.x86.prefetchrs"] + fn prefetchrs(p: *const u8); +} + +/// Prefetches the cache line that contains address `p`, with an indication that the source memory +/// location is likely to become read-shared by multiple processors, i.e., read in the future by at +/// least one other processor before it is written, assuming it is ever written in the future. +/// +/// Note: this intrinsic is safe to use even though it takes a raw pointer argument. In general, this +/// cannot change the behavior of the program, including not trapping on invalid pointers. +#[inline] +#[target_feature(enable = "movrs")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(prefetchrst2))] +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub fn _m_prefetchrs(p: *const u8) { + unsafe { prefetchrs(p) } +} diff --git a/stdarch/crates/core_arch/src/x86/sse.rs b/stdarch/crates/core_arch/src/x86/sse.rs index b83274e60e72a..9183eabd530ca 100644 --- a/stdarch/crates/core_arch/src/x86/sse.rs +++ b/stdarch/crates/core_arch/src/x86/sse.rs @@ -208,7 +208,7 @@ pub fn _mm_min_ss(a: __m128, b: __m128) -> __m128 { #[cfg_attr(test, assert_instr(minps))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm_min_ps(a: __m128, b: __m128) -> __m128 { - // See the `test_mm_min_ps` test why this can't be implemented using `simd_fmin`. + // See the `test_mm_min_ps` test why this can't be implemented using `simd_minimum_number_nsz`. unsafe { minps(a, b) } } @@ -234,7 +234,7 @@ pub fn _mm_max_ss(a: __m128, b: __m128) -> __m128 { #[cfg_attr(test, assert_instr(maxps))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm_max_ps(a: __m128, b: __m128) -> __m128 { - // See the `test_mm_min_ps` test why this can't be implemented using `simd_fmax`. + // See the `test_mm_min_ps` test why this can't be implemented using `simd_maximum_number_nsz`. unsafe { maxps(a, b) } } @@ -968,7 +968,7 @@ pub const fn _mm_set_ps1(a: f32) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_ps) #[inline] #[target_feature(enable = "sse")] -#[cfg_attr(test, assert_instr(unpcklps))] +// This intrinsic has no corresponding instruction. #[stable(feature = "simd_x86", since = "1.27.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_set_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 { @@ -2227,11 +2227,11 @@ mod tests { let r = _mm_min_ps(a, b); assert_eq_m128(r, _mm_setr_ps(-100.0, 5.0, 0.0, -10.0)); - // `_mm_min_ps` can **not** be implemented using the `simd_min` rust intrinsic. `simd_min` - // is lowered by the llvm codegen backend to `llvm.minnum.v*` llvm intrinsic. This intrinsic - // doesn't specify how -0.0 is handled. Unfortunately it happens to behave different from - // the `minps` x86 instruction on x86. The `llvm.minnum.v*` llvm intrinsic equals - // `r1` to `a` and `r2` to `b`. + // `_mm_min_ps` can **not** be implemented using the `simd_minimum_number_nsz` rust + // intrinsic. That intrinsic is lowered by the llvm codegen backend to `llvm.minimumnum.v*` + // llvm intrinsic with the `nsz` attribute. The `nsz` attribute means -0.0 is handled + // non-deterministically. The `minps` x86 instruction however has a deterministic semantics + // for signed zeros. let a = _mm_setr_ps(-0.0, 0.0, 0.0, 0.0); let b = _mm_setr_ps(0.0, 0.0, 0.0, 0.0); let r1 = _mm_min_ps(a, b).as_f32x4().to_bits(); @@ -2816,14 +2816,32 @@ mod tests { let aa = &[3.0f32, 12.0, 23.0, NAN]; let bb = &[3.0f32, 47.5, 1.5, NAN]; - let ee = &[1i32, 0, 1, 0]; + let ee = &[0i32, 0, 1, 0]; for i in 0..4 { let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0); let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0); - let r = _mm_comige_ss(a, b); + let r = _mm_comigt_ss(a, b); + + assert_eq!( + ee[i], r, + "_mm_comigt_ss({:?}, {:?}) = {}, expected: {} (i={})", + a, b, r, ee[i], i + ); + } + } + + #[simd_test(enable = "sse")] + fn test_mm_comige_ss() { + let aa = &[3.0f32, 23.0, 12.0, NAN]; + let bb = &[3.0f32, 1.5, 47.5, NAN]; + let ee = &[1i32, 1, 0, 0]; + for i in 0..4 { + let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0); + let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0); + let r = _mm_comige_ss(a, b); assert_eq!( ee[i], r, "_mm_comige_ss({:?}, {:?}) = {}, expected: {} (i={})", diff --git a/stdarch/crates/core_arch/src/x86/sse2.rs b/stdarch/crates/core_arch/src/x86/sse2.rs index f339a003df4d1..1f97f3c69d0e3 100644 --- a/stdarch/crates/core_arch/src/x86/sse2.rs +++ b/stdarch/crates/core_arch/src/x86/sse2.rs @@ -1484,7 +1484,7 @@ pub const fn _mm_move_epi64(a: __m128i) -> __m128i { } } -/// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers +/// Converts packed signed 16-bit integers from `a` and `b` to packed 8-bit integers /// using signed saturation. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi16) @@ -1492,11 +1492,29 @@ pub const fn _mm_move_epi64(a: __m128i) -> __m128i { #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(packsswb))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(packsswb(a.as_i16x8(), b.as_i16x8())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i { + unsafe { + let max = simd_splat(i8::MAX as i16); + let min = simd_splat(i8::MIN as i16); + + let clamped_a = simd_imax(simd_imin(a.as_i16x8(), max), min) + .as_m128i() + .as_i8x16(); + let clamped_b = simd_imax(simd_imin(b.as_i16x8(), max), min) + .as_m128i() + .as_i8x16(); + + // Shuffle the low i8 of each i16 from two concatenated vectors into + // the low bits of the result register. + const IDXS: [u32; 16] = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]; + let result: i8x16 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m128i() + } } -/// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers +/// Converts packed signed 32-bit integers from `a` and `b` to packed 16-bit integers /// using signed saturation. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi32) @@ -1504,11 +1522,25 @@ pub fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(packssdw))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(packssdw(a.as_i32x4(), b.as_i32x4())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i { + unsafe { + let max = simd_splat(i16::MAX as i32); + let min = simd_splat(i16::MIN as i32); + + let clamped_a = simd_imax(simd_imin(a.as_i32x4(), max), min); + let clamped_b = simd_imax(simd_imin(b.as_i32x4(), max), min); + + let clamped_a: i16x4 = simd_cast(clamped_a); + let clamped_b: i16x4 = simd_cast(clamped_b); + + let a: i64 = transmute(clamped_a); + let b: i64 = transmute(clamped_b); + i64x2::new(a, b).as_m128i() + } } -/// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers +/// Converts packed signed 16-bit integers from `a` and `b` to packed 8-bit integers /// using unsigned saturation. /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi16) @@ -1516,8 +1548,28 @@ pub fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(packuswb))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm_packus_epi16(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(packuswb(a.as_i16x8(), b.as_i16x8())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_packus_epi16(a: __m128i, b: __m128i) -> __m128i { + unsafe { + let max = simd_splat(u8::MAX as i16); + let min = simd_splat(u8::MIN as i16); + + let clamped_a = simd_imax(simd_imin(a.as_i16x8(), max), min) + .as_m128i() + .as_i8x16(); + let clamped_b = simd_imax(simd_imin(b.as_i16x8(), max), min) + .as_m128i() + .as_i8x16(); + + // Shuffle the low bytes of each i16 from two concatenated vectors into + // the low bits of the result register. + // Without `simd_shuffle`, this intrinsic will cause the AVX-512BW + // `_mm_mask_packus_epi16` and `_mm_maskz_packus_epi16` tests to fail. + const IDXS: [u32; 16] = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]; + let result: i8x16 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m128i() + } } /// Returns the `imm8` element of `a`. @@ -3217,12 +3269,6 @@ unsafe extern "C" { fn cvtps2dq(a: __m128) -> i32x4; #[link_name = "llvm.x86.sse2.maskmov.dqu"] fn maskmovdqu(a: i8x16, mask: i8x16, mem_addr: *mut i8); - #[link_name = "llvm.x86.sse2.packsswb.128"] - fn packsswb(a: i16x8, b: i16x8) -> i8x16; - #[link_name = "llvm.x86.sse2.packssdw.128"] - fn packssdw(a: i32x4, b: i32x4) -> i16x8; - #[link_name = "llvm.x86.sse2.packuswb.128"] - fn packuswb(a: i16x8, b: i16x8) -> u8x16; #[link_name = "llvm.x86.sse2.max.sd"] fn maxsd(a: __m128d, b: __m128d) -> __m128d; #[link_name = "llvm.x86.sse2.max.pd"] @@ -4286,7 +4332,7 @@ mod tests { } #[simd_test(enable = "sse2")] - fn test_mm_packs_epi16() { + const fn test_mm_packs_epi16() { let a = _mm_setr_epi16(0x80, -0x81, 0, 0, 0, 0, 0, 0); let b = _mm_setr_epi16(0, 0, 0, 0, 0, 0, -0x81, 0x80); let r = _mm_packs_epi16(a, b); @@ -4300,7 +4346,7 @@ mod tests { } #[simd_test(enable = "sse2")] - fn test_mm_packs_epi32() { + const fn test_mm_packs_epi32() { let a = _mm_setr_epi32(0x8000, -0x8001, 0, 0); let b = _mm_setr_epi32(0, 0, -0x8001, 0x8000); let r = _mm_packs_epi32(a, b); @@ -4311,7 +4357,7 @@ mod tests { } #[simd_test(enable = "sse2")] - fn test_mm_packus_epi16() { + const fn test_mm_packus_epi16() { let a = _mm_setr_epi16(0x100, -1, 0, 0, 0, 0, 0, 0); let b = _mm_setr_epi16(0, 0, 0, 0, 0, 0, -1, 0x100); let r = _mm_packus_epi16(a, b); diff --git a/stdarch/crates/core_arch/src/x86/sse41.rs b/stdarch/crates/core_arch/src/x86/sse41.rs index 7ad4306f36f21..4ebf7d3bd39a8 100644 --- a/stdarch/crates/core_arch/src/x86/sse41.rs +++ b/stdarch/crates/core_arch/src/x86/sse41.rs @@ -418,7 +418,7 @@ pub const fn _mm_min_epu32(a: __m128i, b: __m128i) -> __m128i { unsafe { simd_imin(a.as_u32x4(), b.as_u32x4()).as_m128i() } } -/// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers +/// Converts packed signed 32-bit integers from `a` and `b` to packed 16-bit integers /// using unsigned saturation /// /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi32) @@ -426,8 +426,26 @@ pub const fn _mm_min_epu32(a: __m128i, b: __m128i) -> __m128i { #[target_feature(enable = "sse4.1")] #[cfg_attr(test, assert_instr(packusdw))] #[stable(feature = "simd_x86", since = "1.27.0")] -pub fn _mm_packus_epi32(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(packusdw(a.as_i32x4(), b.as_i32x4())) } +#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] +pub const fn _mm_packus_epi32(a: __m128i, b: __m128i) -> __m128i { + unsafe { + let max = simd_splat(u16::MAX as i32); + let min = simd_splat(u16::MIN as i32); + + let clamped_a = simd_imax(simd_imin(a.as_i32x4(), max), min) + .as_m128i() + .as_i16x8(); + let clamped_b = simd_imax(simd_imin(b.as_i32x4(), max), min) + .as_m128i() + .as_i16x8(); + + // Shuffle the low u16 of each i32 from two concatenated vectors into + // the low bits of the result register. + const IDXS: [u32; 8] = [0, 2, 4, 6, 8, 10, 12, 14]; + let result: i16x8 = simd_shuffle!(clamped_a, clamped_b, IDXS); + + result.as_m128i() + } } /// Compares packed 64-bit integers in `a` and `b` for equality @@ -1166,8 +1184,6 @@ pub unsafe fn _mm_stream_load_si128(mem_addr: *const __m128i) -> __m128i { unsafe extern "C" { #[link_name = "llvm.x86.sse41.insertps"] fn insertps(a: __m128, b: __m128, imm8: u8) -> __m128; - #[link_name = "llvm.x86.sse41.packusdw"] - fn packusdw(a: i32x4, b: i32x4) -> u16x8; #[link_name = "llvm.x86.sse41.dppd"] fn dppd(a: __m128d, b: __m128d, imm8: u8) -> __m128d; #[link_name = "llvm.x86.sse41.dpps"] @@ -1455,7 +1471,7 @@ mod tests { } #[simd_test(enable = "sse4.1")] - fn test_mm_packus_epi32() { + const fn test_mm_packus_epi32() { let a = _mm_setr_epi32(1, 2, 3, 4); let b = _mm_setr_epi32(-1, -2, -3, -4); let r = _mm_packus_epi32(a, b); diff --git a/stdarch/crates/core_arch/src/x86/ssse3.rs b/stdarch/crates/core_arch/src/x86/ssse3.rs index 4426a3274c380..1d7a97944a37b 100644 --- a/stdarch/crates/core_arch/src/x86/ssse3.rs +++ b/stdarch/crates/core_arch/src/x86/ssse3.rs @@ -188,7 +188,13 @@ pub const fn _mm_hadd_epi16(a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(phaddsw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm_hadds_epi16(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(phaddsw128(a.as_i16x8(), b.as_i16x8())) } + let a = a.as_i16x8(); + let b = b.as_i16x8(); + unsafe { + let even: i16x8 = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let odd: i16x8 = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_saturating_add(even, odd).as_m128i() + } } /// Horizontally adds the adjacent pairs of values contained in 2 packed @@ -240,7 +246,13 @@ pub const fn _mm_hsub_epi16(a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(phsubsw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm_hsubs_epi16(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(phsubsw128(a.as_i16x8(), b.as_i16x8())) } + let a = a.as_i16x8(); + let b = b.as_i16x8(); + unsafe { + let even: i16x8 = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let odd: i16x8 = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_saturating_sub(even, odd).as_m128i() + } } /// Horizontally subtract the adjacent pairs of values contained in 2 @@ -337,12 +349,6 @@ unsafe extern "C" { #[link_name = "llvm.x86.ssse3.pshuf.b.128"] fn pshufb128(a: u8x16, b: u8x16) -> u8x16; - #[link_name = "llvm.x86.ssse3.phadd.sw.128"] - fn phaddsw128(a: i16x8, b: i16x8) -> i16x8; - - #[link_name = "llvm.x86.ssse3.phsub.sw.128"] - fn phsubsw128(a: i16x8, b: i16x8) -> i16x8; - #[link_name = "llvm.x86.ssse3.pmadd.ub.sw.128"] fn pmaddubsw128(a: u8x16, b: i8x16) -> i16x8; diff --git a/stdarch/crates/core_arch/src/x86_64/amx.rs b/stdarch/crates/core_arch/src/x86_64/amx.rs index 4e20e014cf20a..03bbe3e449258 100644 --- a/stdarch/crates/core_arch/src/x86_64/amx.rs +++ b/stdarch/crates/core_arch/src/x86_64/amx.rs @@ -398,6 +398,22 @@ pub unsafe fn _tile_cvtrowd2ps(row: u32) -> __m512 { tcvtrowd2ps(TILE as i8, row).as_m512() } +/// Moves a row from a tile register to a zmm register, converting the packed 32-bit signed integer +/// elements to packed single-precision (32-bit) floating-point elements. +#[inline] +#[rustc_legacy_const_generics(0, 1)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, any(target_os = "linux", target_env = "msvc")), + assert_instr(tcvtrowd2ps, TILE = 0, ROW = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowd2psi() -> __m512 { + static_assert_uimm_bits!(TILE, 3); + static_assert_uimm_bits!(ROW, 6); + tcvtrowd2psi(TILE as i8, ROW as u32).as_m512() +} + /// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) /// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting /// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector. @@ -414,6 +430,23 @@ pub unsafe fn _tile_cvtrowps2phh(row: u32) -> __m512h { tcvtrowps2phh(TILE as i8, row).as_m512h() } +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the high 16-bits within each 32-bit element of the returned vector. +#[inline] +#[rustc_legacy_const_generics(0, 1)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, any(target_os = "linux", target_env = "msvc")), + assert_instr(tcvtrowps2phh, TILE = 0, ROW = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowps2phhi() -> __m512h { + static_assert_uimm_bits!(TILE, 3); + static_assert_uimm_bits!(ROW, 6); + tcvtrowps2phhi(TILE as i8, ROW as u32).as_m512h() +} + /// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) /// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting /// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector. @@ -430,6 +463,23 @@ pub unsafe fn _tile_cvtrowps2phl(row: u32) -> __m512h { tcvtrowps2phl(TILE as i8, row).as_m512h() } +/// Moves a row from a tile register to a zmm register, converting the packed single-precision (32-bit) +/// floating-point elements to packed half-precision (16-bit) floating-point elements. The resulting +/// 16-bit elements are placed in the low 16-bits within each 32-bit element of the returned vector. +#[inline] +#[rustc_legacy_const_generics(0, 1)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, any(target_os = "linux", target_env = "msvc")), + assert_instr(tcvtrowps2phl, TILE = 0, ROW = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_cvtrowps2phli() -> __m512h { + static_assert_uimm_bits!(TILE, 3); + static_assert_uimm_bits!(ROW, 6); + tcvtrowps2phli(TILE as i8, ROW as u32).as_m512h() +} + /// Moves one row of tile data into a zmm vector register #[inline] #[rustc_legacy_const_generics(0)] @@ -444,6 +494,21 @@ pub unsafe fn _tile_movrow(row: u32) -> __m512i { tilemovrow(TILE as i8, row).as_m512i() } +/// Moves one row of tile data into a zmm vector register +#[inline] +#[rustc_legacy_const_generics(0, 1)] +#[target_feature(enable = "amx-avx512,avx10.2")] +#[cfg_attr( + all(test, any(target_os = "linux", target_env = "msvc")), + assert_instr(tilemovrow, TILE = 0, ROW = 0) +)] +#[unstable(feature = "x86_amx_intrinsics", issue = "126622")] +pub unsafe fn _tile_movrowi() -> __m512i { + static_assert_uimm_bits!(TILE, 3); + static_assert_uimm_bits!(ROW, 6); + tilemovrowi(TILE as i8, ROW as u32).as_m512i() +} + #[allow(improper_ctypes)] unsafe extern "C" { #[link_name = "llvm.x86.ldtilecfg"] @@ -492,12 +557,20 @@ unsafe extern "C" { fn tmmultf32ps(dst: i8, a: i8, b: i8); #[link_name = "llvm.x86.tcvtrowd2ps"] fn tcvtrowd2ps(tile: i8, row: u32) -> f32x16; + #[link_name = "llvm.x86.tcvtrowd2psi"] + fn tcvtrowd2psi(tile: i8, row: u32) -> f32x16; #[link_name = "llvm.x86.tcvtrowps2phh"] fn tcvtrowps2phh(tile: i8, row: u32) -> f16x32; + #[link_name = "llvm.x86.tcvtrowps2phhi"] + fn tcvtrowps2phhi(tile: i8, row: u32) -> f16x32; #[link_name = "llvm.x86.tcvtrowps2phl"] fn tcvtrowps2phl(tile: i8, row: u32) -> f16x32; + #[link_name = "llvm.x86.tcvtrowps2phli"] + fn tcvtrowps2phli(tile: i8, row: u32) -> f16x32; #[link_name = "llvm.x86.tilemovrow"] fn tilemovrow(tile: i8, row: u32) -> i32x16; + #[link_name = "llvm.x86.tilemovrowi"] + fn tilemovrowi(tile: i8, row: u32) -> i32x16; } #[cfg(test)] @@ -1032,6 +1105,50 @@ mod tests { } } + macro_rules! wrap_imm4 { + ($name:ident :: <$TILE:literal>, $row:expr) => { + match $row { + 0 => $name::<$TILE, 0>(), + 1 => $name::<$TILE, 1>(), + 2 => $name::<$TILE, 2>(), + 3 => $name::<$TILE, 3>(), + 4 => $name::<$TILE, 4>(), + 5 => $name::<$TILE, 5>(), + 6 => $name::<$TILE, 6>(), + 7 => $name::<$TILE, 7>(), + 8 => $name::<$TILE, 8>(), + 9 => $name::<$TILE, 9>(), + 10 => $name::<$TILE, 10>(), + 11 => $name::<$TILE, 11>(), + 12 => $name::<$TILE, 12>(), + 13 => $name::<$TILE, 13>(), + 14 => $name::<$TILE, 14>(), + 15 => $name::<$TILE, 15>(), + _ => panic!("row index out of range"), + } + }; + } + + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_movrowi() { + unsafe { + _init_amx(); + let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + + for i in 0..16 { + let row = wrap_imm4!(_tile_movrowi::<0>, i); + assert_eq!(*row.as_u8x64().as_array(), [i as _; _]); + } + } + } + #[simd_test(enable = "amx-avx512,avx10.2")] fn test_tile_cvtrowd2ps() { unsafe { @@ -1051,6 +1168,26 @@ mod tests { } } + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowd2psi() { + unsafe { + _init_amx(); + let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + + for i in 0..16 { + let row = wrap_imm4!(_tile_cvtrowd2psi::<0>, i); + assert_eq!(*row.as_f32x16().as_array(), [i as _; _]); + } + } + } + #[simd_test(enable = "amx-avx512,avx10.2")] fn test_tile_cvtrowps2phh() { unsafe { @@ -1073,6 +1210,28 @@ mod tests { } } + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2phhi() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = wrap_imm4!(_tile_cvtrowps2phhi::<0>, i); + assert_eq!( + *row.as_f16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ }) + ); + } + } + } + #[simd_test(enable = "amx-avx512,avx10.2")] fn test_tile_cvtrowps2phl() { unsafe { @@ -1095,6 +1254,28 @@ mod tests { } } + #[simd_test(enable = "amx-avx512,avx10.2")] + fn test_tile_cvtrowps2phli() { + unsafe { + _init_amx(); + let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]); + + let mut config = __tilecfg::default(); + config.palette = 1; + config.colsb[0] = 64; + config.rows[0] = 16; + _tile_loadconfig(config.as_ptr()); + _tile_loadd::<0>(array.as_ptr().cast(), 64); + for i in 0..16 { + let row = wrap_imm4!(_tile_cvtrowps2phli::<0>, i); + assert_eq!( + *row.as_f16x32().as_array(), + array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 }) + ); + } + } + } + #[simd_test(enable = "amx-tf32")] fn test_tile_mmultf32ps() { unsafe { diff --git a/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs b/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs index 87e3651ba7441..2a511328bb382 100644 --- a/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs +++ b/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs @@ -10,7 +10,7 @@ use stdarch_test::assert_instr; #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsi2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvti64_sh(a: __m128h, b: i64) -> __m128h { unsafe { vcvtsi642sh(a, b, _MM_FROUND_CUR_DIRECTION) } } @@ -32,7 +32,7 @@ pub fn _mm_cvti64_sh(a: __m128h, b: i64) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsi2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundi64_sh(a: __m128h, b: i64) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -48,7 +48,7 @@ pub fn _mm_cvt_roundi64_sh(a: __m128h, b: i64) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtusi2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtu64_sh(a: __m128h, b: u64) -> __m128h { unsafe { vcvtusi642sh(a, b, _MM_FROUND_CUR_DIRECTION) } } @@ -70,7 +70,7 @@ pub fn _mm_cvtu64_sh(a: __m128h, b: u64) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtusi2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundu64_sh(a: __m128h, b: u64) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -85,7 +85,7 @@ pub fn _mm_cvt_roundu64_sh(a: __m128h, b: u64) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2si))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_i64(a: __m128h) -> i64 { unsafe { vcvtsh2si64(a, _MM_FROUND_CUR_DIRECTION) } } @@ -106,7 +106,7 @@ pub fn _mm_cvtsh_i64(a: __m128h) -> i64 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_i64(a: __m128h) -> i64 { unsafe { static_assert_rounding!(ROUNDING); @@ -121,7 +121,7 @@ pub fn _mm_cvt_roundsh_i64(a: __m128h) -> i64 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2usi))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_u64(a: __m128h) -> u64 { unsafe { vcvtsh2usi64(a, _MM_FROUND_CUR_DIRECTION) } } @@ -142,7 +142,7 @@ pub fn _mm_cvtsh_u64(a: __m128h) -> u64 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2usi, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_u64(a: __m128h) -> u64 { unsafe { static_assert_rounding!(ROUNDING); @@ -157,7 +157,7 @@ pub fn _mm_cvt_roundsh_u64(a: __m128h) -> u64 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2si))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttsh_i64(a: __m128h) -> i64 { unsafe { vcvttsh2si64(a, _MM_FROUND_CUR_DIRECTION) } } @@ -172,7 +172,7 @@ pub fn _mm_cvttsh_i64(a: __m128h) -> i64 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2si, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtt_roundsh_i64(a: __m128h) -> i64 { unsafe { static_assert_sae!(SAE); @@ -187,7 +187,7 @@ pub fn _mm_cvtt_roundsh_i64(a: __m128h) -> i64 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2usi))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttsh_u64(a: __m128h) -> u64 { unsafe { vcvttsh2usi64(a, _MM_FROUND_CUR_DIRECTION) } } @@ -202,7 +202,7 @@ pub fn _mm_cvttsh_u64(a: __m128h) -> u64 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtt_roundsh_u64(a: __m128h) -> u64 { unsafe { static_assert_sae!(SAE); diff --git a/stdarch/crates/core_arch/src/x86_64/mod.rs b/stdarch/crates/core_arch/src/x86_64/mod.rs index c6dc7a85e7852..46384176e005e 100644 --- a/stdarch/crates/core_arch/src/x86_64/mod.rs +++ b/stdarch/crates/core_arch/src/x86_64/mod.rs @@ -75,9 +75,13 @@ mod bt; pub use self::bt::*; mod avx512fp16; -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub use self::avx512fp16::*; mod amx; #[unstable(feature = "x86_amx_intrinsics", issue = "126622")] pub use self::amx::*; + +mod movrs; +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub use self::movrs::*; diff --git a/stdarch/crates/core_arch/src/x86_64/movrs.rs b/stdarch/crates/core_arch/src/x86_64/movrs.rs new file mode 100644 index 0000000000000..fc669bbb1ca59 --- /dev/null +++ b/stdarch/crates/core_arch/src/x86_64/movrs.rs @@ -0,0 +1,94 @@ +//! Read-shared Move instructions + +#[cfg(test)] +use stdarch_test::assert_instr; + +unsafe extern "unadjusted" { + #[link_name = "llvm.x86.movrsqi"] + fn movrsqi(src: *const i8) -> i8; + #[link_name = "llvm.x86.movrshi"] + fn movrshi(src: *const i16) -> i16; + #[link_name = "llvm.x86.movrssi"] + fn movrssi(src: *const i32) -> i32; + #[link_name = "llvm.x86.movrsdi"] + fn movrsdi(src: *const i64) -> i64; +} + +/// Moves a byte from the source to the destination, with an indication that the source memory +/// location is likely to become read-shared by multiple processors, i.e., read in the future by at +/// least one other processor before it is written, assuming it is ever written in the future. +#[inline] +#[target_feature(enable = "movrs")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(movrs))] +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub unsafe fn _movrs_i8(src: *const i8) -> i8 { + movrsqi(src) +} + +/// Moves a 16-bit word from the source to the destination, with an indication that the source memory +/// location is likely to become read-shared by multiple processors, i.e., read in the future by at +/// least one other processor before it is written, assuming it is ever written in the future. +#[inline] +#[target_feature(enable = "movrs")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(movrs))] +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub unsafe fn _movrs_i16(src: *const i16) -> i16 { + movrshi(src) +} + +/// Moves a 32-bit doubleword from the source to the destination, with an indication that the source +/// memory location is likely to become read-shared by multiple processors, i.e., read in the future +/// by at least one other processor before it is written, assuming it is ever written in the future. +#[inline] +#[target_feature(enable = "movrs")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(movrs))] +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub unsafe fn _movrs_i32(src: *const i32) -> i32 { + movrssi(src) +} + +/// Moves a 64-bit quadword from the source to the destination, with an indication that the source +/// memory location is likely to become read-shared by multiple processors, i.e., read in the future +/// by at least one other processor before it is written, assuming it is ever written in the future. +#[inline] +#[target_feature(enable = "movrs")] +#[cfg_attr(all(test, not(target_vendor = "apple")), assert_instr(movrs))] +#[unstable(feature = "movrs_target_feature", issue = "137976")] +pub unsafe fn _movrs_i64(src: *const i64) -> i64 { + movrsdi(src) +} + +#[cfg(test)] +mod tests { + use stdarch_test::simd_test; + + use super::*; + + #[simd_test(enable = "movrs")] + fn test_movrs_i8() { + let x: i8 = 42; + let y = unsafe { _movrs_i8(&x) }; + assert_eq!(x, y); + } + + #[simd_test(enable = "movrs")] + fn test_movrs_i16() { + let x: i16 = 42; + let y = unsafe { _movrs_i16(&x) }; + assert_eq!(x, y); + } + + #[simd_test(enable = "movrs")] + fn test_movrs_i32() { + let x: i32 = 42; + let y = unsafe { _movrs_i32(&x) }; + assert_eq!(x, y); + } + + #[simd_test(enable = "movrs")] + fn test_movrs_i64() { + let x: i64 = 42; + let y = unsafe { _movrs_i64(&x) }; + assert_eq!(x, y); + } +} diff --git a/stdarch/crates/intrinsic-test/src/common/compare.rs b/stdarch/crates/intrinsic-test/src/common/compare.rs index 5214349171591..c22d7fd4ec0aa 100644 --- a/stdarch/crates/intrinsic-test/src/common/compare.rs +++ b/stdarch/crates/intrinsic-test/src/common/compare.rs @@ -109,13 +109,26 @@ pub fn compare_outputs( } }) .inspect(|(intrinsic, diffs)| { - println!("Difference for intrinsic: {intrinsic}"); + use std::io::Write; + + let stdout = std::io::stdout(); + let mut out = stdout.lock(); + + writeln!(out, "Difference for intrinsic: {intrinsic}").unwrap(); diffs.into_iter().for_each(|diff| match diff { - diff::Result::Left(c) => println!("C: {c}"), - diff::Result::Right(rust) => println!("Rust: {rust}"), + diff::Result::Left(c) => { + writeln!(out, "C: {c}").unwrap(); + } + diff::Result::Right(rust) => { + writeln!(out, "Rust: {rust}").unwrap(); + } _ => (), }); - println!("****************************************************************"); + writeln!( + out, + "****************************************************************" + ) + .unwrap(); }) .count(); diff --git a/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index a9bc377924dd0..e88860717b6df 100644 --- a/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -13,9 +13,9 @@ auto_llvm_sign_conversion: false neon-stable: &neon-stable FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] -# #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +# #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] neon-stable-fp16: &neon-stable-fp16 - FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']] + FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "1.94.0"']] # #[cfg(not(target_arch = "arm64ec"))] target-not-arm64ec: &target-not-arm64ec @@ -64,12 +64,16 @@ neon-unstable-feat-lut: &neon-unstable-feat-lut FnCall: [unstable, ['feature = "stdarch_neon_feat_lut"', 'issue = "138050"']] aarch64-stable-jscvt: &aarch64-stable-jscvt - FnCall: [stable, ['feature = "stdarch_aarch64_jscvt"', 'since = "CURRENT_RUSTC_VERSION"']] + FnCall: [stable, ['feature = "stdarch_aarch64_jscvt"', 'since = "1.95.0"']] # #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] neon-unstable-feat-lrcpc3: &neon-unstable-feat-lrcpc3 FnCall: [unstable, ['feature = "stdarch_neon_feat_lrcpc3"', 'issue = "none"']] +# #[cfg(target_has_atomic = "64")] +cfg-target-has-atomic-64: &cfg-target-has-atomic-64 + FnCall: [cfg, ['target_has_atomic = "64"']] + # #[unstable(feature = "stdarch_neon_fp8", issue = "none")] neon-unstable-fp8: &neon-unstable-fp8 FnCall: [unstable, ['feature = "stdarch_neon_fp8"', 'issue = "none"']] @@ -3475,10 +3479,10 @@ intrinsics: - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" - arguments: ["a: {type[0]}"] + arguments: ["ptr: {type[0]}"] return_type: "{neon_type[1]}" attr: [*neon-stable] - assert_instr: [ld1] + assert_instr: [ld] safety: unsafe: [neon] types: @@ -3489,11 +3493,12 @@ intrinsics: - ["*const f64", float64x1x4_t] - ["*const f64", float64x2x4_t] compose: - - LLVMLink: - name: "vld1{neon_type[1].no}" - links: - - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: aarch64,arm64ec + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - ptr + - cast + - [] - name: "vld2{neon_type[1].lane_nox}" doc: Load multiple 2-element structures to two registers @@ -3694,16 +3699,12 @@ intrinsics: types: - ["*const f64", float64x1x2_t, f64, float64x1_t] compose: - - LLVMLink: - name: "vld2.{neon_type[1]}" - arguments: - - "ptr: *const {neon_type[3]}" - links: - - link: "llvm.aarch64.neon.ld2.v{neon_type[1].lane}{type[2]}.p0" - arch: aarch64,arm64ec - FnCall: - - "_vld2{neon_type[1].nox}" - - - "a as _" + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld2{neon_type[1].nox}" doc: Load multiple 2-element structures to two registers @@ -3711,6 +3712,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: [*neon-stable] assert_instr: [ld2] + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4052,20 +4054,19 @@ intrinsics: types: - ['*const f64', float64x1x3_t, '*const float64x1_t', f64] compose: - - LLVMLink: - name: 'vld3{neon_type[1].nox}' - arguments: - - 'ptr: {type[2]}' - links: - - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld3{neon_type[1].nox}" doc: Load multiple 3-element structures to three registers arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: [*neon-stable] + big_endian_inverse: false safety: unsafe: [neon] assert_instr: [ld3] @@ -4197,14 +4198,12 @@ intrinsics: types: - ['*const f64', float64x1x4_t, f64, '*const float64x1_t'] compose: - - LLVMLink: - name: 'vld4{neon_type[1].nox}' - arguments: - - 'ptr: {type[3]}' - links: - - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld4{neon_type[1].nox}" doc: Load multiple 4-element structures to four registers @@ -4212,6 +4211,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: [*neon-stable] assert_instr: [ld4] + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4319,6 +4319,7 @@ intrinsics: - *neon-stable static_defs: - "const LANE: i32" + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4368,6 +4369,7 @@ intrinsics: - *neon-stable static_defs: - "const LANE: i32" + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4418,6 +4420,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-unstable-feat-lrcpc3 + - *cfg-target-has-atomic-64 types: - ['*const i64', int64x1_t, 'static_assert!', 'LANE == 0'] - ['*const i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1'] @@ -4448,6 +4451,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] - *neon-unstable-feat-lrcpc3 + - *cfg-target-has-atomic-64 types: - ['*const u64', uint64x1_t,'static_assert!', 'LANE == 0',''] #- ['*const f64', float64x1_t,'static_assert!', 'LANE == 0',''] # Fails due to bad IR gen from rust @@ -4474,6 +4478,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-unstable-feat-lrcpc3 + - *cfg-target-has-atomic-64 types: - ['*mut i64', int64x1_t,'static_assert!', 'LANE == 0'] - ['*mut i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1'] @@ -4502,6 +4507,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-unstable-feat-lrcpc3 + - *cfg-target-has-atomic-64 types: - ['*mut u64', uint64x1_t, 'static_assert!', 'LANE == 0',''] - ['*mut f64', float64x1_t,'static_assert!', 'LANE == 0',''] @@ -4561,20 +4567,11 @@ intrinsics: unsafe: [neon] attr: - *neon-stable - assert_instr: [st1] + assert_instr: [stp] types: - - ['f64', float64x1x2_t, float64x1_t] + - ['f64', float64x1x2_t] compose: - - LLVMLink: - name: 'st2.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst2{neon_type[1].nox}" doc: "Store multiple 2-element structures from two registers" @@ -4585,19 +4582,10 @@ intrinsics: - *neon-stable assert_instr: [st2] types: - - [i64, int64x2x2_t, int64x2_t] - - [f64, float64x2x2_t, float64x2_t] + - [i64, int64x2x2_t, "2"] + - [f64, float64x2x2_t, "2"] compose: - - LLVMLink: - name: 'st2.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']] + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "2", a, b], [], true] - name: "vst2{neon_type[1].lane_nox}" doc: "Store multiple 2-element structures from two registers" @@ -4775,19 +4763,9 @@ intrinsics: safety: unsafe: [neon] types: - - [f64, float64x1x3_t, float64x1_t] + - [f64, float64x1x3_t] compose: - - LLVMLink: - name: 'st3.{neon_type[1].nox}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst3{neon_type[1].lane_nox}" doc: "Store multiple 3-element structures from three registers" @@ -4854,20 +4832,10 @@ intrinsics: safety: unsafe: [neon] types: - - [i64, int64x2x3_t, int64x2_t] - - [f64, float64x2x3_t, float64x2_t] + - [i64, int64x2x3_t, "2"] + - [f64, float64x2x3_t, "2"] compose: - - LLVMLink: - name: 'st3.{neon_type[1].nox}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "3", a, b], [], true] - name: "vst3{neon_type[1].nox}" doc: "Store multiple 3-element structures from three registers" @@ -4989,20 +4957,9 @@ intrinsics: safety: unsafe: [neon] types: - - [f64, float64x1x4_t, float64x1_t] + - [f64, float64x1x4_t] compose: - - LLVMLink: - name: 'st4.{neon_type[1].nox}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'd: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st4.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst4{neon_type[1].lane_nox}" doc: "Store multiple 4-element structures from four registers" @@ -5069,21 +5026,10 @@ intrinsics: safety: unsafe: [neon] types: - - [i64, int64x2x4_t, int64x2_t] - - [f64, float64x2x4_t, float64x2_t] + - [i64, int64x2x4_t, "2"] + - [f64, float64x2x4_t, "2"] compose: - - LLVMLink: - name: 'st4.{neon_type[1].nox}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'd: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st4.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']] + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "4", a, b], [], true] - name: "vst4{neon_type[1].nox}" doc: "Store multiple 4-element structures from four registers" @@ -5428,7 +5374,7 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - ["q_lane_f64", float64x2_t, float64x1_t, "q_f64", '[LANE as u32, LANE as u32]'] + - ["q_lane_f64", float64x2_t, float64x1_t, "q_f64", '[LANE as u32; 2]'] compose: - FnCall: [static_assert!, ['LANE == 0']] - FnCall: @@ -5497,11 +5443,11 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - ['_lane_f32', float32x2_t, float32x2_t, '1', '_f32', '[LANE as u32, LANE as u32]'] - - ['_laneq_f32', float32x2_t, float32x4_t, '2', '_f32', '[LANE as u32, LANE as u32]'] - - ['q_lane_f32', float32x4_t, float32x2_t, '1', 'q_f32', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - ['q_laneq_f32', float32x4_t, float32x4_t, '2', 'q_f32', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - ['q_laneq_f64', float64x2_t, float64x2_t, '1', 'q_f64', '[LANE as u32, LANE as u32]'] + - ['_lane_f32', float32x2_t, float32x2_t, '1', '_f32', '[LANE as u32; 2]'] + - ['_laneq_f32', float32x2_t, float32x4_t, '2', '_f32', '[LANE as u32; 2]'] + - ['q_lane_f32', float32x4_t, float32x2_t, '1', 'q_f32', '[LANE as u32; 4]'] + - ['q_laneq_f32', float32x4_t, float32x4_t, '2', 'q_f32', '[LANE as u32; 4]'] + - ['q_laneq_f64', float64x2_t, float64x2_t, '1', 'q_f64', '[LANE as u32; 2]'] compose: - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] - FnCall: @@ -5527,10 +5473,10 @@ intrinsics: static_defs: ["const LANE: i32"] safety: safe types: - - ['_lane_f16', float16x4_t, float16x4_t, '2', '_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - ['_laneq_f16', float16x4_t, float16x8_t, '3', '_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - ['q_lane_f16', float16x8_t, float16x4_t, '2', 'q_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - ['q_laneq_f16', float16x8_t, float16x8_t, '3', 'q_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - ['_lane_f16', float16x4_t, float16x4_t, '2', '_f16', '[LANE as u32; 4]'] + - ['_laneq_f16', float16x4_t, float16x8_t, '3', '_f16', '[LANE as u32; 4]'] + - ['q_lane_f16', float16x8_t, float16x4_t, '2', 'q_f16', '[LANE as u32; 8]'] + - ['q_laneq_f16', float16x8_t, float16x8_t, '3', 'q_f16', '[LANE as u32; 8]'] compose: - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] - FnCall: @@ -6679,6 +6625,7 @@ intrinsics: arch: aarch64,arm64ec + - name: "vmaxnm{neon_type.no}" doc: Floating-point Maximum Number (vector) arguments: ["a: {neon_type}", "b: {neon_type}"] @@ -6690,7 +6637,11 @@ intrinsics: - float64x1_t - float64x2_t compose: - - FnCall: [simd_fmax, [a, b]] + - LLVMLink: + name: "fmaxnm.{neon_type}" + links: + - link: "llvm.aarch64.neon.fmaxnm.{neon_type}" + arch: aarch64,arm64ec - name: "vmaxnmh_{type}" @@ -6706,7 +6657,11 @@ intrinsics: types: - f16 compose: - - FnCall: ["f16::max", [a, b]] + - LLVMLink: + name: "vmaxh.{neon_type}" + links: + - link: "llvm.aarch64.neon.fmaxnm.{type}" + arch: aarch64,arm64ec - name: "vminnmh_{type}" @@ -6722,7 +6677,11 @@ intrinsics: types: - f16 compose: - - FnCall: ["f16::min", [a, b]] + - LLVMLink: + name: "vminh.{neon_type}" + links: + - link: "llvm.aarch64.neon.fminnm.{type}" + arch: aarch64,arm64ec - name: "vmaxnmv{neon_type[0].no}" @@ -6736,7 +6695,11 @@ intrinsics: - [float32x2_t, f32] - [float64x2_t, f64] compose: - - FnCall: [simd_reduce_max, [a]] + - LLVMLink: + name: "fmaxnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec - name: "vmaxnmv{neon_type[0].no}" doc: Floating-point maximum number across vector @@ -6748,7 +6711,11 @@ intrinsics: types: - [float32x4_t, f32] compose: - - FnCall: [simd_reduce_max, [a]] + - LLVMLink: + name: "fmaxnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec - name: "vmaxnmv{neon_type[0].no}" @@ -6765,7 +6732,11 @@ intrinsics: - [float16x4_t, f16] - [float16x8_t, f16] compose: - - FnCall: [simd_reduce_max, [a]] + - LLVMLink: + name: "fmaxnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec - name: "vminnmv{neon_type[0].no}" @@ -6782,7 +6753,11 @@ intrinsics: - [float16x4_t, f16] - [float16x8_t, f16] compose: - - FnCall: [simd_reduce_min, [a]] + - LLVMLink: + name: "fminnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec - name: "vmaxv{neon_type[0].no}" @@ -6891,7 +6866,11 @@ intrinsics: - float64x1_t - float64x2_t compose: - - FnCall: [simd_fmin, [a, b]] + - LLVMLink: + name: "fminnm.{neon_type}" + links: + - link: "llvm.aarch64.neon.fminnm.{neon_type}" + arch: aarch64,arm64ec - name: "vminnmv{neon_type[0].no}" doc: "Floating-point minimum number across vector" @@ -6905,7 +6884,11 @@ intrinsics: - [float32x2_t, "f32"] - [float64x2_t, "f64"] compose: - - FnCall: [simd_reduce_min, [a]] + - LLVMLink: + name: "vminnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec - name: "vminnmv{neon_type[0].no}" doc: "Floating-point minimum number across vector" @@ -6918,7 +6901,11 @@ intrinsics: types: - [float32x4_t, "f32"] compose: - - FnCall: [simd_reduce_min, [a]] + - LLVMLink: + name: "vminnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec - name: "vmovl_high{neon_type[0].noq}" doc: Vector move @@ -6956,28 +6943,29 @@ intrinsics: - FnCall: [simd_shuffle!, [a, a, "{type[3]}"]] - FnCall: ["vmovl{neon_type[0].noq}", [a]] - - name: "vpadd{neon_type.no}" - doc: Floating-point add pairwise - arguments: ["a: {neon_type}", "b: {neon_type}"] - return_type: "{type}" + - name: "vpadd{neon_type[0].no}" + doc: "Floating-point add pairwise" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" attr: [*neon-stable] assert_instr: [faddp] safety: safe types: - - float32x4_t - - float64x2_t + - [float32x4_t, "4"] + - [float64x2_t, "2"] compose: - - LLVMLink: - name: "faddp.{neon_type}" - links: - - link: "llvm.aarch64.neon.faddp.{neon_type}" - arch: aarch64,arm64ec - + - Let: + - even + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::even::<{type[1]}>()"]] + - Let: + - odd + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::odd::<{type[1]}>()"]] + - FnCall: [simd_add, [even, odd]] - - name: "vpadd{neon_type.no}" + - name: "vpadd{neon_type[0].no}" doc: Floating-point add pairwise - arguments: ["a: {neon_type}", "b: {neon_type}"] - return_type: "{type}" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" attr: - *neon-fp16 - *neon-stable-fp16 @@ -6985,14 +6973,15 @@ intrinsics: assert_instr: [faddp] safety: safe types: - - float16x8_t + - [float16x8_t, "8"] compose: - - LLVMLink: - name: "faddp.{neon_type}" - links: - - link: "llvm.aarch64.neon.faddp.{neon_type}" - arch: aarch64,arm64ec - + - Let: + - even + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::even::<{type[1]}>()"]] + - Let: + - odd + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::odd::<{type[1]}>()"]] + - FnCall: [simd_add, [even, odd]] - name: "vpmax{neon_type.no}" doc: Floating-point add pairwise @@ -7807,14 +7796,14 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32; 4]'] + - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32; 4]'] + - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]'] + - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]'] + - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32; 2]'] + - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32; 2]'] + - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]'] + - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] - Let: [c, "{type[1]}", {FnCall: [simd_shuffle!, [c, c, "{type[5]}"]]}] @@ -7891,14 +7880,14 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] - - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32; 4]'] + - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32; 4]'] + - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]'] + - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]'] + - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32; 2]'] + - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32; 2]'] + - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]'] + - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] - Let: [c, "{type[1]}", {FnCall: [simd_shuffle!, [c, c, "{type[5]}"]]}] @@ -8958,7 +8947,7 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] @@ -8983,7 +8972,7 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] @@ -9008,7 +8997,7 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] @@ -9037,7 +9026,7 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] @@ -10158,7 +10147,7 @@ intrinsics: attr: - *neon-stable - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sri, 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [bfxil, 'N = 2']]}]] safety: safe types: - i64 @@ -11190,7 +11179,7 @@ intrinsics: - FnCall: - simd_mul - - a - - FnCall: ["simd_shuffle!", [b, b, '[LANE as u32, LANE as u32]']] + - FnCall: ["simd_shuffle!", [b, b, '[LANE as u32; 2]']] - name: "vmuld_lane_f64" doc: "Floating-point multiply" @@ -11247,7 +11236,7 @@ intrinsics: - FnCall: - simd_mul - - a - - FnCall: [simd_shuffle!, [b, b, '[LANE as u32, LANE as u32]']] + - FnCall: [simd_shuffle!, [b, b, '[LANE as u32; 2]']] # vmulq_laneq_f16 @@ -11264,8 +11253,8 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [float16x4_t, float16x8_t, '_lane', "[LANE as u32, LANE as u32, LANE as u32, LANE as u32]"] - - [float16x8_t, float16x8_t, 'q_lane', "[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]"] + - [float16x4_t, float16x8_t, '_lane', "[LANE as u32; 4]"] + - [float16x8_t, float16x8_t, 'q_lane', "[LANE as u32; 8]"] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '3']] - FnCall: @@ -11387,10 +11376,10 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]'] + - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]'] + - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]'] + - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: @@ -11410,10 +11399,10 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32; 8]'] + - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32; 8]'] + - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32; 4]'] + - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: @@ -11712,10 +11701,10 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [int16x8_t, int16x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int16x8_t, int16x8_t, int32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x4_t, int32x2_t, int64x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x4_t, int32x4_t, int64x2_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int16x8_t, int16x4_t, int32x4_t, '2', '[LANE as u32; 8]'] + - [int16x8_t, int16x8_t, int32x4_t, '3', '[LANE as u32; 8]'] + - [int32x4_t, int32x2_t, int64x2_t, '1', '[LANE as u32; 4]'] + - [int32x4_t, int32x4_t, int64x2_t, '2', '[LANE as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: @@ -11734,10 +11723,10 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [uint16x8_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint16x8_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x4_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x4_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint16x8_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32; 8]'] + - [uint16x8_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32; 8]'] + - [uint32x4_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32; 4]'] + - [uint32x4_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] - FnCall: @@ -12025,10 +12014,10 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32; 8]'] + - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32; 8]'] + - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32; 4]'] + - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: [simd_shuffle!, [c, c, '{type[4]}']]}]] @@ -12044,10 +12033,10 @@ intrinsics: static_defs: ['const LANE: i32'] safety: safe types: - - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32; 8]'] + - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32; 8]'] + - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32; 4]'] + - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: [simd_shuffle!, [c, c, '{type[4]}']]}]] @@ -12168,6 +12157,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - [uint8x8_t, uint8x8x4_t, uint8x8_t] @@ -12235,6 +12225,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - [uint8x8x2_t, 'uint8x8_t', 'uint8x8_t'] @@ -12288,7 +12279,7 @@ intrinsics: types: - [uint8x8x3_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t'] - [poly8x8x3_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t'] - big_endian_inverse: true + big_endian_inverse: false compose: - Let: - x @@ -12340,7 +12331,7 @@ intrinsics: types: - [uint8x8x4_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t'] - [poly8x8x4_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t'] - big_endian_inverse: true + big_endian_inverse: false compose: - Let: - x @@ -12449,6 +12440,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - [uint8x8_t, 'uint8x8x2_t', uint8x8_t] @@ -12510,7 +12502,7 @@ intrinsics: types: - [uint8x8_t, 'uint8x8x3_t', 'uint8x16x2', 'u8x8::splat(24)', 'uint8x8'] - [poly8x8_t, 'poly8x8x3_t', 'poly8x16x2', 'u8x8::splat(24)', 'poly8x8'] - big_endian_inverse: true + big_endian_inverse: false compose: - Let: - x @@ -12593,6 +12585,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ['uint8x16x2_t', uint8x8_t, 'vqtbl2', 'uint8x8_t'] @@ -12629,6 +12622,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - [uint8x8_t, 'uint8x16x2_t', uint8x8_t, 'vqtbx2'] @@ -12652,6 +12646,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ['int8x8_t', 'int8x16x3_t', uint8x8_t, 'vqtbl3'] @@ -12666,6 +12661,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ['uint8x8_t', 'uint8x16x3_t', uint8x8_t, 'vqtbl3'] @@ -12703,6 +12699,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - [uint8x8_t, 'uint8x16x3_t', uint8x8_t, 'vqtbx3'] @@ -12727,6 +12724,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ['int8x16x4_t', uint8x8_t, 'vqtbl4', 'int8x8_t'] @@ -12741,6 +12739,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ['uint8x16x4_t', uint8x8_t, 'vqtbl4', 'uint8x8_t'] @@ -12779,6 +12778,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - [uint8x8_t, 'uint8x16x4_t', uint8x8_t, 'vqtbx4'] @@ -12843,6 +12843,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ["vqtbl3", int8x16_t, uint8x8_t, int8x8_t] @@ -12862,6 +12863,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ["vqtbl4", int8x16_t, uint8x8_t, int8x8_t] @@ -13217,26 +13219,6 @@ intrinsics: - link: "llvm.aarch64.neon.usqadd.{neon_type[1]}" arch: aarch64,arm64ec - - name: "vpadd{neon_type.no}" - doc: "Add Pairwise" - arguments: ["a: {neon_type}", "b: {neon_type}"] - return_type: "{neon_type}" - attr: - - *neon-stable - assert_instr: [addp] - safety: safe - types: - - int8x16_t - - int16x8_t - - int32x4_t - - int64x2_t - compose: - - LLVMLink: - name: "vpadd{neon_type.no}" - links: - - link: "llvm.aarch64.neon.addp.{neon_type}" - arch: aarch64,arm64ec - - name: "vpadd{neon_type[0].no}" doc: "Add Pairwise" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] @@ -13246,17 +13228,22 @@ intrinsics: assert_instr: [addp] safety: safe types: - - [uint8x16_t, int8x16_t] - - [uint16x8_t, int16x8_t] - - [uint32x4_t, int32x4_t] - - [uint64x2_t, int64x2_t] + - [int8x16_t, "16"] + - [int16x8_t, "8"] + - [int32x4_t, "4"] + - [int64x2_t, "2"] + - [uint8x16_t, "16"] + - [uint16x8_t, "8"] + - [uint32x4_t, "4"] + - [uint64x2_t, "2"] compose: - - FnCall: - - transmute - - - FnCall: - - 'vpadd{neon_type[1].no}' - - - FnCall: [transmute, [a]] - - FnCall: [transmute, [b]] + - Let: + - even + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::even::<{type[1]}>()"]] + - Let: + - odd + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::odd::<{type[1]}>()"]] + - FnCall: [simd_add, [even, odd]] - name: "vpaddd_s64" doc: "Add pairwise" @@ -13714,26 +13701,17 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [int8x8_t, 'N >= 1 && N <= 8'] - - [int8x16_t, 'N >= 1 && N <= 8'] - - [int16x4_t, 'N >= 1 && N <= 16'] - - [int16x8_t, 'N >= 1 && N <= 16'] - - [int32x2_t, 'N >= 1 && N <= 32'] - - [int32x4_t, 'N >= 1 && N <= 32'] - - [int64x1_t, 'N >= 1 && N <= 64'] - - [int64x2_t, 'N >= 1 && N <= 64'] + - [int8x8_t, u8, '8', 'N >= 1 && N <= 8'] + - [int8x16_t, u8, '16', 'N >= 1 && N <= 8'] + - [int16x4_t, u16, '4', 'N >= 1 && N <= 16'] + - [int16x8_t, u16, '8', 'N >= 1 && N <= 16'] + - [int32x2_t, u32, '2', 'N >= 1 && N <= 32'] + - [int32x4_t, u32, '4', 'N >= 1 && N <= 32'] + - [int64x1_t, u64, '1', 'N >= 1 && N <= 64'] + - [int64x2_t, u64, '2', 'N >= 1 && N <= 64'] compose: - - FnCall: ['static_assert!', ['{type[1]}']] - - LLVMLink: - name: "vsri{neon_type[0].N}" - arguments: - - "a: {neon_type[0]}" - - "b: {neon_type[0]}" - - "n: i32" - links: - - link: "llvm.aarch64.neon.vsri.{neon_type[0]}" - arch: aarch64,arm64ec - - FnCall: ["_vsri{neon_type[0].N}", [a, b, N], [], true] + - FnCall: ['static_assert!', ['{type[3]}']] + - FnCall: ["super::shift_right_and_insert!", ['{type[1]}', '{type[2]}', N, a, b], [], true] - name: "vsri{neon_type[0].N}" doc: "Shift Right and Insert (immediate)" diff --git a/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index 52748a4cc056d..56b2252c9ef0c 100644 --- a/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml +++ b/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -10,9 +10,9 @@ auto_big_endian: true neon-stable: &neon-stable FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] -# #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +# #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] neon-stable-fp16: &neon-stable-fp16 - FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']] + FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "1.94.0"']] # #[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] neon-cfg-arm-unstable: &neon-cfg-arm-unstable @@ -55,9 +55,9 @@ neon-target-aarch64-arm64ec: &neon-target-aarch64-arm64ec neon-not-arm-stable: &neon-not-arm-stable FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] -# #[cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION"))] +# #[cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "1.94.0"))] neon-not-arm-stable-fp16: &neon-not-arm-stable-fp16 - FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']]}]] + FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "1.94.0"']]}]] # #[cfg_attr(all(test, not(target_env = "msvc"))] msvc-disabled: &msvc-disabled @@ -1439,12 +1439,12 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [_lane_s8, int8x8_t, int8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_s8, int8x8_t, int8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_lane_u8, uint8x8_t, uint8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_u8, uint8x8_t, uint8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_lane_p8, poly8x8_t, poly8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_p8, poly8x8_t, poly8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_lane_s8, int8x8_t, int8x8_t, '3', '[N as u32; 8]'] + - [q_lane_s8, int8x8_t, int8x16_t, '3', '[N as u32; 16]'] + - [_lane_u8, uint8x8_t, uint8x8_t, '3', '[N as u32; 8]'] + - [q_lane_u8, uint8x8_t, uint8x16_t, '3', '[N as u32; 16]'] + - [_lane_p8, poly8x8_t, poly8x8_t, '3', '[N as u32; 8]'] + - [q_lane_p8, poly8x8_t, poly8x16_t, '3', '[N as u32; 16]'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] @@ -1463,12 +1463,12 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [q_laneq_s8, int8x16_t, int8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_s8, int8x16_t, int8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [q_laneq_u8, uint8x16_t, uint8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_u8, uint8x16_t, uint8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [q_laneq_p8, poly8x16_t, poly8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_p8, poly8x16_t, poly8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [q_laneq_s8, int8x16_t, int8x16_t, '4', '[N as u32; 16]'] + - [_laneq_s8, int8x16_t, int8x8_t, '4', '[N as u32; 8]'] + - [q_laneq_u8, uint8x16_t, uint8x16_t, '4', '[N as u32; 16]'] + - [_laneq_u8, uint8x16_t, uint8x8_t, '4', '[N as u32; 8]'] + - [q_laneq_p8, poly8x16_t, poly8x16_t, '4', '[N as u32; 16]'] + - [_laneq_p8, poly8x16_t, poly8x8_t, '4', '[N as u32; 8]'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] @@ -1487,12 +1487,12 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [_lane_s16, int16x4_t, int16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_s16, int16x4_t, int16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_u16, uint16x4_t, uint16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_lane_p16, poly16x4_t, poly16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_p16, poly16x4_t, poly16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_lane_s16, int16x4_t, int16x4_t, '2', '[N as u32; 4]'] + - [q_lane_s16, int16x4_t, int16x8_t, '2', '[N as u32; 8]'] + - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[N as u32; 4]'] + - [q_lane_u16, uint16x4_t, uint16x8_t, '2', '[N as u32; 8]'] + - [_lane_p16, poly16x4_t, poly16x4_t, '2', '[N as u32; 4]'] + - [q_lane_p16, poly16x4_t, poly16x8_t, '2', '[N as u32; 8]'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] @@ -1511,12 +1511,12 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_s16, int16x8_t, int16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] - - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_u16, uint16x8_t, uint16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] - - [q_laneq_p16, poly16x8_t, poly16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_p16, poly16x8_t, poly16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] + - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[N as u32; 8]'] + - [_laneq_s16, int16x8_t, int16x4_t, '3', '[N as u32; 4]'] + - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[N as u32; 8]'] + - [_laneq_u16, uint16x8_t, uint16x4_t, '3', '[N as u32; 4]'] + - [q_laneq_p16, poly16x8_t, poly16x8_t, '3', '[N as u32; 8]'] + - [_laneq_p16, poly16x8_t, poly16x4_t, '3', '[N as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] @@ -1538,8 +1538,8 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [q_laneq_f16, float16x8_t, float16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - - [_laneq_f16, float16x8_t, float16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] + - [q_laneq_f16, float16x8_t, float16x8_t, '3', '[N as u32; 8]'] + - [_laneq_f16, float16x8_t, float16x4_t, '3', '[N as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] @@ -1578,8 +1578,8 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [_lane_f16, float16x4_t, float16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - - [q_lane_f16, float16x4_t, float16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_lane_f16, float16x4_t, float16x4_t, '2', '[N as u32; 4]'] + - [q_lane_f16, float16x4_t, float16x8_t, '2', '[N as u32; 8]'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] @@ -2603,8 +2603,8 @@ intrinsics: return_type: "{neon_type[1]}" attr: - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: @@ -2617,13 +2617,12 @@ intrinsics: - ["*const f32", float32x2x4_t] - ["*const f32", float32x4x4_t] compose: - - LLVMLink: - name: "vld1x{neon_type[1].tuple}.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: arm + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2631,8 +2630,8 @@ intrinsics: return_type: "{neon_type[1]}" attr: - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: @@ -2663,13 +2662,12 @@ intrinsics: - ["*const i64", int64x2x3_t] - ["*const i64", int64x2x4_t] compose: - - LLVMLink: - name: "ld1x{neon_type[1].tuple}.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}i{neon_type[1].base}.p0" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}i{neon_type[1].base}.p0" - arch: arm + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2677,10 +2675,11 @@ intrinsics: return_type: "{neon_type[1]}" attr: - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable + big_endian_inverse: false safety: unsafe: [neon] types: @@ -2722,12 +2721,11 @@ intrinsics: - ["*const p16", poly16x8x4_t, int16x8x4_t] compose: - FnCall: - - transmute - - - FnCall: - - "vld1{neon_type[2].no}" - - - FnCall: - - transmute - - - a + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2737,9 +2735,10 @@ intrinsics: - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable + big_endian_inverse: false safety: unsafe: [neon] types: @@ -2750,12 +2749,11 @@ intrinsics: - ["*const p64", poly64x2x4_t, int64x2x4_t] compose: - FnCall: - - transmute - - - FnCall: - - "vld1{neon_type[2].no}" - - - FnCall: - - transmute - - - a + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2764,8 +2762,8 @@ intrinsics: attr: - *neon-aes - *neon-v8 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: @@ -2774,12 +2772,11 @@ intrinsics: - ["*const p64", poly64x1x2_t, int64x1x2_t] compose: - FnCall: - - transmute - - - FnCall: - - "vld1{neon_type[2].no}" - - - FnCall: - - transmute - - - a + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2788,7 +2785,7 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *arm-fp16 - *neon-unstable-f16 - *target-not-arm64ec @@ -2802,13 +2799,12 @@ intrinsics: - ["*const f16", float16x4x4_t] - ["*const f16", float16x8x4_t] compose: - - LLVMLink: - name: "vld1x{neon_type[1].tuple}.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: arm + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{type[2]}_{neon_type[1]}" doc: "Load one single-element structure to one lane of one register" @@ -2980,6 +2976,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable + big_endian_inverse: false safety: unsafe: [neon] types: @@ -3010,6 +3007,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable + big_endian_inverse: false safety: unsafe: [neon] types: @@ -3106,6 +3104,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: - "const LANE: i32" + big_endian_inverse: false safety: unsafe: [neon] types: @@ -3670,19 +3669,11 @@ intrinsics: safety: unsafe: [neon] types: - - ["*const f16", float16x4x3_t, f16] - - ["*const f16", float16x8x3_t, f16] + - ["*const f16", float16x4x3_t, f16, "4"] + - ["*const f16", float16x8x3_t, f16, "8"] compose: - - LLVMLink: - name: "vld3.{neon_type[1]}" - arguments: - - "ptr: {type[0]}" - links: - - link: "llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[2]}.p0" - arch: aarch64,arm64ec - - FnCall: - - "_vld3{neon_type[1].nox}" - - - "a as _" + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "3", a], [], true] + - name: "vld3{neon_type[1].dup_nox}" doc: Load single 3-element structure and replicate to all lanes of two registers @@ -3876,23 +3867,17 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const i8', int8x8x3_t, '*const int8x8_t', i8] - - ['*const i16', int16x4x3_t, '*const int16x4_t', i16] - - ['*const i32', int32x2x3_t, '*const int32x2_t', i32] - - ['*const i8', int8x16x3_t, '*const int8x16_t', i8] - - ['*const i16', int16x8x3_t, '*const int16x8_t', i16] - - ['*const i32', int32x4x3_t, '*const int32x4_t', i32] - - ['*const f32', float32x2x3_t, '*const float32x2_t', f32] - - ['*const f32', float32x4x3_t, '*const float32x4_t', f32] + - ['*const i8', int8x8x3_t, i8, "8"] + - ['*const i16', int16x4x3_t, i16, "4"] + - ['*const i32', int32x2x3_t, i32, "2"] + - ['*const i8', int8x16x3_t, i8, "16"] + - ['*const i16', int16x8x3_t, i16, "8"] + - ['*const i32', int32x4x3_t, i32, "4"] + - ['*const f32', float32x2x3_t, f32, "2"] + - ['*const f32', float32x4x3_t, f32, "4"] compose: - - LLVMLink: - name: 'vld3{neon_type[1].nox}' - arguments: - - 'ptr: {type[2]}' - links: - - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "3", a], [], true] + - name: "vld3{neon_type[1].nox}" doc: Load multiple 3-element structures to three registers @@ -3907,14 +3892,12 @@ intrinsics: types: - ['*const i64', int64x1x3_t, '*const int64x1_t', i64] compose: - - LLVMLink: - name: "vld3{neon_type[1].nox}" - arguments: - - 'ptr: {type[2]}' - links: - - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld3{neon_type[1].nox}" doc: Load multiple 3-element structures to three registers @@ -4110,6 +4093,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable static_defs: ['const LANE: i32'] + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4140,6 +4124,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4372,23 +4357,16 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const i8', int8x8x4_t, i8, '*const int8x8_t'] - - ['*const i32', int32x4x4_t, i32, '*const int32x4_t'] - - ['*const i16', int16x4x4_t, i16, '*const int16x4_t'] - - ['*const i32', int32x2x4_t, i32, '*const int32x2_t'] - - ['*const i8', int8x16x4_t, i8, '*const int8x16_t'] - - ['*const i16', int16x8x4_t, i16, '*const int16x8_t'] - - ['*const f32', float32x2x4_t, f32, '*const float32x2_t'] - - ['*const f32', float32x4x4_t, f32, '*const float32x4_t'] + - ['*const i8', int8x8x4_t, i8, "8"] + - ['*const i32', int32x4x4_t, i32, "4"] + - ['*const i16', int16x4x4_t, i16, "4"] + - ['*const i32', int32x2x4_t, i32, "2"] + - ['*const i8', int8x16x4_t, i8, "16"] + - ['*const i16', int16x8x4_t, i16, "8"] + - ['*const f32', float32x2x4_t, f32, "2"] + - ['*const f32', float32x4x4_t, f32, "4"] compose: - - LLVMLink: - name: 'vld4{neon_type[1].nox}' - arguments: - - 'ptr: {type[3]}' - links: - - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "4", a], [], true] - name: "vld4{neon_type[1].nox}" doc: Load multiple 4-element structures to four registers @@ -4401,14 +4379,12 @@ intrinsics: types: - ['*const i64', int64x1x4_t, i64, '*const int64x1_t'] compose: - - LLVMLink: - name: 'vld4{neon_type[1].nox}' - arguments: - - 'ptr: {type[3]}' - links: - - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld4{neon_type[1].lane_nox}" doc: Load multiple 4-element structures to four registers @@ -4512,6 +4488,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld4]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4633,6 +4610,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable static_defs: ["const LANE: i32"] + big_endian_inverse: false safety: unsafe: [neon] types: @@ -5071,17 +5049,7 @@ intrinsics: types: - [i64, int64x1x2_t, int64x1_t] compose: - - LLVMLink: - name: 'vst2.{neon_type[1]}' - arguments: - - 'ptr: *mut i8' - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'size: i32' - links: - - link: 'llvm.arm.neon.vst2.v{neon_type[1].lane}{type[0]}.p0' - arch: arm - - FnCall: ['_vst2{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', '8']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst2{neon_type[1].nox}" doc: "Store multiple 2-element structures from two registers" @@ -5114,16 +5082,7 @@ intrinsics: types: - [i64, int64x1x2_t, int64x1_t] compose: - - LLVMLink: - name: 'st2.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst2{neon_type[1].nox}" doc: "Store multiple 2-element structures from two registers" @@ -5135,26 +5094,16 @@ intrinsics: safety: unsafe: [neon] types: - - [i8, int8x8x2_t, int8x8_t] - - [i16, int16x4x2_t, int16x4_t] - - [i32, int32x2x2_t, int32x2_t] - - [i8, int8x16x2_t, int8x16_t] - - [i16, int16x8x2_t, int16x8_t] - - [i32, int32x4x2_t, int32x4_t] - - [f32, float32x2x2_t, float32x2_t] - - [f32, float32x4x2_t, float32x4_t] + - [i8, int8x8x2_t, "8"] + - [i16, int16x4x2_t, "4"] + - [i32, int32x2x2_t, "2"] + - [i8, int8x16x2_t, "16"] + - [i16, int16x8x2_t, "8"] + - [i32, int32x4x2_t, "4"] + - [f32, float32x2x2_t, "2"] + - [f32, float32x4x2_t, "4"] compose: - - LLVMLink: - name: 'st2.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']] - + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "2", a, b], [], true] - name: "vst2{neon_type[1].nox}" doc: "Store multiple 2-element structures from two registers" @@ -5448,17 +5397,7 @@ intrinsics: types: - [i64, int64x1x3_t, int64x1_t] compose: - - LLVMLink: - name: 'st3.{neon_type[1].nox}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst3{neon_type[1].nox}" doc: "Store multiple 3-element structures from three registers" @@ -5493,18 +5432,7 @@ intrinsics: types: - [i64, int64x1x3_t, int64x1_t] compose: - - LLVMLink: - name: 'vst3.{neon_type[1]}' - arguments: - - 'ptr: *mut i8' - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'size: i32' - links: - - link: 'llvm.arm.neon.vst3.p0.v{neon_type[1].lane}{type[0]}' - arch: arm - - FnCall: ['_vst3{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', '8']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst3{neon_type[1].nox}" doc: "Store multiple 3-element structures from three registers" @@ -5593,27 +5521,16 @@ intrinsics: safety: unsafe: [neon] types: - - [i8, int8x8x3_t, int8x8_t, '1'] - - [i16, int16x4x3_t, int16x4_t, '2'] - - [i32, int32x2x3_t, int32x2_t, '4'] - - [i8, int8x16x3_t, int8x16_t, '1'] - - [i16, int16x8x3_t, int16x8_t, '2'] - - [i32, int32x4x3_t, int32x4_t, '4'] - - [f32, float32x2x3_t, float32x2_t, '4'] - - [f32, float32x4x3_t, float32x4_t, '4'] + - [i8, int8x8x3_t, '8'] + - [i16, int16x4x3_t, '4'] + - [i32, int32x2x3_t, '2'] + - [i8, int8x16x3_t, '16'] + - [i16, int16x8x3_t, '8'] + - [i32, int32x4x3_t, '4'] + - [f32, float32x2x3_t, '2'] + - [f32, float32x4x3_t, '4'] compose: - - LLVMLink: - name: 'vst3.{neon_type[1]}' - arguments: - - 'ptr: *mut i8' - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'size: i32' - links: - - link: 'llvm.arm.neon.vst3.p0.v{neon_type[1].lane}{type[0]}' - arch: arm - - FnCall: ['_vst3{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', "{type[3]}"]] + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "3", a, b], [], true] - name: "vst3{neon_type[1].nox}" @@ -5875,19 +5792,7 @@ intrinsics: types: - [i64, int64x1x4_t, int64x1_t] compose: - - LLVMLink: - name: 'vst4.{neon_type[1]}' - arguments: - - 'ptr: *mut i8' - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'd: {type[2]}' - - 'size: i32' - links: - - link: 'llvm.arm.neon.vst4.p0.v{neon_type[1].lane}{type[0]}' - arch: arm - - FnCall: ['_vst4{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', '8']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst4{neon_type[1].nox}" doc: "Store multiple 4-element structures from four registers" @@ -5901,18 +5806,7 @@ intrinsics: types: - [i64, int64x1x4_t, int64x1_t] compose: - - LLVMLink: - name: 'vst4.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'd: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st4.{neon_type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']] + - FnCall: [core::ptr::write_unaligned, ['a.cast()', b]] - name: "vst4{neon_type[1].nox}" doc: "Store multiple 4-element structures from four registers" @@ -6136,27 +6030,16 @@ intrinsics: safety: unsafe: [neon] types: - - [i8, int8x8x4_t, int8x8_t] - - [i16, int16x4x4_t, int16x4_t] - - [i32, int32x2x4_t, int32x2_t] - - [i8, int8x16x4_t, int8x16_t] - - [i16, int16x8x4_t, int16x8_t] - - [i32, int32x4x4_t, int32x4_t] - - [f32, float32x2x4_t, float32x2_t] - - [f32, float32x4x4_t, float32x4_t] + - [i8, int8x8x4_t, "8"] + - [i16, int16x4x4_t, "4"] + - [i32, int32x2x4_t, "2"] + - [i8, int8x16x4_t, "16"] + - [i16, int16x8x4_t, "8"] + - [i32, int32x4x4_t, "4"] + - [f32, float32x2x4_t, "2"] + - [f32, float32x4x4_t, "4"] compose: - - LLVMLink: - name: 'vst4.{neon_type[1]}' - arguments: - - 'a: {type[2]}' - - 'b: {type[2]}' - - 'c: {type[2]}' - - 'd: {type[2]}' - - 'ptr: *mut i8' - links: - - link: 'llvm.aarch64.neon.st4.v{neon_type[1].lane}{type[0]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']] + - FnCall: ["crate::core_arch::macros::interleaving_store!", [{ Type: "{type[0]}" }, "{type[2]}", "4", a, b], [], true] - name: "vst4{neon_type[1].nox}" @@ -6511,13 +6394,10 @@ intrinsics: - ["s16", int16x4_t, int32x4_t] - ["s32", int32x2_t, int64x2_t] compose: - - LLVMLink: - name: "smull.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.smull.{neon_type[2]}" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vmulls.{neon_type[2]}" - arch: arm + - FnCall: + - simd_mul + - - FnCall: ['simd_cast', [a]] + - FnCall: ['simd_cast', [b]] - name: "vmull{neon_type[1].no}" doc: "Unsigned multiply long" @@ -6535,13 +6415,10 @@ intrinsics: - ["u16", uint16x4_t, uint32x4_t] - ["u32", uint32x2_t, uint64x2_t] compose: - - LLVMLink: - name: "smull.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.umull.{neon_type[2]}" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vmullu.{neon_type[2]}" - arch: arm + - FnCall: + - simd_mul + - - FnCall: ['simd_cast', [a]] + - FnCall: ['simd_cast', [b]] - name: "vmull{neon_type[1].no}" doc: "Polynomial multiply long" @@ -7447,7 +7324,13 @@ intrinsics: - float32x2_t - float32x4_t compose: - - FnCall: [simd_fmax, [a, b]] + - LLVMLink: + name: "fmaxnm.{neon_type}" + links: + - link: "llvm.arm.neon.vmaxnm.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fmaxnm.{neon_type}" + arch: aarch64,arm64ec - name: "vmaxnm{neon_type.no}" @@ -7467,7 +7350,13 @@ intrinsics: - float16x4_t - float16x8_t compose: - - FnCall: [simd_fmax, [a, b]] + - LLVMLink: + name: "fmaxnm.{neon_type}" + links: + - link: "llvm.arm.neon.vmaxnm.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fmaxnm.{neon_type}" + arch: aarch64,arm64ec - name: "vminnm{neon_type.no}" @@ -7487,7 +7376,13 @@ intrinsics: - float16x4_t - float16x8_t compose: - - FnCall: [simd_fmin, [a, b]] + - LLVMLink: + name: "fminnm.{neon_type}" + links: + - link: "llvm.arm.neon.vminnm.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fminnm.{neon_type}" + arch: aarch64,arm64ec - name: "vmin{neon_type.no}" @@ -7600,7 +7495,13 @@ intrinsics: - float32x2_t - float32x4_t compose: - - FnCall: [simd_fmin, [a, b]] + - LLVMLink: + name: "fminnm.{neon_type}" + links: + - link: "llvm.arm.neon.vminnm.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fminnm.{neon_type}" + arch: aarch64,arm64ec - name: "vpadd{neon_type.no}" doc: Floating-point add pairwise @@ -7703,7 +7604,7 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [int16x4_t, int16x4_t, int32x4_t, '[N as u32, N as u32, N as u32, N as u32]'] + - [int16x4_t, int16x4_t, int32x4_t, '[N as u32; 4]'] compose: - FnCall: [static_assert_uimm_bits!, [N, '2']] - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] @@ -7723,7 +7624,7 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [int32x2_t, int32x2_t, int64x2_t, '[N as u32, N as u32]'] + - [int32x2_t, int32x2_t, int64x2_t, '[N as u32; 2]'] compose: - FnCall: [static_assert_uimm_bits!, [N, '1']] - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] @@ -8348,9 +8249,9 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }'] - - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }'] - - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { uint64x2_t([-N as u64, -N as u64]) }'] + - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { uint16x8_t([-N as u16; 8]) }'] + - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { uint32x4_t([-N as u32; 4]) }'] + - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { uint64x2_t([-N as u64; 2]) }'] compose: - FnCall: [static_assert!, ["{type[2]}"]] - LLVMLink: @@ -10817,9 +10718,9 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [uint16x8_t, uint8x8_t, '8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }'] - - [uint32x4_t, uint16x4_t, '16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }'] - - [uint64x2_t, uint32x2_t, '32', 'const { uint64x2_t([-N as u64, -N as u64]) }'] + - [uint16x8_t, uint8x8_t, '8', 'const { uint16x8_t([-N as u16; 8]) }'] + - [uint32x4_t, uint16x4_t, '16', 'const { uint32x4_t([-N as u32; 4]) }'] + - [uint64x2_t, uint32x2_t, '32', 'const { uint64x2_t([-N as u64; 2]) }'] compose: - FnCall: [static_assert!, ['N >= 1 && N <= {type[2]}']] - LLVMLink: @@ -12437,19 +12338,10 @@ intrinsics: safety: unsafe: [neon] types: - - ["*const f16", float16x4x4_t, f16] - - ["*const f16", float16x8x4_t, f16] + - ["*const f16", float16x4x4_t, f16, "4"] + - ["*const f16", float16x8x4_t, f16, "8"] compose: - - LLVMLink: - name: "vld4.{neon_type[1]}" - arguments: - - "ptr: {type[0]}" - links: - - link: "llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0" - arch: aarch64,arm64ec - - FnCall: - - "_vld4{neon_type[1].nox}" - - - "a as _" + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "4", a], [], true] - name: "vld4{neon_type[1].dup_nox}" doc: Load single 4-element structure and replicate to all lanes of two registers diff --git a/stdarch/crates/stdarch-gen-arm/src/main.rs b/stdarch/crates/stdarch-gen-arm/src/main.rs index 9bf7d0981deb9..e14e2782485b9 100644 --- a/stdarch/crates/stdarch-gen-arm/src/main.rs +++ b/stdarch/crates/stdarch-gen-arm/src/main.rs @@ -139,6 +139,7 @@ fn parse_args() -> Vec<(PathBuf, Option)> { .into_iter() .filter_map(Result::ok) .filter(|f| f.file_type().is_file()) + .filter(|f| f.file_name().to_string_lossy().ends_with(".yml")) .map(|f| (f.into_path(), out_dir.clone())) .collect() } diff --git a/stdarch/crates/stdarch-gen-hexagon/Cargo.toml b/stdarch/crates/stdarch-gen-hexagon/Cargo.toml new file mode 100644 index 0000000000000..397c7816f8d1e --- /dev/null +++ b/stdarch/crates/stdarch-gen-hexagon/Cargo.toml @@ -0,0 +1,9 @@ +[package] +name = "stdarch-gen-hexagon" +version = "0.1.0" +authors = ["The Rust Project Developers"] +license = "MIT OR Apache-2.0" +edition = "2021" + +[dependencies] +regex = "1.10" diff --git a/stdarch/crates/stdarch-gen-hexagon/hvx_hexagon_protos.h b/stdarch/crates/stdarch-gen-hexagon/hvx_hexagon_protos.h new file mode 100644 index 0000000000000..19309a40d6dd1 --- /dev/null +++ b/stdarch/crates/stdarch-gen-hexagon/hvx_hexagon_protos.h @@ -0,0 +1,6003 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// Automatically generated file, do not edit! +//===----------------------------------------------------------------------===// + + +#ifndef _HVX_HEXAGON_PROTOS_H_ +#define _HVX_HEXAGON_PROTOS_H_ 1 + +#ifdef __HVX__ +#if __HVX_LENGTH__ == 128 +#define __BUILTIN_VECTOR_WRAP(a) a ## _128B +#else +#define __BUILTIN_VECTOR_WRAP(a) a +#endif + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rd32=vextract(Vu32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs) + Instruction Type: LD + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=hi(Vss32) + C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=lo(Vss32) + C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vsplat(Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=and(Qs4,Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=and(Qs4,!Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=not(Qs4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=or(Qs4,Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=or(Qs4,!Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vsetq(Rt32) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=xor(Qs4,Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) vmem(Rt32+#s4)=Vs32 + C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) + Instruction Type: CVI_VM_ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) vmem(Rt32+#s4):nt=Vs32 + C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) + Instruction Type: CVI_VM_ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) vmem(Rt32+#s4):nt=Vs32 + C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) + Instruction Type: CVI_VM_ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) vmem(Rt32+#s4)=Vs32 + C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) + Instruction Type: CVI_VM_ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vabsdiff(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vabsdiff(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vabs(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vabs(Vu32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vabs(Vu32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vabs(Vu32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.b+=Vu32.b + C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.b+=Vu32.b + C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.h+=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.h+=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vadd(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vadd(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vadd_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vadd_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wub_vadd_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vadd_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vadd_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vadd_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuh_vadd_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vadd(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vadd_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vadd_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.w+=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_condacc_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.w+=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_condacc_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vadd_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=valign(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=valign(Vu32,Vv32,#u3) + C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_valign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi)(Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vand(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vand_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vand(Qu4,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_QR(HVX_VectorPred Qu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32|=vand(Qu4,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vandor_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vand(Vu32,Rt32) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vand_VR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)(Vu,Rt)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vand(Vu32,Rt32) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vandor_QVR(HVX_VectorPred Qx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Q_vandor_QVR(Qx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Rt)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasl(Vu32.h,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasl_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasl(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasl_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vasl(Vu32.w,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasl_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vasl(Vu32.w,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vaslacc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vaslacc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vasl(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasl_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.h,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vasr(Vu32.w,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasr_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vasr(Vu32.w,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasracc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasracc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VwVwR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vasr(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=Vu32 + C Intrinsic Prototype: HVX_Vector Q6_V_equals_V(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_equals_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=Vuu32 + C Intrinsic Prototype: HVX_VectorPair Q6_W_equals_W(HVX_VectorPair Vuu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_equals_W(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp)(Vuu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vavg_VhVh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vavg_VubVub_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vavg_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vavg_VuhVuh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vavg_VwVw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vcl0(Vu32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcl0_Vuh(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vcl0_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vcl0(Vu32.uw) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vcl0_Vuw(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vcl0_Vuw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=vcombine(Vu32,Vv32) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vcombine_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vcombine_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=#0 + C Intrinsic Prototype: HVX_Vector Q6_V_vzero() + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0)() +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vdeal(Vu32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeal_Vb(HVX_Vector Vu) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vdeal_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vdeale(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeale_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vdeale_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vdeal(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vdeal_Vh(HVX_Vector Vu) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vdeal_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=vdeal(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vdeal_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vdeal_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vdelta(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vdmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpy_VubRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vdmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vdmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpyacc_VhVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vdmpyacc_VhVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vdmpy(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vdmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vdmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vdmpy(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vdmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vdmpy(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vdmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRh_sat(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_WhRh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwWhRh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)(Vx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_VhRh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwVhRh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRuh_sat(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_WhRuh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRuh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwWhRuh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)(Vx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_VhRuh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwVhRuh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhVh_sat(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwVhVh_sat(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsad_WuhRuh(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vdsad_WuhRuh(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsadacc_WuwWuhRuh(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vdsadacc_WuwWuhRuh(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w=vinsert(Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vinsert_VwR(HVX_Vector Vx, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vinsert_VwR(Vx,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr)(Vx,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vlalign(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vlalign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vlalign(Vu32,Vv32,#u3) + C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vlalign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi)(Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vlsr(Vu32.uh,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vlsr_VuhR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vlsr_VuhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vlsr(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vlsr_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vlsr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vlsr(Vu32.uw,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vlsr_VuwR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vlsr_VuwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vlsr(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vlsr_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vlsr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32_VbVbR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbR(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32or_VbVbVbR(Vx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)(Vx,Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16_VbVhR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhR(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16or_WhVbVhR(Vxx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)(Vxx,Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmax(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmax_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vmax_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vmax(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vmax_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vmax_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vmax(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmax_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vmax_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmax(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmax_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vmax_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmin(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmin_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vmin_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vmin(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vmin_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vmin_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vmin(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmin_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vmin_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmin(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmin_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vmin_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpa_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpaacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpa_WubWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWub(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpa_WubWub(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpa(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WhRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpa_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpa(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpaacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubRb(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpyacc_WhVubRb(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpyacc_WhVubVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpy(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpy(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVbVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpyacc_WhVbVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpye(Vu32.w,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Rt32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhRh(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpy_VhRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh_sat(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpyacc_WwVhRh_sat(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpy_VhRh_s1_rnd_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpy_VhRh_s1_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpy_VhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpyacc_WwVhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpy_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpyacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpy_VhVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyieo(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieo_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyieo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyieacc_VwVwVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyie(Vu32.w,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyie_VwVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyie_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVuh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyieacc_VwVwVuh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpyi_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpyiacc_VhVhVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpyi_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpyiacc_VhVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyio(Vu32.w,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyio_VwVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyio_VwVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyi_VwRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyiacc_VwVwRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRh(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyi_VwRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyiacc_VwVwRh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyo_VwVh_s1_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyo_VwVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubRub(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuh_vmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubRub(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuh_vmpyacc_WuhVubRub(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuh_vmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuh_vmpyacc_WuhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhRuh(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vmpy_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhRuh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vmpyacc_WuwVuhRuh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vmpy_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vmpyacc_WuwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vmux(Qt4,Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vmux_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vnavg(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vnavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vnavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vnavg(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vnavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vnavg(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vnavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vnavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vnormamt(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vnormamt_Vh(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vnormamt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vnormamt(Vu32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vnormamt_Vw(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vnormamt_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vnot(Vu32) + C Intrinsic Prototype: HVX_Vector Q6_V_vnot_V(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vnot_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vor(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vor_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vpacke(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacke_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vpacke_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vpacke(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacke_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vpacke_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vpack(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vpack(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vpacko(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacko_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vpacko_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vpacko(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacko_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vpacko_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vpack(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vpack(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vpopcount(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vpopcount_Vh(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vpopcount_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vrdelta(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vrdelta_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vrdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpyacc_VwVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpy_WubRbI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vrmpy_WubRbI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi)(Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpyacc_WwWubRbI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vrmpyacc_WwWubRbI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)(Vxx,Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpyacc_VwVubVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vrmpy(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vrmpy(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpyacc_VwVbVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubRub(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vrmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vrmpyacc_VuwVubRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpy_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vrmpy_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)(Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpyacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vrmpyacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)(Vxx,Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vrmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vrmpyacc_VuwVubVub(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vror(Vu32,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vror_VR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vror_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vround(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vround(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vround(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vround(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsad_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vrsad_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)(Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsadacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vrsadacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)(Vxx,Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vsat(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vsat_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vsat_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vsat(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vsat_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vsat_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vsxt(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsxt_Vb(HVX_Vector Vu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vsxt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsxt(Vu32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsxt_Vh(HVX_Vector Vu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vsxt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vshuffe(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffe_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vshuffe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vshuff(Vu32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuff_Vb(HVX_Vector Vu) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vshuff_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vshuffe(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffe_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vshuffe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vshuff(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuff_Vh(HVX_Vector Vu) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vshuff_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vshuffo(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffo_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vshuffo_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=vshuff(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vshuff_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vshuff_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vshuffoe(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vshuffoe_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vshuffoe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vshuffoe(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vshuffoe_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vshuffoe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vshuffo(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffo_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vshuffo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vsub_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vsub_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.b-=Vu32.b + C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_condnac_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.b-=Vu32.b + C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_condnac_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vsub_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.h-=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_condnac_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.h-=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_condnac_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vsub_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vsub_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsub(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vsub(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vsub_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vsub_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vsub_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wub_vsub_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsub_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vsub_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vsub_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuh_vsub_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsub(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vsub_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vsub_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vsub_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.w-=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_condnac_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.w-=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_condnac_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vsub_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vsub_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=vswap(Qt4,Vu32,Vv32) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vswap_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vswap_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vtmpy(Vuu32.b,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WbRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vtmpy_WbRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.b,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWbRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vtmpyacc_WhWbRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vtmpy(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vtmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vtmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vtmpy(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vtmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vtmpy(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vtmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vunpack(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpack_Vb(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vunpack_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vunpack(Vu32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpack_Vh(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vunpack_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h|=vunpacko(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpackoor_WhVb(HVX_VectorPair Vxx, HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vunpackoor_WhVb(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)(Vxx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w|=vunpacko(Vu32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpackoor_WwVh(HVX_VectorPair Vxx, HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vunpackoor_WwVh(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)(Vxx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vunpack(Vu32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vunpack_Vub(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuh_vunpack_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vunpack(Vu32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vunpack_Vuh(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuw_vunpack_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vxor(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vxor_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vxor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vzxt(Vu32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vzxt_Vub(HVX_Vector Vu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuh_vzxt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vzxt(Vu32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vzxt_Vuh(HVX_Vector Vu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuw_vzxt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vsplat(Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vsplat_R(Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vb_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb)(Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.h=vsplat(Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vsplat_R(Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath)(Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Qd4=vsetq2(Rt32) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq2_R(Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vsetq2_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2)(Rt)),-1) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Qd4.b=vshuffe(Qs4.h,Qt4.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Qb_vshuffe_QhQh(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Qb_vshuffe_QhQh(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Qd4.h=vshuffe(Qs4.w,Qt4.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Qh_vshuffe_QwQw(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Qh_vshuffe_QwQw(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vadd_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vadd_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qx4):carry + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)(Vu,Vv,Qx) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.h=vadd(vclb(Vu32.h),Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_vclb_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vadd_vclb_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(vclb(Vu32.w),Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_vclb_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_vclb_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vadd(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vaddacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vadd(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vaddacc_WhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vaddacc_WhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vadd_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vadd(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vaddacc_WwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vadd_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vadd_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vadd_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuw_vadd_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32=vand(!Qu4,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnR(HVX_VectorPred Qu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vand_QnR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vx32|=vand(!Qu4,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQnR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vandor_VQnR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32=vand(!Qv4,Vu32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV(HVX_VectorPred Qv, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vand_QnV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32=vand(Qv4,Vu32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV(HVX_VectorPred Qv, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vand_QV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_VuwVuwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vlsr(Vu32.ub,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vlsr_VubR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vlsr_VubR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32_VbVbR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbI(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32or_VbVbVbI(Vx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)(Vx,Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,#u3) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32_VbVbI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi)(Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16_VbVhR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhI(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16or_WhVbVhI(Vxx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)(Vxx,Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16_VbVhI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi)(Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vmax(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vmax_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vmax_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vmin(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vmin_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vmin_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpa(Vuu32.uh,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WuhRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpa_WuhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpa(Vuu32.uh,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWuhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpaacc_WwWuhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32=vmpye(Vu32.w,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_W_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRub(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyi_VwRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyiacc_VwVwRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32+=vmpyo(Vu32.w,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpyoacc_WVwVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_W_vmpyoacc_WVwVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vround(Vu32.uh,Vv32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vround_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vround(Vu32.uw,Vv32.uw):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vround_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vsat(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsat_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vsat_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vsub_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vsub_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w,Qx4):carry + C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vsub_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)(Vu,Vv,Qx) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vsub_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vsub_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vsub_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vsub_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuw_vsub_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vabs(Vu32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vabs_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vabs(Vu32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb_sat(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vabs_Vb_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat)(Vu) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vasl(Vu32.h,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vaslacc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vaslacc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vasr(Vu32.h,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasracc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasracc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_VuhVuhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_VuhVuhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_VuwVuwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vavg_VbVb_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vavg_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vavg_VuwVuw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vdd32=#0 + C Intrinsic Prototype: HVX_VectorPair Q6_W_vzero() + Instruction Type: MAPPING + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0)() +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vv32.h).h + C Intrinsic Prototype: void Q6_vgather_ARMVh(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) + Instruction Type: CVI_GATHER + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_ARMVh(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)(Rs,Rt,Mu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h + C Intrinsic Prototype: void Q6_vgather_AQRMVh(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) + Instruction Type: CVI_GATHER + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_AQRMVh(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h + C Intrinsic Prototype: void Q6_vgather_ARMWw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) + Instruction Type: CVI_GATHER_DV + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_ARMWw(Rs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)(Rs,Rt,Mu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h + C Intrinsic Prototype: void Q6_vgather_AQRMWw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) + Instruction Type: CVI_GATHER_DV + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_AQRMWw(Rs,Qs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vtmp.w=vgather(Rt32,Mu2,Vv32.w).w + C Intrinsic Prototype: void Q6_vgather_ARMVw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) + Instruction Type: CVI_GATHER + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_ARMVw(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)(Rs,Rt,Mu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w + C Intrinsic Prototype: void Q6_vgather_AQRMVw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) + Instruction Type: CVI_GATHER + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_AQRMVw(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.h=vlut4(Vu32.uh,Rtt32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vlut4_VuhPh(HVX_Vector Vu, Word64 Rtt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT2 + ========================================================================== */ + +#define Q6_Vh_vlut4_VuhPh(Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4)(Vu,Rtt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRub(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpa_WubRub(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRub(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpaacc_WhWubRub(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.h,Rtt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVhPh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT2 + ========================================================================== */ + +#define Q6_Vh_vmpa_VhVhVhPh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)(Vx,Vu,Rtt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.uh,Rtt32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT2 + ========================================================================== */ + +#define Q6_Vh_vmpa_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)(Vx,Vu,Rtt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h=vmps(Vx32.h,Vu32.uh,Rtt32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmps_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT2 + ========================================================================== */ + +#define Q6_Vh_vmps_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)(Vx,Vu,Rtt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpyacc_WwVhRh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vmpye(Vu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpye_VuhRuh(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vmpye_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.uw+=vmpye(Vu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpyeacc_VuwVuhRuh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vmpyeacc_VuwVuhRuh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vnavg(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vnavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=prefixsum(Qv4) + C Intrinsic Prototype: HVX_Vector Q6_Vb_prefixsum_Q(HVX_VectorPred Qv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.h=prefixsum(Qv4) + C Intrinsic Prototype: HVX_Vector Q6_Vh_prefixsum_Q(HVX_VectorPred Qv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.w=prefixsum(Qv4) + C Intrinsic Prototype: HVX_Vector Q6_Vw_prefixsum_Q(HVX_VectorPred Qv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h=Vw32 + C Intrinsic Prototype: void Q6_vscatter_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh)(Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h+=Vw32 + C Intrinsic Prototype: void Q6_vscatteracc_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatteracc_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)(Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32 + C Intrinsic Prototype: void Q6_vscatter_QRMVhV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_QRMVhV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 + C Intrinsic Prototype: void Q6_vscatter_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER_DV + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)(Rt,Mu,Vvv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32 + C Intrinsic Prototype: void Q6_vscatteracc_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER_DV + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatteracc_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)(Rt,Mu,Vvv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 + C Intrinsic Prototype: void Q6_vscatter_QRMWwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER_DV + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_QRMWwV(Qs,Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w=Vw32 + C Intrinsic Prototype: void Q6_vscatter_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw)(Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w+=Vw32 + C Intrinsic Prototype: void Q6_vscatteracc_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatteracc_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)(Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32 + C Intrinsic Prototype: void Q6_vscatter_QRMVwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_QRMVwV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry_sat(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred Qs) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_VwVwQ_carry_sat(Vu,Vv,Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)(Vu,Vv,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1)) +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HVX_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Vxx32.w=vasrinto(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vasrinto_WwVwVw(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vasrinto_WwVwVw(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HVX_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vrotr(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrotr_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vrotr_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HVX_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Vd32.w=vsatdw(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vsatdw_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vsatdw_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_h(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_v6mpy_WubWbI_h(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)(Vuu,Vvv,Iu2) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_h(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_v6mpyacc_WwWubWbI_h(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)(Vxx,Vuu,Vvv,Iu2) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_v(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_v6mpy_WubWbI_v(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)(Vuu,Vvv,Iu2) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_v(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_v6mpyacc_WwWubWbI_v(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)(Vxx,Vuu,Vvv,Iu2) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vabs(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vabs_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vabs_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vabs(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vabs_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vabs_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vadd(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vadd(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vadd_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vadd_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16_mix)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vadd_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vadd_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32_mix)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vadd(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vadd(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vadd(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.w=vfmv(Vu32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vfmv_Vw(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vfmv_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign_fp)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=Vu32.qf16 + C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_equals_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=Vuu32.qf32 + C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Wqf32(HVX_VectorPair Vuu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_equals_Wqf32(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf32)(Vuu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=Vu32.qf32 + C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vsf_equals_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.b=vcvt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vb_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_b_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.h=vcvt(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vcvt_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_h_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vb(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_b)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vcvt(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vh(HVX_Vector Vu) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vcvt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_h)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vcvt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vcvt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt(Vu32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vub(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_ub)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vcvt(Vu32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vuh(HVX_Vector Vu) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vcvt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_uh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vcvt(Vu32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vcvt_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_sf_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vcvt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vub_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_ub_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vcvt(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcvt_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_uh_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vdmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vdmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpyacc_VsfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vdmpyacc_VsfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vfmax(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vfmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vfmax(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vfmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vfmin(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vfmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vfmin(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vfmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vfneg(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfneg_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vfneg_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vfneg(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfneg_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vfneg_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vmax(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_vmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vmax(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vsf_vmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vmin(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_vmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vmin(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vsf_vmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vx32.hf+=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpyacc_VhfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vmpyacc_VhfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_mix_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf32_vmpy_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wqf32_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wqf32_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_mix_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16) + C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wqf32_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_qf16)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf32_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVhfVhf(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vmpyacc_WsfVhfVhf(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vmpy(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vsub(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vsub_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vsub_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16_mix)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vsub_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vsub_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32_mix)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vsub(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vsub(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_WuhVub_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubrndsat)(Vuu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_sat(HVX_VectorPair Vuu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_WuhVub_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubsat)(Vuu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_WwVuh_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhrndsat)(Vuu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_sat(HVX_VectorPair Vuu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_WwVuh_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhsat)(Vuu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16 + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmpy_VuhVuh_rs16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuh_vmpy_VuhVuh_rs16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhvs)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vadd(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vadd_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.h=Vu32.hf + C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_equals_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.hf=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vh(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_equals_Vh(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_h)(Vu) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.sf=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vw(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vsf_equals_Vw(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_w)(Vu) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.w=Vu32.sf + C Intrinsic Prototype: HVX_Vector Q6_Vw_equals_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_equals_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_w_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.bf=vcvt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vbf_vcvt_VsfVsf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vbf_vcvt_VsfVsf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_bf_sf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ + ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf)(Vu, Vv)), -1) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbfVbf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVbfVbf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ + ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_and)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbfVbf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVbfVbf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ + ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_or)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbfVbf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVbfVbf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ + ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_xor)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.bf=vmax(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmax_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vbf_vmax_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.bf=vmin(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmin_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vbf_vmin_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vmpy(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vmpy_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vxx32.sf+=vmpy(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVbfVbf(HVX_VectorPair + Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution + Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vmpyacc_WsfVbfVbf(Vxx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_bf_acc)(Vxx, Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vsub(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vsub_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32=vgetqfext(Vu32.x,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfext_VR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vgetqfext_VR(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_get_qfext)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vx32|=vgetqfext(Vu32.x,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfextor_VVR(HVX_Vector Vx, + HVX_Vector Vu, Word32 Rt) Instruction Type: CVI_VX Execution Slots: + SLOT23 + ========================================================================== */ + +#define Q6_V_vgetqfextor_VVR(Vx, Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_get_qfext_oracc)(Vx, Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.x=vsetqfext(Vu32,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vsetqfext_VR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vsetqfext_VR(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_set_qfext)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vabs(Vu32.f8) + C Intrinsic Prototype: HVX_Vector Q6_V_vabs_V(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vabs_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_f8)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vadd(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vadd_VV(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vadd_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.b=vcvt2(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt2_VhfVhf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vb_vcvt2_VhfVhf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_b_hf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt2(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt2_Vb(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt2_Vb(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_hf_b)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt2(Vu32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt2_Vub(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt2_Vub(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_hf_ub)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vcvt2(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt2_VhfVhf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vub_vcvt2_VhfVhf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_ub_hf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vcvt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_V_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector + Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vcvt_VhfVhf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_f8_hf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt(Vu32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_V(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt_V(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_f8)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vfmax(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_Vector Q6_V_vfmax_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vfmax_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vfmin(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_Vector Q6_V_vfmin_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vfmin_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vfneg(Vu32.f8) + C Intrinsic Prototype: HVX_Vector Q6_V_vfneg_V(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vfneg_V(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_f8)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32=vmerge(Vu32.x,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_V_vmerge_VVw(HVX_Vector Vu, HVX_Vector + Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vmerge_VVw(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmerge_qf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vmpy(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpy_VV(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vmpy_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vxx32.hf+=vmpy(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpyacc_WhfVV(HVX_VectorPair + Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution + Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vmpyacc_WhfVV(Vxx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_f8_acc)(Vxx, Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Rt32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfRhf(HVX_Vector Vu, Word32 + Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_VhfRhf(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_hf)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Rt32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Rhf(HVX_Vector Vu, + Word32 Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_Vqf16Rhf(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_qf16)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Rt32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfRsf(HVX_Vector Vu, Word32 + Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf32_vmpy_VsfRsf(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_sf)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vsub(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vsub_VV(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vsub_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vabs(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vabs_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vabs(Vu32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vabs_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vabs(Vu32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vabs_Vqf32(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vabs(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vabs_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32=valign4(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector + Vv, Word32 Rt) Instruction Type: CVI_VA Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_valign4_VVR(Vu, Vv, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valign4)(Vu, Vv, Rt) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.bf=Vuu32.qf32 + C Intrinsic Prototype: HVX_Vector Q6_Vbf_equals_Wqf32(HVX_VectorPair Vuu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vbf_equals_Wqf32(Vuu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_bf_qf32)(Vuu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.f8=Vu32.qf16 + C Intrinsic Prototype: HVX_Vector Q6_V_equals_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_equals_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_f8_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.h=Vu32.hf:rnd + C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf_rnd(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_equals_Vhf_rnd(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf_rnd)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vdd32.qf16=Vu32.f8 + C Intrinsic Prototype: HVX_VectorPair Q6_Wqf16_equals_V(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wqf16_equals_V(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_f8)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=Vu32.hf + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_equals_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=Vu32.qf16 + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_equals_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=Vu32.qf32 + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_equals_Vqf32(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=Vu32.sf + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_equals_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VhfVhf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf)(Vu, Vv)), -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVhfVhf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_and)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVhfVhf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_or)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_xor)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VsfVsf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf)(Vu, Vv)), -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVsfVsf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_and)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVsfVsf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_or)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_xor)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.w=vilog2(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vilog2_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.w=vilog2(Vu32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vilog2_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.w=vilog2(Vu32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vilog2_Vqf32(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.w=vilog2(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vilog2_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vneg(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vneg_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vneg(Vu32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vneg_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vneg(Vu32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vneg_Vqf32(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vneg(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vneg_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vsub_VhfVqf16(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_mix)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vsub_VsfVqf32(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_mix)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#endif /* __HVX__ */ + +#endif diff --git a/stdarch/crates/stdarch-gen-hexagon/src/main.rs b/stdarch/crates/stdarch-gen-hexagon/src/main.rs new file mode 100644 index 0000000000000..3cfbabfe0ab28 --- /dev/null +++ b/stdarch/crates/stdarch-gen-hexagon/src/main.rs @@ -0,0 +1,1717 @@ +//! Hexagon HVX Code Generator +//! +//! This generator creates v64.rs and v128.rs from scratch using the LLVM HVX +//! header file as the sole source of truth. It parses the C intrinsic prototypes +//! and generates Rust wrapper functions with appropriate attributes. +//! +//! The two generated files provide: +//! - v64.rs: 64-byte vector mode intrinsics (512-bit vectors) +//! - v128.rs: 128-byte vector mode intrinsics (1024-bit vectors) +//! +//! Both modules are available unconditionally, but require the appropriate +//! target features to actually use the intrinsics. +//! +//! Usage: +//! cd crates/stdarch-gen-hexagon +//! cargo run +//! # Output is written to ../core_arch/src/hexagon/v64.rs and v128.rs + +use regex::Regex; +use std::collections::{HashMap, HashSet}; +use std::fs::File; +use std::io::Write; +use std::path::Path; + +/// Mappings from HVX intrinsics to architecture-independent SIMD intrinsics. +/// These intrinsics have equivalent semantics and can be lowered to the generic form. +fn get_simd_intrinsic_mappings() -> HashMap<&'static str, &'static str> { + let mut map = HashMap::new(); + // Bitwise operations (element-size independent) + map.insert("vxor", "simd_xor"); + map.insert("vand", "simd_and"); + map.insert("vor", "simd_or"); + // Word (32-bit) arithmetic operations + map.insert("vaddw", "simd_add"); + map.insert("vsubw", "simd_sub"); + map +} + +/// The tracking issue number for the stdarch_hexagon feature +const TRACKING_ISSUE: &str = "151523"; + +/// HVX vector length mode +#[derive(Debug, Clone, Copy, PartialEq)] +enum VectorMode { + /// 64-byte vectors (512 bits) + V64, + /// 128-byte vectors (1024 bits) + V128, +} + +impl VectorMode { + fn bytes(&self) -> u32 { + match self { + VectorMode::V64 => 64, + VectorMode::V128 => 128, + } + } + + fn bits(&self) -> u32 { + self.bytes() * 8 + } + + fn lanes(&self) -> u32 { + self.bytes() / 4 // 32-bit lanes + } + + fn target_feature(&self) -> &'static str { + match self { + VectorMode::V64 => "hvx-length64b", + VectorMode::V128 => "hvx-length128b", + } + } +} + +/// LLVM version the header file is from (for reference) +/// Source: https://github.com/llvm/llvm-project/blob/llvmorg-22.1.0-rc1/clang/lib/Headers/hvx_hexagon_protos.h +const LLVM_VERSION: &str = "22.1.0-rc1"; + +/// Maximum HVX architecture version supported by rustc +/// Check with: rustc --target=hexagon-unknown-linux-musl --print target-features +const MAX_SUPPORTED_ARCH: u32 = 79; + +/// Local header file path (checked into the repository) +const HEADER_FILE: &str = "hvx_hexagon_protos.h"; + +/// Intrinsic information parsed from the LLVM header +#[derive(Debug, Clone)] +struct IntrinsicInfo { + /// The Q6_* intrinsic name (e.g., "Q6_V_vadd_VV") + q6_name: String, + /// The LLVM builtin name without prefix (e.g., "V6_vaddb") + builtin_name: String, + /// The short instruction name for assert_instr (e.g., "vaddb") + instr_name: String, + /// The assembly syntax from the comment + asm_syntax: String, + /// Instruction type + instr_type: String, + /// Execution slots + exec_slots: String, + /// Minimum HVX architecture version required + min_arch: u32, + /// Return type + return_type: RustType, + /// Parameters (name, type) + params: Vec<(String, RustType)>, + /// Whether this is a compound intrinsic (multiple builtins) + is_compound: bool, + /// For compound intrinsics: the parsed expression tree + compound_expr: Option, +} + +/// Expression tree for compound intrinsics +#[derive(Debug, Clone)] +enum CompoundExpr { + /// A call to a builtin: (builtin_name without V6_ prefix, arguments) + BuiltinCall(String, Vec), + /// A parameter reference by name + Param(String), + /// An integer literal (like -1) + IntLiteral(i32), +} + +/// Rust type mappings +#[derive(Debug, Clone, PartialEq)] +enum RustType { + HvxVector, + HvxVectorPair, + HvxVectorPred, + I32, + MutPtrHvxVector, + Unit, +} + +impl RustType { + fn from_c_type(c_type: &str) -> Option { + match c_type.trim() { + "HVX_Vector" => Some(RustType::HvxVector), + "HVX_VectorPair" => Some(RustType::HvxVectorPair), + "HVX_VectorPred" => Some(RustType::HvxVectorPred), + "Word32" => Some(RustType::I32), + "HVX_Vector*" => Some(RustType::MutPtrHvxVector), + "void" => Some(RustType::Unit), + _ => None, + } + } + + fn to_rust_str(&self) -> &'static str { + match self { + RustType::HvxVector => "HvxVector", + RustType::HvxVectorPair => "HvxVectorPair", + RustType::HvxVectorPred => "HvxVectorPred", + RustType::I32 => "i32", + RustType::MutPtrHvxVector => "*mut HvxVector", + RustType::Unit => "()", + } + } + + fn to_extern_str(&self) -> &'static str { + match self { + RustType::HvxVector => "HvxVector", + RustType::HvxVectorPair => "HvxVectorPair", + RustType::HvxVectorPred => "HvxVectorPred", + RustType::I32 => "i32", + RustType::MutPtrHvxVector => "*mut HvxVector", + RustType::Unit => "()", + } + } +} + +/// Parse a compound macro expression into an expression tree +fn parse_compound_expr(expr: &str) -> Option { + let expr = expr.trim(); + + // Try to match an integer literal (like -1) + if let Ok(n) = expr.parse::() { + return Some(CompoundExpr::IntLiteral(n)); + } + + // Try to match a simple parameter name (Vu, Vv, Rt, Qs, Qt, Qx, Vx, etc.) + // These are typically short identifiers in the macro + if expr.len() <= 3 + && expr.chars().all(|c| c.is_ascii_alphanumeric() || c == '_') + && !expr.contains("__") + { + return Some(CompoundExpr::Param(expr.to_lowercase())); + } + + // Check if it's wrapped in extra parens first + if expr.starts_with('(') && expr.ends_with(')') { + // Check if these parens wrap the entire expression + let inner = &expr[1..expr.len() - 1]; + // Count depth: if after removing outer parens the expression is balanced, + // the outer parens were enclosing everything + if is_balanced_parens(inner) { + // But we also need to verify these aren't part of a function call + // If the inner expression is balanced and the whole thing starts with ( + // and ends with ), it's a paren wrapper + let result = parse_compound_expr(inner); + if result.is_some() { + return result; + } + } + } + + // Try to match __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_xxx)(args) + // The args portion may contain nested calls, so we need to find the matching paren + if expr.starts_with("__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_") { + // Find the end of the builtin name (after V6_) + let prefix = "__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_"; + let after_prefix = &expr[prefix.len()..]; + if let Some(paren_pos) = after_prefix.find(')') { + let builtin_name = &after_prefix[..paren_pos]; + let rest = &after_prefix[paren_pos + 1..]; // Skip the closing ) of the WRAP + // rest should now be "(args)" + if rest.starts_with('(') && rest.ends_with(')') { + let args_str = &rest[1..rest.len() - 1]; + let args = parse_compound_args(args_str)?; + return Some(CompoundExpr::BuiltinCall(builtin_name.to_string(), args)); + } + } + } + + // Try to match __builtin_HEXAGON_V6_xxx(args) without wrap + if expr.starts_with("__builtin_HEXAGON_V6_") { + let prefix = "__builtin_HEXAGON_V6_"; + let after_prefix = &expr[prefix.len()..]; + if let Some(paren_pos) = after_prefix.find('(') { + let builtin_name = &after_prefix[..paren_pos]; + let rest = &after_prefix[paren_pos..]; + if rest.starts_with('(') && rest.ends_with(')') { + let args_str = &rest[1..rest.len() - 1]; + let args = parse_compound_args(args_str)?; + return Some(CompoundExpr::BuiltinCall(builtin_name.to_string(), args)); + } + } + } + + None +} + +/// Check if parentheses are balanced in a string +fn is_balanced_parens(s: &str) -> bool { + let mut depth = 0; + for c in s.chars() { + match c { + '(' => depth += 1, + ')' => { + depth -= 1; + if depth < 0 { + return false; + } + } + _ => {} + } + } + depth == 0 +} + +/// Parse comma-separated arguments, respecting nested parentheses +fn parse_compound_args(args_str: &str) -> Option> { + let mut args = Vec::new(); + let mut current = String::new(); + let mut depth = 0; + + for c in args_str.chars() { + match c { + '(' => { + depth += 1; + current.push(c); + } + ')' => { + depth -= 1; + current.push(c); + } + ',' if depth == 0 => { + let arg = current.trim().to_string(); + if !arg.is_empty() { + args.push(parse_compound_expr(&arg)?); + } + current.clear(); + } + _ => current.push(c), + } + } + + // Don't forget the last argument + let arg = current.trim().to_string(); + if !arg.is_empty() { + args.push(parse_compound_expr(&arg)?); + } + + Some(args) +} + +/// Extract all builtin names used in a compound expression +fn collect_builtins_from_expr(expr: &CompoundExpr, builtins: &mut HashSet) { + match expr { + CompoundExpr::BuiltinCall(name, args) => { + builtins.insert(name.clone()); + for arg in args { + collect_builtins_from_expr(arg, builtins); + } + } + CompoundExpr::Param(_) | CompoundExpr::IntLiteral(_) => {} + } +} + +/// Read the local HVX header file +fn read_header(crate_dir: &Path) -> Result { + let header_path = crate_dir.join(HEADER_FILE); + println!("Reading HVX header from: {}", header_path.display()); + println!(" (LLVM version: {})", LLVM_VERSION); + + std::fs::read_to_string(&header_path).map_err(|e| { + format!( + "Failed to read header file {}: {}", + header_path.display(), + e + ) + }) +} + +/// Parse a C function prototype to extract return type and parameters +fn parse_prototype(prototype: &str) -> Option<(RustType, Vec<(String, RustType)>)> { + // Pattern: ReturnType FunctionName(ParamType1 Param1, ParamType2 Param2, ...) + let proto_re = Regex::new(r"(\w+(?:\*)?)\s+Q6_\w+\(([^)]*)\)").unwrap(); + + if let Some(caps) = proto_re.captures(prototype) { + let return_type_str = caps[1].trim(); + let params_str = &caps[2]; + + let return_type = RustType::from_c_type(return_type_str)?; + + let mut params = Vec::new(); + if !params_str.trim().is_empty() { + // Pattern: Type Name or Type* Name + let param_re = Regex::new(r"(\w+\*?)\s+(\w+)").unwrap(); + for param in params_str.split(',') { + let param = param.trim(); + if let Some(pcaps) = param_re.captures(param) { + let ptype_str = pcaps[1].trim(); + let pname = pcaps[2].to_lowercase(); + if let Some(ptype) = RustType::from_c_type(ptype_str) { + params.push((pname, ptype)); + } else { + return None; // Unknown type + } + } + } + } + + Some((return_type, params)) + } else { + None + } +} + +/// Parse the LLVM header file to extract intrinsic information +fn parse_header(content: &str) -> Vec { + let mut intrinsics = Vec::new(); + + let arch_re = Regex::new(r"#if __HVX_ARCH__ >= (\d+)").unwrap(); + + // Regex to extract the simple builtin name from a macro body + // Match: __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_xxx)(args) + let simple_builtin_re = + Regex::new(r"__BUILTIN_VECTOR_WRAP\(__builtin_HEXAGON_(\w+)\)\([^)]*\)\s*$").unwrap(); + + // Also handle builtins without VECTOR_WRAP + let simple_builtin_re2 = Regex::new(r"__builtin_HEXAGON_(\w+)\([^)]*\)\s*$").unwrap(); + + // Regex to extract Q6 name from #define + let q6_name_re = Regex::new(r"#define\s+(Q6_\w+)").unwrap(); + + // Regex to extract macro expression body + let macro_expr_re = Regex::new(r"#define\s+Q6_\w+\([^)]*\)\s+(.+)").unwrap(); + + let lines: Vec<&str> = content.lines().collect(); + let mut current_arch: u32 = 60; + let mut i = 0; + + while i < lines.len() { + // Track architecture version + if let Some(caps) = arch_re.captures(lines[i]) { + if let Ok(arch) = caps[1].parse() { + current_arch = arch; + } + } + + // Look for Assembly Syntax comment block + if lines[i].contains("Assembly Syntax:") { + let mut asm_syntax = String::new(); + let mut prototype = String::new(); + let mut instr_type = String::new(); + let mut exec_slots = String::new(); + + // Parse the comment block + let mut j = i; + while j < lines.len() && !lines[j].starts_with("#define") { + let line = lines[j]; + if line.contains("Assembly Syntax:") { + if let Some(pos) = line.find("Assembly Syntax:") { + asm_syntax = line[pos + 16..].trim().to_string(); + } + } else if line.contains("C Intrinsic Prototype:") { + if let Some(pos) = line.find("C Intrinsic Prototype:") { + prototype = line[pos + 22..].trim().to_string(); + } + } else if line.contains("Instruction Type:") { + if let Some(pos) = line.find("Instruction Type:") { + instr_type = line[pos + 17..].trim().to_string(); + } + } else if line.contains("Execution Slots:") { + if let Some(pos) = line.find("Execution Slots:") { + exec_slots = line[pos + 16..].trim().to_string(); + } + } + j += 1; + } + + // Now find the #define line + while j < lines.len() && !lines[j].starts_with("#define") { + j += 1; + } + + if j < lines.len() { + let define_line = lines[j]; + + // Extract Q6 name and check if it's simple or compound + if let Some(caps) = q6_name_re.captures(define_line) { + let q6_name = caps[1].to_string(); + + // Get the full macro body (handle line continuations) + let mut macro_body = define_line.to_string(); + let mut k = j; + while macro_body.trim_end().ends_with('\\') && k + 1 < lines.len() { + k += 1; + macro_body.push_str(lines[k]); + } + + // Try to extract simple builtin name + let builtin_name = simple_builtin_re + .captures(¯o_body) + .or_else(|| simple_builtin_re2.captures(¯o_body)) + .map(|bcaps| bcaps[1].to_string()); + + // Check if it's a compound intrinsic (multiple __builtin calls) + let builtin_count = macro_body.matches("__builtin_HEXAGON_").count(); + let is_compound = builtin_count > 1; + + // Parse prototype + if let Some((return_type, params)) = parse_prototype(&prototype) { + if is_compound { + // For compound intrinsics, parse the expression + // Extract the macro body after the parameter list + if let Some(expr_caps) = macro_expr_re.captures(¯o_body) { + let expr_str = expr_caps[1].trim().replace(['\n', '\\'], " "); + let expr_str = expr_str.trim(); + + if let Some(compound_expr) = parse_compound_expr(expr_str) { + // For compound intrinsics, we use the outermost builtin + // as the "primary" for the instruction name + let (primary_builtin, instr_name) = match &compound_expr { + CompoundExpr::BuiltinCall(name, _) => { + (name.clone(), name.clone()) + } + _ => continue, + }; + + intrinsics.push(IntrinsicInfo { + q6_name, + builtin_name: format!("V6_{}", primary_builtin), + instr_name, + asm_syntax, + instr_type, + exec_slots, + min_arch: current_arch, + return_type, + params, + is_compound: true, + compound_expr: Some(compound_expr), + }); + } + } + } else if let Some(builtin) = builtin_name { + // Extract short instruction name + let instr_name = builtin + .strip_prefix("V6_") + .map(|s| s.to_string()) + .unwrap_or_else(|| builtin.clone()); + + intrinsics.push(IntrinsicInfo { + q6_name, + builtin_name: builtin, + instr_name, + asm_syntax, + instr_type, + exec_slots, + min_arch: current_arch, + return_type, + params, + is_compound: false, + compound_expr: None, + }); + } + } + } + } + i = j; + } + i += 1; + } + + intrinsics +} + +/// Convert Q6 name to Rust function name (lowercase with underscores) +fn q6_to_rust_name(q6_name: &str) -> String { + // Q6_V_hi_W -> q6_v_hi_w + q6_name.to_lowercase() +} + +/// Generate the module documentation +fn generate_module_doc(mode: VectorMode) -> String { + format!( + r#"//! Hexagon HVX {bytes}-byte vector mode intrinsics +//! +//! This module provides intrinsics for the Hexagon Vector Extensions (HVX) +//! in {bytes}-byte vector mode ({bits}-bit vectors). +//! +//! HVX is a wide vector extension designed for high-performance signal processing. +//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61) +//! +//! ## Vector Types +//! +//! In {bytes}-byte mode: +//! - `HvxVector` is {bits} bits ({bytes} bytes) containing {lanes} x 32-bit values +//! - `HvxVectorPair` is {pair_bits} bits ({pair_bytes} bytes) +//! - `HvxVectorPred` is {bits} bits ({bytes} bytes) for predicate operations +//! +//! To use this module, compile with `-C target-feature=+{target_feature}`. +//! +//! ## Architecture Versions +//! +//! Different intrinsics require different HVX architecture versions. Use the +//! appropriate target feature to enable the required version: +//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations) +//! - HVX v62: `-C target-feature=+hvxv62` +//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support) +//! - HVX v66: `-C target-feature=+hvxv66` +//! - HVX v68: `-C target-feature=+hvxv68` +//! - HVX v69: `-C target-feature=+hvxv69` +//! - HVX v73: `-C target-feature=+hvxv73` +//! - HVX v79: `-C target-feature=+hvxv79` +//! +//! Each version includes all features from previous versions. +"#, + bytes = mode.bytes(), + bits = mode.bits(), + lanes = mode.lanes(), + pair_bytes = mode.bytes() * 2, + pair_bits = mode.bits() * 2, + target_feature = mode.target_feature(), + ) +} + +/// Generate the type definitions for a specific vector mode +fn generate_types(mode: VectorMode) -> String { + let lanes = mode.lanes(); + let pair_lanes = lanes * 2; + let bits = mode.bits(); + let bytes = mode.bytes(); + let pair_bits = bits * 2; + let pair_bytes = bytes * 2; + + format!( + r#" +#![allow(non_camel_case_types)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use crate::intrinsics::simd::{{simd_add, simd_and, simd_or, simd_sub, simd_xor}}; + +// HVX type definitions for {bytes}-byte vector mode +types! {{ + #![unstable(feature = "stdarch_hexagon", issue = "{TRACKING_ISSUE}")] + + /// HVX vector type ({bits} bits / {bytes} bytes) + /// + /// This type represents a single HVX vector register containing {lanes} x 32-bit values. + pub struct HvxVector({lanes} x i32); + + /// HVX vector pair type ({pair_bits} bits / {pair_bytes} bytes) + /// + /// This type represents a pair of HVX vector registers, often used for + /// operations that produce double-width results. + pub struct HvxVectorPair({pair_lanes} x i32); + + /// HVX vector predicate type ({bits} bits / {bytes} bytes) + /// + /// This type represents a predicate vector used for conditional operations. + /// Each bit corresponds to a lane in the vector. + pub struct HvxVectorPred({lanes} x i32); +}} +"#, + bytes = bytes, + bits = bits, + lanes = lanes, + pair_bits = pair_bits, + pair_bytes = pair_bytes, + pair_lanes = pair_lanes, + TRACKING_ISSUE = TRACKING_ISSUE, + ) +} + +/// Builtin signature information for extern declarations +struct BuiltinSignature { + /// The V6_ prefixed name + full_name: String, + /// The short name (without V6_) + short_name: String, + /// Return type + return_type: RustType, + /// Parameter types + param_types: Vec, +} + +/// Get known signatures for builtins used in compound operations +/// These are the helper builtins that don't have their own Q6_ wrapper +fn get_compound_helper_signatures() -> HashMap { + let mut map = HashMap::new(); + + // vandvrt: HVX_Vector -> i32 -> HVX_Vector + // Converts predicate to vector representation. LLVM uses HVX_Vector for both. + map.insert( + "vandvrt".to_string(), + BuiltinSignature { + full_name: "V6_vandvrt".to_string(), + short_name: "vandvrt".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::I32], + }, + ); + + // vandqrt: HVX_Vector -> i32 -> HVX_Vector + // Converts vector representation back to predicate. LLVM uses HVX_Vector for both. + map.insert( + "vandqrt".to_string(), + BuiltinSignature { + full_name: "V6_vandqrt".to_string(), + short_name: "vandqrt".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::I32], + }, + ); + + // vandvrt_acc: HVX_Vector -> HVX_Vector -> i32 -> HVX_Vector + map.insert( + "vandvrt_acc".to_string(), + BuiltinSignature { + full_name: "V6_vandvrt_acc".to_string(), + short_name: "vandvrt_acc".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector, RustType::I32], + }, + ); + + // vandqrt_acc: HVX_Vector -> HVX_Vector -> i32 -> HVX_Vector + map.insert( + "vandqrt_acc".to_string(), + BuiltinSignature { + full_name: "V6_vandqrt_acc".to_string(), + short_name: "vandqrt_acc".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector, RustType::I32], + }, + ); + + // pred_and: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_and".to_string(), + BuiltinSignature { + full_name: "V6_pred_and".to_string(), + short_name: "pred_and".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_and_n: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_and_n".to_string(), + BuiltinSignature { + full_name: "V6_pred_and_n".to_string(), + short_name: "pred_and_n".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_or: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_or".to_string(), + BuiltinSignature { + full_name: "V6_pred_or".to_string(), + short_name: "pred_or".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_or_n: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_or_n".to_string(), + BuiltinSignature { + full_name: "V6_pred_or_n".to_string(), + short_name: "pred_or_n".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_xor: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_xor".to_string(), + BuiltinSignature { + full_name: "V6_pred_xor".to_string(), + short_name: "pred_xor".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_not: HVX_Vector -> HVX_Vector + map.insert( + "pred_not".to_string(), + BuiltinSignature { + full_name: "V6_pred_not".to_string(), + short_name: "pred_not".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector], + }, + ); + + // pred_scalar2: i32 -> HVX_Vector + map.insert( + "pred_scalar2".to_string(), + BuiltinSignature { + full_name: "V6_pred_scalar2".to_string(), + short_name: "pred_scalar2".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::I32], + }, + ); + + // Conditional store operations + map.insert( + "vS32b_qpred_ai".to_string(), + BuiltinSignature { + full_name: "V6_vS32b_qpred_ai".to_string(), + short_name: "vS32b_qpred_ai".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::MutPtrHvxVector, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vS32b_nqpred_ai".to_string(), + BuiltinSignature { + full_name: "V6_vS32b_nqpred_ai".to_string(), + short_name: "vS32b_nqpred_ai".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::MutPtrHvxVector, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vS32b_nt_qpred_ai".to_string(), + BuiltinSignature { + full_name: "V6_vS32b_nt_qpred_ai".to_string(), + short_name: "vS32b_nt_qpred_ai".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::MutPtrHvxVector, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vS32b_nt_nqpred_ai".to_string(), + BuiltinSignature { + full_name: "V6_vS32b_nt_nqpred_ai".to_string(), + short_name: "vS32b_nt_nqpred_ai".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::MutPtrHvxVector, + RustType::HvxVector, + ], + }, + ); + + // Conditional accumulation operations + for (suffix, _elem) in [("b", "byte"), ("h", "halfword"), ("w", "word")] { + // vaddbq, vaddhq, vaddwq + map.insert( + format!("vadd{}q", suffix), + BuiltinSignature { + full_name: format!("V6_vadd{}q", suffix), + short_name: format!("vadd{}q", suffix), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + // vaddbnq, vaddhnq, vaddwnq + map.insert( + format!("vadd{}nq", suffix), + BuiltinSignature { + full_name: format!("V6_vadd{}nq", suffix), + short_name: format!("vadd{}nq", suffix), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + } + + // Comparison operations with accumulation + // veqb_and, veqb_or, veqb_xor, etc. + for elem in ["b", "h", "w", "ub", "uh", "uw"] { + for op in ["and", "or", "xor"] { + // veq*_and, veq*_or, veq*_xor + map.insert( + format!("veq{}_{}", elem, op), + BuiltinSignature { + full_name: format!("V6_veq{}_{}", elem, op), + short_name: format!("veq{}_{}", elem, op), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + // vgt*_and, vgt*_or, vgt*_xor + map.insert( + format!("vgt{}_{}", elem, op), + BuiltinSignature { + full_name: format!("V6_vgt{}_{}", elem, op), + short_name: format!("vgt{}_{}", elem, op), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + } + } + + // Floating-point comparison operations (hf = half-float, sf = single-float) + for elem in ["hf", "sf"] { + // Basic comparison: vgt* + map.insert( + format!("vgt{}", elem), + BuiltinSignature { + full_name: format!("V6_vgt{}", elem), + short_name: format!("vgt{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + for op in ["and", "or", "xor"] { + // vgt*_and, vgt*_or, vgt*_xor + map.insert( + format!("vgt{}_{}", elem, op), + BuiltinSignature { + full_name: format!("V6_vgt{}_{}", elem, op), + short_name: format!("vgt{}_{}", elem, op), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + } + } + + // Prefix operations with predicate + for elem in ["b", "h", "w"] { + map.insert( + format!("vprefixq{}", elem), + BuiltinSignature { + full_name: format!("V6_vprefixq{}", elem), + short_name: format!("vprefixq{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector], + }, + ); + } + + // Scatter operations with predicate + map.insert( + "vscattermhq".to_string(), + BuiltinSignature { + full_name: "V6_vscattermhq".to_string(), + short_name: "vscattermhq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vscattermhwq".to_string(), + BuiltinSignature { + full_name: "V6_vscattermhwq".to_string(), + short_name: "vscattermhwq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVectorPair, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vscattermwq".to_string(), + BuiltinSignature { + full_name: "V6_vscattermwq".to_string(), + short_name: "vscattermwq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + // Add with carry saturation + map.insert( + "vaddcarrysat".to_string(), + BuiltinSignature { + full_name: "V6_vaddcarrysat".to_string(), + short_name: "vaddcarrysat".to_string(), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + // Gather operations with predicate + map.insert( + "vgathermhq".to_string(), + BuiltinSignature { + full_name: "V6_vgathermhq".to_string(), + short_name: "vgathermhq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::MutPtrHvxVector, + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vgathermhwq".to_string(), + BuiltinSignature { + full_name: "V6_vgathermhwq".to_string(), + short_name: "vgathermhwq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::MutPtrHvxVector, + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVectorPair, + ], + }, + ); + + map.insert( + "vgathermwq".to_string(), + BuiltinSignature { + full_name: "V6_vgathermwq".to_string(), + short_name: "vgathermwq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::MutPtrHvxVector, + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVector, + ], + }, + ); + + // Basic comparison operations (without accumulation) + for elem in ["b", "h", "w", "ub", "uh", "uw"] { + // vgt* - greater than + map.insert( + format!("vgt{}", elem), + BuiltinSignature { + full_name: format!("V6_vgt{}", elem), + short_name: format!("vgt{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + // veq* - equal + map.insert( + format!("veq{}", elem), + BuiltinSignature { + full_name: format!("V6_veq{}", elem), + short_name: format!("veq{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + } + + // Conditional subtraction operations (vsub*q, vsub*nq) + for elem in ["b", "h", "w"] { + map.insert( + format!("vsub{}q", elem), + BuiltinSignature { + full_name: format!("V6_vsub{}q", elem), + short_name: format!("vsub{}q", elem), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + map.insert( + format!("vsub{}nq", elem), + BuiltinSignature { + full_name: format!("V6_vsub{}nq", elem), + short_name: format!("vsub{}nq", elem), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + } + + // vmux - vector mux (select based on predicate) + map.insert( + "vmux".to_string(), + BuiltinSignature { + full_name: "V6_vmux".to_string(), + short_name: "vmux".to_string(), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + // vswap - vector swap based on predicate + map.insert( + "vswap".to_string(), + BuiltinSignature { + full_name: "V6_vswap".to_string(), + short_name: "vswap".to_string(), + return_type: RustType::HvxVectorPair, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + // shuffeq operations - take vectors (internal pred representation) and return vector + for elem in ["h", "w"] { + map.insert( + format!("shuffeq{}", elem), + BuiltinSignature { + full_name: format!("V6_shuffeq{}", elem), + short_name: format!("shuffeq{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + } + + // Predicate AND with vector operations + map.insert( + "vandvqv".to_string(), + BuiltinSignature { + full_name: "V6_vandvqv".to_string(), + short_name: "vandvqv".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + map.insert( + "vandvnqv".to_string(), + BuiltinSignature { + full_name: "V6_vandvnqv".to_string(), + short_name: "vandvnqv".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // vandnqrt and vandnqrt_acc + map.insert( + "vandnqrt".to_string(), + BuiltinSignature { + full_name: "V6_vandnqrt".to_string(), + short_name: "vandnqrt".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::I32], + }, + ); + + map.insert( + "vandnqrt_acc".to_string(), + BuiltinSignature { + full_name: "V6_vandnqrt_acc".to_string(), + short_name: "vandnqrt_acc".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector, RustType::I32], + }, + ); + + // pred_scalar2v2 + map.insert( + "pred_scalar2v2".to_string(), + BuiltinSignature { + full_name: "V6_pred_scalar2v2".to_string(), + short_name: "pred_scalar2v2".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::I32], + }, + ); + + map +} + +/// Generate extern declarations for all intrinsics for a specific vector mode +fn generate_extern_block(intrinsics: &[IntrinsicInfo], mode: VectorMode) -> String { + let mut output = String::new(); + + // Collect unique builtins to avoid duplicates + let mut seen_builtins: HashSet = HashSet::new(); + let mut decls: Vec<(String, String, RustType, Vec)> = Vec::new(); + + // First, add simple intrinsics + for info in intrinsics.iter().filter(|i| !i.is_compound) { + if seen_builtins.contains(&info.builtin_name) { + continue; + } + seen_builtins.insert(info.builtin_name.clone()); + + let param_types: Vec = info.params.iter().map(|(_, t)| t.clone()).collect(); + decls.push(( + info.builtin_name.clone(), + info.instr_name.clone(), + info.return_type.clone(), + param_types, + )); + } + + // Then, collect all builtins used in compound expressions + let helper_sigs = get_compound_helper_signatures(); + let mut compound_builtins: HashSet = HashSet::new(); + + for info in intrinsics.iter().filter(|i| i.is_compound) { + if let Some(ref expr) = info.compound_expr { + collect_builtins_from_expr(expr, &mut compound_builtins); + } + } + + // Add compound helper builtins + let mut missing_builtins = Vec::new(); + for builtin_name in compound_builtins { + let full_name = format!("V6_{}", builtin_name); + if seen_builtins.contains(&full_name) { + continue; + } + seen_builtins.insert(full_name.clone()); + + if let Some(sig) = helper_sigs.get(&builtin_name) { + decls.push(( + sig.full_name.clone(), + sig.short_name.clone(), + sig.return_type.clone(), + sig.param_types.clone(), + )); + } else { + missing_builtins.push(builtin_name); + } + } + + // Report missing builtins (for development purposes) + if !missing_builtins.is_empty() { + eprintln!("Warning: Missing helper signatures for compound builtins:"); + for name in &missing_builtins { + eprintln!(" - {}", name); + } + } + + // Sort by builtin name for consistent output + decls.sort_by(|a, b| a.0.cmp(&b.0)); + + // Generate intrinsic declarations for the specified mode + output.push_str(&format!( + "// LLVM intrinsic declarations for {}-byte vector mode\n", + mode.bytes() + )); + output.push_str("#[allow(improper_ctypes)]\n"); + output.push_str("unsafe extern \"unadjusted\" {\n"); + + for (builtin_name, instr_name, return_type, param_types) in &decls { + let base_link = builtin_name.replace('_', "."); + // 128-byte mode uses .128B suffix, 64-byte mode doesn't + let link_name = if builtin_name.starts_with("V6_") && mode == VectorMode::V128 { + format!("llvm.hexagon.{}.128B", base_link) + } else { + format!("llvm.hexagon.{}", base_link) + }; + + let params_str = if param_types.is_empty() { + String::new() + } else { + param_types + .iter() + .map(|t| format!("_: {}", t.to_extern_str())) + .collect::>() + .join(", ") + }; + + let return_str = if *return_type == RustType::Unit { + " -> ()".to_string() + } else { + format!(" -> {}", return_type.to_extern_str()) + }; + + output.push_str(&format!( + " #[link_name = \"{}\"]\n fn {}({}){};\n", + link_name, instr_name, params_str, return_str + )); + } + + output.push_str("}\n"); + output +} + +/// Generate Rust code for a compound expression +/// `params` maps parameter names to their types in the function signature +/// Get the type of an expression +fn get_expr_type( + expr: &CompoundExpr, + params: &HashMap, + helper_sigs: &HashMap, +) -> Option { + match expr { + CompoundExpr::BuiltinCall(name, _) => { + helper_sigs.get(name).map(|sig| sig.return_type.clone()) + } + CompoundExpr::Param(name) => params.get(name).cloned(), + CompoundExpr::IntLiteral(_) => Some(RustType::I32), + } +} + +fn generate_compound_expr_code( + expr: &CompoundExpr, + params: &HashMap, + helper_sigs: &HashMap, +) -> String { + match expr { + CompoundExpr::BuiltinCall(name, args) => { + // Get the expected parameter types for this builtin + let expected_types = helper_sigs + .get(name) + .map(|sig| sig.param_types.clone()) + .unwrap_or_default(); + + let args_code: Vec = args + .iter() + .enumerate() + .map(|(i, arg)| { + let arg_code = generate_compound_expr_code(arg, params, helper_sigs); + + // Check if we need to transmute this argument + let expected_type = expected_types.get(i); + let actual_type = get_expr_type(arg, params, helper_sigs); + + // If the builtin expects HvxVector but the arg is HvxVectorPred, transmute + if expected_type == Some(&RustType::HvxVector) + && actual_type == Some(RustType::HvxVectorPred) + { + format!( + "core::mem::transmute::({})", + arg_code + ) + } else { + arg_code + } + }) + .collect(); + format!("{}({})", name, args_code.join(", ")) + } + CompoundExpr::Param(name) => name.clone(), + CompoundExpr::IntLiteral(n) => n.to_string(), + } +} + +/// Get the primary instruction name from a compound expression (innermost significant op) +fn get_compound_primary_instr(expr: &CompoundExpr) -> Option { + match expr { + CompoundExpr::BuiltinCall(name, args) => { + // For vandqrt wrapper, look inside + if name == "vandqrt" && !args.is_empty() { + if let Some(inner) = get_compound_primary_instr(&args[0]) { + return Some(inner); + } + } + // For store operations, use the store name + if name.starts_with("vS32b") { + return Some(name.clone()); + } + // For conditional accumulation, use the add name + if name.starts_with("vadd") && (name.ends_with("q") || name.ends_with("nq")) { + return Some(name.clone()); + } + // For predicate operations + if name.starts_with("pred_") { + return Some(name.clone()); + } + // For comparison operations with accumulation + if (name.starts_with("veq") || name.starts_with("vgt")) + && (name.ends_with("_and") || name.ends_with("_or") || name.ends_with("_xor")) + { + return Some(name.clone()); + } + Some(name.clone()) + } + _ => None, + } +} + +/// Get override implementations for specific compound intrinsics. +/// Some C macros rely on implicit type conversions that don't work with +/// our stricter Rust types, so we provide corrected implementations. +fn get_compound_overrides() -> HashMap<&'static str, &'static str> { + let mut map = HashMap::new(); + + // Q6_V_vand_QR: takes pred, returns vec + // Use transmute to convert pred to vec for LLVM, call vandvrt + map.insert( + "Q6_V_vand_QR", + "vandvrt(core::mem::transmute::(qu), rt)", + ); + + // Q6_V_vandor_VQR: takes vec and pred, returns vec + map.insert( + "Q6_V_vandor_VQR", + "vandvrt_acc(vx, core::mem::transmute::(qu), rt)", + ); + + // Q6_Q_vand_VR: takes vec, returns pred + map.insert( + "Q6_Q_vand_VR", + "core::mem::transmute::(vandqrt(vu, rt))", + ); + + // Q6_Q_vandor_QVR: takes pred and vec, returns pred + map.insert( + "Q6_Q_vandor_QVR", + "core::mem::transmute::(vandqrt_acc(core::mem::transmute::(qx), vu, rt))", + ); + + map +} + +/// Generate wrapper functions for all intrinsics +fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String { + let mut output = String::new(); + let simd_mappings = get_simd_intrinsic_mappings(); + + // Generate simple intrinsics + for info in intrinsics.iter().filter(|i| !i.is_compound) { + let rust_name = q6_to_rust_name(&info.q6_name); + + // Generate doc comment + output.push_str(&format!("/// `{}`\n", info.asm_syntax)); + output.push_str("///\n"); + output.push_str(&format!("/// Instruction Type: {}\n", info.instr_type)); + output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots)); + + // Generate attributes + output.push_str("#[inline(always)]\n"); + output.push_str(&format!( + "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"hvxv{}\"))]\n", + info.min_arch + )); + + // Check if we should use simd intrinsic instead + let use_simd = simd_mappings.get(info.instr_name.as_str()); + + // assert_instr uses the original instruction name + output.push_str(&format!( + "#[cfg_attr(test, assert_instr({}))]\n", + info.instr_name + )); + + output.push_str(&format!( + "#[unstable(feature = \"stdarch_hexagon\", issue = \"{}\")]\n", + TRACKING_ISSUE + )); + + // Generate function signature + let params_str = info + .params + .iter() + .map(|(name, ty)| format!("{}: {}", name, ty.to_rust_str())) + .collect::>() + .join(", "); + + let return_str = if info.return_type == RustType::Unit { + String::new() + } else { + format!(" -> {}", info.return_type.to_rust_str()) + }; + + output.push_str(&format!( + "pub unsafe fn {}({}){} {{\n", + rust_name, params_str, return_str + )); + + // Generate function body + let args_str = info + .params + .iter() + .map(|(name, _)| name.as_str()) + .collect::>() + .join(", "); + + if let Some(simd_fn) = use_simd { + // Use architecture-independent simd intrinsic + output.push_str(&format!(" {}({})\n", simd_fn, args_str)); + } else { + // Use the LLVM intrinsic + output.push_str(&format!(" {}({})\n", info.instr_name, args_str)); + } + + output.push_str("}\n\n"); + } + + // Generate compound intrinsics + let helper_sigs = get_compound_helper_signatures(); + let overrides = get_compound_overrides(); + for info in intrinsics.iter().filter(|i| i.is_compound) { + if let Some(ref compound_expr) = info.compound_expr { + let rust_name = q6_to_rust_name(&info.q6_name); + + // Get the primary instruction for assert_instr + let _primary_instr = get_compound_primary_instr(compound_expr) + .unwrap_or_else(|| info.instr_name.clone()); + + // Generate doc comment + output.push_str(&format!("/// `{}`\n", info.asm_syntax)); + output.push_str("///\n"); + output.push_str( + "/// This is a compound operation composed of multiple HVX instructions.\n", + ); + if !info.instr_type.is_empty() { + output.push_str(&format!("/// Instruction Type: {}\n", info.instr_type)); + } + if !info.exec_slots.is_empty() { + output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots)); + } + + // Generate attributes + output.push_str("#[inline(always)]\n"); + output.push_str(&format!( + "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"hvxv{}\"))]\n", + info.min_arch + )); + + // For compound ops, we skip assert_instr since they emit multiple instructions + // output.push_str(&format!( + // "#[cfg_attr(test, assert_instr({}))]\n", + // primary_instr + // )); + + output.push_str(&format!( + "#[unstable(feature = \"stdarch_hexagon\", issue = \"{}\")]\n", + TRACKING_ISSUE + )); + + // Generate function signature + let params_str = info + .params + .iter() + .map(|(name, ty)| format!("{}: {}", name, ty.to_rust_str())) + .collect::>() + .join(", "); + + let return_str = if info.return_type == RustType::Unit { + String::new() + } else { + format!(" -> {}", info.return_type.to_rust_str()) + }; + + output.push_str(&format!( + "pub unsafe fn {}({}){} {{\n", + rust_name, params_str, return_str + )); + + // Check if we have an override for this intrinsic + let body = if let Some(override_body) = overrides.get(info.q6_name.as_str()) { + override_body.to_string() + } else { + // Build param type map for expression code generation + let param_types: HashMap = info.params.iter().cloned().collect(); + // Generate function body from compound expression + let expr_body = + generate_compound_expr_code(compound_expr, ¶m_types, &helper_sigs); + + // Check if we need to transmute the result + let expr_return_type = get_expr_type(compound_expr, ¶m_types, &helper_sigs); + if info.return_type == RustType::HvxVectorPred + && expr_return_type == Some(RustType::HvxVector) + { + format!( + "core::mem::transmute::({})", + expr_body + ) + } else { + expr_body + } + }; + output.push_str(&format!(" {}\n", body)); + + output.push_str("}\n\n"); + } + } + + output +} + +/// Generate a module file for a specific vector mode +fn generate_module_file( + intrinsics: &[IntrinsicInfo], + output_path: &Path, + mode: VectorMode, +) -> Result<(), String> { + let mut output = + File::create(output_path).map_err(|e| format!("Failed to create output: {}", e))?; + + writeln!(output, "{}", generate_module_doc(mode)).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_types(mode)).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_extern_block(intrinsics, mode)).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_functions(intrinsics)).map_err(|e| e.to_string())?; + + // Ensure file is flushed before running rustfmt + drop(output); + + // Run rustfmt on the generated file + let status = std::process::Command::new("rustfmt") + .arg(output_path) + .status() + .map_err(|e| format!("Failed to run rustfmt: {}", e))?; + + if !status.success() { + return Err("rustfmt failed".to_string()); + } + + Ok(()) +} + +fn main() -> Result<(), String> { + println!("=== Hexagon HVX Code Generator ===\n"); + + // Get the crate directory first (needed for both reading header and writing output) + let crate_dir = std::env::var("CARGO_MANIFEST_DIR") + .map(std::path::PathBuf::from) + .unwrap_or_else(|_| std::env::current_dir().unwrap()); + + // Read and parse the local LLVM header + println!("Step 1: Reading LLVM HVX header..."); + let header_content = read_header(&crate_dir)?; + println!(" Read {} bytes", header_content.len()); + + println!("\nStep 2: Parsing intrinsic definitions..."); + let all_intrinsics = parse_header(&header_content); + println!(" Found {} intrinsic definitions", all_intrinsics.len()); + + // Filter out intrinsics requiring architecture versions not yet supported by rustc + let intrinsics: Vec<_> = all_intrinsics + .into_iter() + .filter(|i| i.min_arch <= MAX_SUPPORTED_ARCH) + .collect(); + let filtered_count = intrinsics.len(); + println!( + " Filtered to {} intrinsics (max supported: hvxv{})", + filtered_count, MAX_SUPPORTED_ARCH + ); + + // Count simple vs compound + let simple_count = intrinsics.iter().filter(|i| !i.is_compound).count(); + let compound_count = intrinsics.iter().filter(|i| i.is_compound).count(); + println!(" Simple intrinsics: {}", simple_count); + println!(" Compound intrinsics: {}", compound_count); + + // Print some sample intrinsics for verification + println!("\n Sample simple intrinsics:"); + for info in intrinsics.iter().filter(|i| !i.is_compound).take(5) { + println!( + " {} -> {} ({})", + info.q6_name, info.builtin_name, info.asm_syntax + ); + } + + println!("\n Sample compound intrinsics:"); + for info in intrinsics.iter().filter(|i| i.is_compound).take(5) { + println!(" {} ({})", info.q6_name, info.asm_syntax); + } + + // Count architecture versions + let mut arch_counts: HashMap = HashMap::new(); + for info in &intrinsics { + *arch_counts.entry(info.min_arch).or_insert(0) += 1; + } + println!("\n By architecture version:"); + let mut archs: Vec<_> = arch_counts.iter().collect(); + archs.sort_by_key(|(k, _)| *k); + for (arch, count) in archs { + println!(" HVX v{}: {} intrinsics", arch, count); + } + + // Generate output files + let hexagon_dir = crate_dir.join("../core_arch/src/hexagon"); + + // Generate v64.rs (64-byte vector mode) + let v64_path = hexagon_dir.join("v64.rs"); + println!("\nStep 3: Generating v64.rs (64-byte mode)..."); + generate_module_file(&intrinsics, &v64_path, VectorMode::V64)?; + println!(" Output: {}", v64_path.display()); + + // Generate v128.rs (128-byte vector mode) + let v128_path = hexagon_dir.join("v128.rs"); + println!("\nStep 4: Generating v128.rs (128-byte mode)..."); + generate_module_file(&intrinsics, &v128_path, VectorMode::V128)?; + println!(" Output: {}", v128_path.display()); + + println!("\n=== Results ==="); + println!( + " Generated {} simple wrapper functions per module", + simple_count + ); + println!( + " Generated {} compound wrapper functions per module", + compound_count + ); + println!( + " Total: {} functions per module", + simple_count + compound_count + ); + println!(" Output files: v64.rs, v128.rs"); + + Ok(()) +} diff --git a/stdarch/crates/stdarch-gen-loongarch/lasx.spec b/stdarch/crates/stdarch-gen-loongarch/lasx.spec index e3bdfcb5e9faa..ac4203a03f207 100644 --- a/stdarch/crates/stdarch-gen-loongarch/lasx.spec +++ b/stdarch/crates/stdarch-gen-loongarch/lasx.spec @@ -2426,7 +2426,7 @@ data-types = V8SI, V4DI, V4DI /// lasx_xvorn_v name = lasx_xvorn_v asm-fmts = xd, xj, xk -data-types = V32QI, V32QI, V32QI +data-types = UV32QI, UV32QI, UV32QI /// lasx_xvldi name = lasx_xvldi @@ -3703,3 +3703,93 @@ name = lasx_xvrepli_w asm-fmts = xd, si10 data-types = V8SI, HI +/// lasx_cast_128_s +name = lasx_cast_128_s +asm-fmts = xd, vj +data-types = V8SF, V4SF + +/// lasx_cast_128_d +name = lasx_cast_128_d +asm-fmts = xd, vj +data-types = V4DF, V2DF + +/// lasx_cast_128 +name = lasx_cast_128 +asm-fmts = xd, vj +data-types = V4DI, V2DI + +/// lasx_concat_128_s +name = lasx_concat_128_s +asm-fmts = xd, vj, vk +data-types = V8SF, V4SF, V4SF + +/// lasx_concat_128_d +name = lasx_concat_128_d +asm-fmts = xd, vj, vk +data-types = V4DF, V2DF, V2DF + +/// lasx_concat_128 +name = lasx_concat_128 +asm-fmts = xd, vj, vk +data-types = V4DI, V2DI, V2DI + +/// lasx_extract_128_lo_s +name = lasx_extract_128_lo_s +asm-fmts = vd, xj +data-types = V4SF, V8SF + +/// lasx_extract_128_hi_s +name = lasx_extract_128_hi_s +asm-fmts = vd, xj +data-types = V4SF, V8SF + +/// lasx_extract_128_lo_d +name = lasx_extract_128_lo_d +asm-fmts = vd, xj +data-types = V2DF, V4DF + +/// lasx_extract_128_hi_d +name = lasx_extract_128_hi_d +asm-fmts = vd, xj +data-types = V2DF, V4DF + +/// lasx_extract_128_lo +name = lasx_extract_128_lo +asm-fmts = vd, xj +data-types = V2DI, V4DI + +/// lasx_extract_128_hi +name = lasx_extract_128_hi +asm-fmts = vd, xj +data-types = V2DI, V4DI + +/// lasx_insert_128_lo_s +name = lasx_insert_128_lo_s +asm-fmts = xd, xj, vk +data-types = V8SF, V8SF, V4SF + +/// lasx_insert_128_hi_s +name = lasx_insert_128_hi_s +asm-fmts = xd, xj, vk +data-types = V8SF, V8SF, V4SF + +/// lasx_insert_128_lo_d +name = lasx_insert_128_lo_d +asm-fmts = xd, xj, vk +data-types = V4DF, V4DF, V2DF + +/// lasx_insert_128_hi_d +name = lasx_insert_128_hi_d +asm-fmts = xd, xj, vk +data-types = V4DF, V4DF, V2DF + +/// lasx_insert_128_lo +name = lasx_insert_128_lo +asm-fmts = xd, xj, vk +data-types = V4DI, V4DI, V2DI + +/// lasx_insert_128_hi +name = lasx_insert_128_hi +asm-fmts = xd, xj, vk +data-types = V4DI, V4DI, V2DI + diff --git a/stdarch/crates/stdarch-gen-loongarch/lasxintrin.h b/stdarch/crates/stdarch-gen-loongarch/lasxintrin.h index c525b6106b897..02bb97918d95d 100644 --- a/stdarch/crates/stdarch-gen-loongarch/lasxintrin.h +++ b/stdarch/crates/stdarch-gen-loongarch/lasxintrin.h @@ -1,10 +1,10 @@ /* - * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lasxintrin.h;hb=61f1001f2f4ab9128e5eb6e9a4adbbb0f9f0bc75 + * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lasxintrin.h;hb=c2013267642fea4a6e89b826940c8aa80a76089d */ /* LARCH Loongson ASX intrinsics include file. - Copyright (C) 2018-2024 Free Software Foundation, Inc. + Copyright (C) 2018-2025 Free Software Foundation, Inc. This file is part of GCC. @@ -27,6 +27,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ +#include + #ifndef _GCC_LOONGSON_ASXINTRIN_H #define _GCC_LOONGSON_ASXINTRIN_H 1 @@ -3568,11 +3570,11 @@ __m256i __lasx_xvssrln_w_d (__m256i _1, __m256i _2) } /* Assembly instruction format: xd, xj, xk. */ -/* Data types in instruction templates: V32QI, V32QI, V32QI. */ +/* Data types in instruction templates: UV32QI, UV32QI, UV32QI. */ extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m256i __lasx_xvorn_v (__m256i _1, __m256i _2) { - return (__m256i)__builtin_lasx_xvorn_v ((v32i8)_1, (v32i8)_2); + return (__m256i)__builtin_lasx_xvorn_v ((v32u8)_1, (v32u8)_2); } /* Assembly instruction format: xd, i13. */ @@ -5372,5 +5374,159 @@ __m256i __lasx_xvfcmp_sun_s (__m256 _1, __m256 _2) #define __lasx_xvrepli_w(/*si10*/ _1) \ ((__m256i)__builtin_lasx_xvrepli_w ((_1))) +#if defined (__loongarch_asx_sx_conv) +/* Add builtin interfaces for 128 and 256 vector conversions. + For the assembly instruction format of some functions of the following vector + conversion, it is not described exactly in accordance with the format of the + generated assembly instruction. + In the front end of the Rust language, different built-in functions are called + by analyzing the format of assembly instructions. The data types of instructions + are all defined based on the interfaces of the defined functions, in the + following order: output, input... . */ +/* Assembly instruction format: xd, vj. */ +/* Data types in instruction templates: V8SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_cast_128_s (__m128 _1) +{ + return (__m256)__builtin_lasx_cast_128_s ((v4f32)_1); +} + +/* Assembly instruction format: xd, vj. */ +/* Data types in instruction templates: V4DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_cast_128_d (__m128d _1) +{ + return (__m256d)__builtin_lasx_cast_128_d ((v2f64)_1); +} + +/* Assembly instruction format: xd, vj. */ +/* Data types in instruction templates: V4DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_cast_128 (__m128i _1) +{ + return (__m256i)__builtin_lasx_cast_128 ((v2i64)_1); +} + +/* Assembly instruction format: xd, vj, vk. */ +/* Data types in instruction templates: V8SF, V4SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_concat_128_s (__m128 _1, __m128 _2) +{ + return (__m256)__builtin_lasx_concat_128_s ((v4f32)_1, (v4f32)_2); +} + +/* Assembly instruction format: xd, vj, vk. */ +/* Data types in instruction templates: V4DF, V2DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_concat_128_d (__m128d _1, __m128d _2) +{ + return (__m256d)__builtin_lasx_concat_128_d ((v2f64)_1, (v2f64)_2); +} + +/* Assembly instruction format: xd, vj, vk. */ +/* Data types in instruction templates: V4DI, V2DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_concat_128 (__m128i _1, __m128i _2) +{ + return (__m256i)__builtin_lasx_concat_128 ((v2i64)_1, (v2i64)_2); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V4SF, V8SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128 __lasx_extract_128_lo_s (__m256 _1) +{ + return (__m128)__builtin_lasx_extract_128_lo_s ((v8f32)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V4SF, V8SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128 __lasx_extract_128_hi_s (__m256 _1) +{ + return (__m128)__builtin_lasx_extract_128_hi_s ((v8f32)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DF, V4DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128d __lasx_extract_128_lo_d (__m256d _1) +{ + return (__m128d)__builtin_lasx_extract_128_lo_d ((v4f64)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DF, V4DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128d __lasx_extract_128_hi_d (__m256d _1) +{ + return (__m128d)__builtin_lasx_extract_128_hi_d ((v4f64)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DI, V4DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128i __lasx_extract_128_lo (__m256i _1) +{ + return (__m128i)__builtin_lasx_extract_128_lo ((v4i64)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DI, V4DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128i __lasx_extract_128_hi (__m256i _1) +{ + return (__m128i)__builtin_lasx_extract_128_hi ((v4i64)_1); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V8SF, V8SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_insert_128_lo_s (__m256 _1, __m128 _2) +{ + return (__m256)__builtin_lasx_insert_128_lo_s ((v8f32)_1, (v4f32)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V8SF, V8SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_insert_128_hi_s (__m256 _1, __m128 _2) +{ + return (__m256)__builtin_lasx_insert_128_hi_s ((v8f32)_1, (v4f32)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DF, V4DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_insert_128_lo_d (__m256d _1, __m128d _2) +{ + return (__m256d)__builtin_lasx_insert_128_lo_d ((v4f64)_1, (v2f64)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DF, V4DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_insert_128_hi_d (__m256d _1, __m128d _2) +{ + return (__m256d)__builtin_lasx_insert_128_hi_d ((v4f64)_1, (v2f64)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DI, V4DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_insert_128_lo (__m256i _1, __m128i _2) +{ + return (__m256i)__builtin_lasx_insert_128_lo ((v4i64)_1, (v2i64)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DI, V4DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_insert_128_hi (__m256i _1, __m128i _2) +{ + return (__m256i)__builtin_lasx_insert_128_hi ((v4i64)_1, (v2i64)_2); +} + +#endif /* defined(__loongarch_asx_sx_conv). */ #endif /* defined(__loongarch_asx). */ #endif /* _GCC_LOONGSON_ASXINTRIN_H. */ diff --git a/stdarch/crates/stdarch-gen-loongarch/lsx.spec b/stdarch/crates/stdarch-gen-loongarch/lsx.spec index dc835770d566e..b5497b6e6207e 100644 --- a/stdarch/crates/stdarch-gen-loongarch/lsx.spec +++ b/stdarch/crates/stdarch-gen-loongarch/lsx.spec @@ -3286,7 +3286,7 @@ data-types = V4SI, V2DI, V2DI /// lsx_vorn_v name = lsx_vorn_v asm-fmts = vd, vj, vk -data-types = V16QI, V16QI, V16QI +data-types = UV16QI, UV16QI, UV16QI /// lsx_vldi name = lsx_vldi diff --git a/stdarch/crates/stdarch-gen-loongarch/lsxintrin.h b/stdarch/crates/stdarch-gen-loongarch/lsxintrin.h index 943f2df913e4d..66b7c7e2187ac 100644 --- a/stdarch/crates/stdarch-gen-loongarch/lsxintrin.h +++ b/stdarch/crates/stdarch-gen-loongarch/lsxintrin.h @@ -1,10 +1,10 @@ /* - * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lsxintrin.h;hb=61f1001f2f4ab9128e5eb6e9a4adbbb0f9f0bc75 + * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lsxintrin.h;hb=6441eb6dc020faae0672ea724dfdb38c6a9bf6a1 */ /* LARCH Loongson SX intrinsics include file. - Copyright (C) 2018-2024 Free Software Foundation, Inc. + Copyright (C) 2018-2025 Free Software Foundation, Inc. This file is part of GCC. @@ -4749,11 +4749,11 @@ __m128i __lsx_vssrln_w_d (__m128i _1, __m128i _2) } /* Assembly instruction format: vd, vj, vk. */ -/* Data types in instruction templates: V16QI, V16QI, V16QI. */ +/* Data types in instruction templates: UV16QI, UV16QI, UV16QI. */ extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m128i __lsx_vorn_v (__m128i _1, __m128i _2) { - return (__m128i)__builtin_lsx_vorn_v ((v16i8)_1, (v16i8)_2); + return (__m128i)__builtin_lsx_vorn_v ((v16u8)_1, (v16u8)_2); } /* Assembly instruction format: vd, i13. */ diff --git a/stdarch/crates/stdarch-gen-loongarch/src/main.rs b/stdarch/crates/stdarch-gen-loongarch/src/main.rs index 5076064ffcdd3..10b87c70e9ede 100644 --- a/stdarch/crates/stdarch-gen-loongarch/src/main.rs +++ b/stdarch/crates/stdarch-gen-loongarch/src/main.rs @@ -157,7 +157,7 @@ fn gen_bind(in_file: String, ext_name: &str) -> io::Result<()> { // ``` use crate::mem::transmute; -use super::types::*; +use super::super::*; "# )); @@ -1551,6 +1551,10 @@ fn gen_test_body( format!( " printf(\"\\n {current_name}{as_params};\\n assert_eq!(r, transmute(o));\\n\"{as_args});" ) + } else if current_name.starts_with("lasx_cast_128") { + format!( + " printf(\"\\n assert_eq!(r.as_array()[0..2], transmute::<_, i64x4>({current_name}{as_params}).as_array()[0..2]);\\n\"{as_args});" + ) } else { format!( " printf(\"\\n assert_eq!(r, transmute({current_name}{as_params}));\\n\"{as_args});" diff --git a/stdarch/crates/stdarch-verify/tests/arm.rs b/stdarch/crates/stdarch-verify/tests/arm.rs index 86897908e062c..3ef9ce2a38b69 100644 --- a/stdarch/crates/stdarch-verify/tests/arm.rs +++ b/stdarch/crates/stdarch-verify/tests/arm.rs @@ -445,6 +445,7 @@ fn verify_all_signatures() { && !rust.file.ends_with("v7.rs\"") && !rust.file.ends_with("v8.rs\"") && !rust.file.ends_with("mte.rs\"") + && !rust.file.ends_with("rand.rs\"") && !rust.file.ends_with("ex.rs\"") && !skip_intrinsic_verify.contains(&rust.name) { diff --git a/stdarch/crates/stdarch-verify/tests/x86-intel.rs b/stdarch/crates/stdarch-verify/tests/x86-intel.rs index 4136463f197fd..7fc47be42e14b 100644 --- a/stdarch/crates/stdarch-verify/tests/x86-intel.rs +++ b/stdarch/crates/stdarch-verify/tests/x86-intel.rs @@ -211,6 +211,7 @@ fn verify_all_signatures() { "_rdseed64_step", // Prefetch "_mm_prefetch", + "_m_prefetchrs", // CMPXCHG "cmpxchg16b", // Undefined @@ -246,7 +247,6 @@ fn verify_all_signatures() { "_xend", "_xabort_code", // Aliases - "_mm_comige_ss", "_mm_cvt_ss2si", "_mm_cvtt_ss2si", "_mm_cvt_si2ss", @@ -306,7 +306,7 @@ fn verify_all_signatures() { } // FIXME: these have not been added to Intrinsics Guide yet - if ["amx-avx512", "amx-fp8", "amx-movrs", "amx-tf32"] + if ["amx-avx512", "amx-fp8", "amx-movrs", "amx-tf32", "movrs"] .iter() .any(|f| feature.contains(f)) { diff --git a/stdarch/examples/Cargo.toml b/stdarch/examples/Cargo.toml index 61451edee841c..c4fc4c7e374c8 100644 --- a/stdarch/examples/Cargo.toml +++ b/stdarch/examples/Cargo.toml @@ -23,6 +23,11 @@ path = "hex.rs" name = "connect5" path = "connect5.rs" +# Hexagon-only: requires --target hexagon-unknown-linux-musl +[[bin]] +name = "gaussian" +path = "gaussian.rs" + [[example]] name = "wasm" crate-type = ["cdylib"] diff --git a/stdarch/examples/gaussian.rs b/stdarch/examples/gaussian.rs new file mode 100644 index 0000000000000..dea16f797aca6 --- /dev/null +++ b/stdarch/examples/gaussian.rs @@ -0,0 +1,351 @@ +//! Hexagon HVX Gaussian 3x3 blur example +//! +//! This example demonstrates the use of Hexagon HVX intrinsics to implement +//! a 3x3 Gaussian blur filter on unsigned 8-bit images. +//! +//! The 3x3 Gaussian kernel is: +//! 1 2 1 +//! 2 4 2 / 16 +//! 1 2 1 +//! +//! This is a separable filter: `[1 2 1]^T * [1 2 1] / 16`. +//! +//! On Hexagon targets, this implementation uses `HvxVectorPair` for widening +//! arithmetic to achieve full precision in the Gaussian computation, avoiding +//! the approximation errors of byte-averaging approaches. On other targets, +//! it runs a reference implementation in pure Rust. +//! +//! # Building and Running (Hexagon) +//! +//! To build (requires Hexagon toolchain): +//! +//! RUSTFLAGS="-C target-feature=+hvxv62,+hvx-length128b \ +//! -C linker=hexagon-unknown-linux-musl-clang" \ +//! cargo +nightly build -p stdarch_examples --bin gaussian \ +//! --target hexagon-unknown-linux-musl \ +//! -Zbuild-std -Zbuild-std-features=llvm-libunwind +//! +//! To run under QEMU: +//! +//! qemu-hexagon -L /target/hexagon-unknown-linux-musl \ +//! target/hexagon-unknown-linux-musl/debug/gaussian +//! +//! # Building and Running (Other targets) +//! +//! cargo +nightly run -p stdarch_examples --bin gaussian + +#![cfg_attr(target_arch = "hexagon", feature(stdarch_hexagon))] +#![cfg_attr(target_arch = "hexagon", feature(hexagon_target_feature))] +#![allow( + unsafe_op_in_unsafe_fn, + clippy::unwrap_used, + clippy::print_stdout, + clippy::missing_docs_in_private_items, + clippy::cast_possible_wrap, + clippy::cast_ptr_alignment +)] + +/// Image width - must be multiple of HVX vector length on Hexagon +const WIDTH: usize = 256; +const HEIGHT: usize = 16; + +// ============================================================================ +// Hexagon HVX implementation +// ============================================================================ + +#[cfg(target_arch = "hexagon")] +mod hvx { + #[cfg(not(target_feature = "hvx-length128b"))] + use core_arch::arch::hexagon::v64::*; + #[cfg(target_feature = "hvx-length128b")] + use core_arch::arch::hexagon::v128::*; + + /// Vector length in bytes for HVX 128-byte mode + #[cfg(target_feature = "hvx-length128b")] + const VLEN: usize = 128; + + /// Vector length in bytes for HVX 64-byte mode + #[cfg(not(target_feature = "hvx-length128b"))] + const VLEN: usize = 64; + + /// Vertical 1-2-1 filter pass using HvxVectorPair widening arithmetic + /// + /// Computes: dst[x] = (row_above[x] + 2*center[x] + row_below[x] + 2) >> 2 + /// + /// Uses HvxVectorPair to widen u8 to u16 for precise arithmetic, avoiding + /// the rounding errors of byte-averaging approximations. + /// + /// # Safety + /// + /// - `src` must point to the center row with valid data at -stride and +stride + /// - `dst` must point to a valid output buffer for `width` bytes + /// - `width` must be a multiple of VLEN + /// - All pointers must be HVX-aligned (128-byte for 128B mode) + #[target_feature(enable = "hvxv62")] + unsafe fn vertical_121_pass(src: *const u8, stride: isize, width: usize, dst: *mut u8) { + let inp0 = src.offset(-stride) as *const HvxVector; + let inp1 = src as *const HvxVector; + let inp2 = src.offset(stride) as *const HvxVector; + let outp = dst as *mut HvxVector; + + let n_chunks = width / VLEN; + for i in 0..n_chunks { + let above = *inp0.add(i); + let center = *inp1.add(i); + let below = *inp2.add(i); + + // Widen above + below to 16-bit using HvxVectorPair + // q6_wh_vadd_vubvub: adds two u8 vectors, producing u16 results in a pair + let above_plus_below: HvxVectorPair = q6_wh_vadd_vubvub(above, below); + + // Widen center * 2 (add center to itself) + let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(center, center); + + // Add them: (above + below) + (center * 2) = above + 2*center + below + let sum: HvxVectorPair = q6_wh_vadd_whwh(above_plus_below, center_x2); + + // Extract high and low vectors from the pair (each contains u16 values) + let sum_lo = q6_v_lo_w(sum); // Lower 64 elements as i16 + let sum_hi = q6_v_hi_w(sum); // Upper 64 elements as i16 + + // Arithmetic right shift by 2 (divide by 4) with rounding + // Add 2 for rounding before shift: (sum + 2) >> 2 + let two = q6_vh_vsplat_r(2); + let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two); + let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two); + let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two); + let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two); + + // Pack back to u8 with saturation: takes hi and lo halfword vectors, + // saturates to u8, and interleaves them back to original order + let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo); + + *outp.add(i) = result; + } + } + + /// Horizontal 1-2-1 filter pass using HvxVectorPair widening arithmetic + /// + /// Computes: dst[x] = (src[x-1] + 2*src[x] + src[x+1] + 2) >> 2 + /// + /// Uses `valign` and `vlalign` to shift vectors by 1 byte for neighbor access, + /// then HvxVectorPair for precise widening arithmetic. + /// + /// # Safety + /// + /// - `src` and `dst` must point to valid buffers of `width` bytes + /// - `width` must be a multiple of VLEN + /// - All pointers must be HVX-aligned + #[target_feature(enable = "hvxv62")] + unsafe fn horizontal_121_pass(src: *const u8, width: usize, dst: *mut u8) { + let inp = src as *const HvxVector; + let outp = dst as *mut HvxVector; + + let n_chunks = width / VLEN; + let mut prev = q6_v_vzero(); + + for i in 0..n_chunks { + let curr = *inp.add(i); + let next = if i + 1 < n_chunks { + *inp.add(i + 1) + } else { + q6_v_vzero() + }; + + // Left neighbor (x-1): shift curr right by 1 byte, filling from prev + let left = q6_v_vlalign_vvr(curr, prev, 1); + + // Right neighbor (x+1): shift curr left by 1 byte, filling from next + let right = q6_v_valign_vvr(next, curr, 1); + + // Widen left + right to 16-bit + let left_plus_right: HvxVectorPair = q6_wh_vadd_vubvub(left, right); + + // Widen center * 2 + let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(curr, curr); + + // Add: left + 2*center + right + let sum: HvxVectorPair = q6_wh_vadd_whwh(left_plus_right, center_x2); + + // Extract high and low vectors + let sum_lo = q6_v_lo_w(sum); + let sum_hi = q6_v_hi_w(sum); + + // Arithmetic right shift by 2 with rounding + let two = q6_vh_vsplat_r(2); + let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two); + let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two); + let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two); + let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two); + + // Pack back to u8 with saturation + let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo); + + *outp.add(i) = result; + + prev = curr; + } + } + + /// Apply Gaussian 3x3 blur to an entire image using separable filtering + /// + /// Two-pass approach: + /// 1. Vertical pass: apply 1-2-1 filter across rows + /// 2. Horizontal pass: apply 1-2-1 filter across columns + /// + /// Combined effect: 3x3 Gaussian kernel [1 2 1; 2 4 2; 1 2 1] / 16 + /// + /// # Safety + /// + /// - `src` and `dst` must point to valid image buffers of `stride * height` bytes + /// - `tmp` must point to a valid temporary buffer of `width` bytes, HVX-aligned + /// - `width` must be a multiple of VLEN and >= VLEN + /// - `stride` must be >= `width` + /// - All buffers must be HVX-aligned (128-byte for 128B mode) + #[target_feature(enable = "hvxv62")] + pub unsafe fn gaussian3x3u8( + src: *const u8, + stride: usize, + width: usize, + height: usize, + dst: *mut u8, + tmp: *mut u8, + ) { + let stride_i = stride as isize; + + // Process interior rows (skip first and last which lack vertical neighbors) + for y in 1..height - 1 { + let row_src = src.offset(y as isize * stride_i); + let row_dst = dst.offset(y as isize * stride_i); + + // Pass 1: vertical 1-2-1 into tmp + vertical_121_pass(row_src, stride_i, width, tmp); + + // Pass 2: horizontal 1-2-1 from tmp into dst + horizontal_121_pass(tmp, width, row_dst); + } + } +} + +// ============================================================================ +// Reference implementation (works on all targets) +// ============================================================================ + +/// Reference implementation of Gaussian 3x3 blur +/// +/// Kernel: +/// 1 2 1 +/// 2 4 2 / 16 +/// 1 2 1 +fn gaussian3x3u8_reference(src: &[u8], stride: usize, width: usize, height: usize, dst: &mut [u8]) { + for y in 1..height - 1 { + for x in 1..width - 1 { + // Compute column sums (vertical 1-2-1 weights) + let mut col = [0u32; 3]; + for i in 0..3 { + col[i] = 1 * src[(y - 1) * stride + x - 1 + i] as u32 + + 2 * src[y * stride + x - 1 + i] as u32 + + 1 * src[(y + 1) * stride + x - 1 + i] as u32; + } + // Apply horizontal 1-2-1 weights and normalize + // (1*col[0] + 2*col[1] + 1*col[2] + 8) / 16 + dst[y * stride + x] = ((1 * col[0] + 2 * col[1] + 1 * col[2] + 8) >> 4) as u8; + } + } +} + +/// Generate deterministic test pattern +fn generate_test_pattern(buf: &mut [u8], width: usize, height: usize) { + for y in 0..height { + for x in 0..width { + buf[y * width + x] = ((x + y * 7) % 256) as u8; + } + } +} + +// ============================================================================ +// Main: runs HVX + reference on Hexagon, reference-only on other targets +// ============================================================================ + +#[cfg(target_arch = "hexagon")] +fn main() { + // Aligned buffers for HVX + #[repr(align(128))] + struct AlignedBuf([u8; N]); + + let mut src = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]); + let mut dst_hvx = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]); + let mut tmp = AlignedBuf::<{ WIDTH }>([0u8; WIDTH]); + let mut dst_ref = vec![0u8; WIDTH * HEIGHT]; + + // Generate test pattern + generate_test_pattern(&mut src.0, WIDTH, HEIGHT); + + // Run HVX implementation + unsafe { + hvx::gaussian3x3u8( + src.0.as_ptr(), + WIDTH, + WIDTH, + HEIGHT, + dst_hvx.0.as_mut_ptr(), + tmp.0.as_mut_ptr(), + ); + } + + // Run reference + gaussian3x3u8_reference(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_ref); + + // Verify HVX matches reference (allowing small rounding differences) + let mut max_diff = 0i32; + for y in 1..HEIGHT - 1 { + for x in 1..WIDTH - 1 { + let idx = y * WIDTH + x; + let diff = (dst_hvx.0[idx] as i32 - dst_ref[idx] as i32).abs(); + max_diff = max_diff.max(diff); + // Allow up to 1 LSB difference due to rounding + assert!( + diff <= 1, + "HVX differs from reference at ({}, {}): hvx={}, ref={}, diff={}", + x, + y, + dst_hvx.0[idx], + dst_ref[idx], + diff + ); + } + } + + println!( + "Gaussian 3x3 HVX test passed! Max difference from reference: {}", + max_diff + ); +} + +#[cfg(not(target_arch = "hexagon"))] +fn main() { + let mut src = vec![0u8; WIDTH * HEIGHT]; + let mut dst = vec![0u8; WIDTH * HEIGHT]; + + // Generate test pattern + generate_test_pattern(&mut src, WIDTH, HEIGHT); + + // Run reference implementation + gaussian3x3u8_reference(&src, WIDTH, WIDTH, HEIGHT, &mut dst); + + // Verify output is non-trivial (blurred values differ from input) + let mut changed = 0; + for y in 1..HEIGHT - 1 { + for x in 1..WIDTH - 1 { + let idx = y * WIDTH + x; + if src[idx] != dst[idx] { + changed += 1; + } + } + } + + println!( + "Gaussian 3x3 reference test passed! {} pixels changed by blur", + changed + ); +} diff --git a/stdarch/examples/hex.rs b/stdarch/examples/hex.rs index 621f55bc0951f..21827b375adaf 100644 --- a/stdarch/examples/hex.rs +++ b/stdarch/examples/hex.rs @@ -13,7 +13,6 @@ //! and you should see `746573740a` get printed out. #![allow(internal_features)] -#![feature(wasm_target_feature)] #![cfg_attr(test, feature(test))] #![cfg_attr( any(target_arch = "x86", target_arch = "x86_64"), diff --git a/stdarch/rust-version b/stdarch/rust-version index ccc0b55d4dc55..db9492636f6ac 100644 --- a/stdarch/rust-version +++ b/stdarch/rust-version @@ -1 +1 @@ -873d4682c7d285540b8f28bfe637006cef8918a6 +eda4fc7733ee89e484d7120cafbd80dcb2fce66e diff --git a/test/src/formatters/junit.rs b/test/src/formatters/junit.rs index 74d99e0f1270e..2772222a05c9a 100644 --- a/test/src/formatters/junit.rs +++ b/test/src/formatters/junit.rs @@ -1,5 +1,5 @@ +use std::io; use std::io::prelude::Write; -use std::io::{self}; use std::time::Duration; use super::OutputFormatter; diff --git a/test/src/lib.rs b/test/src/lib.rs index d554807bbde70..f3dbd3d0556ab 100644 --- a/test/src/lib.rs +++ b/test/src/lib.rs @@ -24,7 +24,7 @@ #![feature(staged_api)] #![feature(process_exitcode_internals)] #![feature(panic_can_unwind)] -#![feature(test)] +#![cfg_attr(test, feature(test))] #![feature(thread_spawn_hook)] #![allow(internal_features)] #![warn(rustdoc::unescaped_backticks)] diff --git a/test/src/term.rs b/test/src/term.rs index d9880a776406d..1e4c7bc879cf7 100644 --- a/test/src/term.rs +++ b/test/src/term.rs @@ -12,8 +12,8 @@ #![deny(missing_docs)] +use std::io; use std::io::prelude::*; -use std::io::{self}; pub(crate) use terminfo::TerminfoTerminal; #[cfg(windows)] diff --git a/unwind/src/lib.rs b/unwind/src/lib.rs index cff2aa7b08b93..cce6ca748cccd 100644 --- a/unwind/src/lib.rs +++ b/unwind/src/lib.rs @@ -1,15 +1,14 @@ #![no_std] #![unstable(feature = "panic_unwind", issue = "32837")] #![feature(cfg_emscripten_wasm_eh)] -#![feature(cfg_select)] #![feature(link_cfg)] #![feature(staged_api)] -#![cfg_attr(not(target_env = "msvc"), feature(libc))] #![cfg_attr( all(target_family = "wasm", any(not(target_os = "emscripten"), emscripten_wasm_eh)), - feature(link_llvm_intrinsics, simd_wasm64) + feature(link_llvm_intrinsics, simd_wasm64, asm_experimental_arch) )] #![allow(internal_features)] +#![allow(unused_features)] #![deny(unsafe_op_in_unsafe_fn)] // Force libc to be included even if unused. This is required by many platforms. diff --git a/unwind/src/wasm.rs b/unwind/src/wasm.rs index 2bff306af293f..37d93bdbb67dd 100644 --- a/unwind/src/wasm.rs +++ b/unwind/src/wasm.rs @@ -2,6 +2,30 @@ #![allow(nonstandard_style)] +// Define the __cpp_exception tag that LLVM's wasm exception handling requires. +// In particular it is required to use either of: +// 1. the wasm_throw llvm intrinsic, or +// 2. the Rust try intrinsic. +// +// This must be provided since LLVM commit +// aee99e8015daa9f53ab1fd4e5b24cc4c694bdc4a which changed the tag from being +// weakly defined in each object file to being an external reference that must +// be linked from somewhere. +// +// We only define this for wasm32-unknown-unknown because on Emscripten/WASI +// targets, this symbol should be defined by the external toolchain. In +// particular, defining this on Emscripten would break Emscripten dynamic +// libraries. +#[cfg(all(target_os = "unknown", panic = "unwind"))] +core::arch::global_asm!( + ".globl __cpp_exception", + #[cfg(target_pointer_width = "64")] + ".tagtype __cpp_exception i64", + #[cfg(target_pointer_width = "32")] + ".tagtype __cpp_exception i32", + "__cpp_exception:", +); + #[repr(C)] #[derive(Debug, Copy, Clone, PartialEq)] pub enum _Unwind_Reason_Code { @@ -73,7 +97,7 @@ pub unsafe fn _Unwind_RaiseException(exception: *mut _Unwind_Exception) -> _Unwi // corresponds with llvm::WebAssembly::Tag::CPP_EXCEPTION // in llvm-project/llvm/include/llvm/CodeGen/WasmEHFuncInfo.h const CPP_EXCEPTION_TAG: i32 = 0; - wasm_throw(CPP_EXCEPTION_TAG, exception.cast()) + unsafe { wasm_throw(CPP_EXCEPTION_TAG, exception.cast()) } } _ => { let _ = exception;

{ diff --git a/core/src/mem/maybe_uninit.rs b/core/src/mem/maybe_uninit.rs index 320eb97f83a43..7e2c6b9b3bcb2 100644 --- a/core/src/mem/maybe_uninit.rs +++ b/core/src/mem/maybe_uninit.rs @@ -8,11 +8,11 @@ use crate::{fmt, intrinsics, ptr, slice}; /// /// # Initialization invariant /// -/// The compiler, in general, assumes that a variable is properly initialized +/// The compiler, in general, assumes that a variable is [properly initialized or "valid"][validity] /// according to the requirements of the variable's type. For example, a variable of /// reference type must be aligned and non-null. This is an invariant that must /// *always* be upheld, even in unsafe code. As a consequence, zero-initializing a -/// variable of reference type causes instantaneous [undefined behavior][ub], +/// variable of reference type causes instantaneous undefined behavior, /// no matter whether that reference ever gets used to access memory: /// /// ```rust,no_run @@ -53,6 +53,11 @@ use crate::{fmt, intrinsics, ptr, slice}; /// // The equivalent code with `MaybeUninit`: /// let x: i32 = unsafe { MaybeUninit::uninit().assume_init() }; // undefined behavior! ⚠️ /// ``` +/// +/// Conversely, sometimes it is okay to not initialize *all* bytes of a `MaybeUninit` +/// before calling `assume_init`. For instance, padding bytes do not have to be initialized. +/// See the field-by-field struct initialization example below for a case of that. +/// /// On top of that, remember that most types have additional invariants beyond merely /// being considered initialized at the type level. For example, a `1`-initialized [`Vec`] /// is considered initialized (under the current implementation; this does not constitute @@ -197,7 +202,12 @@ use crate::{fmt, intrinsics, ptr, slice}; /// ); /// ``` /// [`&raw mut`]: https://doc.rust-lang.org/reference/types/pointer.html#r-type.pointer.raw.constructor -/// [ub]: ../../reference/behavior-considered-undefined.html +/// [validity]: ../../reference/behavior-considered-undefined.html#r-undefined.validity +/// +/// Note that we have not initialized the padding, but that's fine -- it does not have to be +/// initialized. In fact, even if we had initialized the padding in `uninit`, those bytes would be +/// lost when copying the result: no matter the contents of the padding bytes in `uninit`, they will +/// always be uninitialized in `foo`. /// /// # Layout /// @@ -657,11 +667,18 @@ impl MaybeUninit { /// # Safety /// /// It is up to the caller to guarantee that the `MaybeUninit` really is in an initialized - /// state. Calling this when the content is not yet fully initialized causes immediate undefined - /// behavior. The [type-level documentation][inv] contains more information about - /// this initialization invariant. + /// state, i.e., a state that is considered ["valid" for type `T`][validity]. Calling this when + /// the content is not yet fully initialized causes immediate undefined behavior. The + /// [type-level documentation][inv] contains more information about this initialization + /// invariant. + /// + /// It is a common mistake to assume that this function is safe to call on integers because they + /// can hold all bit patterns. It is also a common mistake to think that calling this function + /// is UB if any byte is uninitialized. Both of these assumptions are wrong. If that is + /// surprising to you, please read the [type-level documentation][inv]. /// /// [inv]: #initialization-invariant + /// [validity]: ../../reference/behavior-considered-undefined.html#r-undefined.validity /// /// On top of that, remember that most types have additional invariants beyond merely /// being considered initialized at the type level. For example, a `1`-initialized [`Vec`] @@ -689,12 +706,13 @@ impl MaybeUninit { /// *Incorrect* usage of this method: /// /// ```rust,no_run + /// # #![allow(invalid_value)] /// use std::mem::MaybeUninit; /// - /// let x = MaybeUninit::>::uninit(); - /// let x_init = unsafe { x.assume_init() }; - /// // `x` had not been initialized yet, so this last line caused undefined behavior. ⚠️ + /// let x: i32 = unsafe { MaybeUninit::uninit().assume_init() }; // undefined behavior! ⚠️ /// ``` + /// + /// See the [type-level documentation][#examples] for more examples. #[stable(feature = "maybe_uninit", since = "1.36.0")] #[rustc_const_stable(feature = "const_maybe_uninit_assume_init_by_value", since = "1.59.0")] #[inline(always)] @@ -1532,6 +1550,56 @@ impl MaybeUninit<[T; N]> { } } +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl From<[MaybeUninit; N]> for MaybeUninit<[T; N]> { + #[inline] + fn from(arr: [MaybeUninit; N]) -> Self { + arr.transpose() + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsRef<[MaybeUninit; N]> for MaybeUninit<[T; N]> { + #[inline] + fn as_ref(&self) -> &[MaybeUninit; N] { + // SAFETY: T and MaybeUninit have the same layout + unsafe { &*ptr::from_ref(self).cast() } + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsRef<[MaybeUninit]> for MaybeUninit<[T; N]> { + #[inline] + fn as_ref(&self) -> &[MaybeUninit] { + &*AsRef::<[MaybeUninit; N]>::as_ref(self) + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsMut<[MaybeUninit; N]> for MaybeUninit<[T; N]> { + #[inline] + fn as_mut(&mut self) -> &mut [MaybeUninit; N] { + // SAFETY: T and MaybeUninit have the same layout + unsafe { &mut *ptr::from_mut(self).cast() } + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl AsMut<[MaybeUninit]> for MaybeUninit<[T; N]> { + #[inline] + fn as_mut(&mut self) -> &mut [MaybeUninit] { + &mut *AsMut::<[MaybeUninit; N]>::as_mut(self) + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "1.95.0")] +impl From> for [MaybeUninit; N] { + #[inline] + fn from(arr: MaybeUninit<[T; N]>) -> Self { + arr.transpose() + } +} + impl [MaybeUninit; N] { /// Transposes a `[MaybeUninit; N]` into a `MaybeUninit<[T; N]>`. /// diff --git a/core/src/mem/mod.rs b/core/src/mem/mod.rs index 7c486875a8268..a987970c9bcc3 100644 --- a/core/src/mem/mod.rs +++ b/core/src/mem/mod.rs @@ -1,7 +1,32 @@ -//! Basic functions for dealing with memory. +//! Basic functions for dealing with memory, values, and types. //! -//! This module contains functions for querying the size and alignment of -//! types, initializing and manipulating memory. +//! The contents of this module can be seen as belonging to a few families: +//! +//! * [`drop`], [`replace`], [`swap`], and [`take`] +//! are safe functions for moving values in particular ways. +//! They are useful in everyday Rust code. +//! +//! * [`size_of`], [`size_of_val`], [`align_of`], [`align_of_val`], and [`offset_of`] +//! give information about the representation of values in memory. +//! +//! * [`discriminant`] +//! allows comparing the variants of [`enum`] values while ignoring their fields. +//! +//! * [`forget`] and [`ManuallyDrop`] +//! prevent destructors from running, which is used in certain kinds of ownership transfer. +//! [`needs_drop`] +//! tells you whether a type’s destructor even does anything. +//! +//! * [`transmute`], [`transmute_copy`], and [`MaybeUninit`] +//! convert and construct values in [`unsafe`] ways. +//! +//! See also the [`alloc`] and [`ptr`] modules for more primitive operations on memory. +//! +// core::alloc exists but doesn’t contain all the items we want to discuss +//! [`alloc`]: ../../std/alloc/index.html +//! [`enum`]: ../../std/keyword.enum.html +//! [`ptr`]: crate::ptr +//! [`unsafe`]: ../../std/keyword.unsafe.html #![stable(feature = "rust1", since = "1.0.0")] @@ -9,9 +34,12 @@ use crate::alloc::Layout; use crate::clone::TrivialClone; use crate::marker::{Destruct, DiscriminantKind}; use crate::panic::const_assert; -use crate::ptr::Alignment; use crate::{clone, cmp, fmt, hash, intrinsics, ptr}; +mod alignment; +#[unstable(feature = "ptr_alignment_type", issue = "102070")] +pub use alignment::Alignment; + mod manually_drop; #[stable(feature = "manually_drop", since = "1.20.0")] pub use manually_drop::ManuallyDrop; @@ -1260,7 +1288,10 @@ pub trait SizedTypeProperties: Sized { #[doc(hidden)] #[unstable(feature = "ptr_alignment_type", issue = "102070")] - const ALIGNMENT: Alignment = Alignment::of::(); + const ALIGNMENT: Alignment = { + // This can't panic since type alignment is always a power of two. + Alignment::new(Self::ALIGN).unwrap() + }; /// `true` if this type requires no storage. /// `false` if its [size](size_of) is greater than zero. @@ -1485,12 +1516,13 @@ pub macro offset_of($Container:ty, $($fields:expr)+ $(,)?) { /// /// [inhabited]: https://doc.rust-lang.org/reference/glossary.html#inhabited #[unstable(feature = "mem_conjure_zst", issue = "95383")] +#[rustc_const_unstable(feature = "mem_conjure_zst", issue = "95383")] pub const unsafe fn conjure_zst() -> T { const_assert!( size_of::() == 0, - "mem::conjure_zst invoked on a nonzero-sized type", - "mem::conjure_zst invoked on type {t}, which is not zero-sized", - t: &str = stringify!(T) + "mem::conjure_zst invoked on a non-zero-sized type", + "mem::conjure_zst invoked on type {name}, which is not zero-sized", + name: &str = crate::any::type_name::() ); // SAFETY: because the caller must guarantee that it's inhabited and zero-sized, diff --git a/core/src/mem/type_info.rs b/core/src/mem/type_info.rs index 8b30803c97c98..e4d47dedb8606 100644 --- a/core/src/mem/type_info.rs +++ b/core/src/mem/type_info.rs @@ -2,7 +2,9 @@ //! runtime or const-eval processable way. use crate::any::TypeId; -use crate::intrinsics::type_of; +use crate::intrinsics::{type_id, type_of}; +use crate::marker::PointeeSized; +use crate::ptr::DynMetadata; /// Compile-time type information. #[derive(Debug)] @@ -16,6 +18,21 @@ pub struct Type { pub size: Option, } +/// Info of a trait implementation, you can retrieve the vtable with [Self::get_vtable] +#[derive(Debug, PartialEq, Eq)] +#[unstable(feature = "type_info", issue = "146922")] +#[non_exhaustive] +pub struct TraitImpl { + pub(crate) vtable: DynMetadata, +} + +impl TraitImpl { + /// Gets the raw vtable for type reflection mapping + pub const fn get_vtable(&self) -> DynMetadata { + self.vtable + } +} + impl TypeId { /// Compute the type information of a concrete type. /// It can only be called at compile time. @@ -28,11 +45,17 @@ impl TypeId { impl Type { /// Returns the type information of the generic type parameter. + /// + /// Note: Unlike `TypeId`s obtained via `TypeId::of`, the `Type` + /// struct and its fields contain `TypeId`s that are not necessarily + /// derived from types that outlive `'static`. This means that using + /// the `TypeId`s (transitively) obtained from this function will + /// be able to break invariants that other `TypeId` consuming crates + /// may have assumed to hold. #[unstable(feature = "type_info", issue = "146922")] #[rustc_const_unstable(feature = "type_info", issue = "146922")] - // FIXME(reflection): don't require the 'static bound - pub const fn of() -> Self { - const { TypeId::of::().info() } + pub const fn of() -> Self { + const { type_id::().info() } } } @@ -49,6 +72,12 @@ pub enum TypeKind { Slice(Slice), /// Dynamic Traits. DynTrait(DynTrait), + /// Structs. + Struct(Struct), + /// Enums. + Enum(Enum), + /// Unions. + Union(Union), /// Primitive boolean type. Bool(Bool), /// Primitive character type. @@ -63,6 +92,8 @@ pub enum TypeKind { Reference(Reference), /// Pointers. Pointer(Pointer), + /// Function pointers. + FnPtr(FnPtr), /// FIXME(#146922): add all the common types Other, } @@ -81,6 +112,8 @@ pub struct Tuple { #[non_exhaustive] #[unstable(feature = "type_info", issue = "146922")] pub struct Field { + /// The name of the field. + pub name: &'static str, /// The field's type. pub ty: TypeId, /// Offset in bytes from the parent type @@ -137,6 +170,95 @@ pub struct Trait { pub is_auto: bool, } +/// Compile-time type information about structs. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Struct { + /// Instantiated generics of the struct. + pub generics: &'static [Generic], + /// All fields of the struct. + pub fields: &'static [Field], + /// Whether the struct field list is non-exhaustive. + pub non_exhaustive: bool, +} + +/// Compile-time type information about unions. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Union { + /// Instantiated generics of the union. + pub generics: &'static [Generic], + /// All fields of the union. + pub fields: &'static [Field], +} + +/// Compile-time type information about enums. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Enum { + /// Instantiated generics of the enum. + pub generics: &'static [Generic], + /// All variants of the enum. + pub variants: &'static [Variant], + /// Whether the enum variant list is non-exhaustive. + pub non_exhaustive: bool, +} + +/// Compile-time type information about variants of enums. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Variant { + /// The name of the variant. + pub name: &'static str, + /// All fields of the variant. + pub fields: &'static [Field], + /// Whether the enum variant fields is non-exhaustive. + pub non_exhaustive: bool, +} + +/// Compile-time type information about instantiated generics of structs, enum and union variants. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub enum Generic { + /// Lifetimes. + Lifetime(Lifetime), + /// Types. + Type(GenericType), + /// Const parameters. + Const(Const), +} + +/// Compile-time type information about generic lifetimes. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Lifetime { + // No additional information to provide for now. +} + +/// Compile-time type information about instantiated generic types. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct GenericType { + /// The type itself. + pub ty: TypeId, +} + +/// Compile-time type information about generic const parameters. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Const { + /// The const's type. + pub ty: TypeId, +} + /// Compile-time type information about `bool`. #[derive(Debug)] #[non_exhaustive] @@ -202,3 +324,39 @@ pub struct Pointer { /// Whether this pointer is mutable or not. pub mutable: bool, } + +#[derive(Debug)] +#[unstable(feature = "type_info", issue = "146922")] +/// Function pointer, e.g. fn(u8), +pub struct FnPtr { + /// Unsafety, true is unsafe + pub unsafety: bool, + + /// Abi, e.g. extern "C" + pub abi: Abi, + + /// Function inputs + pub inputs: &'static [TypeId], + + /// Function return type, default is TypeId::of::<()> + pub output: TypeId, + + /// Vardiadic function, e.g. extern "C" fn add(n: usize, mut args: ...); + pub variadic: bool, +} + +#[derive(Debug, Default)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +/// Abi of [FnPtr] +pub enum Abi { + /// Named abi, e.g. extern "custom", "stdcall" etc. + Named(&'static str), + + /// Default + #[default] + ExternRust, + + /// C-calling convention + ExternC, +} diff --git a/core/src/net/ip_addr.rs b/core/src/net/ip_addr.rs index a1bfd774710d5..db94f52c4e8d7 100644 --- a/core/src/net/ip_addr.rs +++ b/core/src/net/ip_addr.rs @@ -68,7 +68,8 @@ pub enum IpAddr { /// assert!("0xcb.0x0.0x71.0x00".parse::().is_err()); // all octets are in hex /// ``` #[rustc_diagnostic_item = "Ipv4Addr"] -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Copy)] +#[derive_const(Clone, PartialEq, Eq)] #[stable(feature = "rust1", since = "1.0.0")] pub struct Ipv4Addr { octets: [u8; 4], @@ -161,7 +162,8 @@ impl Hash for Ipv4Addr { /// assert_eq!(localhost.is_loopback(), true); /// ``` #[rustc_diagnostic_item = "Ipv6Addr"] -#[derive(Copy, Clone, PartialEq, Eq)] +#[derive(Copy)] +#[derive_const(Clone, PartialEq, Eq)] #[stable(feature = "rust1", since = "1.0.0")] pub struct Ipv6Addr { octets: [u8; 16], @@ -177,15 +179,17 @@ impl Hash for Ipv6Addr { } } -/// Scope of an [IPv6 multicast address] as defined in [IETF RFC 7346 section 2]. +/// Scope of an [IPv6 multicast address] as defined in [IETF RFC 7346 section 2], +/// which updates [IETF RFC 4291 section 2.7]. /// /// # Stability Guarantees /// -/// Not all possible values for a multicast scope have been assigned. -/// Future RFCs may introduce new scopes, which will be added as variants to this enum; -/// because of this the enum is marked as `#[non_exhaustive]`. +/// Scopes 0 and F are currently reserved by IETF, and may be assigned in the future. +/// For this reason, the enum variants for those two scopes are not currently nameable. +/// You can still check for them in your code using `as` casts. /// /// # Examples +/// /// ``` /// #![feature(ip)] /// @@ -204,32 +208,76 @@ impl Hash for Ipv6Addr { /// Some(SiteLocal) => println!("Site-Local scope"), /// Some(OrganizationLocal) => println!("Organization-Local scope"), /// Some(Global) => println!("Global scope"), -/// Some(_) => println!("Unknown scope"), +/// Some(s) => { +/// let snum = s as u8; +/// if matches!(0x0 | 0xF, snum) { +/// println!("Reserved scope {snum:X}") +/// } else { +/// println!("Unassigned scope {snum:X}") +/// } +/// } /// None => println!("Not a multicast address!") /// } -/// /// ``` /// /// [IPv6 multicast address]: Ipv6Addr /// [IETF RFC 7346 section 2]: https://tools.ietf.org/html/rfc7346#section-2 -#[derive(Copy, PartialEq, Eq, Clone, Hash, Debug)] +/// [IETF RFC 4291 section 2.7]: https://datatracker.ietf.org/doc/html/rfc4291#section-2.7 +#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)] #[unstable(feature = "ip", issue = "27709")] -#[non_exhaustive] pub enum Ipv6MulticastScope { + /// Reserved by IETF. + #[doc(hidden)] + #[unstable( + feature = "ip_multicast_reserved", + reason = "not yet assigned by IETF", + issue = "none" + )] + Reserved0 = 0x0, /// Interface-Local scope. - InterfaceLocal, + InterfaceLocal = 0x1, /// Link-Local scope. - LinkLocal, + LinkLocal = 0x2, /// Realm-Local scope. - RealmLocal, + RealmLocal = 0x3, /// Admin-Local scope. - AdminLocal, + AdminLocal = 0x4, /// Site-Local scope. - SiteLocal, + SiteLocal = 0x5, + + /// Scope 6. Unassigned, available for administrators + /// to define additional multicast regions. + Unassigned6 = 0x6, + /// Scope 7. Unassigned, available for administrators + /// to define additional multicast regions. + Unassigned7 = 0x7, /// Organization-Local scope. - OrganizationLocal, + OrganizationLocal = 0x8, + /// Scope 9. Unassigned, available for administrators + /// to define additional multicast regions. + Unassigned9 = 0x9, + /// Scope A. Unassigned, available for administrators + /// to define additional multicast regions. + UnassignedA = 0xA, + /// Scope B. Unassigned, available for administrators + /// to define additional multicast regions. + UnassignedB = 0xB, + /// Scope C. Unassigned, available for administrators + /// to define additional multicast regions. + UnassignedC = 0xC, + /// Scope D. Unassigned, available for administrators + /// to define additional multicast regions. + UnassignedD = 0xD, /// Global scope. - Global, + Global = 0xE, + /// Reserved by IETF. + #[doc(hidden)] + #[unstable( + feature = "ip_multicast_reserved", + reason = "not yet assigned by IETF", + issue = "none" + )] + ReservedF = 0xF, } impl IpAddr { @@ -1183,7 +1231,8 @@ impl PartialEq for Ipv4Addr { } #[stable(feature = "rust1", since = "1.0.0")] -impl PartialOrd for Ipv4Addr { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const PartialOrd for Ipv4Addr { #[inline] fn partial_cmp(&self, other: &Ipv4Addr) -> Option { Some(self.cmp(other)) @@ -1213,7 +1262,8 @@ impl PartialOrd for Ipv4Addr { } #[stable(feature = "rust1", since = "1.0.0")] -impl Ord for Ipv4Addr { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const Ord for Ipv4Addr { #[inline] fn cmp(&self, other: &Ipv4Addr) -> Ordering { self.octets.cmp(&other.octets) @@ -1848,14 +1898,23 @@ impl Ipv6Addr { pub const fn multicast_scope(&self) -> Option { if self.is_multicast() { match self.segments()[0] & 0x000f { - 1 => Some(Ipv6MulticastScope::InterfaceLocal), - 2 => Some(Ipv6MulticastScope::LinkLocal), - 3 => Some(Ipv6MulticastScope::RealmLocal), - 4 => Some(Ipv6MulticastScope::AdminLocal), - 5 => Some(Ipv6MulticastScope::SiteLocal), - 8 => Some(Ipv6MulticastScope::OrganizationLocal), - 14 => Some(Ipv6MulticastScope::Global), - _ => None, + 0x0 => Some(Ipv6MulticastScope::Reserved0), + 0x1 => Some(Ipv6MulticastScope::InterfaceLocal), + 0x2 => Some(Ipv6MulticastScope::LinkLocal), + 0x3 => Some(Ipv6MulticastScope::RealmLocal), + 0x4 => Some(Ipv6MulticastScope::AdminLocal), + 0x5 => Some(Ipv6MulticastScope::SiteLocal), + 0x6 => Some(Ipv6MulticastScope::Unassigned6), + 0x7 => Some(Ipv6MulticastScope::Unassigned7), + 0x8 => Some(Ipv6MulticastScope::OrganizationLocal), + 0x9 => Some(Ipv6MulticastScope::Unassigned9), + 0xA => Some(Ipv6MulticastScope::UnassignedA), + 0xB => Some(Ipv6MulticastScope::UnassignedB), + 0xC => Some(Ipv6MulticastScope::UnassignedC), + 0xD => Some(Ipv6MulticastScope::UnassignedD), + 0xE => Some(Ipv6MulticastScope::Global), + 0xF => Some(Ipv6MulticastScope::ReservedF), + _ => unreachable!(), } } else { None @@ -2177,7 +2236,8 @@ impl PartialEq for IpAddr { } #[stable(feature = "rust1", since = "1.0.0")] -impl PartialOrd for Ipv6Addr { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const PartialOrd for Ipv6Addr { #[inline] fn partial_cmp(&self, other: &Ipv6Addr) -> Option { Some(self.cmp(other)) @@ -2207,7 +2267,8 @@ impl PartialOrd for Ipv6Addr { } #[stable(feature = "rust1", since = "1.0.0")] -impl Ord for Ipv6Addr { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const Ord for Ipv6Addr { #[inline] fn cmp(&self, other: &Ipv6Addr) -> Ordering { self.segments().cmp(&other.segments()) diff --git a/core/src/num/f128.rs b/core/src/num/f128.rs index 140b955259ab8..d833653fdba65 100644 --- a/core/src/num/f128.rs +++ b/core/src/num/f128.rs @@ -148,7 +148,10 @@ pub mod consts { pub const LN_10: f128 = 2.30258509299404568401799145468436420760110148862877297603333_f128; } -#[doc(test(attr(feature(cfg_target_has_reliable_f16_f128), allow(internal_features))))] +#[doc(test(attr( + feature(cfg_target_has_reliable_f16_f128), + allow(internal_features, unused_features) +)))] impl f128 { /// The radix or base of the internal representation of `f128`. #[unstable(feature = "f128", issue = "116909")] @@ -272,6 +275,70 @@ impl f128 { #[unstable(feature = "f128", issue = "116909")] pub const NEG_INFINITY: f128 = -1.0_f128 / 0.0_f128; + /// Maximum integer that can be represented exactly in an [`f128`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i128`] and [`f128`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f128`] and back to + /// [`i128`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f128`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// [`MAX_EXACT_INTEGER`]: f128::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f128::MIN_EXACT_INTEGER + /// ``` + /// #![feature(f128)] + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// # #[cfg(target_has_reliable_f128)] { + /// let max_exact_int = f128::MAX_EXACT_INTEGER; + /// assert_eq!(max_exact_int, max_exact_int as f128 as i128); + /// assert_eq!(max_exact_int + 1, (max_exact_int + 1) as f128 as i128); + /// assert_ne!(max_exact_int + 2, (max_exact_int + 2) as f128 as i128); + /// + /// // Beyond `f128::MAX_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((max_exact_int + 1) as f128, (max_exact_int + 2) as f128); + /// # }} + /// ``` + // #[unstable(feature = "f128", issue = "116909")] + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MAX_EXACT_INTEGER: i128 = (1 << Self::MANTISSA_DIGITS) - 1; + + /// Minimum integer that can be represented exactly in an [`f128`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i128`] and [`f128`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f128`] and back to + /// [`i128`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f128`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// This constant is equivalent to `-MAX_EXACT_INTEGER`. + /// + /// [`MAX_EXACT_INTEGER`]: f128::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f128::MIN_EXACT_INTEGER + /// ``` + /// #![feature(f128)] + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// # #[cfg(target_has_reliable_f128)] { + /// let min_exact_int = f128::MIN_EXACT_INTEGER; + /// assert_eq!(min_exact_int, min_exact_int as f128 as i128); + /// assert_eq!(min_exact_int - 1, (min_exact_int - 1) as f128 as i128); + /// assert_ne!(min_exact_int - 2, (min_exact_int - 2) as f128 as i128); + /// + /// // Below `f128::MIN_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((min_exact_int - 1) as f128, (min_exact_int - 2) as f128); + /// # }} + /// ``` + // #[unstable(feature = "f128", issue = "116909")] + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MIN_EXACT_INTEGER: i128 = -Self::MAX_EXACT_INTEGER; + /// Sign bit pub(crate) const SIGN_MASK: u128 = 0x8000_0000_0000_0000_0000_0000_0000_0000; @@ -723,7 +790,7 @@ impl f128 { #[rustc_const_unstable(feature = "f128", issue = "116909")] #[must_use = "this returns the result of the comparison, without modifying either input"] pub const fn max(self, other: f128) -> f128 { - intrinsics::maxnumf128(self, other) + intrinsics::maximum_number_nsz_f128(self, other) } /// Returns the minimum of the two numbers, ignoring NaN. @@ -754,7 +821,7 @@ impl f128 { #[rustc_const_unstable(feature = "f128", issue = "116909")] #[must_use = "this returns the result of the comparison, without modifying either input"] pub const fn min(self, other: f128) -> f128 { - intrinsics::minnumf128(self, other) + intrinsics::minimum_number_nsz_f128(self, other) } /// Returns the maximum of the two numbers, propagating NaN. @@ -1342,7 +1409,7 @@ impl f128 { #[rustc_const_unstable(feature = "f128", issue = "116909")] #[must_use = "method returns a new number and does not mutate the original value"] pub const fn abs(self) -> Self { - intrinsics::fabsf128(self) + intrinsics::fabs(self) } /// Returns a number that represents the sign of `self`. @@ -1470,7 +1537,11 @@ impl f128 { // Functions in this module fall into `core_float_math` // #[unstable(feature = "core_float_math", issue = "137578")] #[cfg(not(test))] -#[doc(test(attr(feature(cfg_target_has_reliable_f16_f128), expect(internal_features))))] +#[doc(test(attr( + feature(cfg_target_has_reliable_f16_f128), + expect(internal_features), + allow(unused_features) +)))] impl f128 { /// Returns the largest integer less than or equal to `self`. /// diff --git a/core/src/num/f16.rs b/core/src/num/f16.rs index 463f07da91b28..b0664abcdc739 100644 --- a/core/src/num/f16.rs +++ b/core/src/num/f16.rs @@ -14,7 +14,7 @@ use crate::convert::FloatToInt; use crate::num::FpCategory; #[cfg(not(test))] -use crate::num::libm; +use crate::num::imp::libm; use crate::panic::const_assert; use crate::{intrinsics, mem}; @@ -142,7 +142,10 @@ pub mod consts { pub const LN_10: f16 = 2.30258509299404568401799145468436421_f16; } -#[doc(test(attr(feature(cfg_target_has_reliable_f16_f128), allow(internal_features))))] +#[doc(test(attr( + feature(cfg_target_has_reliable_f16_f128), + allow(internal_features, unused_features) +)))] impl f16 { /// The radix or base of the internal representation of `f16`. #[unstable(feature = "f16", issue = "116909")] @@ -266,6 +269,70 @@ impl f16 { #[unstable(feature = "f16", issue = "116909")] pub const NEG_INFINITY: f16 = -1.0_f16 / 0.0_f16; + /// Maximum integer that can be represented exactly in an [`f16`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i16`] and [`f16`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f16`] and back to + /// [`i16`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f16`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// [`MAX_EXACT_INTEGER`]: f16::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f16::MIN_EXACT_INTEGER + /// ``` + /// #![feature(f16)] + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// # #[cfg(target_has_reliable_f16)] { + /// let max_exact_int = f16::MAX_EXACT_INTEGER; + /// assert_eq!(max_exact_int, max_exact_int as f16 as i16); + /// assert_eq!(max_exact_int + 1, (max_exact_int + 1) as f16 as i16); + /// assert_ne!(max_exact_int + 2, (max_exact_int + 2) as f16 as i16); + /// + /// // Beyond `f16::MAX_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((max_exact_int + 1) as f16, (max_exact_int + 2) as f16); + /// # }} + /// ``` + // #[unstable(feature = "f16", issue = "116909")] + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MAX_EXACT_INTEGER: i16 = (1 << Self::MANTISSA_DIGITS) - 1; + + /// Minimum integer that can be represented exactly in an [`f16`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i16`] and [`f16`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f16`] and back to + /// [`i16`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f16`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// This constant is equivalent to `-MAX_EXACT_INTEGER`. + /// + /// [`MAX_EXACT_INTEGER`]: f16::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f16::MIN_EXACT_INTEGER + /// ``` + /// #![feature(f16)] + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// # #[cfg(target_has_reliable_f16)] { + /// let min_exact_int = f16::MIN_EXACT_INTEGER; + /// assert_eq!(min_exact_int, min_exact_int as f16 as i16); + /// assert_eq!(min_exact_int - 1, (min_exact_int - 1) as f16 as i16); + /// assert_ne!(min_exact_int - 2, (min_exact_int - 2) as f16 as i16); + /// + /// // Below `f16::MIN_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((min_exact_int - 1) as f16, (min_exact_int - 2) as f16); + /// # }} + /// ``` + // #[unstable(feature = "f16", issue = "116909")] + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MIN_EXACT_INTEGER: i16 = -Self::MAX_EXACT_INTEGER; + /// Sign bit pub(crate) const SIGN_MASK: u16 = 0x8000; @@ -717,7 +784,7 @@ impl f16 { #[rustc_const_unstable(feature = "f16", issue = "116909")] #[must_use = "this returns the result of the comparison, without modifying either input"] pub const fn max(self, other: f16) -> f16 { - intrinsics::maxnumf16(self, other) + intrinsics::maximum_number_nsz_f16(self, other) } /// Returns the minimum of the two numbers, ignoring NaN. @@ -748,7 +815,7 @@ impl f16 { #[rustc_const_unstable(feature = "f16", issue = "116909")] #[must_use = "this returns the result of the comparison, without modifying either input"] pub const fn min(self, other: f16) -> f16 { - intrinsics::minnumf16(self, other) + intrinsics::minimum_number_nsz_f16(self, other) } /// Returns the maximum of the two numbers, propagating NaN. @@ -1326,7 +1393,7 @@ impl f16 { #[rustc_const_unstable(feature = "f16", issue = "116909")] #[must_use = "method returns a new number and does not mutate the original value"] pub const fn abs(self) -> Self { - intrinsics::fabsf16(self) + intrinsics::fabs(self) } /// Returns a number that represents the sign of `self`. @@ -1454,7 +1521,11 @@ impl f16 { // Functions in this module fall into `core_float_math` // #[unstable(feature = "core_float_math", issue = "137578")] #[cfg(not(test))] -#[doc(test(attr(feature(cfg_target_has_reliable_f16_f128), expect(internal_features))))] +#[doc(test(attr( + feature(cfg_target_has_reliable_f16_f128), + expect(internal_features), + allow(unused_features) +)))] impl f16 { /// Returns the largest integer less than or equal to `self`. /// diff --git a/core/src/num/f32.rs b/core/src/num/f32.rs index be908cb3894b7..b85bd2b271588 100644 --- a/core/src/num/f32.rs +++ b/core/src/num/f32.rs @@ -393,6 +393,7 @@ pub mod consts { pub const LN_10: f32 = 2.30258509299404568401799145468436421_f32; } +#[doc(test(attr(allow(unused_features))))] impl f32 { /// The radix or base of the internal representation of `f32`. #[stable(feature = "assoc_int_consts", since = "1.43.0")] @@ -513,6 +514,64 @@ impl f32 { #[stable(feature = "assoc_int_consts", since = "1.43.0")] pub const NEG_INFINITY: f32 = -1.0_f32 / 0.0_f32; + /// Maximum integer that can be represented exactly in an [`f32`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i32`] and [`f32`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f32`] and back to + /// [`i32`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f32`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// [`MAX_EXACT_INTEGER`]: f32::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f32::MIN_EXACT_INTEGER + /// ``` + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// let max_exact_int = f32::MAX_EXACT_INTEGER; + /// assert_eq!(max_exact_int, max_exact_int as f32 as i32); + /// assert_eq!(max_exact_int + 1, (max_exact_int + 1) as f32 as i32); + /// assert_ne!(max_exact_int + 2, (max_exact_int + 2) as f32 as i32); + /// + /// // Beyond `f32::MAX_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((max_exact_int + 1) as f32, (max_exact_int + 2) as f32); + /// # } + /// ``` + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MAX_EXACT_INTEGER: i32 = (1 << Self::MANTISSA_DIGITS) - 1; + + /// Minimum integer that can be represented exactly in an [`f32`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i32`] and [`f32`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f32`] and back to + /// [`i32`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f32`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// This constant is equivalent to `-MAX_EXACT_INTEGER`. + /// + /// [`MAX_EXACT_INTEGER`]: f32::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f32::MIN_EXACT_INTEGER + /// ``` + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// let min_exact_int = f32::MIN_EXACT_INTEGER; + /// assert_eq!(min_exact_int, min_exact_int as f32 as i32); + /// assert_eq!(min_exact_int - 1, (min_exact_int - 1) as f32 as i32); + /// assert_ne!(min_exact_int - 2, (min_exact_int - 2) as f32 as i32); + /// + /// // Below `f32::MIN_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((min_exact_int - 1) as f32, (min_exact_int - 2) as f32); + /// # } + /// ``` + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MIN_EXACT_INTEGER: i32 = -Self::MAX_EXACT_INTEGER; + /// Sign bit pub(crate) const SIGN_MASK: u32 = 0x8000_0000; @@ -931,7 +990,7 @@ impl f32 { #[rustc_const_stable(feature = "const_float_methods", since = "1.85.0")] #[inline] pub const fn max(self, other: f32) -> f32 { - intrinsics::maxnumf32(self, other) + intrinsics::maximum_number_nsz_f32(self, other) } /// Returns the minimum of the two numbers, ignoring NaN. @@ -958,7 +1017,7 @@ impl f32 { #[rustc_const_stable(feature = "const_float_methods", since = "1.85.0")] #[inline] pub const fn min(self, other: f32) -> f32 { - intrinsics::minnumf32(self, other) + intrinsics::minimum_number_nsz_f32(self, other) } /// Returns the maximum of the two numbers, propagating NaN. @@ -1509,7 +1568,7 @@ impl f32 { #[rustc_const_stable(feature = "const_float_methods", since = "1.85.0")] #[inline] pub const fn abs(self) -> f32 { - intrinsics::fabsf32(self) + intrinsics::fabs(self) } /// Returns a number that represents the sign of `self`. @@ -1633,7 +1692,7 @@ impl f32 { #[unstable(feature = "core_float_math", issue = "137578")] pub mod math { use crate::intrinsics; - use crate::num::libm; + use crate::num::imp::libm; /// Experimental version of `floor` in `core`. See [`f32::floor`] for details. /// @@ -1821,6 +1880,7 @@ pub mod math { /// # Examples /// /// ``` + /// # #![allow(unused_features)] /// #![feature(core_float_math)] /// /// # // FIXME(#140515): mingw has an incorrect fma diff --git a/core/src/num/f64.rs b/core/src/num/f64.rs index 73b20a50ff8ee..3e7c1e792ace6 100644 --- a/core/src/num/f64.rs +++ b/core/src/num/f64.rs @@ -393,6 +393,7 @@ pub mod consts { pub const LN_10: f64 = 2.30258509299404568401799145468436421_f64; } +#[doc(test(attr(allow(unused_features))))] impl f64 { /// The radix or base of the internal representation of `f64`. #[stable(feature = "assoc_int_consts", since = "1.43.0")] @@ -512,6 +513,64 @@ impl f64 { #[stable(feature = "assoc_int_consts", since = "1.43.0")] pub const NEG_INFINITY: f64 = -1.0_f64 / 0.0_f64; + /// Maximum integer that can be represented exactly in an [`f64`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i64`] and [`f64`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f64`] and back to + /// [`i64`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f64`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// [`MAX_EXACT_INTEGER`]: f64::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f64::MIN_EXACT_INTEGER + /// ``` + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// let max_exact_int = f64::MAX_EXACT_INTEGER; + /// assert_eq!(max_exact_int, max_exact_int as f64 as i64); + /// assert_eq!(max_exact_int + 1, (max_exact_int + 1) as f64 as i64); + /// assert_ne!(max_exact_int + 2, (max_exact_int + 2) as f64 as i64); + /// + /// // Beyond `f64::MAX_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((max_exact_int + 1) as f64, (max_exact_int + 2) as f64); + /// # } + /// ``` + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MAX_EXACT_INTEGER: i64 = (1 << Self::MANTISSA_DIGITS) - 1; + + /// Minimum integer that can be represented exactly in an [`f64`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i64`] and [`f64`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f64`] and back to + /// [`i64`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f64`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// This constant is equivalent to `-MAX_EXACT_INTEGER`. + /// + /// [`MAX_EXACT_INTEGER`]: f64::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f64::MIN_EXACT_INTEGER + /// ``` + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// let min_exact_int = f64::MIN_EXACT_INTEGER; + /// assert_eq!(min_exact_int, min_exact_int as f64 as i64); + /// assert_eq!(min_exact_int - 1, (min_exact_int - 1) as f64 as i64); + /// assert_ne!(min_exact_int - 2, (min_exact_int - 2) as f64 as i64); + /// + /// // Below `f64::MIN_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((min_exact_int - 1) as f64, (min_exact_int - 2) as f64); + /// # } + /// ``` + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MIN_EXACT_INTEGER: i64 = -Self::MAX_EXACT_INTEGER; + /// Sign bit pub(crate) const SIGN_MASK: u64 = 0x8000_0000_0000_0000; @@ -949,7 +1008,7 @@ impl f64 { #[rustc_const_stable(feature = "const_float_methods", since = "1.85.0")] #[inline] pub const fn max(self, other: f64) -> f64 { - intrinsics::maxnumf64(self, other) + intrinsics::maximum_number_nsz_f64(self, other) } /// Returns the minimum of the two numbers, ignoring NaN. @@ -976,7 +1035,7 @@ impl f64 { #[rustc_const_stable(feature = "const_float_methods", since = "1.85.0")] #[inline] pub const fn min(self, other: f64) -> f64 { - intrinsics::minnumf64(self, other) + intrinsics::minimum_number_nsz_f64(self, other) } /// Returns the maximum of the two numbers, propagating NaN. @@ -1507,7 +1566,7 @@ impl f64 { #[rustc_const_stable(feature = "const_float_methods", since = "1.85.0")] #[inline] pub const fn abs(self) -> f64 { - intrinsics::fabsf64(self) + intrinsics::fabs(self) } /// Returns a number that represents the sign of `self`. @@ -1631,7 +1690,7 @@ impl f64 { /// They will be stabilized as inherent methods._ pub mod math { use crate::intrinsics; - use crate::num::libm; + use crate::num::imp::libm; /// Experimental version of `floor` in `core`. See [`f64::floor`] for details. /// @@ -1819,6 +1878,7 @@ pub mod math { /// # Examples /// /// ``` + /// # #![allow(unused_features)] /// #![feature(core_float_math)] /// /// # // FIXME(#140515): mingw has an incorrect fma diff --git a/core/src/num/float_parse.rs b/core/src/num/float_parse.rs new file mode 100644 index 0000000000000..d8846a0cc0a8e --- /dev/null +++ b/core/src/num/float_parse.rs @@ -0,0 +1,133 @@ +//! User-facing API for float parsing. + +use crate::error::Error; +use crate::fmt; +use crate::num::imp::dec2flt; +use crate::str::FromStr; + +macro_rules! from_str_float_impl { + ($t:ty) => { + #[stable(feature = "rust1", since = "1.0.0")] + impl FromStr for $t { + type Err = ParseFloatError; + + /// Converts a string in base 10 to a float. + /// Accepts an optional decimal exponent. + /// + /// This function accepts strings such as + /// + /// * '3.14' + /// * '-3.14' + /// * '2.5E10', or equivalently, '2.5e10' + /// * '2.5E-10' + /// * '5.' + /// * '.5', or, equivalently, '0.5' + /// * '7' + /// * '007' + /// * 'inf', '-inf', '+infinity', 'NaN' + /// + /// Note that alphabetical characters are not case-sensitive. + /// + /// Leading and trailing whitespace represent an error. + /// + /// # Grammar + /// + /// All strings that adhere to the following [EBNF] grammar when + /// lowercased will result in an [`Ok`] being returned: + /// + /// ```txt + /// Float ::= Sign? ( 'inf' | 'infinity' | 'nan' | Number ) + /// Number ::= ( Digit+ | + /// Digit+ '.' Digit* | + /// Digit* '.' Digit+ ) Exp? + /// Exp ::= 'e' Sign? Digit+ + /// Sign ::= [+-] + /// Digit ::= [0-9] + /// ``` + /// + /// [EBNF]: https://www.w3.org/TR/REC-xml/#sec-notation + /// + /// # Arguments + /// + /// * src - A string + /// + /// # Return value + /// + /// `Err(ParseFloatError)` if the string did not represent a valid + /// number. Otherwise, `Ok(n)` where `n` is the closest + /// representable floating-point number to the number represented + /// by `src` (following the same rules for rounding as for the + /// results of primitive operations). + // We add the `#[inline(never)]` attribute, since its content will + // be filled with that of `dec2flt`, which has #[inline(always)]. + // Since `dec2flt` is generic, a normal inline attribute on this function + // with `dec2flt` having no attributes results in heavily repeated + // generation of `dec2flt`, despite the fact only a maximum of 2 + // possible instances can ever exist. Adding #[inline(never)] avoids this. + #[inline(never)] + fn from_str(src: &str) -> Result { + dec2flt::dec2flt(src) + } + } + }; +} + +#[cfg(target_has_reliable_f16)] +from_str_float_impl!(f16); +from_str_float_impl!(f32); +from_str_float_impl!(f64); + +// FIXME(f16): A fallback is used when the backend+target does not support f16 well, in order +// to avoid ICEs. + +#[cfg(not(target_has_reliable_f16))] +#[expect(ineffective_unstable_trait_impl, reason = "stable trait on unstable type")] +#[unstable(feature = "f16", issue = "116909")] +impl FromStr for f16 { + type Err = ParseFloatError; + + #[inline] + fn from_str(_src: &str) -> Result { + unimplemented!("requires target_has_reliable_f16") + } +} + +/// An error which can be returned when parsing a float. +/// +/// This error is used as the error type for the [`FromStr`] implementation +/// for [`f32`] and [`f64`]. +/// +/// # Example +/// +/// ``` +/// use std::str::FromStr; +/// +/// if let Err(e) = f64::from_str("a.12") { +/// println!("Failed conversion to f64: {e}"); +/// } +/// ``` +#[derive(Debug, Clone, PartialEq, Eq)] +#[stable(feature = "rust1", since = "1.0.0")] +pub struct ParseFloatError { + pub(super) kind: FloatErrorKind, +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub(super) enum FloatErrorKind { + Empty, + Invalid, +} + +#[stable(feature = "rust1", since = "1.0.0")] +impl Error for ParseFloatError {} + +#[stable(feature = "rust1", since = "1.0.0")] +impl fmt::Display for ParseFloatError { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self.kind { + FloatErrorKind::Empty => "cannot parse float from empty string", + FloatErrorKind::Invalid => "invalid float literal", + } + .fmt(f) + } +} diff --git a/core/src/num/bignum.rs b/core/src/num/imp/bignum.rs similarity index 98% rename from core/src/num/bignum.rs rename to core/src/num/imp/bignum.rs index 95b49a38ded06..9e930ed15a234 100644 --- a/core/src/num/bignum.rs +++ b/core/src/num/imp/bignum.rs @@ -251,7 +251,7 @@ macro_rules! define_bignum { /// Multiplies itself by `5^e` and returns its own mutable reference. pub fn mul_pow5(&mut self, mut e: usize) -> &mut $name { - use crate::num::bignum::SMALL_POW5; + use crate::num::imp::bignum::SMALL_POW5; // There are exactly n trailing zeros on 2^n, and the only relevant digit sizes // are consecutive powers of two, so this is well suited index for the table. @@ -281,7 +281,7 @@ macro_rules! define_bignum { pub fn mul_digits<'a>(&'a mut self, other: &[$ty]) -> &'a mut $name { // the internal routine. works best when aa.len() <= bb.len(). fn mul_inner(ret: &mut [$ty; $n], aa: &[$ty], bb: &[$ty]) -> usize { - use crate::num::bignum::FullOps; + use crate::num::imp::bignum::FullOps; let mut retsz = 0; for (i, &a) in aa.iter().enumerate() { @@ -320,7 +320,7 @@ macro_rules! define_bignum { /// Divides itself by a digit-sized `other` and returns its own /// mutable reference *and* the remainder. pub fn div_rem_small(&mut self, other: $ty) -> (&mut $name, $ty) { - use crate::num::bignum::FullOps; + use crate::num::imp::bignum::FullOps; assert!(other > 0); diff --git a/core/src/num/dec2flt/common.rs b/core/src/num/imp/dec2flt/common.rs similarity index 100% rename from core/src/num/dec2flt/common.rs rename to core/src/num/imp/dec2flt/common.rs diff --git a/core/src/num/dec2flt/decimal.rs b/core/src/num/imp/dec2flt/decimal.rs similarity index 93% rename from core/src/num/dec2flt/decimal.rs rename to core/src/num/imp/dec2flt/decimal.rs index db7176c124318..c9b0cc531b386 100644 --- a/core/src/num/dec2flt/decimal.rs +++ b/core/src/num/imp/dec2flt/decimal.rs @@ -1,7 +1,9 @@ //! Representation of a float as the significant digits and exponent. -use crate::num::dec2flt::float::RawFloat; -use crate::num::dec2flt::fpu::set_precision; +use dec2flt::Lemire; +use dec2flt::fpu::set_precision; + +use crate::num::imp::dec2flt; const INT_POW10: [u64; 16] = [ 1, @@ -34,7 +36,7 @@ pub struct Decimal { impl Decimal { /// Detect if the float can be accurately reconstructed from native floats. #[inline] - fn can_use_fast_path(&self) -> bool { + fn can_use_fast_path(&self) -> bool { F::MIN_EXPONENT_FAST_PATH <= self.exponent && self.exponent <= F::MAX_EXPONENT_DISGUISED_FAST_PATH && self.mantissa <= F::MAX_MANTISSA_FAST_PATH @@ -51,7 +53,7 @@ impl Decimal { /// /// There is an exception: disguised fast-path cases, where we can shift /// powers-of-10 from the exponent to the significant digits. - pub fn try_fast_path(&self) -> Option { + pub fn try_fast_path(&self) -> Option { // Here we need to work around . // The fast path crucially depends on arithmetic being rounded to the correct number of bits // without any intermediate rounding. On x86 (without SSE or SSE2) this requires the precision diff --git a/core/src/num/dec2flt/decimal_seq.rs b/core/src/num/imp/dec2flt/decimal_seq.rs similarity index 99% rename from core/src/num/dec2flt/decimal_seq.rs rename to core/src/num/imp/dec2flt/decimal_seq.rs index de22280c001c9..0c73cdaa03a0f 100644 --- a/core/src/num/dec2flt/decimal_seq.rs +++ b/core/src/num/imp/dec2flt/decimal_seq.rs @@ -9,7 +9,9 @@ //! algorithm can be found in "ParseNumberF64 by Simple Decimal Conversion", //! available online: . -use crate::num::dec2flt::common::{ByteSlice, is_8digits}; +use dec2flt::common::{ByteSlice, is_8digits}; + +use crate::num::imp::dec2flt; /// A decimal floating-point number, represented as a sequence of decimal digits. #[derive(Clone, Debug, PartialEq)] diff --git a/core/src/num/dec2flt/fpu.rs b/core/src/num/imp/dec2flt/fpu.rs similarity index 100% rename from core/src/num/dec2flt/fpu.rs rename to core/src/num/imp/dec2flt/fpu.rs diff --git a/core/src/num/dec2flt/lemire.rs b/core/src/num/imp/dec2flt/lemire.rs similarity index 96% rename from core/src/num/dec2flt/lemire.rs rename to core/src/num/imp/dec2flt/lemire.rs index f84929a03c172..f89d16c843477 100644 --- a/core/src/num/dec2flt/lemire.rs +++ b/core/src/num/imp/dec2flt/lemire.rs @@ -1,10 +1,9 @@ //! Implementation of the Eisel-Lemire algorithm. -use crate::num::dec2flt::common::BiasedFp; -use crate::num::dec2flt::float::RawFloat; -use crate::num::dec2flt::table::{ - LARGEST_POWER_OF_FIVE, POWER_OF_FIVE_128, SMALLEST_POWER_OF_FIVE, -}; +use dec2flt::common::BiasedFp; +use dec2flt::table::{LARGEST_POWER_OF_FIVE, POWER_OF_FIVE_128, SMALLEST_POWER_OF_FIVE}; + +use crate::num::imp::{Float, dec2flt}; /// Compute w * 10^q using an extended-precision float representation. /// @@ -24,7 +23,7 @@ use crate::num::dec2flt::table::{ /// at a Gigabyte per Second" in section 5, "Fast Algorithm", and /// section 6, "Exact Numbers And Ties", available online: /// . -pub fn compute_float(q: i64, mut w: u64) -> BiasedFp { +pub fn compute_float(q: i64, mut w: u64) -> BiasedFp { let fp_zero = BiasedFp::zero_pow2(0); let fp_inf = BiasedFp::zero_pow2(F::INFINITE_POWER); let fp_error = BiasedFp::zero_pow2(-1); diff --git a/core/src/num/dec2flt/mod.rs b/core/src/num/imp/dec2flt/mod.rs similarity index 61% rename from core/src/num/dec2flt/mod.rs rename to core/src/num/imp/dec2flt/mod.rs index 66e30e1c5f7f1..76b8d416ee0f1 100644 --- a/core/src/num/dec2flt/mod.rs +++ b/core/src/num/imp/dec2flt/mod.rs @@ -87,148 +87,103 @@ issue = "none" )] -use self::common::BiasedFp; -use self::float::RawFloat; -use self::lemire::compute_float; -use self::parse::{parse_inf_nan, parse_number}; -use self::slow::parse_long_mantissa; -use crate::error::Error; -use crate::fmt; -use crate::str::FromStr; +use common::BiasedFp; +use lemire::compute_float; +use parse::{parse_inf_nan, parse_number}; +use slow::parse_long_mantissa; + +use crate::f64; +use crate::num::ParseFloatError; +use crate::num::float_parse::FloatErrorKind; +use crate::num::imp::FloatExt; mod common; pub mod decimal; pub mod decimal_seq; mod fpu; -mod slow; -mod table; -// float is used in flt2dec, and all are used in unit tests. -pub mod float; pub mod lemire; pub mod parse; +mod slow; +mod table; -macro_rules! from_str_float_impl { - ($t:ty) => { - #[stable(feature = "rust1", since = "1.0.0")] - impl FromStr for $t { - type Err = ParseFloatError; - - /// Converts a string in base 10 to a float. - /// Accepts an optional decimal exponent. - /// - /// This function accepts strings such as - /// - /// * '3.14' - /// * '-3.14' - /// * '2.5E10', or equivalently, '2.5e10' - /// * '2.5E-10' - /// * '5.' - /// * '.5', or, equivalently, '0.5' - /// * '7' - /// * '007' - /// * 'inf', '-inf', '+infinity', 'NaN' - /// - /// Note that alphabetical characters are not case-sensitive. - /// - /// Leading and trailing whitespace represent an error. - /// - /// # Grammar - /// - /// All strings that adhere to the following [EBNF] grammar when - /// lowercased will result in an [`Ok`] being returned: - /// - /// ```txt - /// Float ::= Sign? ( 'inf' | 'infinity' | 'nan' | Number ) - /// Number ::= ( Digit+ | - /// Digit+ '.' Digit* | - /// Digit* '.' Digit+ ) Exp? - /// Exp ::= 'e' Sign? Digit+ - /// Sign ::= [+-] - /// Digit ::= [0-9] - /// ``` - /// - /// [EBNF]: https://www.w3.org/TR/REC-xml/#sec-notation - /// - /// # Arguments - /// - /// * src - A string - /// - /// # Return value - /// - /// `Err(ParseFloatError)` if the string did not represent a valid - /// number. Otherwise, `Ok(n)` where `n` is the closest - /// representable floating-point number to the number represented - /// by `src` (following the same rules for rounding as for the - /// results of primitive operations). - // We add the `#[inline(never)]` attribute, since its content will - // be filled with that of `dec2flt`, which has #[inline(always)]. - // Since `dec2flt` is generic, a normal inline attribute on this function - // with `dec2flt` having no attributes results in heavily repeated - // generation of `dec2flt`, despite the fact only a maximum of 2 - // possible instances can ever exist. Adding #[inline(never)] avoids this. - #[inline(never)] - fn from_str(src: &str) -> Result { - dec2flt(src) - } - } +/// Extension to `Float` that are necessary for parsing using the Lemire method. +/// +/// See the parent module's doc comment for why this is necessary. +/// +/// Not intended for use outside of the `dec2flt` module. +#[doc(hidden)] +pub trait Lemire: FloatExt { + /// Maximum exponent for a fast path case, or `⌊(SIG_BITS+1)/log2(5)⌋` + // assuming FLT_EVAL_METHOD = 0 + const MAX_EXPONENT_FAST_PATH: i64 = { + let log2_5 = f64::consts::LOG2_10 - 1.0; + (Self::SIG_TOTAL_BITS as f64 / log2_5) as i64 }; -} -#[cfg(target_has_reliable_f16)] -from_str_float_impl!(f16); -from_str_float_impl!(f32); -from_str_float_impl!(f64); + /// Minimum exponent for a fast path case, or `-⌊(SIG_BITS+1)/log2(5)⌋` + const MIN_EXPONENT_FAST_PATH: i64 = -Self::MAX_EXPONENT_FAST_PATH; + + /// Maximum exponent that can be represented for a disguised-fast path case. + /// This is `MAX_EXPONENT_FAST_PATH + ⌊(SIG_BITS+1)/log2(10)⌋` + const MAX_EXPONENT_DISGUISED_FAST_PATH: i64 = + Self::MAX_EXPONENT_FAST_PATH + (Self::SIG_TOTAL_BITS as f64 / f64::consts::LOG2_10) as i64; + + /// Maximum mantissa for the fast-path (`1 << 53` for f64). + const MAX_MANTISSA_FAST_PATH: u64 = 1 << Self::SIG_TOTAL_BITS; + + /// Gets a small power-of-ten for fast-path multiplication. + fn pow10_fast_path(exponent: usize) -> Self; -// FIXME(f16): A fallback is used when the backend+target does not support f16 well, in order -// to avoid ICEs. + /// Converts integer into float through an as cast. + /// This is only called in the fast-path algorithm, and therefore + /// will not lose precision, since the value will always have + /// only if the value is <= Self::MAX_MANTISSA_FAST_PATH. + fn from_u64(v: u64) -> Self; +} -#[cfg(not(target_has_reliable_f16))] -impl FromStr for f16 { - type Err = ParseFloatError; +#[cfg(target_has_reliable_f16)] +impl Lemire for f16 { + fn pow10_fast_path(exponent: usize) -> Self { + #[allow(clippy::use_self)] + const TABLE: [f16; 8] = [1e0, 1e1, 1e2, 1e3, 1e4, 0.0, 0.0, 0.]; + TABLE[exponent & 7] + } #[inline] - fn from_str(_src: &str) -> Result { - unimplemented!("requires target_has_reliable_f16") + fn from_u64(v: u64) -> Self { + debug_assert!(v <= Self::MAX_MANTISSA_FAST_PATH); + v as _ } } -/// An error which can be returned when parsing a float. -/// -/// This error is used as the error type for the [`FromStr`] implementation -/// for [`f32`] and [`f64`]. -/// -/// # Example -/// -/// ``` -/// use std::str::FromStr; -/// -/// if let Err(e) = f64::from_str("a.12") { -/// println!("Failed conversion to f64: {e}"); -/// } -/// ``` -#[derive(Debug, Clone, PartialEq, Eq)] -#[stable(feature = "rust1", since = "1.0.0")] -pub struct ParseFloatError { - kind: FloatErrorKind, -} +impl Lemire for f32 { + fn pow10_fast_path(exponent: usize) -> Self { + #[allow(clippy::use_self)] + const TABLE: [f32; 16] = + [1e0, 1e1, 1e2, 1e3, 1e4, 1e5, 1e6, 1e7, 1e8, 1e9, 1e10, 0., 0., 0., 0., 0.]; + TABLE[exponent & 15] + } -#[derive(Debug, Clone, PartialEq, Eq)] -enum FloatErrorKind { - Empty, - Invalid, + #[inline] + fn from_u64(v: u64) -> Self { + debug_assert!(v <= Self::MAX_MANTISSA_FAST_PATH); + v as _ + } } -#[stable(feature = "rust1", since = "1.0.0")] -impl Error for ParseFloatError {} +impl Lemire for f64 { + fn pow10_fast_path(exponent: usize) -> Self { + const TABLE: [f64; 32] = [ + 1e0, 1e1, 1e2, 1e3, 1e4, 1e5, 1e6, 1e7, 1e8, 1e9, 1e10, 1e11, 1e12, 1e13, 1e14, 1e15, + 1e16, 1e17, 1e18, 1e19, 1e20, 1e21, 1e22, 0., 0., 0., 0., 0., 0., 0., 0., 0., + ]; + TABLE[exponent & 31] + } -#[stable(feature = "rust1", since = "1.0.0")] -impl fmt::Display for ParseFloatError { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - match self.kind { - FloatErrorKind::Empty => "cannot parse float from empty string", - FloatErrorKind::Invalid => "invalid float literal", - } - .fmt(f) + #[inline] + fn from_u64(v: u64) -> Self { + debug_assert!(v <= Self::MAX_MANTISSA_FAST_PATH); + v as _ } } @@ -245,7 +200,7 @@ pub fn pfe_invalid() -> ParseFloatError { } /// Converts a `BiasedFp` to the closest machine float type. -fn biased_fp_to_float(x: BiasedFp) -> F { +fn biased_fp_to_float(x: BiasedFp) -> F { let mut word = x.m; word |= (x.p_biased as u64) << F::SIG_BITS; F::from_u64_bits(word) @@ -253,7 +208,7 @@ fn biased_fp_to_float(x: BiasedFp) -> F { /// Converts a decimal string into a floating point number. #[inline(always)] // Will be inlined into a function with `#[inline(never)]`, see above -pub fn dec2flt(s: &str) -> Result { +pub fn dec2flt(s: &str) -> Result { let mut s = s.as_bytes(); let Some(&c) = s.first() else { return Err(pfe_empty()) }; let negative = c == b'-'; diff --git a/core/src/num/dec2flt/parse.rs b/core/src/num/imp/dec2flt/parse.rs similarity index 96% rename from core/src/num/dec2flt/parse.rs rename to core/src/num/imp/dec2flt/parse.rs index e38fedc58bec0..ee55eadbc7b9e 100644 --- a/core/src/num/dec2flt/parse.rs +++ b/core/src/num/imp/dec2flt/parse.rs @@ -1,8 +1,9 @@ //! Functions to parse floating-point numbers. -use crate::num::dec2flt::common::{ByteSlice, is_8digits}; -use crate::num::dec2flt::decimal::Decimal; -use crate::num::dec2flt::float::RawFloat; +use dec2flt::common::{ByteSlice, is_8digits}; +use dec2flt::decimal::Decimal; + +use crate::num::imp::{Float, dec2flt}; const MIN_19DIGIT_INT: u64 = 100_0000_0000_0000_0000; @@ -195,7 +196,7 @@ pub fn parse_number(s: &[u8]) -> Option { } /// Try to parse a special, non-finite float. -pub(crate) fn parse_inf_nan(s: &[u8], negative: bool) -> Option { +pub(crate) fn parse_inf_nan(s: &[u8], negative: bool) -> Option { // Since a valid string has at most the length 8, we can load // all relevant characters into a u64 and work from there. // This also generates much better code. diff --git a/core/src/num/dec2flt/slow.rs b/core/src/num/imp/dec2flt/slow.rs similarity index 94% rename from core/src/num/dec2flt/slow.rs rename to core/src/num/imp/dec2flt/slow.rs index 3baed42652393..f1b2525cf38e6 100644 --- a/core/src/num/dec2flt/slow.rs +++ b/core/src/num/imp/dec2flt/slow.rs @@ -1,8 +1,9 @@ //! Slow, fallback algorithm for cases the Eisel-Lemire algorithm cannot round. -use crate::num::dec2flt::common::BiasedFp; -use crate::num::dec2flt::decimal_seq::{DecimalSeq, parse_decimal_seq}; -use crate::num::dec2flt::float::RawFloat; +use dec2flt::common::BiasedFp; +use dec2flt::decimal_seq::{DecimalSeq, parse_decimal_seq}; + +use crate::num::imp::{Float, dec2flt}; /// Parse the significant digits and biased, binary exponent of a float. /// @@ -23,7 +24,7 @@ use crate::num::dec2flt::float::RawFloat; /// /// The algorithms described here are based on "Processing Long Numbers Quickly", /// available here: . -pub(crate) fn parse_long_mantissa(s: &[u8]) -> BiasedFp { +pub(crate) fn parse_long_mantissa(s: &[u8]) -> BiasedFp { const MAX_SHIFT: usize = 60; const NUM_POWERS: usize = 19; const POWERS: [u8; 19] = diff --git a/core/src/num/dec2flt/table.rs b/core/src/num/imp/dec2flt/table.rs similarity index 100% rename from core/src/num/dec2flt/table.rs rename to core/src/num/imp/dec2flt/table.rs diff --git a/core/src/num/diy_float.rs b/core/src/num/imp/diy_float.rs similarity index 100% rename from core/src/num/diy_float.rs rename to core/src/num/imp/diy_float.rs diff --git a/core/src/num/flt2dec/decoder.rs b/core/src/num/imp/flt2dec/decoder.rs similarity index 97% rename from core/src/num/flt2dec/decoder.rs rename to core/src/num/imp/flt2dec/decoder.rs index bd6e2cdbafec8..5ccc91f4c9faf 100644 --- a/core/src/num/flt2dec/decoder.rs +++ b/core/src/num/imp/flt2dec/decoder.rs @@ -1,7 +1,7 @@ //! Decodes a floating-point value into individual parts and error ranges. use crate::num::FpCategory; -use crate::num::dec2flt::float::RawFloat; +use crate::num::imp::FloatExt; /// Decoded unsigned finite value, such that: /// @@ -40,7 +40,7 @@ pub enum FullDecoded { } /// A floating point type which can be `decode`d. -pub trait DecodableFloat: RawFloat + Copy { +pub trait DecodableFloat: FloatExt + Copy { /// The minimum positive normalized value. fn min_pos_norm_value() -> Self; } diff --git a/core/src/num/flt2dec/estimator.rs b/core/src/num/imp/flt2dec/estimator.rs similarity index 100% rename from core/src/num/flt2dec/estimator.rs rename to core/src/num/imp/flt2dec/estimator.rs diff --git a/core/src/num/flt2dec/mod.rs b/core/src/num/imp/flt2dec/mod.rs similarity index 100% rename from core/src/num/flt2dec/mod.rs rename to core/src/num/imp/flt2dec/mod.rs diff --git a/core/src/num/flt2dec/strategy/dragon.rs b/core/src/num/imp/flt2dec/strategy/dragon.rs similarity index 98% rename from core/src/num/flt2dec/strategy/dragon.rs rename to core/src/num/imp/flt2dec/strategy/dragon.rs index dd73e4b4846d5..de19ca6bb664d 100644 --- a/core/src/num/flt2dec/strategy/dragon.rs +++ b/core/src/num/imp/flt2dec/strategy/dragon.rs @@ -4,11 +4,13 @@ //! [^1]: Burger, R. G. and Dybvig, R. K. 1996. Printing floating-point numbers //! quickly and accurately. SIGPLAN Not. 31, 5 (May. 1996), 108-116. +use flt2dec::estimator::estimate_scaling_factor; +use flt2dec::{Decoded, MAX_SIG_DIGITS, round_up}; + use crate::cmp::Ordering; use crate::mem::MaybeUninit; -use crate::num::bignum::{Big32x40 as Big, Digit32 as Digit}; -use crate::num::flt2dec::estimator::estimate_scaling_factor; -use crate::num::flt2dec::{Decoded, MAX_SIG_DIGITS, round_up}; +use crate::num::imp::bignum::{Big32x40 as Big, Digit32 as Digit}; +use crate::num::imp::flt2dec; static POW10: [Digit; 10] = [1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000]; diff --git a/core/src/num/flt2dec/strategy/grisu.rs b/core/src/num/imp/flt2dec/strategy/grisu.rs similarity index 99% rename from core/src/num/flt2dec/strategy/grisu.rs rename to core/src/num/imp/flt2dec/strategy/grisu.rs index d3bbb0934e0ff..f7ee465829340 100644 --- a/core/src/num/flt2dec/strategy/grisu.rs +++ b/core/src/num/imp/flt2dec/strategy/grisu.rs @@ -5,9 +5,11 @@ //! [^1]: Florian Loitsch. 2010. Printing floating-point numbers quickly and //! accurately with integers. SIGPLAN Not. 45, 6 (June 2010), 233-243. +use flt2dec::{Decoded, MAX_SIG_DIGITS, round_up}; + use crate::mem::MaybeUninit; -use crate::num::diy_float::Fp; -use crate::num::flt2dec::{Decoded, MAX_SIG_DIGITS, round_up}; +use crate::num::imp::diy_float::Fp; +use crate::num::imp::flt2dec; // see the comments in `format_shortest_opt` for the rationale. #[doc(hidden)] @@ -455,7 +457,7 @@ pub fn format_shortest<'a>( d: &Decoded, buf: &'a mut [MaybeUninit], ) -> (/*digits*/ &'a [u8], /*exp*/ i16) { - use crate::num::flt2dec::strategy::dragon::format_shortest as fallback; + use flt2dec::strategy::dragon::format_shortest as fallback; // SAFETY: The borrow checker is not smart enough to let us use `buf` // in the second branch, so we launder the lifetime here. But we only re-use // `buf` if `format_shortest_opt` returned `None` so this is okay. @@ -765,7 +767,7 @@ pub fn format_exact<'a>( buf: &'a mut [MaybeUninit], limit: i16, ) -> (/*digits*/ &'a [u8], /*exp*/ i16) { - use crate::num::flt2dec::strategy::dragon::format_exact as fallback; + use flt2dec::strategy::dragon::format_exact as fallback; // SAFETY: The borrow checker is not smart enough to let us use `buf` // in the second branch, so we launder the lifetime here. But we only re-use // `buf` if `format_exact_opt` returned `None` so this is okay. diff --git a/core/src/num/fmt.rs b/core/src/num/imp/fmt.rs similarity index 100% rename from core/src/num/fmt.rs rename to core/src/num/imp/fmt.rs diff --git a/core/src/num/int_bits.rs b/core/src/num/imp/int_bits.rs similarity index 97% rename from core/src/num/int_bits.rs rename to core/src/num/imp/int_bits.rs index 7e54591922358..2bc95e66e7ef6 100644 --- a/core/src/num/int_bits.rs +++ b/core/src/num/imp/int_bits.rs @@ -64,7 +64,7 @@ macro_rules! uint_impl { ($U:ident) => { - pub(super) mod $U { + pub(in crate::num) mod $U { const STAGES: usize = $U::BITS.ilog2() as usize; #[inline] const fn prepare(sparse: $U) -> [$U; STAGES] { @@ -100,7 +100,7 @@ macro_rules! uint_impl { } #[inline(always)] - pub(in super::super) const fn extract_impl(mut x: $U, sparse: $U) -> $U { + pub(in crate::num) const fn extract_impl(mut x: $U, sparse: $U) -> $U { let masks = prepare(sparse); x &= sparse; let mut stage = 0; @@ -131,7 +131,7 @@ macro_rules! uint_impl { x } #[inline(always)] - pub(in super::super) const fn deposit_impl(mut x: $U, sparse: $U) -> $U { + pub(in crate::num) const fn deposit_impl(mut x: $U, sparse: $U) -> $U { let masks = prepare(sparse); let mut stage = STAGES; while stage > 0 { diff --git a/core/src/num/int_log10.rs b/core/src/num/imp/int_log10.rs similarity index 94% rename from core/src/num/int_log10.rs rename to core/src/num/imp/int_log10.rs index af8e1f90968d6..1da029c6a21c4 100644 --- a/core/src/num/int_log10.rs +++ b/core/src/num/imp/int_log10.rs @@ -96,7 +96,7 @@ const fn u128_impl(mut val: u128) -> u32 { macro_rules! define_unsigned_ilog10 { ($($ty:ident => $impl_fn:ident,)*) => {$( #[inline] - pub(super) const fn $ty(val: NonZero<$ty>) -> u32 { + pub(in crate::num) const fn $ty(val: NonZero<$ty>) -> u32 { let result = $impl_fn(val.get()); // SAFETY: Integer logarithm is monotonic non-decreasing, so the computed `result` cannot @@ -117,7 +117,7 @@ define_unsigned_ilog10! { } #[inline] -pub(super) const fn usize(val: NonZero) -> u32 { +pub(in crate::num) const fn usize(val: NonZero) -> u32 { #[cfg(target_pointer_width = "16")] let impl_fn = u16; @@ -136,7 +136,7 @@ macro_rules! define_signed_ilog10 { ($($ty:ident => $impl_fn:ident,)*) => {$( // 0 < val <= $ty::MAX #[inline] - pub(super) const fn $ty(val: $ty) -> Option { + pub(in crate::num) const fn $ty(val: $ty) -> Option { if val > 0 { let result = $impl_fn(val.cast_unsigned()); @@ -166,6 +166,6 @@ define_signed_ilog10! { /// on every single primitive type. #[cold] #[track_caller] -pub(super) const fn panic_for_nonpositive_argument() -> ! { +pub(in crate::num) const fn panic_for_nonpositive_argument() -> ! { panic!("argument of integer logarithm must be positive") } diff --git a/core/src/num/int_sqrt.rs b/core/src/num/imp/int_sqrt.rs similarity index 97% rename from core/src/num/int_sqrt.rs rename to core/src/num/imp/int_sqrt.rs index c7a322c08c139..152841793d56e 100644 --- a/core/src/num/int_sqrt.rs +++ b/core/src/num/imp/int_sqrt.rs @@ -37,7 +37,7 @@ const U8_ISQRT_WITH_REMAINDER: [(u8, u8); 256] = { #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline] -pub(super) const fn u8(n: u8) -> u8 { +pub(in crate::num) const fn u8(n: u8) -> u8 { U8_ISQRT_WITH_REMAINDER[n as usize].0 } @@ -58,7 +58,7 @@ macro_rules! signed_fn { #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline] - pub(super) const unsafe fn $SignedT(n: $SignedT) -> $SignedT { + pub(in crate::num) const unsafe fn $SignedT(n: $SignedT) -> $SignedT { debug_assert!(n >= 0, "Negative input inside `isqrt`."); $UnsignedT(n as $UnsignedT) as $SignedT } @@ -83,7 +83,7 @@ macro_rules! unsigned_fn { #[must_use = "this returns the result of the operation, \ without modifying the original"] #[inline] - pub(super) const fn $UnsignedT(mut n: $UnsignedT) -> $UnsignedT { + pub(in crate::num) const fn $UnsignedT(mut n: $UnsignedT) -> $UnsignedT { if n <= <$HalfBitsT>::MAX as $UnsignedT { $HalfBitsT(n as $HalfBitsT) as $UnsignedT } else { @@ -311,6 +311,6 @@ unsigned_fn!(u128, u64, u128_stages); /// on every single primitive type. #[cold] #[track_caller] -pub(super) const fn panic_for_negative_argument() -> ! { +pub(in crate::num) const fn panic_for_negative_argument() -> ! { panic!("argument of integer square root cannot be negative") } diff --git a/core/src/num/libm.rs b/core/src/num/imp/libm.rs similarity index 100% rename from core/src/num/libm.rs rename to core/src/num/imp/libm.rs diff --git a/core/src/num/imp/mod.rs b/core/src/num/imp/mod.rs new file mode 100644 index 0000000000000..6fccfd1c238ed --- /dev/null +++ b/core/src/num/imp/mod.rs @@ -0,0 +1,21 @@ +//! Numeric routines, separate from API. + +// These modules are public only for testing. +#[cfg(not(no_fp_fmt_parse))] +pub mod bignum; +#[cfg(not(no_fp_fmt_parse))] +pub mod dec2flt; +#[cfg(not(no_fp_fmt_parse))] +pub mod diy_float; +#[cfg(not(no_fp_fmt_parse))] +pub mod flt2dec; +pub mod fmt; + +pub(crate) mod int_bits; +pub(crate) mod int_log10; +pub(crate) mod int_sqrt; +pub(crate) mod libm; +pub(crate) mod overflow_panic; +mod traits; + +pub use traits::{Float, FloatExt, Int}; diff --git a/core/src/num/overflow_panic.rs b/core/src/num/imp/overflow_panic.rs similarity index 68% rename from core/src/num/overflow_panic.rs rename to core/src/num/imp/overflow_panic.rs index e30573dd3f392..a9b91daba954b 100644 --- a/core/src/num/overflow_panic.rs +++ b/core/src/num/imp/overflow_panic.rs @@ -4,48 +4,48 @@ #[cold] #[track_caller] -pub(super) const fn add() -> ! { +pub(in crate::num) const fn add() -> ! { panic!("attempt to add with overflow") } #[cold] #[track_caller] -pub(super) const fn sub() -> ! { +pub(in crate::num) const fn sub() -> ! { panic!("attempt to subtract with overflow") } #[cold] #[track_caller] -pub(super) const fn mul() -> ! { +pub(in crate::num) const fn mul() -> ! { panic!("attempt to multiply with overflow") } #[cold] #[track_caller] -pub(super) const fn div() -> ! { +pub(in crate::num) const fn div() -> ! { panic!("attempt to divide with overflow") } #[cold] #[track_caller] -pub(super) const fn rem() -> ! { +pub(in crate::num) const fn rem() -> ! { panic!("attempt to calculate the remainder with overflow") } #[cold] #[track_caller] -pub(super) const fn neg() -> ! { +pub(in crate::num) const fn neg() -> ! { panic!("attempt to negate with overflow") } #[cold] #[track_caller] -pub(super) const fn shr() -> ! { +pub(in crate::num) const fn shr() -> ! { panic!("attempt to shift right with overflow") } #[cold] #[track_caller] -pub(super) const fn shl() -> ! { +pub(in crate::num) const fn shl() -> ! { panic!("attempt to shift left with overflow") } diff --git a/core/src/num/dec2flt/float.rs b/core/src/num/imp/traits.rs similarity index 72% rename from core/src/num/dec2flt/float.rs rename to core/src/num/imp/traits.rs index 21aabdc8addb4..7b84f7a4a5aa2 100644 --- a/core/src/num/dec2flt/float.rs +++ b/core/src/num/imp/traits.rs @@ -1,10 +1,14 @@ -//! Helper trait for generic float types. +//! Numeric traits used for internal implementations. -use core::f64; +#![doc(hidden)] +#![unstable( + feature = "num_internals", + reason = "internal routines only exposed for testing", + issue = "none" +)] -use crate::fmt::{Debug, LowerExp}; use crate::num::FpCategory; -use crate::ops::{self, Add, Div, Mul, Neg}; +use crate::{f64, fmt, ops}; /// Lossy `as` casting between two types. pub trait CastInto: Copy { @@ -12,11 +16,11 @@ pub trait CastInto: Copy { } /// Collection of traits that allow us to be generic over integer size. -pub trait Integer: +pub trait Int: Sized + Clone + Copy - + Debug + + fmt::Debug + ops::Shr + ops::Shl + ops::BitAnd @@ -37,7 +41,7 @@ macro_rules! int { } } - impl Integer for $ty { + impl Int for $ty { const ZERO: Self = 0; const ONE: Self = 1; } @@ -48,27 +52,22 @@ macro_rules! int { int!(u16, u32, u64); /// A helper trait to avoid duplicating basically all the conversion code for IEEE floats. -/// -/// See the parent module's doc comment for why this is necessary. -/// -/// Should **never ever** be implemented for other types or be used outside the `dec2flt` module. #[doc(hidden)] -pub trait RawFloat: +pub trait Float: Sized - + Div - + Neg - + Mul - + Add - + LowerExp + + ops::Div + + ops::Neg + + ops::Mul + + ops::Add + + fmt::Debug + PartialEq + PartialOrd + Default + Clone + Copy - + Debug { /// The unsigned integer with the same size as the float - type Int: Integer + Into; + type Int: Int + Into; /* general constants */ @@ -128,8 +127,6 @@ pub trait RawFloat: const MIN_EXPONENT_ROUND_TO_EVEN: i32; const MAX_EXPONENT_ROUND_TO_EVEN: i32; - /* limits related to Fast pathing */ - /// Largest decimal exponent for a non-infinite value. /// /// This is the max exponent in binary converted to the max exponent in decimal. Allows fast @@ -151,41 +148,19 @@ pub trait RawFloat: /// compile time since intermediates exceed the range of an `f64`. const SMALLEST_POWER_OF_TEN: i32; - /// Maximum exponent for a fast path case, or `⌊(SIG_BITS+1)/log2(5)⌋` - // assuming FLT_EVAL_METHOD = 0 - const MAX_EXPONENT_FAST_PATH: i64 = { - let log2_5 = f64::consts::LOG2_10 - 1.0; - (Self::SIG_TOTAL_BITS as f64 / log2_5) as i64 - }; - - /// Minimum exponent for a fast path case, or `-⌊(SIG_BITS+1)/log2(5)⌋` - const MIN_EXPONENT_FAST_PATH: i64 = -Self::MAX_EXPONENT_FAST_PATH; - - /// Maximum exponent that can be represented for a disguised-fast path case. - /// This is `MAX_EXPONENT_FAST_PATH + ⌊(SIG_BITS+1)/log2(10)⌋` - const MAX_EXPONENT_DISGUISED_FAST_PATH: i64 = - Self::MAX_EXPONENT_FAST_PATH + (Self::SIG_TOTAL_BITS as f64 / f64::consts::LOG2_10) as i64; - - /// Maximum mantissa for the fast-path (`1 << 53` for f64). - const MAX_MANTISSA_FAST_PATH: u64 = 1 << Self::SIG_TOTAL_BITS; - - /// Converts integer into float through an as cast. - /// This is only called in the fast-path algorithm, and therefore - /// will not lose precision, since the value will always have - /// only if the value is <= Self::MAX_MANTISSA_FAST_PATH. - fn from_u64(v: u64) -> Self; - - /// Performs a raw transmutation from an integer. - fn from_u64_bits(v: u64) -> Self; - - /// Gets a small power-of-ten for fast-path multiplication. - fn pow10_fast_path(exponent: usize) -> Self; - /// Returns the category that this number falls into. fn classify(self) -> FpCategory; /// Transmute to the integer representation fn to_bits(self) -> Self::Int; +} + +/// Items that ideally would be on `Float`, but don't apply to all float types because they +/// rely on the mantissa fitting into a `u64` (which isn't true for `f128`). +#[doc(hidden)] +pub trait FloatExt: Float { + /// Performs a raw transmutation from an integer. + fn from_u64_bits(v: u64) -> Self; /// Returns the mantissa, exponent and sign as integers. /// @@ -219,7 +194,7 @@ const fn pow2_to_pow10(a: i64) -> i64 { } #[cfg(target_has_reliable_f16)] -impl RawFloat for f16 { +impl Float for f16 { type Int = u16; const INFINITY: Self = Self::INFINITY; @@ -236,23 +211,6 @@ impl RawFloat for f16 { const MAX_EXPONENT_ROUND_TO_EVEN: i32 = 5; const SMALLEST_POWER_OF_TEN: i32 = -27; - #[inline] - fn from_u64(v: u64) -> Self { - debug_assert!(v <= Self::MAX_MANTISSA_FAST_PATH); - v as _ - } - - #[inline] - fn from_u64_bits(v: u64) -> Self { - Self::from_bits((v & 0xFFFF) as u16) - } - - fn pow10_fast_path(exponent: usize) -> Self { - #[allow(clippy::use_self)] - const TABLE: [f16; 8] = [1e0, 1e1, 1e2, 1e3, 1e4, 0.0, 0.0, 0.]; - TABLE[exponent & 7] - } - fn to_bits(self) -> Self::Int { self.to_bits() } @@ -262,7 +220,15 @@ impl RawFloat for f16 { } } -impl RawFloat for f32 { +#[cfg(target_has_reliable_f16)] +impl FloatExt for f16 { + #[inline] + fn from_u64_bits(v: u64) -> Self { + Self::from_bits((v & 0xFFFF) as u16) + } +} + +impl Float for f32 { type Int = u32; const INFINITY: Self = f32::INFINITY; @@ -279,24 +245,6 @@ impl RawFloat for f32 { const MAX_EXPONENT_ROUND_TO_EVEN: i32 = 10; const SMALLEST_POWER_OF_TEN: i32 = -65; - #[inline] - fn from_u64(v: u64) -> Self { - debug_assert!(v <= Self::MAX_MANTISSA_FAST_PATH); - v as _ - } - - #[inline] - fn from_u64_bits(v: u64) -> Self { - f32::from_bits((v & 0xFFFFFFFF) as u32) - } - - fn pow10_fast_path(exponent: usize) -> Self { - #[allow(clippy::use_self)] - const TABLE: [f32; 16] = - [1e0, 1e1, 1e2, 1e3, 1e4, 1e5, 1e6, 1e7, 1e8, 1e9, 1e10, 0., 0., 0., 0., 0.]; - TABLE[exponent & 15] - } - fn to_bits(self) -> Self::Int { self.to_bits() } @@ -306,7 +254,14 @@ impl RawFloat for f32 { } } -impl RawFloat for f64 { +impl FloatExt for f32 { + #[inline] + fn from_u64_bits(v: u64) -> Self { + f32::from_bits((v & 0xFFFFFFFF) as u32) + } +} + +impl Float for f64 { type Int = u64; const INFINITY: Self = Self::INFINITY; @@ -323,25 +278,6 @@ impl RawFloat for f64 { const MAX_EXPONENT_ROUND_TO_EVEN: i32 = 23; const SMALLEST_POWER_OF_TEN: i32 = -342; - #[inline] - fn from_u64(v: u64) -> Self { - debug_assert!(v <= Self::MAX_MANTISSA_FAST_PATH); - v as _ - } - - #[inline] - fn from_u64_bits(v: u64) -> Self { - f64::from_bits(v) - } - - fn pow10_fast_path(exponent: usize) -> Self { - const TABLE: [f64; 32] = [ - 1e0, 1e1, 1e2, 1e3, 1e4, 1e5, 1e6, 1e7, 1e8, 1e9, 1e10, 1e11, 1e12, 1e13, 1e14, 1e15, - 1e16, 1e17, 1e18, 1e19, 1e20, 1e21, 1e22, 0., 0., 0., 0., 0., 0., 0., 0., 0., - ]; - TABLE[exponent & 31] - } - fn to_bits(self) -> Self::Int { self.to_bits() } @@ -350,3 +286,10 @@ impl RawFloat for f64 { self.classify() } } + +impl FloatExt for f64 { + #[inline] + fn from_u64_bits(v: u64) -> Self { + f64::from_bits(v) + } +} diff --git a/core/src/num/int_macros.rs b/core/src/num/int_macros.rs index b21865a9ae546..aba0eaf8d4842 100644 --- a/core/src/num/int_macros.rs +++ b/core/src/num/int_macros.rs @@ -553,7 +553,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_add(self, rhs: Self) -> Self { let (a, b) = self.overflowing_add(rhs); - if b { overflow_panic::add() } else { a } + if b { imp::overflow_panic::add() } else { a } } /// Unchecked integer addition. Computes `self + rhs`, assuming overflow @@ -643,7 +643,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_add_unsigned(self, rhs: $UnsignedT) -> Self { let (a, b) = self.overflowing_add_unsigned(rhs); - if b { overflow_panic::add() } else { a } + if b { imp::overflow_panic::add() } else { a } } /// Checked integer subtraction. Computes `self - rhs`, returning `None` if @@ -693,7 +693,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_sub(self, rhs: Self) -> Self { let (a, b) = self.overflowing_sub(rhs); - if b { overflow_panic::sub() } else { a } + if b { imp::overflow_panic::sub() } else { a } } /// Unchecked integer subtraction. Computes `self - rhs`, assuming overflow @@ -783,7 +783,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_sub_unsigned(self, rhs: $UnsignedT) -> Self { let (a, b) = self.overflowing_sub_unsigned(rhs); - if b { overflow_panic::sub() } else { a } + if b { imp::overflow_panic::sub() } else { a } } /// Checked integer multiplication. Computes `self * rhs`, returning `None` if @@ -833,7 +833,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_mul(self, rhs: Self) -> Self { let (a, b) = self.overflowing_mul(rhs); - if b { overflow_panic::mul() } else { a } + if b { imp::overflow_panic::mul() } else { a } } /// Unchecked integer multiplication. Computes `self * rhs`, assuming overflow @@ -940,7 +940,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_div(self, rhs: Self) -> Self { let (a, b) = self.overflowing_div(rhs); - if b { overflow_panic::div() } else { a } + if b { imp::overflow_panic::div() } else { a } } /// Checked Euclidean division. Computes `self.div_euclid(rhs)`, @@ -1007,7 +1007,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_div_euclid(self, rhs: Self) -> Self { let (a, b) = self.overflowing_div_euclid(rhs); - if b { overflow_panic::div() } else { a } + if b { imp::overflow_panic::div() } else { a } } /// Checked integer division without remainder. Computes `self / rhs`, @@ -1179,7 +1179,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_rem(self, rhs: Self) -> Self { let (a, b) = self.overflowing_rem(rhs); - if b { overflow_panic::rem() } else { a } + if b { imp::overflow_panic::rem() } else { a } } /// Checked Euclidean remainder. Computes `self.rem_euclid(rhs)`, returning `None` @@ -1245,7 +1245,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_rem_euclid(self, rhs: Self) -> Self { let (a, b) = self.overflowing_rem_euclid(rhs); - if b { overflow_panic::rem() } else { a } + if b { imp::overflow_panic::rem() } else { a } } /// Checked negation. Computes `-self`, returning `None` if `self == MIN`. @@ -1323,7 +1323,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_neg(self) -> Self { let (a, b) = self.overflowing_neg(); - if b { overflow_panic::neg() } else { a } + if b { imp::overflow_panic::neg() } else { a } } /// Checked shift left. Computes `self << rhs`, returning `None` if `rhs` is larger @@ -1379,7 +1379,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_shl(self, rhs: u32) -> Self { let (a, b) = self.overflowing_shl(rhs); - if b { overflow_panic::shl() } else { a } + if b { imp::overflow_panic::shl() } else { a } } /// Unchecked shift left. Computes `self << rhs`, assuming that @@ -1558,7 +1558,7 @@ macro_rules! int_impl { #[track_caller] pub const fn strict_shr(self, rhs: u32) -> Self { let (a, b) = self.overflowing_shr(rhs); - if b { overflow_panic::shr() } else { a } + if b { imp::overflow_panic::shr() } else { a } } /// Unchecked shift right. Computes `self >> rhs`, assuming that @@ -1847,7 +1847,7 @@ macro_rules! int_impl { } else { // SAFETY: Input is nonnegative in this `else` branch. let result = unsafe { - crate::num::int_sqrt::$ActualT(self as $ActualT) as $SelfT + imp::int_sqrt::$ActualT(self as $ActualT) as $SelfT }; // Inform the optimizer what the range of outputs is. If @@ -1864,7 +1864,7 @@ macro_rules! int_impl { unsafe { // SAFETY: `<$ActualT>::MAX` is nonnegative. const MAX_RESULT: $SelfT = unsafe { - crate::num::int_sqrt::$ActualT(<$ActualT>::MAX) as $SelfT + imp::int_sqrt::$ActualT(<$ActualT>::MAX) as $SelfT }; crate::hint::assert_unchecked(result >= 0); @@ -2481,7 +2481,8 @@ macro_rules! int_impl { /// /// Returns a tuple of the addition along with a boolean indicating /// whether an arithmetic overflow would occur. If an overflow would have - /// occurred then the wrapped value is returned. + /// occurred then the wrapped value is returned (negative if overflowed + /// above [`MAX`](Self::MAX), non-negative if below [`MIN`](Self::MIN)). /// /// # Examples /// @@ -2516,6 +2517,9 @@ macro_rules! int_impl { /// The output boolean returned by this method is *not* a carry flag, /// and should *not* be added to a more significant word. /// + /// If overflow occurred, the wrapped value is returned (negative if overflowed + /// above [`MAX`](Self::MAX), non-negative if below [`MIN`](Self::MIN)). + /// /// If the input carry is false, this method is equivalent to /// [`overflowing_add`](Self::overflowing_add). /// @@ -2583,7 +2587,8 @@ macro_rules! int_impl { /// Calculates `self` - `rhs`. /// /// Returns a tuple of the subtraction along with a boolean indicating whether an arithmetic overflow - /// would occur. If an overflow would have occurred then the wrapped value is returned. + /// would occur. If an overflow would have occurred then the wrapped value is returned + /// (negative if overflowed above [`MAX`](Self::MAX), non-negative if below [`MIN`](Self::MIN)). /// /// # Examples /// @@ -2619,6 +2624,9 @@ macro_rules! int_impl { /// The output boolean returned by this method is *not* a borrow flag, /// and should *not* be subtracted from a more significant word. /// + /// If overflow occurred, the wrapped value is returned (negative if overflowed + /// above [`MAX`](Self::MAX), non-negative if below [`MIN`](Self::MIN)). + /// /// If the input borrow is false, this method is equivalent to /// [`overflowing_sub`](Self::overflowing_sub). /// @@ -3134,7 +3142,7 @@ macro_rules! int_impl { pub const fn isqrt(self) -> Self { match self.checked_isqrt() { Some(sqrt) => sqrt, - None => crate::num::int_sqrt::panic_for_negative_argument(), + None => imp::int_sqrt::panic_for_negative_argument(), } } @@ -3440,7 +3448,7 @@ macro_rules! int_impl { if let Some(log) = self.checked_ilog(base) { log } else { - int_log10::panic_for_nonpositive_argument() + imp::int_log10::panic_for_nonpositive_argument() } } @@ -3465,7 +3473,7 @@ macro_rules! int_impl { if let Some(log) = self.checked_ilog2() { log } else { - int_log10::panic_for_nonpositive_argument() + imp::int_log10::panic_for_nonpositive_argument() } } @@ -3490,7 +3498,7 @@ macro_rules! int_impl { if let Some(log) = self.checked_ilog10() { log } else { - int_log10::panic_for_nonpositive_argument() + imp::int_log10::panic_for_nonpositive_argument() } } @@ -3562,7 +3570,7 @@ macro_rules! int_impl { without modifying the original"] #[inline] pub const fn checked_ilog10(self) -> Option { - int_log10::$ActualT(self as $ActualT) + imp::int_log10::$ActualT(self as $ActualT) } /// Computes the absolute value of `self`. diff --git a/core/src/num/mod.rs b/core/src/num/mod.rs index 558426c94e5dc..333e44649d8f6 100644 --- a/core/src/num/mod.rs +++ b/core/src/num/mod.rs @@ -27,16 +27,14 @@ macro_rules! sign_dependent_expr { }; } -// All these modules are technically private and only exposed for coretests: -#[cfg(not(no_fp_fmt_parse))] -pub mod bignum; -#[cfg(not(no_fp_fmt_parse))] -pub mod dec2flt; -#[cfg(not(no_fp_fmt_parse))] -pub mod diy_float; -#[cfg(not(no_fp_fmt_parse))] -pub mod flt2dec; -pub mod fmt; +// These modules are public only for testing. +#[doc(hidden)] +#[unstable( + feature = "num_internals", + reason = "internal routines only exposed for testing", + issue = "none" +)] +pub mod imp; #[macro_use] mod int_macros; // import int_impl! @@ -44,12 +42,9 @@ mod int_macros; // import int_impl! mod uint_macros; // import uint_impl! mod error; -mod int_bits; -mod int_log10; -mod int_sqrt; -pub(crate) mod libm; +#[cfg(not(no_fp_fmt_parse))] +mod float_parse; mod nonzero; -mod overflow_panic; mod saturating; mod wrapping; @@ -57,15 +52,15 @@ mod wrapping; #[doc(hidden)] pub mod niche_types; -#[stable(feature = "rust1", since = "1.0.0")] -#[cfg(not(no_fp_fmt_parse))] -pub use dec2flt::ParseFloatError; #[stable(feature = "int_error_matching", since = "1.55.0")] pub use error::IntErrorKind; #[stable(feature = "rust1", since = "1.0.0")] pub use error::ParseIntError; #[stable(feature = "try_from", since = "1.34.0")] pub use error::TryFromIntError; +#[stable(feature = "rust1", since = "1.0.0")] +#[cfg(not(no_fp_fmt_parse))] +pub use float_parse::ParseFloatError; #[stable(feature = "generic_nonzero", since = "1.79.0")] pub use nonzero::NonZero; #[unstable( @@ -244,6 +239,104 @@ macro_rules! midpoint_impl { }; } +macro_rules! widening_carryless_mul_impl { + ($SelfT:ty, $WideT:ty) => { + /// Performs a widening carry-less multiplication. + /// + /// # Examples + /// + /// ``` + /// #![feature(uint_carryless_mul)] + /// + #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX.widening_carryless_mul(", + stringify!($SelfT), "::MAX), ", stringify!($WideT), "::MAX / 3);")] + /// ``` + #[rustc_const_unstable(feature = "uint_carryless_mul", issue = "152080")] + #[doc(alias = "clmul")] + #[unstable(feature = "uint_carryless_mul", issue = "152080")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline] + pub const fn widening_carryless_mul(self, rhs: $SelfT) -> $WideT { + (self as $WideT).carryless_mul(rhs as $WideT) + } + } +} + +macro_rules! carrying_carryless_mul_impl { + (u128, u256) => { + carrying_carryless_mul_impl! { @internal u128 => + pub const fn carrying_carryless_mul(self, rhs: Self, carry: Self) -> (Self, Self) { + let x0 = self as u64; + let x1 = (self >> 64) as u64; + let y0 = rhs as u64; + let y1 = (rhs >> 64) as u64; + + let z0 = u64::widening_carryless_mul(x0, y0); + let z2 = u64::widening_carryless_mul(x1, y1); + + // The grade school algorithm would compute: + // z1 = x0y1 ^ x1y0 + + // Instead, Karatsuba first computes: + let z3 = u64::widening_carryless_mul(x0 ^ x1, y0 ^ y1); + // Since it distributes over XOR, + // z3 == x0y0 ^ x0y1 ^ x1y0 ^ x1y1 + // |--| |---------| |--| + // == z0 ^ z1 ^ z2 + // so we can compute z1 as + let z1 = z3 ^ z0 ^ z2; + + let lo = z0 ^ (z1 << 64); + let hi = z2 ^ (z1 >> 64); + + (lo ^ carry, hi) + } + } + }; + ($SelfT:ty, $WideT:ty) => { + carrying_carryless_mul_impl! { @internal $SelfT => + pub const fn carrying_carryless_mul(self, rhs: Self, carry: Self) -> (Self, Self) { + // Can't use widening_carryless_mul because it's not implemented for usize. + let p = (self as $WideT).carryless_mul(rhs as $WideT); + + let lo = (p as $SelfT); + let hi = (p >> Self::BITS) as $SelfT; + + (lo ^ carry, hi) + } + } + }; + (@internal $SelfT:ty => $($fn:tt)*) => { + /// Calculates the "full carryless multiplication" without the possibility to overflow. + /// + /// This returns the low-order (wrapping) bits and the high-order (overflow) bits + /// of the result as two separate values, in that order. + /// + /// # Examples + /// + /// Please note that this example is shared among integer types, which is why `u8` is used. + /// + /// ``` + /// #![feature(uint_carryless_mul)] + /// + /// assert_eq!(0b1000_0000u8.carrying_carryless_mul(0b1000_0000, 0b0000), (0, 0b0100_0000)); + /// assert_eq!(0b1000_0000u8.carrying_carryless_mul(0b1000_0000, 0b1111), (0b1111, 0b0100_0000)); + #[doc = concat!("assert_eq!(", + stringify!($SelfT), "::MAX.carrying_carryless_mul(", stringify!($SelfT), "::MAX, ", stringify!($SelfT), "::MAX), ", + "(!(", stringify!($SelfT), "::MAX / 3), ", stringify!($SelfT), "::MAX / 3));" + )] + /// ``` + #[rustc_const_unstable(feature = "uint_carryless_mul", issue = "152080")] + #[doc(alias = "clmul")] + #[unstable(feature = "uint_carryless_mul", issue = "152080")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline] + $($fn)* + } +} + impl i8 { int_impl! { Self = i8, @@ -458,6 +551,9 @@ impl u8 { fsh_op = "0x36", fshl_result = "0x8", fshr_result = "0x8d", + clmul_lhs = "0x12", + clmul_rhs = "0x34", + clmul_result = "0x28", swap_op = "0x12", swapped = "0x12", reversed = "0x48", @@ -468,6 +564,8 @@ impl u8 { bound_condition = "", } midpoint_impl! { u8, u16, unsigned } + widening_carryless_mul_impl! { u8, u16 } + carrying_carryless_mul_impl! { u8, u16 } /// Checks if the value is within the ASCII range. /// @@ -1095,6 +1193,9 @@ impl u16 { fsh_op = "0x2de", fshl_result = "0x30", fshr_result = "0x302d", + clmul_lhs = "0x9012", + clmul_rhs = "0xcd34", + clmul_result = "0x928", swap_op = "0x1234", swapped = "0x3412", reversed = "0x2c48", @@ -1105,6 +1206,8 @@ impl u16 { bound_condition = "", } midpoint_impl! { u16, u32, unsigned } + widening_carryless_mul_impl! { u16, u32 } + carrying_carryless_mul_impl! { u16, u32 } /// Checks if the value is a Unicode surrogate code point, which are disallowed values for [`char`]. /// @@ -1145,6 +1248,9 @@ impl u32 { fsh_op = "0x2fe78e45", fshl_result = "0xb32f", fshr_result = "0xb32fe78e", + clmul_lhs = "0x56789012", + clmul_rhs = "0xf52ecd34", + clmul_result = "0x9b980928", swap_op = "0x12345678", swapped = "0x78563412", reversed = "0x1e6a2c48", @@ -1155,6 +1261,8 @@ impl u32 { bound_condition = "", } midpoint_impl! { u32, u64, unsigned } + widening_carryless_mul_impl! { u32, u64 } + carrying_carryless_mul_impl! { u32, u64 } } impl u64 { @@ -1171,6 +1279,9 @@ impl u64 { fsh_op = "0x2fe78e45983acd98", fshl_result = "0x6e12fe", fshr_result = "0x6e12fe78e45983ac", + clmul_lhs = "0x7890123456789012", + clmul_rhs = "0xdd358416f52ecd34", + clmul_result = "0xa6299579b980928", swap_op = "0x1234567890123456", swapped = "0x5634129078563412", reversed = "0x6a2c48091e6a2c48", @@ -1181,6 +1292,8 @@ impl u64 { bound_condition = "", } midpoint_impl! { u64, u128, unsigned } + widening_carryless_mul_impl! { u64, u128 } + carrying_carryless_mul_impl! { u64, u128 } } impl u128 { @@ -1197,6 +1310,9 @@ impl u128 { fsh_op = "0x2fe78e45983acd98039000008736273", fshl_result = "0x4f7602fe", fshr_result = "0x4f7602fe78e45983acd9803900000873", + clmul_lhs = "0x12345678901234567890123456789012", + clmul_rhs = "0x4317e40ab4ddcf05dd358416f52ecd34", + clmul_result = "0xb9cf660de35d0c170a6299579b980928", swap_op = "0x12345678901234567890123456789012", swapped = "0x12907856341290785634129078563412", reversed = "0x48091e6a2c48091e6a2c48091e6a2c48", @@ -1209,6 +1325,7 @@ impl u128 { bound_condition = "", } midpoint_impl! { u128, unsigned } + carrying_carryless_mul_impl! { u128, u256 } } #[cfg(target_pointer_width = "16")] @@ -1223,9 +1340,12 @@ impl usize { rot = 4, rot_op = "0xa003", rot_result = "0x3a", - fsh_op = "0x2fe78e45983acd98039000008736273", - fshl_result = "0x4f7602fe", - fshr_result = "0x4f7602fe78e45983acd9803900000873", + fsh_op = "0x2de", + fshl_result = "0x30", + fshr_result = "0x302d", + clmul_lhs = "0x9012", + clmul_rhs = "0xcd34", + clmul_result = "0x928", swap_op = "0x1234", swapped = "0x3412", reversed = "0x2c48", @@ -1236,6 +1356,7 @@ impl usize { bound_condition = " on 16-bit targets", } midpoint_impl! { usize, u32, unsigned } + carrying_carryless_mul_impl! { usize, u32 } } #[cfg(target_pointer_width = "32")] @@ -1253,6 +1374,9 @@ impl usize { fsh_op = "0x2fe78e45", fshl_result = "0xb32f", fshr_result = "0xb32fe78e", + clmul_lhs = "0x56789012", + clmul_rhs = "0xf52ecd34", + clmul_result = "0x9b980928", swap_op = "0x12345678", swapped = "0x78563412", reversed = "0x1e6a2c48", @@ -1263,6 +1387,7 @@ impl usize { bound_condition = " on 32-bit targets", } midpoint_impl! { usize, u64, unsigned } + carrying_carryless_mul_impl! { usize, u64 } } #[cfg(target_pointer_width = "64")] @@ -1280,6 +1405,9 @@ impl usize { fsh_op = "0x2fe78e45983acd98", fshl_result = "0x6e12fe", fshr_result = "0x6e12fe78e45983ac", + clmul_lhs = "0x7890123456789012", + clmul_rhs = "0xdd358416f52ecd34", + clmul_result = "0xa6299579b980928", swap_op = "0x1234567890123456", swapped = "0x5634129078563412", reversed = "0x6a2c48091e6a2c48", @@ -1290,6 +1418,7 @@ impl usize { bound_condition = " on 64-bit targets", } midpoint_impl! { usize, u128, unsigned } + carrying_carryless_mul_impl! { usize, u128 } } impl usize { diff --git a/core/src/num/niche_types.rs b/core/src/num/niche_types.rs index 9ac0eb72bdcbc..33b2a6741abdf 100644 --- a/core/src/num/niche_types.rs +++ b/core/src/num/niche_types.rs @@ -5,45 +5,33 @@ )] use crate::cmp::Ordering; -use crate::fmt; use crate::hash::{Hash, Hasher}; use crate::marker::StructuralPartialEq; +use crate::{fmt, pattern_type}; macro_rules! define_valid_range_type { ($( $(#[$m:meta])* - $vis:vis struct $name:ident($int:ident as $uint:ident in $low:literal..=$high:literal); + $vis:vis struct $name:ident($int:ident is $pat:pat); )+) => {$( - #[derive(Clone, Copy, Eq)] + #[derive(Clone, Copy)] #[repr(transparent)] - #[rustc_layout_scalar_valid_range_start($low)] - #[rustc_layout_scalar_valid_range_end($high)] $(#[$m])* - $vis struct $name($int); - - const _: () = { - // With the `valid_range` attributes, it's always specified as unsigned - assert!(<$uint>::MIN == 0); - let ulow: $uint = $low; - let uhigh: $uint = $high; - assert!(ulow <= uhigh); - - assert!(size_of::<$int>() == size_of::<$uint>()); - }; - + $vis struct $name(pattern_type!($int is $pat)); impl $name { #[inline] pub const fn new(val: $int) -> Option { - if (val as $uint) >= ($low as $uint) && (val as $uint) <= ($high as $uint) { - // SAFETY: just checked the inclusive range - Some(unsafe { $name(val) }) + #[allow(non_contiguous_range_endpoints)] + if let $pat = val { + // SAFETY: just checked that the value matches the pattern + Some(unsafe { $name(crate::mem::transmute(val)) }) } else { None } } /// Constructs an instance of this type from the underlying integer - /// primitive without checking whether its zero. + /// primitive without checking whether its valid. /// /// # Safety /// Immediate language UB if `val` is not within the valid range for this @@ -51,13 +39,13 @@ macro_rules! define_valid_range_type { #[inline] pub const unsafe fn new_unchecked(val: $int) -> Self { // SAFETY: Caller promised that `val` is within the valid range. - unsafe { $name(val) } + unsafe { crate::mem::transmute(val) } } #[inline] pub const fn as_inner(self) -> $int { - // SAFETY: This is a transparent wrapper, so unwrapping it is sound - // (Not using `.0` due to MCP#807.) + // SAFETY: pattern types are always legal values of their base type + // (Not using `.0` because that has perf regressions.) unsafe { crate::mem::transmute(self) } } } @@ -67,6 +55,8 @@ macro_rules! define_valid_range_type { // by . impl StructuralPartialEq for $name {} + impl Eq for $name {} + impl PartialEq for $name { #[inline] fn eq(&self, other: &Self) -> bool { @@ -104,7 +94,7 @@ macro_rules! define_valid_range_type { } define_valid_range_type! { - pub struct Nanoseconds(u32 as u32 in 0..=999_999_999); + pub struct Nanoseconds(u32 is 0..=999_999_999); } impl Nanoseconds { @@ -120,47 +110,32 @@ impl const Default for Nanoseconds { } } -define_valid_range_type! { - pub struct NonZeroU8Inner(u8 as u8 in 1..=0xff); - pub struct NonZeroU16Inner(u16 as u16 in 1..=0xff_ff); - pub struct NonZeroU32Inner(u32 as u32 in 1..=0xffff_ffff); - pub struct NonZeroU64Inner(u64 as u64 in 1..=0xffffffff_ffffffff); - pub struct NonZeroU128Inner(u128 as u128 in 1..=0xffffffffffffffff_ffffffffffffffff); - - pub struct NonZeroI8Inner(i8 as u8 in 1..=0xff); - pub struct NonZeroI16Inner(i16 as u16 in 1..=0xff_ff); - pub struct NonZeroI32Inner(i32 as u32 in 1..=0xffff_ffff); - pub struct NonZeroI64Inner(i64 as u64 in 1..=0xffffffff_ffffffff); - pub struct NonZeroI128Inner(i128 as u128 in 1..=0xffffffffffffffff_ffffffffffffffff); - - pub struct NonZeroCharInner(char as u32 in 1..=0x10ffff); -} +const HALF_USIZE: usize = usize::MAX >> 1; -#[cfg(target_pointer_width = "16")] -define_valid_range_type! { - pub struct UsizeNoHighBit(usize as usize in 0..=0x7fff); - pub struct NonZeroUsizeInner(usize as usize in 1..=0xffff); - pub struct NonZeroIsizeInner(isize as usize in 1..=0xffff); -} -#[cfg(target_pointer_width = "32")] define_valid_range_type! { - pub struct UsizeNoHighBit(usize as usize in 0..=0x7fff_ffff); - pub struct NonZeroUsizeInner(usize as usize in 1..=0xffff_ffff); - pub struct NonZeroIsizeInner(isize as usize in 1..=0xffff_ffff); -} -#[cfg(target_pointer_width = "64")] -define_valid_range_type! { - pub struct UsizeNoHighBit(usize as usize in 0..=0x7fff_ffff_ffff_ffff); - pub struct NonZeroUsizeInner(usize as usize in 1..=0xffff_ffff_ffff_ffff); - pub struct NonZeroIsizeInner(isize as usize in 1..=0xffff_ffff_ffff_ffff); -} + pub struct NonZeroU8Inner(u8 is 1..); + pub struct NonZeroU16Inner(u16 is 1..); + pub struct NonZeroU32Inner(u32 is 1..); + pub struct NonZeroU64Inner(u64 is 1..); + pub struct NonZeroU128Inner(u128 is 1..); -define_valid_range_type! { - pub struct U32NotAllOnes(u32 as u32 in 0..=0xffff_fffe); - pub struct I32NotAllOnes(i32 as u32 in 0..=0xffff_fffe); + pub struct NonZeroI8Inner(i8 is ..0 | 1..); + pub struct NonZeroI16Inner(i16 is ..0 | 1..); + pub struct NonZeroI32Inner(i32 is ..0 | 1..); + pub struct NonZeroI64Inner(i64 is ..0 | 1..); + pub struct NonZeroI128Inner(i128 is ..0 | 1..); + + pub struct UsizeNoHighBit(usize is 0..=HALF_USIZE); + pub struct NonZeroUsizeInner(usize is 1..); + pub struct NonZeroIsizeInner(isize is ..0 | 1..); + + pub struct U32NotAllOnes(u32 is 0..u32::MAX); + pub struct I32NotAllOnes(i32 is ..-1 | 0..); + + pub struct U64NotAllOnes(u64 is 0..u64::MAX); + pub struct I64NotAllOnes(i64 is ..-1 | 0..); - pub struct U64NotAllOnes(u64 as u64 in 0..=0xffff_ffff_ffff_fffe); - pub struct I64NotAllOnes(i64 as u64 in 0..=0xffff_ffff_ffff_fffe); + pub struct NonZeroCharInner(char is '\u{1}' ..= '\u{10ffff}'); } pub trait NotAllOnesHelper { @@ -181,7 +156,7 @@ impl NotAllOnesHelper for i64 { } define_valid_range_type! { - pub struct CodePointInner(u32 as u32 in 0..=0x10ffff); + pub struct CodePointInner(u32 is 0..=0x10ffff); } impl CodePointInner { diff --git a/core/src/num/nonzero.rs b/core/src/num/nonzero.rs index 2b5279efb7f79..3415e1d435ce0 100644 --- a/core/src/num/nonzero.rs +++ b/core/src/num/nonzero.rs @@ -5,6 +5,7 @@ use crate::clone::{TrivialClone, UseCloned}; use crate::cmp::Ordering; use crate::hash::{Hash, Hasher}; use crate::marker::{Destruct, Freeze, StructuralPartialEq}; +use crate::num::imp; use crate::ops::{BitOr, BitOrAssign, Div, DivAssign, Neg, Rem, RemAssign}; use crate::panic::{RefUnwindSafe, UnwindSafe}; use crate::str::FromStr; @@ -31,7 +32,7 @@ use crate::{fmt, intrinsics, ptr, ub_checks}; issue = "none" )] pub unsafe trait ZeroablePrimitive: Sized + Copy + private::Sealed { - #[doc(hidden)] + /// A type like `Self` but with a niche that includes zero. type NonZeroInner: Sized + Copy; } @@ -1240,16 +1241,176 @@ macro_rules! nonzero_integer { // So the result cannot be zero. unsafe { Self::new_unchecked(self.get().saturating_pow(other)) } } + + /// Parses a non-zero integer from an ASCII-byte slice with decimal digits. + /// + /// The characters are expected to be an optional + #[doc = sign_dependent_expr!{ + $signedness ? + if signed { + " `+` or `-` " + } + if unsigned { + " `+` " + } + }] + /// sign followed by only digits. Leading and trailing non-digit characters (including + /// whitespace) represent an error. Underscores (which are accepted in Rust literals) + /// also represent an error. + /// + /// # Examples + /// + /// ``` + /// #![feature(int_from_ascii)] + /// + /// # use std::num::NonZero; + /// # + /// # fn main() { test().unwrap(); } + /// # fn test() -> Option<()> { + #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::from_ascii(b\"+10\"), Ok(NonZero::new(10)?));")] + /// # Some(()) + /// # } + /// ``` + /// + /// Trailing space returns error: + /// + /// ``` + /// #![feature(int_from_ascii)] + /// + /// # use std::num::NonZero; + /// # + #[doc = concat!("assert!(NonZero::<", stringify!($Int), ">::from_ascii(b\"1 \").is_err());")] + /// ``` + #[unstable(feature = "int_from_ascii", issue = "134821")] + #[inline] + pub const fn from_ascii(src: &[u8]) -> Result { + Self::from_ascii_radix(src, 10) + } + + /// Parses a non-zero integer from an ASCII-byte slice with digits in a given base. + /// + /// The characters are expected to be an optional + #[doc = sign_dependent_expr!{ + $signedness ? + if signed { + " `+` or `-` " + } + if unsigned { + " `+` " + } + }] + /// sign followed by only digits. Leading and trailing non-digit characters (including + /// whitespace) represent an error. Underscores (which are accepted in Rust literals) + /// also represent an error. + /// + /// Digits are a subset of these characters, depending on `radix`: + /// + /// - `0-9` + /// - `a-z` + /// - `A-Z` + /// + /// # Panics + /// + /// This method panics if `radix` is not in the range from 2 to 36. + /// + /// # Examples + /// + /// ``` + /// #![feature(int_from_ascii)] + /// + /// # use std::num::NonZero; + /// # + /// # fn main() { test().unwrap(); } + /// # fn test() -> Option<()> { + #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::from_ascii_radix(b\"A\", 16), Ok(NonZero::new(10)?));")] + /// # Some(()) + /// # } + /// ``` + /// + /// Trailing space returns error: + /// + /// ``` + /// #![feature(int_from_ascii)] + /// + /// # use std::num::NonZero; + /// # + #[doc = concat!("assert!(NonZero::<", stringify!($Int), ">::from_ascii_radix(b\"1 \", 10).is_err());")] + /// ``` + #[unstable(feature = "int_from_ascii", issue = "134821")] + #[inline] + pub const fn from_ascii_radix(src: &[u8], radix: u32) -> Result { + let n = match <$Int>::from_ascii_radix(src, radix) { + Ok(n) => n, + Err(err) => return Err(err), + }; + if let Some(n) = Self::new(n) { + Ok(n) + } else { + Err(ParseIntError { kind: IntErrorKind::Zero }) + } + } + + /// Parses a non-zero integer from a string slice with digits in a given base. + /// + /// The string is expected to be an optional + #[doc = sign_dependent_expr!{ + $signedness ? + if signed { + " `+` or `-` " + } + if unsigned { + " `+` " + } + }] + /// sign followed by only digits. Leading and trailing non-digit characters (including + /// whitespace) represent an error. Underscores (which are accepted in Rust literals) + /// also represent an error. + /// + /// Digits are a subset of these characters, depending on `radix`: + /// + /// - `0-9` + /// - `a-z` + /// - `A-Z` + /// + /// # Panics + /// + /// This method panics if `radix` is not in the range from 2 to 36. + /// + /// # Examples + /// + /// ``` + /// #![feature(nonzero_from_str_radix)] + /// + /// # use std::num::NonZero; + /// # + /// # fn main() { test().unwrap(); } + /// # fn test() -> Option<()> { + #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::from_str_radix(\"A\", 16), Ok(NonZero::new(10)?));")] + /// # Some(()) + /// # } + /// ``` + /// + /// Trailing space returns error: + /// + /// ``` + /// #![feature(nonzero_from_str_radix)] + /// + /// # use std::num::NonZero; + /// # + #[doc = concat!("assert!(NonZero::<", stringify!($Int), ">::from_str_radix(\"1 \", 10).is_err());")] + /// ``` + #[unstable(feature = "nonzero_from_str_radix", issue = "152193")] + #[inline] + pub const fn from_str_radix(src: &str, radix: u32) -> Result { + Self::from_ascii_radix(src.as_bytes(), radix) + } } #[stable(feature = "nonzero_parse", since = "1.35.0")] impl FromStr for NonZero<$Int> { type Err = ParseIntError; fn from_str(src: &str) -> Result { - Self::new(<$Int>::from_str_radix(src, 10)?) - .ok_or(ParseIntError { - kind: IntErrorKind::Zero - }) + Self::from_str_radix(src, 10) } } @@ -1657,7 +1818,7 @@ macro_rules! nonzero_integer_signedness_dependent_methods { without modifying the original"] #[inline] pub const fn ilog10(self) -> u32 { - super::int_log10::$Int(self) + imp::int_log10::$Int(self) } /// Calculates the midpoint (average) between `self` and `rhs`. diff --git a/core/src/num/uint_macros.rs b/core/src/num/uint_macros.rs index 5c263ea845cc2..27dbe6d3f1d8b 100644 --- a/core/src/num/uint_macros.rs +++ b/core/src/num/uint_macros.rs @@ -17,6 +17,9 @@ macro_rules! uint_impl { fsh_op = $fsh_op:literal, fshl_result = $fshl_result:literal, fshr_result = $fshr_result:literal, + clmul_lhs = $clmul_lhs:literal, + clmul_rhs = $clmul_rhs:literal, + clmul_result = $clmul_result:literal, swap_op = $swap_op:literal, swapped = $swapped:literal, reversed = $reversed:literal, @@ -444,7 +447,7 @@ macro_rules! uint_impl { pub const fn funnel_shl(self, rhs: Self, n: u32) -> Self { assert!(n < Self::BITS, "attempt to funnel shift left with overflow"); // SAFETY: just checked that `shift` is in-range - unsafe { intrinsics::unchecked_funnel_shl(self, rhs, n) } + unsafe { self.unchecked_funnel_shl(rhs, n) } } /// Performs a right funnel shift (concatenates `self` and `rhs`, with `self` @@ -479,7 +482,117 @@ macro_rules! uint_impl { pub const fn funnel_shr(self, rhs: Self, n: u32) -> Self { assert!(n < Self::BITS, "attempt to funnel shift right with overflow"); // SAFETY: just checked that `shift` is in-range - unsafe { intrinsics::unchecked_funnel_shr(self, rhs, n) } + unsafe { self.unchecked_funnel_shr(rhs, n) } + } + + /// Unchecked funnel shift left. + /// + /// # Safety + /// + /// This results in undefined behavior if `n` is greater than or equal to + #[doc = concat!("`", stringify!($SelfT) , "::BITS`,")] + /// i.e. when [`funnel_shl`](Self::funnel_shl) would panic. + /// + #[rustc_const_unstable(feature = "funnel_shifts", issue = "145686")] + #[unstable(feature = "funnel_shifts", issue = "145686")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + #[track_caller] + pub const unsafe fn unchecked_funnel_shl(self, low: Self, n: u32) -> Self { + assert_unsafe_precondition!( + check_language_ub, + concat!(stringify!($SelfT), "::unchecked_funnel_shl cannot overflow"), + (n: u32 = n) => n < <$ActualT>::BITS, + ); + + // SAFETY: this is guaranteed to be safe by the caller. + unsafe { + intrinsics::unchecked_funnel_shl(self, low, n) + } + } + + /// Unchecked funnel shift right. + /// + /// # Safety + /// + /// This results in undefined behavior if `n` is greater than or equal to + #[doc = concat!("`", stringify!($SelfT) , "::BITS`,")] + /// i.e. when [`funnel_shr`](Self::funnel_shr) would panic. + /// + #[rustc_const_unstable(feature = "funnel_shifts", issue = "145686")] + #[unstable(feature = "funnel_shifts", issue = "145686")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + #[track_caller] + pub const unsafe fn unchecked_funnel_shr(self, low: Self, n: u32) -> Self { + assert_unsafe_precondition!( + check_language_ub, + concat!(stringify!($SelfT), "::unchecked_funnel_shr cannot overflow"), + (n: u32 = n) => n < <$ActualT>::BITS, + ); + + // SAFETY: this is guaranteed to be safe by the caller. + unsafe { + intrinsics::unchecked_funnel_shr(self, low, n) + } + } + + /// Performs a carry-less multiplication, returning the lower bits. + /// + /// This operation is similar to long multiplication in base 2, except that exclusive or is + /// used instead of addition. The implementation is equivalent to: + /// + /// ```no_run + #[doc = concat!("pub fn carryless_mul(lhs: ", stringify!($SelfT), ", rhs: ", stringify!($SelfT), ") -> ", stringify!($SelfT), "{")] + /// let mut retval = 0; + #[doc = concat!(" for i in 0..", stringify!($SelfT), "::BITS {")] + /// if (rhs >> i) & 1 != 0 { + /// // long multiplication would use += + /// retval ^= lhs << i; + /// } + /// } + /// retval + /// } + /// ``` + /// + /// The actual implementation is more efficient, and on some platforms lowers directly to a + /// dedicated instruction. + /// + /// # Uses + /// + /// Carryless multiplication can be used to turn a bitmask of quote characters into a + /// bit mask of characters surrounded by quotes: + /// + /// ```no_run + /// r#"abc xxx "foobar" zzz "a"!"#; // input string + /// 0b0000000010000001000001010; // quote_mask + /// 0b0000000001111110000000100; // quote_mask.carryless_mul(!0) & !quote_mask + /// ``` + /// + /// Another use is in cryptography, where carryless multiplication allows for efficient + /// implementations of polynomial multiplication in `GF(2)[X]`, the polynomial ring + /// over `GF(2)`. + /// + /// # Examples + /// + /// ``` + /// #![feature(uint_carryless_mul)] + /// + #[doc = concat!("let a = ", $clmul_lhs, stringify!($SelfT), ";")] + #[doc = concat!("let b = ", $clmul_rhs, stringify!($SelfT), ";")] + /// + #[doc = concat!("assert_eq!(a.carryless_mul(b), ", $clmul_result, ");")] + /// ``` + #[rustc_const_unstable(feature = "uint_carryless_mul", issue = "152080")] + #[doc(alias = "clmul")] + #[unstable(feature = "uint_carryless_mul", issue = "152080")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + pub const fn carryless_mul(self, rhs: Self) -> Self { + intrinsics::carryless_mul(self, rhs) } /// Reverses the byte order of the integer. @@ -515,7 +628,7 @@ macro_rules! uint_impl { without modifying the original"] #[inline] pub const fn extract_bits(self, mask: Self) -> Self { - crate::num::int_bits::$ActualT::extract_impl(self as $ActualT, mask as $ActualT) as $SelfT + imp::int_bits::$ActualT::extract_impl(self as $ActualT, mask as $ActualT) as $SelfT } /// Returns an integer with the least significant bits of `self` @@ -532,7 +645,7 @@ macro_rules! uint_impl { without modifying the original"] #[inline] pub const fn deposit_bits(self, mask: Self) -> Self { - crate::num::int_bits::$ActualT::deposit_impl(self as $ActualT, mask as $ActualT) as $SelfT + imp::int_bits::$ActualT::deposit_impl(self as $ActualT, mask as $ActualT) as $SelfT } /// Reverses the order of bits in the integer. The least significant bit becomes the most significant bit, @@ -743,7 +856,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_add(self, rhs: Self) -> Self { let (a, b) = self.overflowing_add(rhs); - if b { overflow_panic::add() } else { a } + if b { imp::overflow_panic::add() } else { a } } /// Unchecked integer addition. Computes `self + rhs`, assuming overflow @@ -838,7 +951,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_add_signed(self, rhs: $SignedT) -> Self { let (a, b) = self.overflowing_add_signed(rhs); - if b { overflow_panic::add() } else { a } + if b { imp::overflow_panic::add() } else { a } } /// Checked integer subtraction. Computes `self - rhs`, returning @@ -897,7 +1010,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_sub(self, rhs: Self) -> Self { let (a, b) = self.overflowing_sub(rhs); - if b { overflow_panic::sub() } else { a } + if b { imp::overflow_panic::sub() } else { a } } /// Unchecked integer subtraction. Computes `self - rhs`, assuming overflow @@ -1022,7 +1135,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_sub_signed(self, rhs: $SignedT) -> Self { let (a, b) = self.overflowing_sub_signed(rhs); - if b { overflow_panic::sub() } else { a } + if b { imp::overflow_panic::sub() } else { a } } #[doc = concat!( @@ -1131,7 +1244,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_mul(self, rhs: Self) -> Self { let (a, b) = self.overflowing_mul(rhs); - if b { overflow_panic::mul() } else { a } + if b { imp::overflow_panic::mul() } else { a } } /// Unchecked integer multiplication. Computes `self * rhs`, assuming overflow @@ -1556,7 +1669,7 @@ macro_rules! uint_impl { if let Some(log) = self.checked_ilog(base) { log } else { - int_log10::panic_for_nonpositive_argument() + imp::int_log10::panic_for_nonpositive_argument() } } @@ -1581,7 +1694,7 @@ macro_rules! uint_impl { if let Some(log) = self.checked_ilog2() { log } else { - int_log10::panic_for_nonpositive_argument() + imp::int_log10::panic_for_nonpositive_argument() } } @@ -1606,7 +1719,7 @@ macro_rules! uint_impl { if let Some(log) = self.checked_ilog10() { log } else { - int_log10::panic_for_nonpositive_argument() + imp::int_log10::panic_for_nonpositive_argument() } } @@ -1768,7 +1881,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_neg(self) -> Self { let (a, b) = self.overflowing_neg(); - if b { overflow_panic::neg() } else { a } + if b { imp::overflow_panic::neg() } else { a } } /// Checked shift left. Computes `self << rhs`, returning `None` @@ -1824,7 +1937,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_shl(self, rhs: u32) -> Self { let (a, b) = self.overflowing_shl(rhs); - if b { overflow_panic::shl() } else { a } + if b { imp::overflow_panic::shl() } else { a } } /// Unchecked shift left. Computes `self << rhs`, assuming that @@ -2009,7 +2122,7 @@ macro_rules! uint_impl { #[track_caller] pub const fn strict_shr(self, rhs: u32) -> Self { let (a, b) = self.overflowing_shr(rhs); - if b { overflow_panic::shr() } else { a } + if b { imp::overflow_panic::shr() } else { a } } /// Unchecked shift right. Computes `self >> rhs`, assuming that @@ -3072,7 +3185,6 @@ macro_rules! uint_impl { /// implementing it for wider-than-native types. /// /// ``` - /// #![feature(const_unsigned_bigint_helpers)] /// fn scalar_mul_eq(little_endian_digits: &mut Vec, multiplicand: u16) { /// let mut carry = 0; /// for d in little_endian_digits.iter_mut() { @@ -3097,6 +3209,7 @@ macro_rules! uint_impl { /// except that it gives the value of the overflow instead of just whether one happened: /// /// ``` + /// # #![allow(unused_features)] /// #![feature(const_unsigned_bigint_helpers)] /// let r = u8::carrying_mul(7, 13, 0); /// assert_eq!((r.0, r.1 != 0), u8::overflowing_mul(7, 13)); @@ -3109,6 +3222,7 @@ macro_rules! uint_impl { /// [`wrapping_add`](Self::wrapping_add) methods: /// /// ``` + /// # #![allow(unused_features)] /// #![feature(const_unsigned_bigint_helpers)] /// assert_eq!( /// 789_u16.carrying_mul(456, 123).0, @@ -3481,7 +3595,7 @@ macro_rules! uint_impl { without modifying the original"] #[inline] pub const fn isqrt(self) -> Self { - let result = crate::num::int_sqrt::$ActualT(self as $ActualT) as $SelfT; + let result = imp::int_sqrt::$ActualT(self as $ActualT) as $SelfT; // Inform the optimizer what the range of outputs is. If testing // `core` crashes with no panic message and a `num::int_sqrt::u*` @@ -3494,7 +3608,7 @@ macro_rules! uint_impl { // integers is bounded by `[0, <$ActualT>::MAX]`, sqrt(n) will be // bounded by `[sqrt(0), sqrt(<$ActualT>::MAX)]`. unsafe { - const MAX_RESULT: $SelfT = crate::num::int_sqrt::$ActualT(<$ActualT>::MAX) as $SelfT; + const MAX_RESULT: $SelfT = imp::int_sqrt::$ActualT(<$ActualT>::MAX) as $SelfT; crate::hint::assert_unchecked(result <= MAX_RESULT); } diff --git a/core/src/ops/arith.rs b/core/src/ops/arith.rs index 6c6479c998459..aec52424af3c4 100644 --- a/core/src/ops/arith.rs +++ b/core/src/ops/arith.rs @@ -716,6 +716,7 @@ macro_rules! neg_impl { type Output = $t; #[inline] + #[track_caller] #[rustc_inherit_overflow_checks] fn neg(self) -> $t { -self } } diff --git a/core/src/ops/bit.rs b/core/src/ops/bit.rs index 0cd61b0737381..e347a20d2d869 100644 --- a/core/src/ops/bit.rs +++ b/core/src/ops/bit.rs @@ -484,6 +484,7 @@ macro_rules! shl_impl { type Output = $t; #[inline] + #[track_caller] #[rustc_inherit_overflow_checks] fn shl(self, other: $f) -> $t { self << other @@ -606,6 +607,7 @@ macro_rules! shr_impl { type Output = $t; #[inline] + #[track_caller] #[rustc_inherit_overflow_checks] fn shr(self, other: $f) -> $t { self >> other @@ -958,6 +960,7 @@ macro_rules! shl_assign_impl { #[rustc_const_unstable(feature = "const_ops", issue = "143802")] impl const ShlAssign<$f> for $t { #[inline] + #[track_caller] #[rustc_inherit_overflow_checks] fn shl_assign(&mut self, other: $f) { *self <<= other @@ -1044,6 +1047,7 @@ macro_rules! shr_assign_impl { #[rustc_const_unstable(feature = "const_ops", issue = "143802")] impl const ShrAssign<$f> for $t { #[inline] + #[track_caller] #[rustc_inherit_overflow_checks] fn shr_assign(&mut self, other: $f) { *self >>= other diff --git a/core/src/ops/control_flow.rs b/core/src/ops/control_flow.rs index 3cc184f0ab75c..b15712d3599c6 100644 --- a/core/src/ops/control_flow.rs +++ b/core/src/ops/control_flow.rs @@ -151,7 +151,7 @@ impl ControlFlow { /// ``` #[inline] #[stable(feature = "control_flow_enum_is", since = "1.59.0")] - #[rustc_const_unstable(feature = "min_const_control_flow", issue = "148738")] + #[rustc_const_stable(feature = "min_const_control_flow", since = "1.95.0")] pub const fn is_break(&self) -> bool { matches!(*self, ControlFlow::Break(_)) } @@ -168,7 +168,7 @@ impl ControlFlow { /// ``` #[inline] #[stable(feature = "control_flow_enum_is", since = "1.59.0")] - #[rustc_const_unstable(feature = "min_const_control_flow", issue = "148738")] + #[rustc_const_stable(feature = "min_const_control_flow", since = "1.95.0")] pub const fn is_continue(&self) -> bool { matches!(*self, ControlFlow::Continue(_)) } @@ -197,14 +197,12 @@ impl ControlFlow { } } - /// Converts the `ControlFlow` into an `Result` which is `Ok` if the + /// Converts the `ControlFlow` into a `Result` which is `Ok` if the /// `ControlFlow` was `Break` and `Err` if otherwise. /// /// # Examples /// /// ``` - /// #![feature(control_flow_ok)] - /// /// use std::ops::ControlFlow; /// /// struct TreeNode { @@ -263,8 +261,9 @@ impl ControlFlow { /// assert_eq!(res, Ok(&5)); /// ``` #[inline] - #[unstable(feature = "control_flow_ok", issue = "140266")] - #[rustc_const_unstable(feature = "min_const_control_flow", issue = "148738")] + #[stable(feature = "control_flow_ok", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "control_flow_ok", since = "CURRENT_RUSTC_VERSION")] + #[rustc_allow_const_fn_unstable(const_precise_live_drops)] pub const fn break_ok(self) -> Result { match self { ControlFlow::Continue(c) => Err(c), @@ -311,14 +310,12 @@ impl ControlFlow { } } - /// Converts the `ControlFlow` into an `Result` which is `Ok` if the + /// Converts the `ControlFlow` into a `Result` which is `Ok` if the /// `ControlFlow` was `Continue` and `Err` if otherwise. /// /// # Examples /// /// ``` - /// #![feature(control_flow_ok)] - /// /// use std::ops::ControlFlow; /// /// struct TreeNode { @@ -376,8 +373,9 @@ impl ControlFlow { /// assert_eq!(res, Err("too big value detected")); /// ``` #[inline] - #[unstable(feature = "control_flow_ok", issue = "140266")] - #[rustc_const_unstable(feature = "min_const_control_flow", issue = "148738")] + #[stable(feature = "control_flow_ok", since = "CURRENT_RUSTC_VERSION")] + #[rustc_const_stable(feature = "control_flow_ok", since = "CURRENT_RUSTC_VERSION")] + #[rustc_allow_const_fn_unstable(const_precise_live_drops)] pub const fn continue_ok(self) -> Result { match self { ControlFlow::Continue(c) => Ok(c), @@ -422,9 +420,9 @@ impl ControlFlow { } } -/// These are used only as part of implementing the iterator adapters. -/// They have mediocre names and non-obvious semantics, so aren't -/// currently on a path to potential stabilization. +// These are used only as part of implementing the iterator adapters. +// They have mediocre names and non-obvious semantics, so aren't +// currently on a path to potential stabilization. impl ControlFlow { /// Creates a `ControlFlow` from any type implementing `Try`. #[inline] diff --git a/core/src/option.rs b/core/src/option.rs index 3dc53941977cb..d4dd33b948193 100644 --- a/core/src/option.rs +++ b/core/src/option.rs @@ -1777,7 +1777,7 @@ impl Option { #[rustc_const_unstable(feature = "const_option_ops", issue = "143956")] pub const fn get_or_insert_default(&mut self) -> &mut T where - T: [const] Default + [const] Destruct, + T: [const] Default, { self.get_or_insert_with(T::default) } @@ -1805,10 +1805,25 @@ impl Option { pub const fn get_or_insert_with(&mut self, f: F) -> &mut T where F: [const] FnOnce() -> T + [const] Destruct, - T: [const] Destruct, { if let None = self { - *self = Some(f()); + // The effect of the following statement is identical to + // *self = Some(f()); + // except that it does not drop the old value of `*self`. This is not a leak, because + // we just checked that the old value is `None`, which contains no fields to drop. + // This implementation strategy + // + // * avoids needing a `T: [const] Destruct` bound, to the benefit of `const` callers, + // * and avoids possibly compiling needless drop code (as would sometimes happen in the + // previous implementation), to the benefit of non-`const` callers. + // + // FIXME(const-hack): It would be nice if this weird trick were made obsolete + // (though that is likely to be hard/wontfix). + // + // It could also be expressed as `unsafe { core::ptr::write(self, Some(f())) }`, but + // no reason is currently known to use additional unsafe code here. + + mem::forget(mem::replace(self, Some(f()))); } // SAFETY: a `None` variant for `self` would have been replaced by a `Some` @@ -2743,9 +2758,6 @@ impl> FromIterator> for Option { /// so the final value of `shared` is 6 (= `3 + 2 + 1`), not 16. #[inline] fn from_iter>>(iter: I) -> Option { - // FIXME(#11084): This could be replaced with Iterator::scan when this - // performance bug is closed. - iter::try_process(iter.into_iter(), |i| i.collect()) } } diff --git a/core/src/panic/unwind_safe.rs b/core/src/panic/unwind_safe.rs index 21dbd09f49606..20f85b5ca9cd8 100644 --- a/core/src/panic/unwind_safe.rs +++ b/core/src/panic/unwind_safe.rs @@ -2,6 +2,7 @@ use crate::async_iter::AsyncIterator; use crate::cell::UnsafeCell; use crate::fmt; use crate::future::Future; +use crate::marker::PointeeSized; use crate::ops::{Deref, DerefMut}; use crate::pin::Pin; use crate::ptr::{NonNull, Unique}; @@ -178,17 +179,17 @@ pub struct AssertUnwindSafe(#[stable(feature = "catch_unwind", since = "1.9.0 // * Our custom AssertUnwindSafe wrapper is indeed unwind safe #[stable(feature = "catch_unwind", since = "1.9.0")] -impl !UnwindSafe for &mut T {} +impl !UnwindSafe for &mut T {} #[stable(feature = "catch_unwind", since = "1.9.0")] -impl UnwindSafe for &T {} +impl UnwindSafe for &T {} #[stable(feature = "catch_unwind", since = "1.9.0")] -impl UnwindSafe for *const T {} +impl UnwindSafe for *const T {} #[stable(feature = "catch_unwind", since = "1.9.0")] -impl UnwindSafe for *mut T {} +impl UnwindSafe for *mut T {} #[unstable(feature = "ptr_internals", issue = "none")] -impl UnwindSafe for Unique {} +impl UnwindSafe for Unique {} #[stable(feature = "nonnull", since = "1.25.0")] -impl UnwindSafe for NonNull {} +impl UnwindSafe for NonNull {} #[stable(feature = "catch_unwind", since = "1.9.0")] impl UnwindSafe for AssertUnwindSafe {} @@ -313,3 +314,16 @@ impl AsyncIterator for AssertUnwindSafe { self.0.size_hint() } } + +/// If a value's type is already `UnwindSafe`, +/// wrapping it in `AssertUnwindSafe` is never incorrect. +#[stable(feature = "from_wrapper_impls", since = "CURRENT_RUSTC_VERSION")] +impl From for AssertUnwindSafe +where + T: UnwindSafe, +{ + #[inline(always)] + fn from(value: T) -> Self { + Self(value) + } +} diff --git a/core/src/pin.rs b/core/src/pin.rs index c4981facc04c3..ffdcd9fad49a5 100644 --- a/core/src/pin.rs +++ b/core/src/pin.rs @@ -600,7 +600,7 @@ //! automatically called [`Pin::get_unchecked_mut`]. //! //! This can never cause a problem in purely safe code because creating a pinning pointer to -//! a type which has an address-sensitive (thus does not implement `Unpin`) requires `unsafe`, +//! a type which has address-sensitive states (and thus does not implement `Unpin`) requires `unsafe`, //! but it is important to note that choosing to take advantage of pinning-related guarantees //! to justify validity in the implementation of your type has consequences for that type's //! [`Drop`][Drop] implementation as well: if an element of your type could have been pinned, @@ -1829,9 +1829,10 @@ where /// /// # Safety /// -/// If this type implements `Deref`, then the concrete type returned by `deref` -/// and `deref_mut` must not change without a modification. The following -/// operations are not considered modifications: +/// Given a pointer of this type, the concrete type returned by its +/// `deref` method and (if it implements `DerefMut`) its `deref_mut` method +/// must be the same type and must not change without a modification. +/// The following operations are not considered modifications: /// /// * Moving the pointer. /// * Performing unsizing coercions on the pointer. @@ -1842,7 +1843,7 @@ where /// to. The concrete type of a slice is an array of the same element type and /// the length specified in the metadata. The concrete type of a sized type /// is the type itself. -pub unsafe trait PinCoerceUnsized {} +pub unsafe trait PinCoerceUnsized: Deref {} #[stable(feature = "pin", since = "1.33.0")] unsafe impl<'a, T: ?Sized> PinCoerceUnsized for &'a T {} @@ -1853,12 +1854,6 @@ unsafe impl<'a, T: ?Sized> PinCoerceUnsized for &'a mut T {} #[stable(feature = "pin", since = "1.33.0")] unsafe impl PinCoerceUnsized for Pin {} -#[stable(feature = "pin", since = "1.33.0")] -unsafe impl PinCoerceUnsized for *const T {} - -#[stable(feature = "pin", since = "1.33.0")] -unsafe impl PinCoerceUnsized for *mut T {} - /// Constructs a [Pin]<[&mut] T>, by pinning a `value: T` locally. /// /// Unlike [`Box::pin`], this does not create a new heap allocation. As explained diff --git a/core/src/prelude/v1.rs b/core/src/prelude/v1.rs index 354be271ff131..f2eb047d342bc 100644 --- a/core/src/prelude/v1.rs +++ b/core/src/prelude/v1.rs @@ -80,7 +80,7 @@ mod ambiguous_macros_only { #[doc(no_inline)] pub use self::ambiguous_macros_only::{env, panic}; -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "1.95.0")] #[doc(no_inline)] pub use crate::cfg_select; diff --git a/core/src/ptr/const_ptr.rs b/core/src/ptr/const_ptr.rs index 75777144dfb85..8b7b08bf82317 100644 --- a/core/src/ptr/const_ptr.rs +++ b/core/src/ptr/const_ptr.rs @@ -290,8 +290,8 @@ impl *const T { /// assert_eq!(ptr.as_ref_unchecked(), &10); /// } /// ``` - #[stable(feature = "ptr_as_ref_unchecked", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "ptr_as_ref_unchecked", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "ptr_as_ref_unchecked", since = "1.95.0")] + #[rustc_const_stable(feature = "ptr_as_ref_unchecked", since = "1.95.0")] #[inline] #[must_use] pub const unsafe fn as_ref_unchecked<'a>(self) -> &'a T { diff --git a/core/src/ptr/mod.rs b/core/src/ptr/mod.rs index ad74a8628c61c..ddeb1ccc72af7 100644 --- a/core/src/ptr/mod.rs +++ b/core/src/ptr/mod.rs @@ -15,22 +15,19 @@ //! The precise rules for validity are not determined yet. The guarantees that are //! provided at this point are very minimal: //! -//! * For memory accesses of [size zero][zst], *every* pointer is valid, including the [null] -//! pointer. The following points are only concerned with non-zero-sized accesses. -//! * A [null] pointer is *never* valid. -//! * For a pointer to be valid, it is necessary, but not always sufficient, that the pointer be -//! *dereferenceable*. The [provenance] of the pointer is used to determine which [allocation] -//! it is derived from; a pointer is dereferenceable if the memory range of the given size -//! starting at the pointer is entirely contained within the bounds of that allocation. Note +//! * A [null] pointer is *never* valid for reads/writes. +//! * For memory accesses of [size zero][zst], *every* non-null pointer is valid for reads/writes. +//! The following points are only concerned with non-zero-sized accesses. +//! * For a pointer to be valid for reads/writes, it is necessary, but not always sufficient, that +//! the pointer be *dereferenceable*. The [provenance] of the pointer is used to determine which +//! [allocation] it is derived from; a pointer is dereferenceable if the memory range of the given +//! size starting at the pointer is entirely contained within the bounds of that allocation. Note //! that in Rust, every (stack-allocated) variable is considered a separate allocation. //! * All accesses performed by functions in this module are *non-atomic* in the sense //! of [atomic operations] used to synchronize between threads. This means it is //! undefined behavior to perform two concurrent accesses to the same location from different -//! threads unless both accesses only read from memory. Notice that this explicitly -//! includes [`read_volatile`] and [`write_volatile`]: Volatile accesses cannot -//! be used for inter-thread synchronization, regardless of whether they are acting on -//! Rust memory or not. -//! * The result of casting a reference to a pointer is valid for as long as the +//! threads unless both accesses only read from memory. +//! * The result of casting a reference to a pointer is valid for reads/writes for as long as the //! underlying allocation is live and no reference (just raw pointers) is used to //! access the same memory. That is, reference and pointer accesses cannot be //! interleaved. @@ -41,6 +38,13 @@ //! information, see the [book] as well as the section in the reference devoted //! to [undefined behavior][ub]. //! +//! Note that some operations such as [`read`] and [`write`][`write()`] do allow null pointers if +//! the total size of the access is zero. However, other operations internally convert pointers into +//! references. Therefore, the general notion of "valid for reads/writes" excludes null pointers, +//! and the specific operations that permit null pointers mention that as an exception. Furthermore, +//! [`read_volatile`] and [`write_volatile`] can be used in even more situations; see their +//! documentation for details. +//! //! We say that a pointer is "dangling" if it is not valid for any non-zero-sized accesses. This //! means out-of-bounds pointers, pointers to freed memory, null pointers, and pointers created with //! [`NonNull::dangling`] are all dangling. @@ -408,9 +412,10 @@ use crate::mem::{self, MaybeUninit, SizedTypeProperties}; use crate::num::NonZero; use crate::{fmt, hash, intrinsics, ub_checks}; -mod alignment; #[unstable(feature = "ptr_alignment_type", issue = "102070")] -pub use alignment::Alignment; +#[deprecated(since = "CURRENT_RUSTC_VERSION", note = "moved from `ptr` to `mem`")] +/// Deprecated re-export of [mem::Alignment]. +pub type Alignment = mem::Alignment; mod metadata; #[unstable(feature = "ptr_metadata", issue = "81513")] @@ -450,9 +455,9 @@ mod mut_ptr; /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `src` must be [valid] for reads of `count * size_of::()` bytes. +/// * `src` must be [valid] for reads of `count * size_of::()` bytes or that number must be 0. /// -/// * `dst` must be [valid] for writes of `count * size_of::()` bytes. +/// * `dst` must be [valid] for writes of `count * size_of::()` bytes or that number must be 0. /// /// * Both `src` and `dst` must be properly aligned. /// @@ -568,11 +573,11 @@ pub const unsafe fn copy_nonoverlapping(src: *const T, dst: *mut T, count: us /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `src` must be [valid] for reads of `count * size_of::()` bytes. +/// * `src` must be [valid] for reads of `count * size_of::()` bytes or that number must be 0. /// -/// * `dst` must be [valid] for writes of `count * size_of::()` bytes, and must remain valid even -/// when `src` is read for `count * size_of::()` bytes. (This means if the memory ranges -/// overlap, the `dst` pointer must not be invalidated by `src` reads.) +/// * `dst` must be [valid] for writes of `count * size_of::()` bytes or that number must be 0, +/// and `dst` must remain valid even when `src` is read for `count * size_of::()` bytes. (This +/// means if the memory ranges overlap, the `dst` pointer must not be invalidated by `src` reads.) /// /// * Both `src` and `dst` must be properly aligned. /// @@ -1508,7 +1513,7 @@ unsafe fn swap_nonoverlapping_bytes(x: *mut u8, y: *mut u8, bytes: NonZero(dst: *mut T, src: T) -> T { // SAFETY: the caller must guarantee that `dst` is valid to be // cast to a mutable reference (valid for writes, aligned, initialized), // and cannot overlap `src` since `dst` must point to a distinct - // allocation. + // allocation. We are excluding null (with a ZST check) before creating a reference. unsafe { ub_checks::assert_unsafe_precondition!( check_language_ub, @@ -1554,6 +1559,12 @@ pub const unsafe fn replace(dst: *mut T, src: T) -> T { is_zst: bool = T::IS_ZST, ) => ub_checks::maybe_is_aligned_and_not_null(addr, align, is_zst) ); + if T::IS_ZST { + // If `T` is a ZST, `dst` is allowed to be null. However, we also don't have to actually + // do anything since there isn't actually any data to be copied anyway. All values of + // type `T` are bit-identical, so we can just return `src` here. + return src; + } mem::replace(&mut *dst, src) } } @@ -1565,7 +1576,7 @@ pub const unsafe fn replace(dst: *mut T, src: T) -> T { /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `src` must be [valid] for reads. +/// * `src` must be [valid] for reads or `T` must be a ZST. /// /// * `src` must be properly aligned. Use [`read_unaligned`] if this is not the /// case. @@ -1817,7 +1828,7 @@ pub const unsafe fn read_unaligned(src: *const T) -> T { /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `dst` must be [valid] for writes. +/// * `dst` must be [valid] for writes or `T` must be a ZST. /// /// * `dst` must be properly aligned. Use [`write_unaligned`] if this is not the /// case. @@ -2040,8 +2051,8 @@ pub const unsafe fn write_unaligned(dst: *mut T, src: T) { /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `src` must be either [valid] for reads, or it must point to memory outside of all Rust -/// allocations and reading from that memory must: +/// * `src` must be either [valid] for reads, or `T` must be a ZST, or `src` must point to memory +/// outside of all Rust allocations and reading from that memory must: /// - not trap, and /// - not cause any memory inside a Rust allocation to be modified. /// @@ -2128,8 +2139,8 @@ pub unsafe fn read_volatile(src: *const T) -> T { /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `dst` must be either [valid] for writes, or it must point to memory outside of all Rust -/// allocations and writing to that memory must: +/// * `dst` must be either [valid] for writes, or `T` must be a ZST, or `dst` must point to memory +/// outside of all Rust allocations and writing to that memory must: /// - not trap, and /// - not cause any memory inside a Rust allocation to be modified. /// diff --git a/core/src/ptr/mut_ptr.rs b/core/src/ptr/mut_ptr.rs index 02e12d56fa659..289dd972f679c 100644 --- a/core/src/ptr/mut_ptr.rs +++ b/core/src/ptr/mut_ptr.rs @@ -288,8 +288,8 @@ impl *mut T { /// println!("We got back the value: {}!", ptr.as_ref_unchecked()); /// } /// ``` - #[stable(feature = "ptr_as_ref_unchecked", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "ptr_as_ref_unchecked", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "ptr_as_ref_unchecked", since = "1.95.0")] + #[rustc_const_stable(feature = "ptr_as_ref_unchecked", since = "1.95.0")] #[inline] #[must_use] pub const unsafe fn as_ref_unchecked<'a>(self) -> &'a T { @@ -611,8 +611,8 @@ impl *mut T { /// # assert_eq!(s, [4, 2, 3]); /// println!("{s:?}"); // It'll print: "[4, 2, 3]". /// ``` - #[stable(feature = "ptr_as_ref_unchecked", since = "CURRENT_RUSTC_VERSION")] - #[rustc_const_stable(feature = "ptr_as_ref_unchecked", since = "CURRENT_RUSTC_VERSION")] + #[stable(feature = "ptr_as_ref_unchecked", since = "1.95.0")] + #[rustc_const_stable(feature = "ptr_as_ref_unchecked", since = "1.95.0")] #[inline] #[must_use] pub const unsafe fn as_mut_unchecked<'a>(self) -> &'a mut T { @@ -1800,7 +1800,6 @@ impl *mut [T] { /// /// ``` /// #![feature(raw_slice_split)] - /// #![feature(slice_ptr_get)] /// /// let mut v = [1, 0, 3, 0, 5, 6]; /// let ptr = &mut v as *mut [_]; diff --git a/core/src/ptr/non_null.rs b/core/src/ptr/non_null.rs index 7b9e638289bf0..90f27ca8bdb0a 100644 --- a/core/src/ptr/non_null.rs +++ b/core/src/ptr/non_null.rs @@ -1,10 +1,9 @@ use crate::clone::TrivialClone; use crate::cmp::Ordering; use crate::marker::{Destruct, PointeeSized, Unsize}; -use crate::mem::{MaybeUninit, SizedTypeProperties}; +use crate::mem::{MaybeUninit, SizedTypeProperties, transmute}; use crate::num::NonZero; use crate::ops::{CoerceUnsized, DispatchFromDyn}; -use crate::pin::PinCoerceUnsized; use crate::ptr::Unique; use crate::slice::{self, SliceIndex}; use crate::ub_checks::assert_unsafe_precondition; @@ -100,9 +99,8 @@ impl NonNull { #[must_use] #[inline] pub const fn without_provenance(addr: NonZero) -> Self { - let pointer = crate::ptr::without_provenance(addr.get()); - // SAFETY: we know `addr` is non-zero. - unsafe { NonNull { pointer } } + // SAFETY: we know `addr` is non-zero and all nonzero integers are valid raw pointers. + unsafe { transmute(addr) } } /// Creates a new `NonNull` that is dangling, but well-aligned. @@ -129,8 +127,8 @@ impl NonNull { #[must_use] #[inline] pub const fn dangling() -> Self { - let align = crate::ptr::Alignment::of::(); - NonNull::without_provenance(align.as_nonzero()) + let align = crate::mem::Alignment::of::(); + NonNull::without_provenance(align.as_nonzero_usize()) } /// Converts an address back to a mutable pointer, picking up some previously 'exposed' @@ -140,8 +138,9 @@ impl NonNull { /// /// This is an [Exposed Provenance][crate::ptr#exposed-provenance] API. #[stable(feature = "nonnull_provenance", since = "1.89.0")] + #[rustc_const_unstable(feature = "const_nonnull_with_exposed_provenance", issue = "154215")] #[inline] - pub fn with_exposed_provenance(addr: NonZero) -> Self { + pub const fn with_exposed_provenance(addr: NonZero) -> Self { // SAFETY: we know `addr` is non-zero. unsafe { let ptr = crate::ptr::with_exposed_provenance_mut(addr.get()); @@ -239,7 +238,7 @@ impl NonNull { "NonNull::new_unchecked requires that the pointer is non-null", (ptr: *mut () = ptr as *mut ()) => !ptr.is_null() ); - NonNull { pointer: ptr as _ } + transmute(ptr) } } @@ -282,7 +281,7 @@ impl NonNull { #[inline] pub const fn from_ref(r: &T) -> Self { // SAFETY: A reference cannot be null. - unsafe { NonNull { pointer: r as *const T } } + unsafe { transmute(r as *const T) } } /// Converts a mutable reference to a `NonNull` pointer. @@ -291,7 +290,7 @@ impl NonNull { #[inline] pub const fn from_mut(r: &mut T) -> Self { // SAFETY: A mutable reference cannot be null. - unsafe { NonNull { pointer: r as *mut T } } + unsafe { transmute(r as *mut T) } } /// Performs the same functionality as [`std::ptr::from_raw_parts`], except that a @@ -502,7 +501,7 @@ impl NonNull { #[inline] pub const fn cast(self) -> NonNull { // SAFETY: `self` is a `NonNull` pointer which is necessarily non-null - unsafe { NonNull { pointer: self.as_ptr() as *mut U } } + unsafe { transmute(self.as_ptr() as *mut U) } } /// Try to cast to a pointer of another type by checking alignment. @@ -581,7 +580,7 @@ impl NonNull { // Additionally safety contract of `offset` guarantees that the resulting pointer is // pointing to an allocation, there can't be an allocation at null, thus it's safe to // construct `NonNull`. - unsafe { NonNull { pointer: intrinsics::offset(self.as_ptr(), count) } } + unsafe { transmute(intrinsics::offset(self.as_ptr(), count)) } } /// Calculates the offset from a pointer in bytes. @@ -605,7 +604,7 @@ impl NonNull { // Additionally safety contract of `offset` guarantees that the resulting pointer is // pointing to an allocation, there can't be an allocation at null, thus it's safe to // construct `NonNull`. - unsafe { NonNull { pointer: self.as_ptr().byte_offset(count) } } + unsafe { transmute(self.as_ptr().byte_offset(count)) } } /// Adds an offset to a pointer (convenience for `.offset(count as isize)`). @@ -657,7 +656,7 @@ impl NonNull { // Additionally safety contract of `offset` guarantees that the resulting pointer is // pointing to an allocation, there can't be an allocation at null, thus it's safe to // construct `NonNull`. - unsafe { NonNull { pointer: intrinsics::offset(self.as_ptr(), count) } } + unsafe { transmute(intrinsics::offset(self.as_ptr(), count)) } } /// Calculates the offset from a pointer in bytes (convenience for `.byte_offset(count as isize)`). @@ -681,7 +680,7 @@ impl NonNull { // Additionally safety contract of `add` guarantees that the resulting pointer is pointing // to an allocation, there can't be an allocation at null, thus it's safe to construct // `NonNull`. - unsafe { NonNull { pointer: self.as_ptr().byte_add(count) } } + unsafe { transmute(self.as_ptr().byte_add(count)) } } /// Subtracts an offset from a pointer (convenience for @@ -763,7 +762,7 @@ impl NonNull { // Additionally safety contract of `sub` guarantees that the resulting pointer is pointing // to an allocation, there can't be an allocation at null, thus it's safe to construct // `NonNull`. - unsafe { NonNull { pointer: self.as_ptr().byte_sub(count) } } + unsafe { transmute(self.as_ptr().byte_sub(count)) } } /// Calculates the distance between two pointers within the same allocation. The returned value is in @@ -1693,9 +1692,6 @@ impl CoerceUnsized> for NonNull #[unstable(feature = "dispatch_from_dyn", issue = "none")] impl DispatchFromDyn> for NonNull where T: Unsize {} -#[stable(feature = "pin", since = "1.33.0")] -unsafe impl PinCoerceUnsized for NonNull {} - #[stable(feature = "nonnull", since = "1.25.0")] impl fmt::Debug for NonNull { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { diff --git a/core/src/ptr/unique.rs b/core/src/ptr/unique.rs index 3160c9de4b7e9..6e55f0e71bec7 100644 --- a/core/src/ptr/unique.rs +++ b/core/src/ptr/unique.rs @@ -2,7 +2,6 @@ use crate::clone::TrivialClone; use crate::fmt; use crate::marker::{PhantomData, PointeeSized, Unsize}; use crate::ops::{CoerceUnsized, DispatchFromDyn}; -use crate::pin::PinCoerceUnsized; use crate::ptr::NonNull; /// A wrapper around a raw non-null `*mut T` that indicates that the possessor @@ -176,9 +175,6 @@ impl CoerceUnsized> for Unique wh #[unstable(feature = "ptr_internals", issue = "none")] impl DispatchFromDyn> for Unique where T: Unsize {} -#[unstable(feature = "pin_coerce_unsized_trait", issue = "150112")] -unsafe impl PinCoerceUnsized for Unique {} - #[unstable(feature = "ptr_internals", issue = "none")] impl fmt::Debug for Unique { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { diff --git a/core/src/random.rs b/core/src/random.rs index 8a51fb289d8f3..06f4f30efe2b5 100644 --- a/core/src/random.rs +++ b/core/src/random.rs @@ -1,6 +1,6 @@ //! Random value generation. -use crate::range::RangeFull; +use crate::ops::RangeFull; /// A source of randomness. #[unstable(feature = "random", issue = "130703")] diff --git a/core/src/range.rs b/core/src/range.rs index 4b87d426bda76..d4be1b67d3862 100644 --- a/core/src/range.rs +++ b/core/src/range.rs @@ -1,19 +1,18 @@ -//! # Experimental replacement range types +//! # Replacement range types //! -//! The types within this module are meant to replace the existing -//! `Range`, `RangeInclusive`, and `RangeFrom` types in a future edition. +//! The types within this module are meant to replace the legacy `Range`, +//! `RangeInclusive`, `RangeToInclusive` and `RangeFrom` types in a future edition. //! //! ``` -//! #![feature(new_range_api)] -//! use core::range::{Range, RangeFrom, RangeInclusive}; +//! use core::range::{Range, RangeFrom, RangeInclusive, RangeToInclusive}; //! //! let arr = [0, 1, 2, 3, 4]; -//! assert_eq!(arr[ .. ], [0, 1, 2, 3, 4]); -//! assert_eq!(arr[ .. 3 ], [0, 1, 2 ]); -//! assert_eq!(arr[ ..=3 ], [0, 1, 2, 3 ]); -//! assert_eq!(arr[ RangeFrom::from(1.. )], [ 1, 2, 3, 4]); -//! assert_eq!(arr[ Range::from(1..3 )], [ 1, 2 ]); -//! assert_eq!(arr[RangeInclusive::from(1..=3)], [ 1, 2, 3 ]); +//! assert_eq!(arr[ .. ], [0, 1, 2, 3, 4]); +//! assert_eq!(arr[ .. 3 ], [0, 1, 2 ]); +//! assert_eq!(arr[RangeToInclusive::from( ..=3)], [0, 1, 2, 3 ]); +//! assert_eq!(arr[ RangeFrom::from(1.. )], [ 1, 2, 3, 4]); +//! assert_eq!(arr[ Range::from(1..3 )], [ 1, 2 ]); +//! assert_eq!(arr[ RangeInclusive::from(1..=3)], [ 1, 2, 3 ]); //! ``` use crate::fmt; @@ -21,17 +20,32 @@ use crate::hash::Hash; mod iter; -#[unstable(feature = "new_range_api", issue = "125687")] +#[unstable(feature = "new_range_api_legacy", issue = "125687")] pub mod legacy; -use Bound::{Excluded, Included, Unbounded}; #[doc(inline)] -pub use iter::{RangeFromIter, RangeInclusiveIter, RangeIter}; - +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] +pub use iter::RangeFromIter; #[doc(inline)] -pub use crate::iter::Step; +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] +pub use iter::RangeInclusiveIter; #[doc(inline)] -pub use crate::ops::{Bound, IntoBounds, OneSidedRange, RangeBounds, RangeFull, RangeTo}; +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] +pub use iter::RangeIter; + +// FIXME(#125687): re-exports temporarily removed +// Because re-exports of stable items (Bound, RangeBounds, RangeFull, RangeTo) +// can't be made unstable. +// +// #[doc(inline)] +// #[unstable(feature = "new_range_api", issue = "125687")] +// pub use crate::iter::Step; +// #[doc(inline)] +// #[unstable(feature = "new_range_api", issue = "125687")] +// pub use crate::ops::{Bound, IntoBounds, OneSidedRange, RangeBounds, RangeFull, RangeTo}; +use crate::iter::Step; +use crate::ops::Bound::{self, Excluded, Included, Unbounded}; +use crate::ops::{IntoBounds, OneSidedRange, OneSidedRangeBound, RangeBounds}; /// A (half-open) range bounded inclusively below and exclusively above /// (`start..end` in a future edition). @@ -42,7 +56,6 @@ pub use crate::ops::{Bound, IntoBounds, OneSidedRange, RangeBounds, RangeFull, R /// # Examples /// /// ``` -/// #![feature(new_range_api)] /// use core::range::Range; /// /// assert_eq!(Range::from(3..5), Range { start: 3, end: 5 }); @@ -51,17 +64,17 @@ pub use crate::ops::{Bound, IntoBounds, OneSidedRange, RangeBounds, RangeFull, R #[lang = "RangeCopy"] #[derive(Copy, Hash)] #[derive_const(Clone, Default, PartialEq, Eq)] -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] pub struct Range { /// The lower bound of the range (inclusive). - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] pub start: Idx, /// The upper bound of the range (exclusive). - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] pub end: Idx, } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] impl fmt::Debug for Range { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { self.start.fmt(fmt)?; @@ -79,7 +92,6 @@ impl Range { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::Range; /// /// let mut i = Range::from(3..9).iter().map(|n| n*n); @@ -87,7 +99,7 @@ impl Range { /// assert_eq!(i.next(), Some(16)); /// assert_eq!(i.next(), Some(25)); /// ``` - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] #[inline] pub fn iter(&self) -> RangeIter { self.clone().into_iter() @@ -100,7 +112,6 @@ impl> Range { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::Range; /// /// assert!(!Range::from(3..5).contains(&2)); @@ -117,7 +128,7 @@ impl> Range { /// assert!(!Range::from(f32::NAN..1.0).contains(&0.5)); /// ``` #[inline] - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -132,7 +143,6 @@ impl> Range { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::Range; /// /// assert!(!Range::from(3..5).is_empty()); @@ -143,7 +153,6 @@ impl> Range { /// The range is empty if either side is incomparable: /// /// ``` - /// #![feature(new_range_api)] /// use core::range::Range; /// /// assert!(!Range::from(3.0..5.0).is_empty()); @@ -151,7 +160,7 @@ impl> Range { /// assert!( Range::from(f32::NAN..5.0).is_empty()); /// ``` #[inline] - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn is_empty(&self) -> bool where @@ -161,7 +170,7 @@ impl> Range { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for Range { fn start_bound(&self) -> Bound<&T> { @@ -178,7 +187,7 @@ impl const RangeBounds for Range { /// If you need to use this implementation where `T` is unsized, /// consider using the `RangeBounds` impl for a 2-tuple of [`Bound<&T>`][Bound], /// i.e. replace `start..end` with `(Bound::Included(start), Bound::Excluded(end))`. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for Range<&T> { fn start_bound(&self) -> Bound<&T> { @@ -189,8 +198,7 @@ impl const RangeBounds for Range<&T> { } } -// #[unstable(feature = "range_into_bounds", issue = "136903")] -#[unstable(feature = "new_range_api", issue = "125687")] +#[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const IntoBounds for Range { fn into_bounds(self) -> (Bound, Bound) { @@ -198,7 +206,7 @@ impl const IntoBounds for Range { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] impl const From> for legacy::Range { #[inline] @@ -206,8 +214,7 @@ impl const From> for legacy::Range { Self { start: value.start, end: value.end } } } - -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] impl const From> for Range { #[inline] @@ -226,7 +233,6 @@ impl const From> for Range { /// The `start..=last` syntax is a `RangeInclusive`: /// /// ``` -/// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// assert_eq!(RangeInclusive::from(3..=5), RangeInclusive { start: 3, last: 5 }); @@ -234,17 +240,17 @@ impl const From> for Range { /// ``` #[lang = "RangeInclusiveCopy"] #[derive(Clone, Copy, PartialEq, Eq, Hash)] -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] pub struct RangeInclusive { /// The lower bound of the range (inclusive). - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] pub start: Idx, /// The upper bound of the range (inclusive). - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] pub last: Idx, } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl fmt::Debug for RangeInclusive { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { self.start.fmt(fmt)?; @@ -260,7 +266,6 @@ impl> RangeInclusive { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// assert!(!RangeInclusive::from(3..=5).contains(&2)); @@ -278,7 +283,7 @@ impl> RangeInclusive { /// assert!(!RangeInclusive::from(f32::NAN..=1.0).contains(&1.0)); /// ``` #[inline] - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -293,7 +298,6 @@ impl> RangeInclusive { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// assert!(!RangeInclusive::from(3..=5).is_empty()); @@ -304,14 +308,13 @@ impl> RangeInclusive { /// The range is empty if either side is incomparable: /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// assert!(!RangeInclusive::from(3.0..=5.0).is_empty()); /// assert!( RangeInclusive::from(3.0..=f32::NAN).is_empty()); /// assert!( RangeInclusive::from(f32::NAN..=5.0).is_empty()); /// ``` - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[inline] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn is_empty(&self) -> bool @@ -330,7 +333,6 @@ impl RangeInclusive { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// let mut i = RangeInclusive::from(3..=8).iter().map(|n| n*n); @@ -338,23 +340,14 @@ impl RangeInclusive { /// assert_eq!(i.next(), Some(16)); /// assert_eq!(i.next(), Some(25)); /// ``` - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[inline] pub fn iter(&self) -> RangeInclusiveIter { self.clone().into_iter() } } -impl RangeInclusive { - /// Converts to an exclusive `Range` for `SliceIndex` implementations. - /// The caller is responsible for dealing with `last == usize::MAX`. - #[inline] - pub(crate) const fn into_slice_range(self) -> Range { - Range { start: self.start, end: self.last + 1 } - } -} - -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for RangeInclusive { fn start_bound(&self) -> Bound<&T> { @@ -371,7 +364,7 @@ impl const RangeBounds for RangeInclusive { /// If you need to use this implementation where `T` is unsized, /// consider using the `RangeBounds` impl for a 2-tuple of [`Bound<&T>`][Bound], /// i.e. replace `start..=end` with `(Bound::Included(start), Bound::Included(end))`. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for RangeInclusive<&T> { fn start_bound(&self) -> Bound<&T> { @@ -382,8 +375,8 @@ impl const RangeBounds for RangeInclusive<&T> { } } -// #[unstable(feature = "range_into_bounds", issue = "136903")] -#[unstable(feature = "new_range_api", issue = "125687")] +// #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] +#[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const IntoBounds for RangeInclusive { fn into_bounds(self) -> (Bound, Bound) { @@ -391,7 +384,7 @@ impl const IntoBounds for RangeInclusive { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] impl const From> for legacy::RangeInclusive { #[inline] @@ -399,7 +392,7 @@ impl const From> for legacy::RangeInclusive { Self::new(value.start, value.last) } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] impl const From> for RangeInclusive { #[inline] @@ -418,14 +411,13 @@ impl const From> for RangeInclusive { /// /// The `RangeFrom` `start..` contains all values with `x >= start`. /// -/// *Note*: Overflow in the [`Iterator`] implementation (when the contained +/// *Note*: Overflow in the [`IntoIterator`] implementation (when the contained /// data type reaches its numerical limit) is allowed to panic, wrap, or /// saturate. This behavior is defined by the implementation of the [`Step`] /// trait. For primitive integers, this follows the normal rules, and respects -/// the overflow checks profile (panic in debug, wrap in release). Note also -/// that overflow happens earlier than you might assume: the overflow happens -/// in the call to `next` that yields the maximum value, as the range must be -/// set to a state to yield the next value. +/// the overflow checks profile (panic in debug, wrap in release). Unlike +/// its legacy counterpart, the iterator will only panic after yielding the +/// maximum value when overflow checks are enabled. /// /// [`Step`]: crate::iter::Step /// @@ -434,7 +426,6 @@ impl const From> for RangeInclusive { /// The `start..` syntax is a `RangeFrom`: /// /// ``` -/// #![feature(new_range_api)] /// use core::range::RangeFrom; /// /// assert_eq!(RangeFrom::from(2..), core::range::RangeFrom { start: 2 }); @@ -443,14 +434,14 @@ impl const From> for RangeInclusive { #[lang = "RangeFromCopy"] #[derive(Copy, Hash)] #[derive_const(Clone, PartialEq, Eq)] -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] pub struct RangeFrom { /// The lower bound of the range (inclusive). - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] pub start: Idx, } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] impl fmt::Debug for RangeFrom { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { self.start.fmt(fmt)?; @@ -467,7 +458,6 @@ impl RangeFrom { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeFrom; /// /// let mut i = RangeFrom::from(3..).iter().map(|n| n*n); @@ -475,7 +465,7 @@ impl RangeFrom { /// assert_eq!(i.next(), Some(16)); /// assert_eq!(i.next(), Some(25)); /// ``` - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] #[inline] pub fn iter(&self) -> RangeFromIter { self.clone().into_iter() @@ -488,7 +478,6 @@ impl> RangeFrom { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeFrom; /// /// assert!(!RangeFrom::from(3..).contains(&2)); @@ -500,7 +489,7 @@ impl> RangeFrom { /// assert!(!RangeFrom::from(f32::NAN..).contains(&0.5)); /// ``` #[inline] - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -511,7 +500,7 @@ impl> RangeFrom { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for RangeFrom { fn start_bound(&self) -> Bound<&T> { @@ -528,7 +517,7 @@ impl const RangeBounds for RangeFrom { /// If you need to use this implementation where `T` is unsized, /// consider using the `RangeBounds` impl for a 2-tuple of [`Bound<&T>`][Bound], /// i.e. replace `start..` with `(Bound::Included(start), Bound::Unbounded)`. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for RangeFrom<&T> { fn start_bound(&self) -> Bound<&T> { @@ -539,8 +528,7 @@ impl const RangeBounds for RangeFrom<&T> { } } -// #[unstable(feature = "range_into_bounds", issue = "136903")] -#[unstable(feature = "new_range_api", issue = "125687")] +#[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const IntoBounds for RangeFrom { fn into_bounds(self) -> (Bound, Bound) { @@ -548,7 +536,18 @@ impl const IntoBounds for RangeFrom { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[unstable(feature = "one_sided_range", issue = "69780")] +#[rustc_const_unstable(feature = "const_range", issue = "none")] +impl const OneSidedRange for RangeFrom +where + Self: RangeBounds, +{ + fn bound(self) -> (OneSidedRangeBound, T) { + (OneSidedRangeBound::StartInclusive, self.start) + } +} + +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] impl const From> for legacy::RangeFrom { #[inline] @@ -556,7 +555,7 @@ impl const From> for legacy::RangeFrom { Self { start: value.start } } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] impl const From> for RangeFrom { #[inline] @@ -574,10 +573,9 @@ impl const From> for RangeFrom { /// /// The `..=last` syntax is a `RangeToInclusive`: /// -/// ``` -/// #![feature(new_range_api)] +/// ```standalone_crate /// #![feature(new_range)] -/// assert_eq!((..=5), std::range::RangeToInclusive{ last: 5 }); +/// assert_eq!((..=5), std::range::RangeToInclusive { last: 5 }); /// ``` /// /// It does not have an [`IntoIterator`] implementation, so you can't use it in a @@ -608,14 +606,14 @@ impl const From> for RangeFrom { #[lang = "RangeToInclusiveCopy"] #[doc(alias = "..=")] #[derive(Copy, Clone, PartialEq, Eq, Hash)] -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] pub struct RangeToInclusive { /// The upper bound of the range (inclusive) - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] pub last: Idx, } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] impl fmt::Debug for RangeToInclusive { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { write!(fmt, "..=")?; @@ -639,7 +637,7 @@ impl> RangeToInclusive { /// assert!(!(..=f32::NAN).contains(&0.5)); /// ``` #[inline] - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -650,12 +648,13 @@ impl> RangeToInclusive { } } +#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] impl From> for RangeToInclusive { fn from(value: legacy::RangeToInclusive) -> Self { Self { last: value.end } } } - +#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] impl From> for legacy::RangeToInclusive { fn from(value: RangeToInclusive) -> Self { Self { end: value.last } @@ -665,7 +664,7 @@ impl From> for legacy::RangeToInclusive { // RangeToInclusive cannot impl From> // because underflow would be possible with (..0).into() -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for RangeToInclusive { fn start_bound(&self) -> Bound<&T> { @@ -676,6 +675,17 @@ impl const RangeBounds for RangeToInclusive { } } +#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[rustc_const_unstable(feature = "const_range", issue = "none")] +impl const RangeBounds for RangeToInclusive<&T> { + fn start_bound(&self) -> Bound<&T> { + Unbounded + } + fn end_bound(&self) -> Bound<&T> { + Included(self.last) + } +} + #[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const IntoBounds for RangeToInclusive { @@ -683,3 +693,14 @@ impl const IntoBounds for RangeToInclusive { (Unbounded, Included(self.last)) } } + +#[unstable(feature = "one_sided_range", issue = "69780")] +#[rustc_const_unstable(feature = "const_range", issue = "none")] +impl const OneSidedRange for RangeToInclusive +where + Self: RangeBounds, +{ + fn bound(self) -> (OneSidedRangeBound, T) { + (OneSidedRangeBound::EndInclusive, self.last) + } +} diff --git a/core/src/range/iter.rs b/core/src/range/iter.rs index 6fe5d9b34361a..a5db3699bc402 100644 --- a/core/src/range/iter.rs +++ b/core/src/range/iter.rs @@ -6,12 +6,27 @@ use crate::range::{Range, RangeFrom, RangeInclusive, legacy}; use crate::{intrinsics, mem}; /// By-value [`Range`] iterator. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] #[derive(Debug, Clone)] pub struct RangeIter(legacy::Range); impl RangeIter { + #[unstable(feature = "new_range_remainder", issue = "154458")] /// Returns the remainder of the range being iterated over. + /// + /// # Examples + /// + /// ``` + /// #![feature(new_range_remainder)] + /// + /// let range = core::range::Range::from(3..11); + /// let mut iter = range.into_iter(); + /// assert_eq!(iter.clone().remainder(), range); + /// iter.next(); + /// assert_eq!(iter.clone().remainder(), core::range::Range::from(4..11)); + /// iter.by_ref().for_each(drop); + /// assert!(iter.remainder().is_empty()); + /// ``` pub fn remainder(self) -> Range { Range { start: self.0.start, end: self.0.end } } @@ -49,7 +64,7 @@ unsafe_range_trusted_random_access_impl! { u64 i64 } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] impl Iterator for RangeIter { type Item = A; @@ -117,7 +132,7 @@ impl Iterator for RangeIter { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] impl DoubleEndedIterator for RangeIter { #[inline] fn next_back(&mut self) -> Option { @@ -138,10 +153,10 @@ impl DoubleEndedIterator for RangeIter { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RangeIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] impl FusedIterator for RangeIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] impl IntoIterator for Range { type Item = A; type IntoIter = RangeIter; @@ -152,7 +167,7 @@ impl IntoIterator for Range { } /// By-value [`RangeInclusive`] iterator. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[derive(Debug, Clone)] pub struct RangeInclusiveIter(legacy::RangeInclusive); @@ -160,6 +175,21 @@ impl RangeInclusiveIter { /// Returns the remainder of the range being iterated over. /// /// If the iterator is exhausted or empty, returns `None`. + /// + /// # Examples + /// + /// ``` + /// #![feature(new_range_remainder)] + /// + /// let range = core::range::RangeInclusive::from(3..=11); + /// let mut iter = range.into_iter(); + /// assert_eq!(iter.clone().remainder().unwrap(), range); + /// iter.next(); + /// assert_eq!(iter.clone().remainder().unwrap(), core::range::RangeInclusive::from(4..=11)); + /// iter.by_ref().for_each(drop); + /// assert!(iter.remainder().is_none()); + /// ``` + #[unstable(feature = "new_range_remainder", issue = "154458")] pub fn remainder(self) -> Option> { if self.0.is_empty() { return None; @@ -169,7 +199,7 @@ impl RangeInclusiveIter { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl Iterator for RangeInclusiveIter { type Item = A; @@ -225,7 +255,7 @@ impl Iterator for RangeInclusiveIter { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl DoubleEndedIterator for RangeInclusiveIter { #[inline] fn next_back(&mut self) -> Option { @@ -246,10 +276,10 @@ impl DoubleEndedIterator for RangeInclusiveIter { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RangeInclusiveIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl FusedIterator for RangeInclusiveIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl IntoIterator for RangeInclusive { type Item = A; type IntoIter = RangeInclusiveIter; @@ -269,14 +299,14 @@ impl IntoIterator for RangeInclusive { // since e.g. `(0..=u64::MAX).len()` would be `u64::MAX + 1`. macro_rules! range_exact_iter_impl { ($($t:ty)*) => ($( - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] impl ExactSizeIterator for RangeIter<$t> { } )*) } macro_rules! range_incl_exact_iter_impl { ($($t:ty)*) => ($( - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl ExactSizeIterator for RangeInclusiveIter<$t> { } )*) } @@ -292,45 +322,75 @@ range_incl_exact_iter_impl! { } /// By-value [`RangeFrom`] iterator. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] #[derive(Debug, Clone)] pub struct RangeFromIter { start: A, - /// Whether the first element of the iterator has yielded. + /// Whether the maximum value of the iterator has yielded. /// Only used when overflow checks are enabled. - first: bool, + exhausted: bool, } impl RangeFromIter { /// Returns the remainder of the range being iterated over. + /// + /// # Examples + /// + /// ``` + /// #![feature(new_range_remainder)] + /// + /// let range = core::range::RangeFrom::from(3..); + /// let mut iter = range.into_iter(); + /// assert_eq!(iter.clone().remainder(), range); + /// iter.next(); + /// assert_eq!(iter.remainder(), core::range::RangeFrom::from(4..)); + /// ``` #[inline] #[rustc_inherit_overflow_checks] + #[unstable(feature = "new_range_remainder", issue = "154458")] pub fn remainder(self) -> RangeFrom { - if intrinsics::overflow_checks() { - if !self.first { - return RangeFrom { start: Step::forward(self.start, 1) }; - } + // Need to handle this case even if overflow-checks are disabled, + // because a `RangeFromIter` could be exhausted in a crate with + // overflow-checks enabled, but then passed to a crate with them + // disabled before this is called. + if self.exhausted { + return RangeFrom { start: Step::forward(self.start, 1) }; } RangeFrom { start: self.start } } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] impl Iterator for RangeFromIter { type Item = A; #[inline] #[rustc_inherit_overflow_checks] fn next(&mut self) -> Option { + if self.exhausted { + // This should panic if overflow checks are enabled, since + // `forward_checked` returned `None` in prior iteration. + self.start = Step::forward(self.start.clone(), 1); + + // If we get here, if means this iterator was exhausted by a crate + // with overflow-checks enabled, but now we're iterating in a crate with + // overflow-checks disabled. Since we successfully incremented `self.start` + // above (in many cases this will wrap around to MIN), we now unset + // the flag so we don't repeat this process in the next iteration. + // + // This could also happen if `forward_checked` returned None but + // (for whatever reason, not applicable to any std implementors) + // `forward` doesn't panic when overflow-checks are enabled. In that + // case, this is also the correct behavior. + self.exhausted = false; + } if intrinsics::overflow_checks() { - if self.first { - self.first = false; + let Some(n) = Step::forward_checked(self.start.clone(), 1) else { + self.exhausted = true; return Some(self.start.clone()); - } - - self.start = Step::forward(self.start.clone(), 1); - return Some(self.start.clone()); + }; + return Some(mem::replace(&mut self.start, n)); } let n = Step::forward(self.start.clone(), 1); @@ -345,18 +405,22 @@ impl Iterator for RangeFromIter { #[inline] #[rustc_inherit_overflow_checks] fn nth(&mut self, n: usize) -> Option { + // Typically `forward` will cause an overflow-check panic here, + // but unset the exhausted flag to handle the uncommon cases. + // See the comments in `next` for more details. + if self.exhausted { + self.start = Step::forward(self.start.clone(), 1); + self.exhausted = false; + } if intrinsics::overflow_checks() { - if self.first { - self.first = false; - - let plus_n = Step::forward(self.start.clone(), n); + let plus_n = Step::forward(self.start.clone(), n); + if let Some(plus_n1) = Step::forward_checked(plus_n.clone(), 1) { + self.start = plus_n1; + } else { self.start = plus_n.clone(); - return Some(plus_n); + self.exhausted = true; } - - let plus_n = Step::forward(self.start.clone(), n); - self.start = Step::forward(plus_n.clone(), 1); - return Some(self.start.clone()); + return Some(plus_n); } let plus_n = Step::forward(self.start.clone(), n); @@ -368,15 +432,15 @@ impl Iterator for RangeFromIter { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RangeFromIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] impl FusedIterator for RangeFromIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] impl IntoIterator for RangeFrom { type Item = A; type IntoIter = RangeFromIter; fn into_iter(self) -> Self::IntoIter { - RangeFromIter { start: self.start, first: true } + RangeFromIter { start: self.start, exhausted: false } } } diff --git a/core/src/slice/cmp.rs b/core/src/slice/cmp.rs index 2390ca74a8e09..69a01eef88f97 100644 --- a/core/src/slice/cmp.rs +++ b/core/src/slice/cmp.rs @@ -3,7 +3,9 @@ use super::{from_raw_parts, memchr}; use crate::ascii; use crate::cmp::{self, BytewiseEq, Ordering}; +use crate::convert::Infallible; use crate::intrinsics::compare_bytes; +use crate::marker::Destruct; use crate::mem::SizedTypeProperties; use crate::num::NonZero; use crate::ops::ControlFlow; @@ -33,7 +35,8 @@ impl const Eq for [T] {} /// Implements comparison of slices [lexicographically](Ord#lexicographical-comparison). #[stable(feature = "rust1", since = "1.0.0")] -impl Ord for [T] { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const Ord for [T] { fn cmp(&self, other: &[T]) -> Ordering { SliceOrd::compare(self, other) } @@ -52,7 +55,8 @@ const fn as_underlying(x: ControlFlow) -> u8 { /// Implements comparison of slices [lexicographically](Ord#lexicographical-comparison). #[stable(feature = "rust1", since = "1.0.0")] -impl PartialOrd for [T] { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const PartialOrd for [T] { #[inline] fn partial_cmp(&self, other: &[T]) -> Option { SlicePartialOrd::partial_compare(self, other) @@ -175,19 +179,31 @@ const trait SliceChain: Sized { type AlwaysBreak = ControlFlow; -impl SlicePartialOrd for A { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const SlicePartialOrd for A { default fn partial_compare(left: &[A], right: &[A]) -> Option { - let elem_chain = |a, b| match PartialOrd::partial_cmp(a, b) { - Some(Ordering::Equal) => ControlFlow::Continue(()), - non_eq => ControlFlow::Break(non_eq), - }; - let len_chain = |a: &_, b: &_| ControlFlow::Break(usize::partial_cmp(a, b)); + // FIXME(const-hack): revert this to a const closure once possible + #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] + const fn elem_chain(a: &A, b: &A) -> ControlFlow> { + match PartialOrd::partial_cmp(a, b) { + Some(Ordering::Equal) => ControlFlow::Continue(()), + non_eq => ControlFlow::Break(non_eq), + } + } + + // FIXME(const-hack): revert this to a const closure once possible + #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] + const fn len_chain(a: &usize, b: &usize) -> ControlFlow, Infallible> { + ControlFlow::Break(usize::partial_cmp(a, b)) + } + let AlwaysBreak::Break(b) = chaining_impl(left, right, elem_chain, len_chain); b } } -impl SliceChain for A { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const SliceChain for A { default fn chaining_lt(left: &[Self], right: &[Self]) -> ControlFlow { chaining_impl(left, right, PartialOrd::__chaining_lt, usize::__chaining_lt) } @@ -202,12 +218,13 @@ impl SliceChain for A { } } +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] #[inline] -fn chaining_impl<'l, 'r, A: PartialOrd, B, C>( +const fn chaining_impl<'l, 'r, A: PartialOrd, B, C>( left: &'l [A], right: &'r [A], - elem_chain: impl Fn(&'l A, &'r A) -> ControlFlow, - len_chain: impl for<'a> FnOnce(&'a usize, &'a usize) -> ControlFlow, + elem_chain: impl [const] Fn(&'l A, &'r A) -> ControlFlow + [const] Destruct, + len_chain: impl for<'a> [const] FnOnce(&'a usize, &'a usize) -> ControlFlow + [const] Destruct, ) -> ControlFlow { let l = cmp::min(left.len(), right.len()); @@ -216,8 +233,11 @@ fn chaining_impl<'l, 'r, A: PartialOrd, B, C>( let lhs = &left[..l]; let rhs = &right[..l]; - for i in 0..l { + // FIXME(const-hack): revert this to `for i in 0..l` once `impl const Iterator for Range` + let mut i: usize = 0; + while i < l { elem_chain(&lhs[i], &rhs[i])?; + i += 1; } len_chain(&left.len(), &right.len()) @@ -270,13 +290,24 @@ const trait SliceOrd: Sized { fn compare(left: &[Self], right: &[Self]) -> Ordering; } -impl SliceOrd for A { +#[rustc_const_unstable(feature = "const_cmp", issue = "143800")] +impl const SliceOrd for A { default fn compare(left: &[Self], right: &[Self]) -> Ordering { - let elem_chain = |a, b| match Ord::cmp(a, b) { - Ordering::Equal => ControlFlow::Continue(()), - non_eq => ControlFlow::Break(non_eq), - }; - let len_chain = |a: &_, b: &_| ControlFlow::Break(usize::cmp(a, b)); + // FIXME(const-hack): revert this to a const closure once possible + #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] + const fn elem_chain(a: &A, b: &A) -> ControlFlow { + match Ord::cmp(a, b) { + Ordering::Equal => ControlFlow::Continue(()), + non_eq => ControlFlow::Break(non_eq), + } + } + + // FIXME(const-hack): revert this to a const closure once possible + #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] + const fn len_chain(a: &usize, b: &usize) -> ControlFlow { + ControlFlow::Break(usize::cmp(a, b)) + } + let AlwaysBreak::Break(b) = chaining_impl(left, right, elem_chain, len_chain); b } diff --git a/core/src/slice/index.rs b/core/src/slice/index.rs index 59802989c18fb..f1727a1f629cb 100644 --- a/core/src/slice/index.rs +++ b/core/src/slice/index.rs @@ -125,13 +125,13 @@ mod private_slice_index { #[stable(feature = "slice_index_with_ops_bound_pair", since = "1.53.0")] impl Sealed for (ops::Bound, ops::Bound) {} - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] impl Sealed for range::Range {} - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "1.95.0")] impl Sealed for range::RangeInclusive {} - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] impl Sealed for range::RangeToInclusive {} - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] impl Sealed for range::RangeFrom {} impl Sealed for ops::IndexRange {} @@ -458,7 +458,7 @@ unsafe impl const SliceIndex<[T]> for ops::Range { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex<[T]> for range::Range { type Output = [T]; @@ -588,7 +588,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeFrom { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex<[T]> for range::RangeFrom { type Output = [T]; @@ -663,7 +663,6 @@ unsafe impl const SliceIndex<[T]> for ops::RangeFull { } /// The methods `index` and `index_mut` panic if: -/// - the end of the range is `usize::MAX` or /// - the start of the range is greater than the end of the range or /// - the end of the range is out of bounds. #[stable(feature = "inclusive_range", since = "1.26.0")] @@ -673,12 +672,12 @@ unsafe impl const SliceIndex<[T]> for ops::RangeInclusive { #[inline] fn get(self, slice: &[T]) -> Option<&[T]> { - if *self.end() == usize::MAX { None } else { self.into_slice_range().get(slice) } + if *self.end() >= slice.len() { None } else { self.into_slice_range().get(slice) } } #[inline] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { - if *self.end() == usize::MAX { None } else { self.into_slice_range().get_mut(slice) } + if *self.end() >= slice.len() { None } else { self.into_slice_range().get_mut(slice) } } #[inline] @@ -724,7 +723,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeInclusive { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex<[T]> for range::RangeInclusive { type Output = [T]; @@ -802,7 +801,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeToInclusive { } /// The methods `index` and `index_mut` panic if the end of the range is out of bounds. -#[stable(feature = "inclusive_range", since = "1.26.0")] +#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex<[T]> for range::RangeToInclusive { type Output = [T]; @@ -950,8 +949,7 @@ where R: ops::RangeBounds, { let len = bounds.end; - let r = into_range(len, (range.start_bound().copied(), range.end_bound().copied()))?; - if r.start > r.end || r.end > len { None } else { Some(r) } + try_into_slice_range(len, (range.start_bound().copied(), range.end_bound().copied())) } /// Converts a pair of `ops::Bound`s into `ops::Range` without performing any @@ -978,25 +976,31 @@ pub(crate) const fn into_range_unchecked( /// Returns `None` on overflowing indices. #[rustc_const_unstable(feature = "const_range", issue = "none")] #[inline] -pub(crate) const fn into_range( +pub(crate) const fn try_into_slice_range( len: usize, (start, end): (ops::Bound, ops::Bound), ) -> Option> { - use ops::Bound; - let start = match start { - Bound::Included(start) => start, - Bound::Excluded(start) => start.checked_add(1)?, - Bound::Unbounded => 0, - }; - let end = match end { - Bound::Included(end) => end.checked_add(1)?, - Bound::Excluded(end) => end, - Bound::Unbounded => len, + ops::Bound::Included(end) if end >= len => return None, + // Cannot overflow because `end < len` implies `end < usize::MAX`. + ops::Bound::Included(end) => end + 1, + + ops::Bound::Excluded(end) if end > len => return None, + ops::Bound::Excluded(end) => end, + + ops::Bound::Unbounded => len, }; - // Don't bother with checking `start < end` and `end <= len` - // since these checks are handled by `Range` impls + let start = match start { + ops::Bound::Excluded(start) if start >= end => return None, + // Cannot overflow because `start < end` implies `start < usize::MAX`. + ops::Bound::Excluded(start) => start + 1, + + ops::Bound::Included(start) if start > end => return None, + ops::Bound::Included(start) => start, + + ops::Bound::Unbounded => 0, + }; Some(start..end) } @@ -1039,12 +1043,12 @@ unsafe impl SliceIndex<[T]> for (ops::Bound, ops::Bound) { #[inline] fn get(self, slice: &[T]) -> Option<&Self::Output> { - into_range(slice.len(), self)?.get(slice) + try_into_slice_range(slice.len(), self)?.get(slice) } #[inline] fn get_mut(self, slice: &mut [T]) -> Option<&mut Self::Output> { - into_range(slice.len(), self)?.get_mut(slice) + try_into_slice_range(slice.len(), self)?.get_mut(slice) } #[inline] diff --git a/core/src/slice/iter.rs b/core/src/slice/iter.rs index a289b0d6df401..ac096afb38af0 100644 --- a/core/src/slice/iter.rs +++ b/core/src/slice/iter.rs @@ -2175,7 +2175,7 @@ unsafe impl Sync for ChunksExactMut<'_, T> where T: Sync {} /// /// [`array_windows`]: slice::array_windows /// [slices]: slice -#[derive(Debug, Clone, Copy)] +#[derive(Debug)] #[stable(feature = "array_windows", since = "1.94.0")] #[must_use = "iterators are lazy and do nothing unless consumed"] pub struct ArrayWindows<'a, T: 'a, const N: usize> { @@ -2189,6 +2189,14 @@ impl<'a, T: 'a, const N: usize> ArrayWindows<'a, T, N> { } } +// FIXME(#26925) Remove in favor of `#[derive(Clone)]` +#[stable(feature = "array_windows", since = "1.94.0")] +impl Clone for ArrayWindows<'_, T, N> { + fn clone(&self) -> Self { + Self { v: self.v } + } +} + #[stable(feature = "array_windows", since = "1.94.0")] impl<'a, T, const N: usize> Iterator for ArrayWindows<'a, T, N> { type Item = &'a [T; N]; @@ -2224,6 +2232,14 @@ impl<'a, T, const N: usize> Iterator for ArrayWindows<'a, T, N> { fn last(self) -> Option { self.v.last_chunk() } + + unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item { + // SAFETY: since the caller guarantees that `idx` is in bounds, + // which means that `idx` cannot overflow an `isize`, and the + // "slice" created by `cast_array` is a subslice of `self.v` + // thus is guaranteed to be valid for the lifetime `'a` of `self.v`. + unsafe { &*self.v.as_ptr().add(idx).cast_array() } + } } #[stable(feature = "array_windows", since = "1.94.0")] @@ -2252,6 +2268,22 @@ impl ExactSizeIterator for ArrayWindows<'_, T, N> { } } +#[unstable(feature = "trusted_len", issue = "37572")] +unsafe impl TrustedLen for ArrayWindows<'_, T, N> {} + +#[stable(feature = "array_windows", since = "1.94.0")] +impl FusedIterator for ArrayWindows<'_, T, N> {} + +#[doc(hidden)] +#[unstable(feature = "trusted_random_access", issue = "none")] +unsafe impl TrustedRandomAccess for ArrayWindows<'_, T, N> {} + +#[doc(hidden)] +#[unstable(feature = "trusted_random_access", issue = "none")] +unsafe impl TrustedRandomAccessNoCoerce for ArrayWindows<'_, T, N> { + const MAY_HAVE_SIDE_EFFECT: bool = false; +} + /// An iterator over a slice in (non-overlapping) chunks (`chunk_size` elements at a /// time), starting at the end of the slice. /// diff --git a/core/src/str/iter.rs b/core/src/str/iter.rs index d2985d8a18669..283aa9a6a73ae 100644 --- a/core/src/str/iter.rs +++ b/core/src/str/iter.rs @@ -99,9 +99,6 @@ impl<'a> Iterator for Chars<'a> { #[inline] fn size_hint(&self) -> (usize, Option) { let len = self.iter.len(); - // `(len + 3)` can't overflow, because we know that the `slice::Iter` - // belongs to a slice in memory which has a maximum length of - // `isize::MAX` (that's well below `usize::MAX`). (len.div_ceil(4), Some(len)) } @@ -1528,9 +1525,6 @@ impl<'a> Iterator for EncodeUtf16<'a> { // is therefore determined by assuming the remaining bytes contain as // many 3-byte sequences as possible. The highest bytes:code units // ratio is for 1-byte sequences, so use this for the upper bound. - // `(len + 2)` can't overflow, because we know that the `slice::Iter` - // belongs to a slice in memory which has a maximum length of - // `isize::MAX` (that's well below `usize::MAX`) if self.extra == 0 { (len.div_ceil(3), Some(len)) } else { diff --git a/core/src/str/mod.rs b/core/src/str/mod.rs index ab7389a1300c5..0d52bfb8c9aa4 100644 --- a/core/src/str/mod.rs +++ b/core/src/str/mod.rs @@ -81,38 +81,50 @@ const fn slice_error_fail_ct(_: &str, _: usize, _: usize) -> ! { #[track_caller] fn slice_error_fail_rt(s: &str, begin: usize, end: usize) -> ! { - const MAX_DISPLAY_LENGTH: usize = 256; - let trunc_len = s.floor_char_boundary(MAX_DISPLAY_LENGTH); - let s_trunc = &s[..trunc_len]; - let ellipsis = if trunc_len < s.len() { "[...]" } else { "" }; - - // 1. out of bounds - if begin > s.len() || end > s.len() { - let oob_index = if begin > s.len() { begin } else { end }; - panic!("byte index {oob_index} is out of bounds of `{s_trunc}`{ellipsis}"); - } - - // 2. begin <= end - assert!( - begin <= end, - "begin <= end ({} <= {}) when slicing `{}`{}", - begin, - end, - s_trunc, - ellipsis - ); - - // 3. character boundary - let index = if !s.is_char_boundary(begin) { begin } else { end }; - // find the character - let char_start = s.floor_char_boundary(index); - // `char_start` must be less than len and a char boundary - let ch = s[char_start..].chars().next().unwrap(); - let char_range = char_start..char_start + ch.len_utf8(); - panic!( - "byte index {} is not a char boundary; it is inside {:?} (bytes {:?}) of `{}`{}", - index, ch, char_range, s_trunc, ellipsis - ); + let len = s.len(); + + // 1. begin is OOB. + if begin > len { + panic!("start byte index {begin} is out of bounds for string of length {len}"); + } + + // 2. end is OOB. + if end > len { + panic!("end byte index {end} is out of bounds for string of length {len}"); + } + + // 3. range is backwards. + if begin > end { + panic!("byte range starts at {begin} but ends at {end}"); + } + + // 4. begin is inside a character. + if !s.is_char_boundary(begin) { + let floor = s.floor_char_boundary(begin); + let ceil = s.ceil_char_boundary(begin); + let range = floor..ceil; + let ch = s[floor..ceil].chars().next().unwrap(); + panic!( + "start byte index {begin} is not a char boundary; it is inside {ch:?} (bytes {range:?} of string)" + ) + } + + // 5. end is inside a character. + if !s.is_char_boundary(end) { + let floor = s.floor_char_boundary(end); + let ceil = s.ceil_char_boundary(end); + let range = floor..ceil; + let ch = s[floor..ceil].chars().next().unwrap(); + panic!( + "end byte index {end} is not a char boundary; it is inside {ch:?} (bytes {range:?} of string)" + ) + } + + // 6. end is OOB and range is inclusive (end == len). + // This test cannot be combined with 2. above because for cases like + // `"abcαβγ"[4..9]` the error is that 4 is inside 'α', not that 9 is OOB. + debug_assert_eq!(end, len); + panic!("end byte index {end} is out of bounds for string of length {len}"); } impl str { diff --git a/core/src/str/pattern.rs b/core/src/str/pattern.rs index b54522fcc886f..25202ffd67313 100644 --- a/core/src/str/pattern.rs +++ b/core/src/str/pattern.rs @@ -997,7 +997,8 @@ impl<'b> Pattern for &'b str { #[cfg(any( all(target_arch = "x86_64", target_feature = "sse2"), - all(target_arch = "loongarch64", target_feature = "lsx") + all(target_arch = "loongarch64", target_feature = "lsx"), + all(target_arch = "aarch64", target_feature = "neon") ))] if self.len() <= 32 { if let Some(result) = simd_contains(self, haystack) { @@ -1782,7 +1783,8 @@ impl TwoWayStrategy for RejectAndMatch { /// [0]: http://0x80.pl/articles/simd-strfind.html#sse-avx2 #[cfg(any( all(target_arch = "x86_64", target_feature = "sse2"), - all(target_arch = "loongarch64", target_feature = "lsx") + all(target_arch = "loongarch64", target_feature = "lsx"), + all(target_arch = "aarch64", target_feature = "neon") ))] #[inline] fn simd_contains(needle: &str, haystack: &str) -> Option { @@ -1917,7 +1919,8 @@ fn simd_contains(needle: &str, haystack: &str) -> Option { /// Both slices must have the same length. #[cfg(any( all(target_arch = "x86_64", target_feature = "sse2"), - all(target_arch = "loongarch64", target_feature = "lsx") + all(target_arch = "loongarch64", target_feature = "lsx"), + all(target_arch = "aarch64", target_feature = "neon") ))] #[inline] unsafe fn small_slice_eq(x: &[u8], y: &[u8]) -> bool { diff --git a/core/src/str/traits.rs b/core/src/str/traits.rs index a7cc943994c53..da0039f055fde 100644 --- a/core/src/str/traits.rs +++ b/core/src/str/traits.rs @@ -76,13 +76,6 @@ where } } -#[inline(never)] -#[cold] -#[track_caller] -const fn str_index_overflow_fail() -> ! { - panic!("attempted to index str up to maximum usize"); -} - /// Implements substring slicing with syntax `&self[..]` or `&mut self[..]`. /// /// Returns a slice of the whole string, i.e., returns `&self` or `&mut @@ -265,7 +258,7 @@ unsafe impl const SliceIndex for ops::Range { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex for range::Range { type Output = str; @@ -389,12 +382,12 @@ unsafe impl SliceIndex for (ops::Bound, ops::Bound) { #[inline] fn get(self, slice: &str) -> Option<&str> { - crate::slice::index::into_range(slice.len(), self)?.get(slice) + crate::slice::index::try_into_slice_range(slice.len(), self)?.get(slice) } #[inline] fn get_mut(self, slice: &mut str) -> Option<&mut str> { - crate::slice::index::into_range(slice.len(), self)?.get_mut(slice) + crate::slice::index::try_into_slice_range(slice.len(), self)?.get_mut(slice) } #[inline] @@ -562,7 +555,7 @@ unsafe impl const SliceIndex for ops::RangeFrom { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_from_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex for range::RangeFrom { type Output = str; @@ -640,11 +633,11 @@ unsafe impl const SliceIndex for ops::RangeInclusive { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { - if *self.end() == usize::MAX { None } else { self.into_slice_range().get(slice) } + if *self.end() >= slice.len() { None } else { self.into_slice_range().get(slice) } } #[inline] fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> { - if *self.end() == usize::MAX { None } else { self.into_slice_range().get_mut(slice) } + if *self.end() >= slice.len() { None } else { self.into_slice_range().get_mut(slice) } } #[inline] unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output { @@ -658,55 +651,69 @@ unsafe impl const SliceIndex for ops::RangeInclusive { } #[inline] fn index(self, slice: &str) -> &Self::Output { - if *self.end() == usize::MAX { - str_index_overflow_fail(); + let Self { mut start, mut end, exhausted } = self; + let len = slice.len(); + if end < len { + end = end + 1; + start = if exhausted { end } else { start }; + if start <= end && slice.is_char_boundary(start) && slice.is_char_boundary(end) { + // SAFETY: just checked that `start` and `end` are on a char boundary, + // and we are passing in a safe reference, so the return value will also be one. + // We also checked char boundaries, so this is valid UTF-8. + unsafe { return &*(start..end).get_unchecked(slice) } + } } - self.into_slice_range().index(slice) + + super::slice_error_fail(slice, start, end) } #[inline] fn index_mut(self, slice: &mut str) -> &mut Self::Output { - if *self.end() == usize::MAX { - str_index_overflow_fail(); + let Self { mut start, mut end, exhausted } = self; + let len = slice.len(); + if end < len { + end = end + 1; + start = if exhausted { end } else { start }; + if start <= end && slice.is_char_boundary(start) && slice.is_char_boundary(end) { + // SAFETY: just checked that `start` and `end` are on a char boundary, + // and we are passing in a safe reference, so the return value will also be one. + // We also checked char boundaries, so this is valid UTF-8. + unsafe { return &mut *(start..end).get_unchecked_mut(slice) } + } } - self.into_slice_range().index_mut(slice) + + super::slice_error_fail(slice, start, end) } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "1.95.0")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex for range::RangeInclusive { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { - if self.last == usize::MAX { None } else { self.into_slice_range().get(slice) } + ops::RangeInclusive::from(self).get(slice) } #[inline] fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> { - if self.last == usize::MAX { None } else { self.into_slice_range().get_mut(slice) } + ops::RangeInclusive::from(self).get_mut(slice) } #[inline] unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output { // SAFETY: the caller must uphold the safety contract for `get_unchecked`. - unsafe { self.into_slice_range().get_unchecked(slice) } + unsafe { ops::RangeInclusive::from(self).get_unchecked(slice) } } #[inline] unsafe fn get_unchecked_mut(self, slice: *mut str) -> *mut Self::Output { // SAFETY: the caller must uphold the safety contract for `get_unchecked_mut`. - unsafe { self.into_slice_range().get_unchecked_mut(slice) } + unsafe { ops::RangeInclusive::from(self).get_unchecked_mut(slice) } } #[inline] fn index(self, slice: &str) -> &Self::Output { - if self.last == usize::MAX { - str_index_overflow_fail(); - } - self.into_slice_range().index(slice) + ops::RangeInclusive::from(self).index(slice) } #[inline] fn index_mut(self, slice: &mut str) -> &mut Self::Output { - if self.last == usize::MAX { - str_index_overflow_fail(); - } - self.into_slice_range().index_mut(slice) + ops::RangeInclusive::from(self).index_mut(slice) } } @@ -756,6 +763,52 @@ unsafe impl const SliceIndex for ops::RangeToInclusive { } } +/// Implements substring slicing with syntax `&self[..= last]` or `&mut +/// self[..= last]`. +/// +/// Returns a slice of the given string from the byte range \[0, `last`\]. +/// Equivalent to `&self [0 .. last + 1]`, except if `last` has the maximum +/// value for `usize`. +/// +/// This operation is *O*(1). +/// +/// # Panics +/// +/// Panics if `last` does not point to the ending byte offset of a character +/// (`last + 1` is either a starting byte offset as defined by +/// `is_char_boundary`, or equal to `len`), or if `last >= len`. +#[stable(feature = "new_range_to_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[rustc_const_unstable(feature = "const_index", issue = "143775")] +unsafe impl const SliceIndex for range::RangeToInclusive { + type Output = str; + #[inline] + fn get(self, slice: &str) -> Option<&Self::Output> { + (0..=self.last).get(slice) + } + #[inline] + fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> { + (0..=self.last).get_mut(slice) + } + #[inline] + unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output { + // SAFETY: the caller must uphold the safety contract for `get_unchecked`. + unsafe { (0..=self.last).get_unchecked(slice) } + } + #[inline] + unsafe fn get_unchecked_mut(self, slice: *mut str) -> *mut Self::Output { + // SAFETY: the caller must uphold the safety contract for `get_unchecked_mut`. + unsafe { (0..=self.last).get_unchecked_mut(slice) } + } + #[inline] + fn index(self, slice: &str) -> &Self::Output { + (0..=self.last).index(slice) + } + #[inline] + fn index_mut(self, slice: &mut str) -> &mut Self::Output { + (0..=self.last).index_mut(slice) + } +} + /// Parse a value from a string /// /// `FromStr`'s [`from_str`] method is often used implicitly, through diff --git a/core/src/sync/atomic.rs b/core/src/sync/atomic.rs index 22f46ec385ced..004772267da74 100644 --- a/core/src/sync/atomic.rs +++ b/core/src/sync/atomic.rs @@ -238,7 +238,6 @@ #![stable(feature = "rust1", since = "1.0.0")] #![cfg_attr(not(target_has_atomic_load_store = "8"), allow(dead_code))] #![cfg_attr(not(target_has_atomic_load_store = "8"), allow(unused_imports))] -#![rustc_diagnostic_item = "atomic_mod"] // Clippy complains about the pattern of "safe function calling unsafe function taking pointers". // This happens with AtomicPtr intrinsics but is fine, as the pointers clippy is concerned about // are just normal values that get loaded/stored, but not dereferenced. @@ -248,40 +247,60 @@ use self::Ordering::*; use crate::cell::UnsafeCell; use crate::hint::spin_loop; use crate::intrinsics::AtomicOrdering as AO; +use crate::mem::transmute; use crate::{fmt, intrinsics}; -trait Sealed {} +#[unstable( + feature = "atomic_internals", + reason = "implementation detail which may disappear or be replaced at any time", + issue = "none" +)] +#[expect(missing_debug_implementations)] +mod private { + pub(super) trait Sealed {} + + #[cfg(target_has_atomic_load_store = "8")] + #[repr(C, align(1))] + pub struct Align1(T); + #[cfg(target_has_atomic_load_store = "16")] + #[repr(C, align(2))] + pub struct Align2(T); + #[cfg(target_has_atomic_load_store = "32")] + #[repr(C, align(4))] + pub struct Align4(T); + #[cfg(target_has_atomic_load_store = "64")] + #[repr(C, align(8))] + pub struct Align8(T); + #[cfg(target_has_atomic_load_store = "128")] + #[repr(C, align(16))] + pub struct Align16(T); +} /// A marker trait for primitive types which can be modified atomically. /// /// This is an implementation detail for [Atomic]\ which may disappear or be replaced at any time. -/// -/// # Safety -/// -/// Types implementing this trait must be primitives that can be modified atomically. -/// -/// The associated `Self::AtomicInner` type must have the same size and bit validity as `Self`, -/// but may have a higher alignment requirement, so the following `transmute`s are sound: -/// -/// - `&mut Self::AtomicInner` as `&mut Self` -/// - `Self` as `Self::AtomicInner` or the reverse +// +// # Safety +// +// Types implementing this trait must be primitives that can be modified atomically. +// +// The associated `Self::Storage` type must have the same size, but may have fewer validity +// invariants or a higher alignment requirement than `Self`. #[unstable( feature = "atomic_internals", reason = "implementation detail which may disappear or be replaced at any time", issue = "none" )] #[expect(private_bounds)] -pub unsafe trait AtomicPrimitive: Sized + Copy + Sealed { +pub unsafe trait AtomicPrimitive: Sized + Copy + private::Sealed { /// Temporary implementation detail. - type AtomicInner: Sized; + type Storage: Sized; } macro impl_atomic_primitive( - $Atom:ident $(<$T:ident>)? ($Primitive:ty), - size($size:literal), - align($align:literal) $(,)? + [$($T:ident)?] $Primitive:ty as $Storage:ident<$Operand:ty>, size($size:literal) ) { - impl $(<$T>)? Sealed for $Primitive {} + impl $(<$T>)? private::Sealed for $Primitive {} #[unstable( feature = "atomic_internals", @@ -290,42 +309,42 @@ macro impl_atomic_primitive( )] #[cfg(target_has_atomic_load_store = $size)] unsafe impl $(<$T>)? AtomicPrimitive for $Primitive { - type AtomicInner = $Atom $(<$T>)?; + type Storage = private::$Storage<$Operand>; } } -impl_atomic_primitive!(AtomicBool(bool), size("8"), align(1)); -impl_atomic_primitive!(AtomicI8(i8), size("8"), align(1)); -impl_atomic_primitive!(AtomicU8(u8), size("8"), align(1)); -impl_atomic_primitive!(AtomicI16(i16), size("16"), align(2)); -impl_atomic_primitive!(AtomicU16(u16), size("16"), align(2)); -impl_atomic_primitive!(AtomicI32(i32), size("32"), align(4)); -impl_atomic_primitive!(AtomicU32(u32), size("32"), align(4)); -impl_atomic_primitive!(AtomicI64(i64), size("64"), align(8)); -impl_atomic_primitive!(AtomicU64(u64), size("64"), align(8)); -impl_atomic_primitive!(AtomicI128(i128), size("128"), align(16)); -impl_atomic_primitive!(AtomicU128(u128), size("128"), align(16)); +impl_atomic_primitive!([] bool as Align1, size("8")); +impl_atomic_primitive!([] i8 as Align1, size("8")); +impl_atomic_primitive!([] u8 as Align1, size("8")); +impl_atomic_primitive!([] i16 as Align2, size("16")); +impl_atomic_primitive!([] u16 as Align2, size("16")); +impl_atomic_primitive!([] i32 as Align4, size("32")); +impl_atomic_primitive!([] u32 as Align4, size("32")); +impl_atomic_primitive!([] i64 as Align8, size("64")); +impl_atomic_primitive!([] u64 as Align8, size("64")); +impl_atomic_primitive!([] i128 as Align16, size("128")); +impl_atomic_primitive!([] u128 as Align16, size("128")); #[cfg(target_pointer_width = "16")] -impl_atomic_primitive!(AtomicIsize(isize), size("ptr"), align(2)); +impl_atomic_primitive!([] isize as Align2, size("ptr")); #[cfg(target_pointer_width = "32")] -impl_atomic_primitive!(AtomicIsize(isize), size("ptr"), align(4)); +impl_atomic_primitive!([] isize as Align4, size("ptr")); #[cfg(target_pointer_width = "64")] -impl_atomic_primitive!(AtomicIsize(isize), size("ptr"), align(8)); +impl_atomic_primitive!([] isize as Align8, size("ptr")); #[cfg(target_pointer_width = "16")] -impl_atomic_primitive!(AtomicUsize(usize), size("ptr"), align(2)); +impl_atomic_primitive!([] usize as Align2, size("ptr")); #[cfg(target_pointer_width = "32")] -impl_atomic_primitive!(AtomicUsize(usize), size("ptr"), align(4)); +impl_atomic_primitive!([] usize as Align4, size("ptr")); #[cfg(target_pointer_width = "64")] -impl_atomic_primitive!(AtomicUsize(usize), size("ptr"), align(8)); +impl_atomic_primitive!([] usize as Align8, size("ptr")); #[cfg(target_pointer_width = "16")] -impl_atomic_primitive!(AtomicPtr(*mut T), size("ptr"), align(2)); +impl_atomic_primitive!([T] *mut T as Align2<*mut T>, size("ptr")); #[cfg(target_pointer_width = "32")] -impl_atomic_primitive!(AtomicPtr(*mut T), size("ptr"), align(4)); +impl_atomic_primitive!([T] *mut T as Align4<*mut T>, size("ptr")); #[cfg(target_pointer_width = "64")] -impl_atomic_primitive!(AtomicPtr(*mut T), size("ptr"), align(8)); +impl_atomic_primitive!([T] *mut T as Align8<*mut T>, size("ptr")); /// A memory location which can be safely modified from multiple threads. /// @@ -342,7 +361,16 @@ impl_atomic_primitive!(AtomicPtr(*mut T), size("ptr"), align(8)); /// /// [module-level documentation]: crate::sync::atomic #[unstable(feature = "generic_atomic", issue = "130539")] -pub type Atomic = ::AtomicInner; +#[repr(C)] +#[rustc_diagnostic_item = "Atomic"] +pub struct Atomic { + v: UnsafeCell, +} + +#[stable(feature = "rust1", since = "1.0.0")] +unsafe impl Send for Atomic {} +#[stable(feature = "rust1", since = "1.0.0")] +unsafe impl Sync for Atomic {} // Some architectures don't have byte-sized atomics, which results in LLVM // emulating them using a LL/SC loop. However for AtomicBool we can take @@ -367,11 +395,7 @@ const EMULATE_ATOMIC_BOOL: bool = cfg!(any( /// loads and stores of `u8`. #[cfg(target_has_atomic_load_store = "8")] #[stable(feature = "rust1", since = "1.0.0")] -#[rustc_diagnostic_item = "AtomicBool"] -#[repr(C, align(1))] -pub struct AtomicBool { - v: UnsafeCell, -} +pub type AtomicBool = Atomic; #[cfg(target_has_atomic_load_store = "8")] #[stable(feature = "rust1", since = "1.0.0")] @@ -383,11 +407,6 @@ impl Default for AtomicBool { } } -// Send is implicitly implemented for AtomicBool. -#[cfg(target_has_atomic_load_store = "8")] -#[stable(feature = "rust1", since = "1.0.0")] -unsafe impl Sync for AtomicBool {} - /// A raw pointer type which can be safely shared between threads. /// /// This type has the same size and bit validity as a `*mut T`. @@ -396,13 +415,7 @@ unsafe impl Sync for AtomicBool {} /// loads and stores of pointers. Its size depends on the target pointer's size. #[cfg(target_has_atomic_load_store = "ptr")] #[stable(feature = "rust1", since = "1.0.0")] -#[rustc_diagnostic_item = "AtomicPtr"] -#[cfg_attr(target_pointer_width = "16", repr(C, align(2)))] -#[cfg_attr(target_pointer_width = "32", repr(C, align(4)))] -#[cfg_attr(target_pointer_width = "64", repr(C, align(8)))] -pub struct AtomicPtr { - p: UnsafeCell<*mut T>, -} +pub type AtomicPtr = Atomic<*mut T>; #[cfg(target_has_atomic_load_store = "ptr")] #[stable(feature = "rust1", since = "1.0.0")] @@ -413,13 +426,6 @@ impl Default for AtomicPtr { } } -#[cfg(target_has_atomic_load_store = "ptr")] -#[stable(feature = "rust1", since = "1.0.0")] -unsafe impl Send for AtomicPtr {} -#[cfg(target_has_atomic_load_store = "ptr")] -#[stable(feature = "rust1", since = "1.0.0")] -unsafe impl Sync for AtomicPtr {} - /// Atomic memory orderings /// /// Memory orderings specify the way atomic operations synchronize memory. @@ -528,7 +534,9 @@ impl AtomicBool { #[rustc_const_stable(feature = "const_atomic_new", since = "1.24.0")] #[must_use] pub const fn new(v: bool) -> AtomicBool { - AtomicBool { v: UnsafeCell::new(v as u8) } + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { transmute(v) } } /// Creates a new `AtomicBool` from a pointer. @@ -597,7 +605,7 @@ impl AtomicBool { #[stable(feature = "atomic_access", since = "1.15.0")] pub fn get_mut(&mut self) -> &mut bool { // SAFETY: the mutable reference guarantees unique ownership. - unsafe { &mut *(self.v.get() as *mut bool) } + unsafe { &mut *self.as_ptr() } } /// Gets atomic access to a `&mut bool`. @@ -699,7 +707,11 @@ impl AtomicBool { #[stable(feature = "atomic_access", since = "1.15.0")] #[rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0")] pub const fn into_inner(self) -> bool { - self.v.into_inner() != 0 + // SAFETY: + // * `Atomic` is essentially a transparent wrapper around `T`. + // * all operations on `Atomic` ensure that `T::Storage` remains + // a valid `bool`. + unsafe { transmute(self) } } /// Loads a value from the bool. @@ -726,7 +738,7 @@ impl AtomicBool { pub fn load(&self, order: Ordering) -> bool { // SAFETY: any data races are prevented by atomic intrinsics and the raw // pointer passed in is valid because we got it from a reference. - unsafe { atomic_load(self.v.get(), order) != 0 } + unsafe { atomic_load(self.v.get().cast::(), order) != 0 } } /// Stores a value into the bool. @@ -756,7 +768,7 @@ impl AtomicBool { // SAFETY: any data races are prevented by atomic intrinsics and the raw // pointer passed in is valid because we got it from a reference. unsafe { - atomic_store(self.v.get(), val as u8, order); + atomic_store(self.v.get().cast::(), val as u8, order); } } @@ -790,7 +802,7 @@ impl AtomicBool { if val { self.fetch_or(true, order) } else { self.fetch_and(false, order) } } else { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_swap(self.v.get(), val as u8, order) != 0 } + unsafe { atomic_swap(self.v.get().cast::(), val as u8, order) != 0 } } } @@ -950,7 +962,13 @@ impl AtomicBool { } else { // SAFETY: data races are prevented by atomic intrinsics. match unsafe { - atomic_compare_exchange(self.v.get(), current as u8, new as u8, success, failure) + atomic_compare_exchange( + self.v.get().cast::(), + current as u8, + new as u8, + success, + failure, + ) } { Ok(x) => Ok(x != 0), Err(x) => Err(x != 0), @@ -1024,7 +1042,13 @@ impl AtomicBool { // SAFETY: data races are prevented by atomic intrinsics. match unsafe { - atomic_compare_exchange_weak(self.v.get(), current as u8, new as u8, success, failure) + atomic_compare_exchange_weak( + self.v.get().cast::(), + current as u8, + new as u8, + success, + failure, + ) } { Ok(x) => Ok(x != 0), Err(x) => Err(x != 0), @@ -1070,7 +1094,7 @@ impl AtomicBool { #[rustc_should_not_be_called_on_const_items] pub fn fetch_and(&self, val: bool, order: Ordering) -> bool { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_and(self.v.get(), val as u8, order) != 0 } + unsafe { atomic_and(self.v.get().cast::(), val as u8, order) != 0 } } /// Logical "nand" with a boolean value. @@ -1166,7 +1190,7 @@ impl AtomicBool { #[rustc_should_not_be_called_on_const_items] pub fn fetch_or(&self, val: bool, order: Ordering) -> bool { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_or(self.v.get(), val as u8, order) != 0 } + unsafe { atomic_or(self.v.get().cast::(), val as u8, order) != 0 } } /// Logical "xor" with a boolean value. @@ -1208,7 +1232,7 @@ impl AtomicBool { #[rustc_should_not_be_called_on_const_items] pub fn fetch_xor(&self, val: bool, order: Ordering) -> bool { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_xor(self.v.get(), val as u8, order) != 0 } + unsafe { atomic_xor(self.v.get().cast::(), val as u8, order) != 0 } } /// Logical "not" with a boolean value. @@ -1287,73 +1311,27 @@ impl AtomicBool { self.v.get().cast() } - /// Fetches the value, and applies a function to it that returns an optional - /// new value. Returns a `Result` of `Ok(previous_value)` if the function - /// returned `Some(_)`, else `Err(previous_value)`. - /// - /// Note: This may call the function multiple times if the value has been - /// changed from other threads in the meantime, as long as the function - /// returns `Some(_)`, but the function will have been applied only once to - /// the stored value. - /// - /// `fetch_update` takes two [`Ordering`] arguments to describe the memory - /// ordering of this operation. The first describes the required ordering for - /// when the operation finally succeeds while the second describes the - /// required ordering for loads. These correspond to the success and failure - /// orderings of [`AtomicBool::compare_exchange`] respectively. - /// - /// Using [`Acquire`] as success ordering makes the store part of this - /// operation [`Relaxed`], and using [`Release`] makes the final successful - /// load [`Relaxed`]. The (failed) load ordering can only be [`SeqCst`], - /// [`Acquire`] or [`Relaxed`]. - /// - /// **Note:** This method is only available on platforms that support atomic - /// operations on `u8`. - /// - /// # Considerations - /// - /// This method is not magic; it is not provided by the hardware, and does not act like a - /// critical section or mutex. - /// - /// It is implemented on top of an atomic [compare-and-swap operation], and thus is subject to - /// the usual drawbacks of CAS operations. In particular, be careful of the [ABA problem]. - /// - /// [ABA Problem]: https://en.wikipedia.org/wiki/ABA_problem - /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap - /// - /// # Examples - /// - /// ```rust - /// use std::sync::atomic::{AtomicBool, Ordering}; - /// - /// let x = AtomicBool::new(false); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |_| None), Err(false)); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(!x)), Ok(false)); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(!x)), Ok(true)); - /// assert_eq!(x.load(Ordering::SeqCst), false); - /// ``` + /// An alias for [`AtomicBool::try_update`]. #[inline] #[stable(feature = "atomic_fetch_update", since = "1.53.0")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] + #[deprecated( + since = "1.99.0", + note = "renamed to `try_update` for consistency", + suggestion = "try_update" + )] pub fn fetch_update( &self, set_order: Ordering, fetch_order: Ordering, - mut f: F, + f: F, ) -> Result where F: FnMut(bool) -> Option, { - let mut prev = self.load(fetch_order); - while let Some(next) = f(prev) { - match self.compare_exchange_weak(prev, next, set_order, fetch_order) { - x @ Ok(_) => return x, - Err(next_prev) => prev = next_prev, - } - } - Err(prev) + self.try_update(set_order, fetch_order, f) } /// Fetches the value, and applies a function to it that returns an optional @@ -1395,7 +1373,6 @@ impl AtomicBool { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] /// use std::sync::atomic::{AtomicBool, Ordering}; /// /// let x = AtomicBool::new(false); @@ -1405,7 +1382,7 @@ impl AtomicBool { /// assert_eq!(x.load(Ordering::SeqCst), false); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "1.95.0")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -1413,11 +1390,16 @@ impl AtomicBool { &self, set_order: Ordering, fetch_order: Ordering, - f: impl FnMut(bool) -> Option, + mut f: impl FnMut(bool) -> Option, ) -> Result { - // FIXME(atomic_try_update): this is currently an unstable alias to `fetch_update`; - // when stabilizing, turn `fetch_update` into a deprecated alias to `try_update`. - self.fetch_update(set_order, fetch_order, f) + let mut prev = self.load(fetch_order); + while let Some(next) = f(prev) { + match self.compare_exchange_weak(prev, next, set_order, fetch_order) { + x @ Ok(_) => return x, + Err(next_prev) => prev = next_prev, + } + } + Err(prev) } /// Fetches the value, applies a function to it that it return a new value. @@ -1454,7 +1436,6 @@ impl AtomicBool { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] /// /// use std::sync::atomic::{AtomicBool, Ordering}; /// @@ -1464,7 +1445,7 @@ impl AtomicBool { /// assert_eq!(x.load(Ordering::SeqCst), false); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "1.95.0")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -1500,7 +1481,9 @@ impl AtomicPtr { #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_stable(feature = "const_atomic_new", since = "1.24.0")] pub const fn new(p: *mut T) -> AtomicPtr { - AtomicPtr { p: UnsafeCell::new(p) } + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { transmute(p) } } /// Creates a new `AtomicPtr` from a pointer. @@ -1587,7 +1570,9 @@ impl AtomicPtr { #[inline] #[stable(feature = "atomic_access", since = "1.15.0")] pub fn get_mut(&mut self) -> &mut *mut T { - self.p.get_mut() + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { &mut *self.as_ptr() } } /// Gets atomic access to a pointer. @@ -1715,7 +1700,9 @@ impl AtomicPtr { #[stable(feature = "atomic_access", since = "1.15.0")] #[rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0")] pub const fn into_inner(self) -> *mut T { - self.p.into_inner() + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { transmute(self) } } /// Loads a value from the pointer. @@ -1742,7 +1729,7 @@ impl AtomicPtr { #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub fn load(&self, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_load(self.p.get(), order) } + unsafe { atomic_load(self.as_ptr(), order) } } /// Stores a value into the pointer. @@ -1773,7 +1760,7 @@ impl AtomicPtr { pub fn store(&self, ptr: *mut T, order: Ordering) { // SAFETY: data races are prevented by atomic intrinsics. unsafe { - atomic_store(self.p.get(), ptr, order); + atomic_store(self.as_ptr(), ptr, order); } } @@ -1806,7 +1793,7 @@ impl AtomicPtr { #[rustc_should_not_be_called_on_const_items] pub fn swap(&self, ptr: *mut T, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_swap(self.p.get(), ptr, order) } + unsafe { atomic_swap(self.as_ptr(), ptr, order) } } /// Stores a value into the pointer if the current value is the same as the `current` value. @@ -1930,7 +1917,7 @@ impl AtomicPtr { failure: Ordering, ) -> Result<*mut T, *mut T> { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_compare_exchange(self.p.get(), current, new, success, failure) } + unsafe { atomic_compare_exchange(self.as_ptr(), current, new, success, failure) } } /// Stores a value into the pointer if the current value is the same as the `current` value. @@ -1997,86 +1984,30 @@ impl AtomicPtr { // but we know for sure that the pointer is valid (we just got it from // an `UnsafeCell` that we have by reference) and the atomic operation // itself allows us to safely mutate the `UnsafeCell` contents. - unsafe { atomic_compare_exchange_weak(self.p.get(), current, new, success, failure) } + unsafe { atomic_compare_exchange_weak(self.as_ptr(), current, new, success, failure) } } - /// Fetches the value, and applies a function to it that returns an optional - /// new value. Returns a `Result` of `Ok(previous_value)` if the function - /// returned `Some(_)`, else `Err(previous_value)`. - /// - /// Note: This may call the function multiple times if the value has been - /// changed from other threads in the meantime, as long as the function - /// returns `Some(_)`, but the function will have been applied only once to - /// the stored value. - /// - /// `fetch_update` takes two [`Ordering`] arguments to describe the memory - /// ordering of this operation. The first describes the required ordering for - /// when the operation finally succeeds while the second describes the - /// required ordering for loads. These correspond to the success and failure - /// orderings of [`AtomicPtr::compare_exchange`] respectively. - /// - /// Using [`Acquire`] as success ordering makes the store part of this - /// operation [`Relaxed`], and using [`Release`] makes the final successful - /// load [`Relaxed`]. The (failed) load ordering can only be [`SeqCst`], - /// [`Acquire`] or [`Relaxed`]. - /// - /// **Note:** This method is only available on platforms that support atomic - /// operations on pointers. - /// - /// # Considerations - /// - /// This method is not magic; it is not provided by the hardware, and does not act like a - /// critical section or mutex. - /// - /// It is implemented on top of an atomic [compare-and-swap operation], and thus is subject to - /// the usual drawbacks of CAS operations. In particular, be careful of the [ABA problem], - /// which is a particularly common pitfall for pointers! - /// - /// [ABA Problem]: https://en.wikipedia.org/wiki/ABA_problem - /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap - /// - /// # Examples - /// - /// ```rust - /// use std::sync::atomic::{AtomicPtr, Ordering}; - /// - /// let ptr: *mut _ = &mut 5; - /// let some_ptr = AtomicPtr::new(ptr); - /// - /// let new: *mut _ = &mut 10; - /// assert_eq!(some_ptr.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |_| None), Err(ptr)); - /// let result = some_ptr.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| { - /// if x == ptr { - /// Some(new) - /// } else { - /// None - /// } - /// }); - /// assert_eq!(result, Ok(ptr)); - /// assert_eq!(some_ptr.load(Ordering::SeqCst), new); - /// ``` + /// An alias for [`AtomicPtr::try_update`]. #[inline] #[stable(feature = "atomic_fetch_update", since = "1.53.0")] #[cfg(target_has_atomic = "ptr")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] + #[deprecated( + since = "1.99.0", + note = "renamed to `try_update` for consistency", + suggestion = "try_update" + )] pub fn fetch_update( &self, set_order: Ordering, fetch_order: Ordering, - mut f: F, + f: F, ) -> Result<*mut T, *mut T> where F: FnMut(*mut T) -> Option<*mut T>, { - let mut prev = self.load(fetch_order); - while let Some(next) = f(prev) { - match self.compare_exchange_weak(prev, next, set_order, fetch_order) { - x @ Ok(_) => return x, - Err(next_prev) => prev = next_prev, - } - } - Err(prev) + self.try_update(set_order, fetch_order, f) } /// Fetches the value, and applies a function to it that returns an optional /// new value. Returns a `Result` of `Ok(previous_value)` if the function @@ -2118,7 +2049,6 @@ impl AtomicPtr { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] /// use std::sync::atomic::{AtomicPtr, Ordering}; /// /// let ptr: *mut _ = &mut 5; @@ -2137,7 +2067,7 @@ impl AtomicPtr { /// assert_eq!(some_ptr.load(Ordering::SeqCst), new); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "1.95.0")] #[cfg(target_has_atomic = "ptr")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -2145,11 +2075,16 @@ impl AtomicPtr { &self, set_order: Ordering, fetch_order: Ordering, - f: impl FnMut(*mut T) -> Option<*mut T>, + mut f: impl FnMut(*mut T) -> Option<*mut T>, ) -> Result<*mut T, *mut T> { - // FIXME(atomic_try_update): this is currently an unstable alias to `fetch_update`; - // when stabilizing, turn `fetch_update` into a deprecated alias to `try_update`. - self.fetch_update(set_order, fetch_order, f) + let mut prev = self.load(fetch_order); + while let Some(next) = f(prev) { + match self.compare_exchange_weak(prev, next, set_order, fetch_order) { + x @ Ok(_) => return x, + Err(next_prev) => prev = next_prev, + } + } + Err(prev) } /// Fetches the value, applies a function to it that it return a new value. @@ -2188,7 +2123,6 @@ impl AtomicPtr { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] /// /// use std::sync::atomic::{AtomicPtr, Ordering}; /// @@ -2201,8 +2135,8 @@ impl AtomicPtr { /// assert_eq!(some_ptr.load(Ordering::SeqCst), new); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] - #[cfg(target_has_atomic = "8")] + #[stable(feature = "atomic_try_update", since = "1.95.0")] + #[cfg(target_has_atomic = "ptr")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] pub fn update( @@ -2339,7 +2273,7 @@ impl AtomicPtr { #[rustc_should_not_be_called_on_const_items] pub fn fetch_byte_add(&self, val: usize, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_add(self.p.get(), val, order).cast() } + unsafe { atomic_add(self.as_ptr(), val, order).cast() } } /// Offsets the pointer's address by subtracting `val` *bytes*, returning the @@ -2375,7 +2309,7 @@ impl AtomicPtr { #[rustc_should_not_be_called_on_const_items] pub fn fetch_byte_sub(&self, val: usize, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_sub(self.p.get(), val, order).cast() } + unsafe { atomic_sub(self.as_ptr(), val, order).cast() } } /// Performs a bitwise "or" operation on the address of the current pointer, @@ -2426,7 +2360,7 @@ impl AtomicPtr { #[rustc_should_not_be_called_on_const_items] pub fn fetch_or(&self, val: usize, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_or(self.p.get(), val, order).cast() } + unsafe { atomic_or(self.as_ptr(), val, order).cast() } } /// Performs a bitwise "and" operation on the address of the current @@ -2476,7 +2410,7 @@ impl AtomicPtr { #[rustc_should_not_be_called_on_const_items] pub fn fetch_and(&self, val: usize, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_and(self.p.get(), val, order).cast() } + unsafe { atomic_and(self.as_ptr(), val, order).cast() } } /// Performs a bitwise "xor" operation on the address of the current @@ -2524,7 +2458,7 @@ impl AtomicPtr { #[rustc_should_not_be_called_on_const_items] pub fn fetch_xor(&self, val: usize, order: Ordering) -> *mut T { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_xor(self.p.get(), val, order).cast() } + unsafe { atomic_xor(self.as_ptr(), val, order).cast() } } /// Returns a mutable pointer to the underlying pointer. @@ -2563,7 +2497,7 @@ impl AtomicPtr { #[rustc_const_stable(feature = "atomic_as_ptr", since = "1.70.0")] #[rustc_never_returns_null_ptr] pub const fn as_ptr(&self) -> *mut *mut T { - self.p.get() + self.v.get().cast() } } @@ -2616,7 +2550,6 @@ macro_rules! atomic_int { $stable_nand:meta, $const_stable_new:meta, $const_stable_into_inner:meta, - $diagnostic_item:meta, $s_int_type:literal, $extra_feature:expr, $min_fn:ident, $max_fn:ident, @@ -2653,11 +2586,7 @@ macro_rules! atomic_int { /// /// [module-level documentation]: crate::sync::atomic #[$stable] - #[$diagnostic_item] - #[repr(C, align($align))] - pub struct $atomic_type { - v: UnsafeCell<$int_type>, - } + pub type $atomic_type = Atomic<$int_type>; #[$stable] impl Default for $atomic_type { @@ -2682,10 +2611,6 @@ macro_rules! atomic_int { } } - // Send is implicitly implemented. - #[$stable] - unsafe impl Sync for $atomic_type {} - impl $atomic_type { /// Creates a new atomic integer. /// @@ -2701,7 +2626,9 @@ macro_rules! atomic_int { #[$const_stable_new] #[must_use] pub const fn new(v: $int_type) -> Self { - Self {v: UnsafeCell::new(v)} + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { transmute(v) } } /// Creates a new reference to an atomic integer from a pointer. @@ -2763,7 +2690,6 @@ macro_rules! atomic_int { unsafe { &*ptr.cast() } } - /// Returns a mutable reference to the underlying integer. /// /// This is safe because the mutable reference guarantees that no other threads are @@ -2782,7 +2708,9 @@ macro_rules! atomic_int { #[inline] #[$stable_access] pub fn get_mut(&mut self) -> &mut $int_type { - self.v.get_mut() + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { &mut *self.as_ptr() } } #[doc = concat!("Get atomic access to a `&mut ", stringify!($int_type), "`.")] @@ -2911,7 +2839,9 @@ macro_rules! atomic_int { #[$stable_access] #[$const_stable_into_inner] pub const fn into_inner(self) -> $int_type { - self.v.into_inner() + // SAFETY: + // `Atomic` is essentially a transparent wrapper around `T`. + unsafe { transmute(self) } } /// Loads a value from the atomic integer. @@ -2937,7 +2867,7 @@ macro_rules! atomic_int { #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub fn load(&self, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_load(self.v.get(), order) } + unsafe { atomic_load(self.as_ptr(), order) } } /// Stores a value into the atomic integer. @@ -2965,7 +2895,7 @@ macro_rules! atomic_int { #[rustc_should_not_be_called_on_const_items] pub fn store(&self, val: $int_type, order: Ordering) { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_store(self.v.get(), val, order); } + unsafe { atomic_store(self.as_ptr(), val, order); } } /// Stores a value into the atomic integer, returning the previous value. @@ -2994,7 +2924,7 @@ macro_rules! atomic_int { #[rustc_should_not_be_called_on_const_items] pub fn swap(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_swap(self.v.get(), val, order) } + unsafe { atomic_swap(self.as_ptr(), val, order) } } /// Stores a value into the atomic integer if the current value is the same as @@ -3132,7 +3062,7 @@ macro_rules! atomic_int { success: Ordering, failure: Ordering) -> Result<$int_type, $int_type> { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_compare_exchange(self.v.get(), current, new, success, failure) } + unsafe { atomic_compare_exchange(self.as_ptr(), current, new, success, failure) } } /// Stores a value into the atomic integer if the current value is the same as @@ -3197,7 +3127,7 @@ macro_rules! atomic_int { failure: Ordering) -> Result<$int_type, $int_type> { // SAFETY: data races are prevented by atomic intrinsics. unsafe { - atomic_compare_exchange_weak(self.v.get(), current, new, success, failure) + atomic_compare_exchange_weak(self.as_ptr(), current, new, success, failure) } } @@ -3229,7 +3159,7 @@ macro_rules! atomic_int { #[rustc_should_not_be_called_on_const_items] pub fn fetch_add(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_add(self.v.get(), val, order) } + unsafe { atomic_add(self.as_ptr(), val, order) } } /// Subtracts from the current value, returning the previous value. @@ -3260,7 +3190,7 @@ macro_rules! atomic_int { #[rustc_should_not_be_called_on_const_items] pub fn fetch_sub(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_sub(self.v.get(), val, order) } + unsafe { atomic_sub(self.as_ptr(), val, order) } } /// Bitwise "and" with the current value. @@ -3294,7 +3224,7 @@ macro_rules! atomic_int { #[rustc_should_not_be_called_on_const_items] pub fn fetch_and(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_and(self.v.get(), val, order) } + unsafe { atomic_and(self.as_ptr(), val, order) } } /// Bitwise "nand" with the current value. @@ -3328,7 +3258,7 @@ macro_rules! atomic_int { #[rustc_should_not_be_called_on_const_items] pub fn fetch_nand(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_nand(self.v.get(), val, order) } + unsafe { atomic_nand(self.as_ptr(), val, order) } } /// Bitwise "or" with the current value. @@ -3362,7 +3292,7 @@ macro_rules! atomic_int { #[rustc_should_not_be_called_on_const_items] pub fn fetch_or(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_or(self.v.get(), val, order) } + unsafe { atomic_or(self.as_ptr(), val, order) } } /// Bitwise "xor" with the current value. @@ -3396,72 +3326,28 @@ macro_rules! atomic_int { #[rustc_should_not_be_called_on_const_items] pub fn fetch_xor(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { atomic_xor(self.v.get(), val, order) } + unsafe { atomic_xor(self.as_ptr(), val, order) } } - /// Fetches the value, and applies a function to it that returns an optional - /// new value. Returns a `Result` of `Ok(previous_value)` if the function returned `Some(_)`, else - /// `Err(previous_value)`. - /// - /// Note: This may call the function multiple times if the value has been changed from other threads in - /// the meantime, as long as the function returns `Some(_)`, but the function will have been applied - /// only once to the stored value. - /// - /// `fetch_update` takes two [`Ordering`] arguments to describe the memory ordering of this operation. - /// The first describes the required ordering for when the operation finally succeeds while the second - /// describes the required ordering for loads. These correspond to the success and failure orderings of - #[doc = concat!("[`", stringify!($atomic_type), "::compare_exchange`]")] - /// respectively. - /// - /// Using [`Acquire`] as success ordering makes the store part - /// of this operation [`Relaxed`], and using [`Release`] makes the final successful load - /// [`Relaxed`]. The (failed) load ordering can only be [`SeqCst`], [`Acquire`] or [`Relaxed`]. - /// - /// **Note**: This method is only available on platforms that support atomic operations on - #[doc = concat!("[`", $s_int_type, "`].")] - /// - /// # Considerations - /// - /// This method is not magic; it is not provided by the hardware, and does not act like a - /// critical section or mutex. - /// - /// It is implemented on top of an atomic [compare-and-swap operation], and thus is subject to - /// the usual drawbacks of CAS operations. In particular, be careful of the [ABA problem] - /// if this atomic integer is an index or more generally if knowledge of only the *bitwise value* - /// of the atomic is not in and of itself sufficient to ensure any required preconditions. - /// - /// [ABA Problem]: https://en.wikipedia.org/wiki/ABA_problem - /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap - /// - /// # Examples - /// - /// ```rust - #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] - /// - #[doc = concat!("let x = ", stringify!($atomic_type), "::new(7);")] - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |_| None), Err(7)); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(x + 1)), Ok(7)); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(x + 1)), Ok(8)); - /// assert_eq!(x.load(Ordering::SeqCst), 9); - /// ``` + /// An alias for + #[doc = concat!("[`", stringify!($atomic_type), "::try_update`]")] + /// . #[inline] #[stable(feature = "no_more_cas", since = "1.45.0")] #[$cfg_cas] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] + #[deprecated( + since = "1.99.0", + note = "renamed to `try_update` for consistency", + suggestion = "try_update" + )] pub fn fetch_update(&self, set_order: Ordering, fetch_order: Ordering, - mut f: F) -> Result<$int_type, $int_type> + f: F) -> Result<$int_type, $int_type> where F: FnMut($int_type) -> Option<$int_type> { - let mut prev = self.load(fetch_order); - while let Some(next) = f(prev) { - match self.compare_exchange_weak(prev, next, set_order, fetch_order) { - x @ Ok(_) => return x, - Err(next_prev) => prev = next_prev - } - } - Err(prev) + self.try_update(set_order, fetch_order, f) } /// Fetches the value, and applies a function to it that returns an optional @@ -3503,7 +3389,6 @@ macro_rules! atomic_int { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let x = ", stringify!($atomic_type), "::new(7);")] @@ -3513,7 +3398,7 @@ macro_rules! atomic_int { /// assert_eq!(x.load(Ordering::SeqCst), 9); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "1.95.0")] #[$cfg_cas] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -3521,11 +3406,16 @@ macro_rules! atomic_int { &self, set_order: Ordering, fetch_order: Ordering, - f: impl FnMut($int_type) -> Option<$int_type>, + mut f: impl FnMut($int_type) -> Option<$int_type>, ) -> Result<$int_type, $int_type> { - // FIXME(atomic_try_update): this is currently an unstable alias to `fetch_update`; - // when stabilizing, turn `fetch_update` into a deprecated alias to `try_update`. - self.fetch_update(set_order, fetch_order, f) + let mut prev = self.load(fetch_order); + while let Some(next) = f(prev) { + match self.compare_exchange_weak(prev, next, set_order, fetch_order) { + x @ Ok(_) => return x, + Err(next_prev) => prev = next_prev + } + } + Err(prev) } /// Fetches the value, applies a function to it that it return a new value. @@ -3566,7 +3456,6 @@ macro_rules! atomic_int { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let x = ", stringify!($atomic_type), "::new(7);")] @@ -3575,7 +3464,7 @@ macro_rules! atomic_int { /// assert_eq!(x.load(Ordering::SeqCst), 9); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "1.95.0")] #[$cfg_cas] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -3636,7 +3525,7 @@ macro_rules! atomic_int { #[rustc_should_not_be_called_on_const_items] pub fn fetch_max(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { $max_fn(self.v.get(), val, order) } + unsafe { $max_fn(self.as_ptr(), val, order) } } /// Minimum with the current value. @@ -3683,7 +3572,7 @@ macro_rules! atomic_int { #[rustc_should_not_be_called_on_const_items] pub fn fetch_min(&self, val: $int_type, order: Ordering) -> $int_type { // SAFETY: data races are prevented by atomic intrinsics. - unsafe { $min_fn(self.v.get(), val, order) } + unsafe { $min_fn(self.as_ptr(), val, order) } } /// Returns a mutable pointer to the underlying integer. @@ -3723,7 +3612,7 @@ macro_rules! atomic_int { #[rustc_const_stable(feature = "atomic_as_ptr", since = "1.70.0")] #[rustc_never_returns_null_ptr] pub const fn as_ptr(&self) -> *mut $int_type { - self.v.get() + self.v.get().cast() } } } @@ -3741,7 +3630,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicI8", "i8", "", atomic_min, atomic_max, @@ -3760,7 +3648,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicU8", "u8", "", atomic_umin, atomic_umax, @@ -3779,7 +3666,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicI16", "i16", "", atomic_min, atomic_max, @@ -3798,7 +3684,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicU16", "u16", "", atomic_umin, atomic_umax, @@ -3817,7 +3702,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicI32", "i32", "", atomic_min, atomic_max, @@ -3836,7 +3720,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicU32", "u32", "", atomic_umin, atomic_umax, @@ -3855,7 +3738,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicI64", "i64", "", atomic_min, atomic_max, @@ -3874,7 +3756,6 @@ atomic_int! { stable(feature = "integer_atomics_stable", since = "1.34.0"), rustc_const_stable(feature = "const_integer_atomics", since = "1.34.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicU64", "u64", "", atomic_umin, atomic_umax, @@ -3893,7 +3774,6 @@ atomic_int! { unstable(feature = "integer_atomics", issue = "99069"), rustc_const_unstable(feature = "integer_atomics", issue = "99069"), rustc_const_unstable(feature = "integer_atomics", issue = "99069"), - rustc_diagnostic_item = "AtomicI128", "i128", "#![feature(integer_atomics)]\n\n", atomic_min, atomic_max, @@ -3912,7 +3792,6 @@ atomic_int! { unstable(feature = "integer_atomics", issue = "99069"), rustc_const_unstable(feature = "integer_atomics", issue = "99069"), rustc_const_unstable(feature = "integer_atomics", issue = "99069"), - rustc_diagnostic_item = "AtomicU128", "u128", "#![feature(integer_atomics)]\n\n", atomic_umin, atomic_umax, @@ -3935,7 +3814,6 @@ macro_rules! atomic_int_ptr_sized { stable(feature = "atomic_nand", since = "1.27.0"), rustc_const_stable(feature = "const_ptr_sized_atomics", since = "1.24.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicIsize", "isize", "", atomic_min, atomic_max, @@ -3954,7 +3832,6 @@ macro_rules! atomic_int_ptr_sized { stable(feature = "atomic_nand", since = "1.27.0"), rustc_const_stable(feature = "const_ptr_sized_atomics", since = "1.24.0"), rustc_const_stable(feature = "const_atomic_into_inner", since = "1.79.0"), - rustc_diagnostic_item = "AtomicUsize", "usize", "", atomic_umin, atomic_umax, diff --git a/core/src/time.rs b/core/src/time.rs index b4efc09684e7f..a5b654033ba14 100644 --- a/core/src/time.rs +++ b/core/src/time.rs @@ -690,7 +690,6 @@ impl Duration { /// # Examples /// /// ``` - /// #![feature(duration_constants)] /// use std::time::Duration; /// /// assert_eq!(Duration::new(0, 0).saturating_add(Duration::new(0, 1)), Duration::new(0, 1)); @@ -801,7 +800,6 @@ impl Duration { /// # Examples /// /// ``` - /// #![feature(duration_constants)] /// use std::time::Duration; /// /// assert_eq!(Duration::new(0, 500_000_001).saturating_mul(2), Duration::new(1, 2)); diff --git a/core/src/unicode/mod.rs b/core/src/unicode/mod.rs index c71fa754e68fb..22a1166fdf168 100644 --- a/core/src/unicode/mod.rs +++ b/core/src/unicode/mod.rs @@ -4,12 +4,12 @@ // for use in alloc, not re-exported in std. #[rustfmt::skip] -pub use unicode_data::case_ignorable::lookup as Case_Ignorable; -pub use unicode_data::cased::lookup as Cased; pub use unicode_data::conversions; #[rustfmt::skip] pub(crate) use unicode_data::alphabetic::lookup as Alphabetic; +pub(crate) use unicode_data::case_ignorable::lookup as Case_Ignorable; +pub(crate) use unicode_data::cased::lookup as Cased; pub(crate) use unicode_data::grapheme_extend::lookup as Grapheme_Extend; pub(crate) use unicode_data::lowercase::lookup as Lowercase; pub(crate) use unicode_data::n::lookup as N; @@ -19,7 +19,7 @@ pub(crate) use unicode_data::white_space::lookup as White_Space; pub(crate) mod printable; #[allow(unreachable_pub)] -mod unicode_data; +pub mod unicode_data; /// The version of [Unicode](https://www.unicode.org/) that the Unicode parts of /// `char` and `str` methods are based on. diff --git a/core/src/unicode/unicode_data.rs b/core/src/unicode/unicode_data.rs index 429b60a68f439..f602cd5c5b6b3 100644 --- a/core/src/unicode/unicode_data.rs +++ b/core/src/unicode/unicode_data.rs @@ -7,9 +7,10 @@ // N : 463 bytes, 1914 codepoints in 145 ranges (U+0000B2 - U+01FBFA) using skiplist // Uppercase : 799 bytes, 1980 codepoints in 659 ranges (U+0000C0 - U+01F18A) using bitset // White_Space : 256 bytes, 19 codepoints in 8 ranges (U+000085 - U+003001) using cascading -// to_lower : 11708 bytes -// to_upper : 13656 bytes -// Total : 31911 bytes +// to_lower : 1112 bytes, 1462 codepoints in 185 ranges (U+0000C0 - U+01E921) using 2-level LUT +// to_upper : 1998 bytes, 1554 codepoints in 299 ranges (U+0000B5 - U+01E943) using 2-level LUT +// to_title : 340 bytes, 135 codepoints in 49 ranges (U+0000DF - U+00FB17) using 2-level LUT +// Total : 9997 bytes #[inline(always)] const fn bitset_search< @@ -758,833 +759,453 @@ pub mod white_space { #[rustfmt::skip] pub mod conversions { - const INDEX_MASK: u32 = 0x400000; + + + use crate::ops::RangeInclusive; + + struct L1Lut { + l2_luts: [L2Lut; 2], + } + + struct L2Lut { + singles: &'static [(Range, i16)], + multis: &'static [(u16, [u16; 3])], + } + + #[derive(Copy, Clone)] + struct Range { + start: u16, + len: u8, + parity: bool, + } + + impl Range { + const fn new(range: RangeInclusive, parity: bool) -> Self { + let start = *range.start(); + let end = *range.end(); + assert!(start <= end); + + let len = end - start; + assert!(len <= 255); + + Self { start, len: len as u8, parity } + } + + const fn singleton(start: u16) -> Self { + Self::new(start..=start, false) + } + + const fn step_by_1(range: RangeInclusive) -> Self { + Self::new(range, false) + } + + const fn step_by_2(range: RangeInclusive) -> Self { + Self::new(range, true) + } + + const fn start(&self) -> u16 { + self.start + } + + const fn end(&self) -> u16 { + self.start + self.len as u16 + } + } + + fn deconstruct(c: char) -> (u16, u16) { + let c = c as u32; + let plane = (c >> 16) as u16; + let low = c as u16; + (plane, low) + } + + unsafe fn reconstruct(plane: u16, low: u16) -> char { + // SAFETY: The caller must ensure that the result is a valid `char`. + unsafe { char::from_u32_unchecked(((plane as u32) << 16) | (low as u32)) } + } + + fn lookup(input: char, l1_lut: &L1Lut) -> Option<[char; 3]> { + let (input_high, input_low) = deconstruct(input); + let Some(l2_lut) = l1_lut.l2_luts.get(input_high as usize) else { + return None; + }; + + let idx = l2_lut.singles.binary_search_by(|(range, _)| { + use crate::cmp::Ordering; + + if input_low < range.start() { + Ordering::Greater + } else if input_low > range.end() { + Ordering::Less + } else { + Ordering::Equal + } + }); + + if let Ok(idx) = idx { + // SAFETY: binary search guarantees that the index is in bounds. + let &(range, output_delta) = unsafe { l2_lut.singles.get_unchecked(idx) }; + let mask = range.parity as u16; + if input_low & mask == range.start() & mask { + let output_low = input_low.wrapping_add_signed(output_delta); + // SAFETY: Table data are guaranteed to be valid Unicode. + let output = unsafe { reconstruct(input_high, output_low) }; + return Some([output, '\0', '\0']); + } + }; + + if let Ok(idx) = l2_lut.multis.binary_search_by_key(&input_low, |&(p, _)| p) { + // SAFETY: binary search guarantees that the index is in bounds. + let &(_, output_lows) = unsafe { l2_lut.multis.get_unchecked(idx) }; + // SAFETY: Table data are guaranteed to be valid Unicode. + let output = output_lows.map(|output_low| unsafe { reconstruct(input_high, output_low) }); + return Some(output); + }; + + None + } pub fn to_lower(c: char) -> [char; 3] { - if c.is_ascii() { - [(c as u8).to_ascii_lowercase() as char, '\0', '\0'] - } else { - LOWERCASE_TABLE - .binary_search_by(|&(key, _)| key.cmp(&c)) - .map(|i| { - // SAFETY: i is the result of the binary search - let u = unsafe { LOWERCASE_TABLE.get_unchecked(i) }.1; - char::from_u32(u).map(|c| [c, '\0', '\0']).unwrap_or_else(|| { - // SAFETY: Index comes from statically generated table - unsafe { *LOWERCASE_TABLE_MULTI.get_unchecked((u & (INDEX_MASK - 1)) as usize) } - }) - }) - .unwrap_or([c, '\0', '\0']) + // https://util.unicode.org/UnicodeJsps/list-unicodeset.jsp?a=%5B%253AChanges_When_Lowercased%253A%5D-%5B%253AASCII%253A%5D&abb=on + if c < '\u{C0}' { + return [c.to_ascii_lowercase(), '\0', '\0']; } + + lookup(c, &LOWERCASE_LUT).unwrap_or([c, '\0', '\0']) } pub fn to_upper(c: char) -> [char; 3] { - if c.is_ascii() { - [(c as u8).to_ascii_uppercase() as char, '\0', '\0'] - } else { - UPPERCASE_TABLE - .binary_search_by(|&(key, _)| key.cmp(&c)) - .map(|i| { - // SAFETY: i is the result of the binary search - let u = unsafe { UPPERCASE_TABLE.get_unchecked(i) }.1; - char::from_u32(u).map(|c| [c, '\0', '\0']).unwrap_or_else(|| { - // SAFETY: Index comes from statically generated table - unsafe { *UPPERCASE_TABLE_MULTI.get_unchecked((u & (INDEX_MASK - 1)) as usize) } - }) - }) - .unwrap_or([c, '\0', '\0']) + // https://util.unicode.org/UnicodeJsps/list-unicodeset.jsp?a=%5B%253AChanges_When_Uppercased%253A%5D-%5B%253AASCII%253A%5D&abb=on + if c < '\u{B5}' { + return [c.to_ascii_uppercase(), '\0', '\0']; } + + lookup(c, &UPPERCASE_LUT).unwrap_or([c, '\0', '\0']) } - static LOWERCASE_TABLE: &[(char, u32); 1462] = &[ - ('\u{c0}', 224), ('\u{c1}', 225), ('\u{c2}', 226), ('\u{c3}', 227), ('\u{c4}', 228), - ('\u{c5}', 229), ('\u{c6}', 230), ('\u{c7}', 231), ('\u{c8}', 232), ('\u{c9}', 233), - ('\u{ca}', 234), ('\u{cb}', 235), ('\u{cc}', 236), ('\u{cd}', 237), ('\u{ce}', 238), - ('\u{cf}', 239), ('\u{d0}', 240), ('\u{d1}', 241), ('\u{d2}', 242), ('\u{d3}', 243), - ('\u{d4}', 244), ('\u{d5}', 245), ('\u{d6}', 246), ('\u{d8}', 248), ('\u{d9}', 249), - ('\u{da}', 250), ('\u{db}', 251), ('\u{dc}', 252), ('\u{dd}', 253), ('\u{de}', 254), - ('\u{100}', 257), ('\u{102}', 259), ('\u{104}', 261), ('\u{106}', 263), ('\u{108}', 265), - ('\u{10a}', 267), ('\u{10c}', 269), ('\u{10e}', 271), ('\u{110}', 273), ('\u{112}', 275), - ('\u{114}', 277), ('\u{116}', 279), ('\u{118}', 281), ('\u{11a}', 283), ('\u{11c}', 285), - ('\u{11e}', 287), ('\u{120}', 289), ('\u{122}', 291), ('\u{124}', 293), ('\u{126}', 295), - ('\u{128}', 297), ('\u{12a}', 299), ('\u{12c}', 301), ('\u{12e}', 303), - ('\u{130}', 4194304), ('\u{132}', 307), ('\u{134}', 309), ('\u{136}', 311), - ('\u{139}', 314), ('\u{13b}', 316), ('\u{13d}', 318), ('\u{13f}', 320), ('\u{141}', 322), - ('\u{143}', 324), ('\u{145}', 326), ('\u{147}', 328), ('\u{14a}', 331), ('\u{14c}', 333), - ('\u{14e}', 335), ('\u{150}', 337), ('\u{152}', 339), ('\u{154}', 341), ('\u{156}', 343), - ('\u{158}', 345), ('\u{15a}', 347), ('\u{15c}', 349), ('\u{15e}', 351), ('\u{160}', 353), - ('\u{162}', 355), ('\u{164}', 357), ('\u{166}', 359), ('\u{168}', 361), ('\u{16a}', 363), - ('\u{16c}', 365), ('\u{16e}', 367), ('\u{170}', 369), ('\u{172}', 371), ('\u{174}', 373), - ('\u{176}', 375), ('\u{178}', 255), ('\u{179}', 378), ('\u{17b}', 380), ('\u{17d}', 382), - ('\u{181}', 595), ('\u{182}', 387), ('\u{184}', 389), ('\u{186}', 596), ('\u{187}', 392), - ('\u{189}', 598), ('\u{18a}', 599), ('\u{18b}', 396), ('\u{18e}', 477), ('\u{18f}', 601), - ('\u{190}', 603), ('\u{191}', 402), ('\u{193}', 608), ('\u{194}', 611), ('\u{196}', 617), - ('\u{197}', 616), ('\u{198}', 409), ('\u{19c}', 623), ('\u{19d}', 626), ('\u{19f}', 629), - ('\u{1a0}', 417), ('\u{1a2}', 419), ('\u{1a4}', 421), ('\u{1a6}', 640), ('\u{1a7}', 424), - ('\u{1a9}', 643), ('\u{1ac}', 429), ('\u{1ae}', 648), ('\u{1af}', 432), ('\u{1b1}', 650), - ('\u{1b2}', 651), ('\u{1b3}', 436), ('\u{1b5}', 438), ('\u{1b7}', 658), ('\u{1b8}', 441), - ('\u{1bc}', 445), ('\u{1c4}', 454), ('\u{1c5}', 454), ('\u{1c7}', 457), ('\u{1c8}', 457), - ('\u{1ca}', 460), ('\u{1cb}', 460), ('\u{1cd}', 462), ('\u{1cf}', 464), ('\u{1d1}', 466), - ('\u{1d3}', 468), ('\u{1d5}', 470), ('\u{1d7}', 472), ('\u{1d9}', 474), ('\u{1db}', 476), - ('\u{1de}', 479), ('\u{1e0}', 481), ('\u{1e2}', 483), ('\u{1e4}', 485), ('\u{1e6}', 487), - ('\u{1e8}', 489), ('\u{1ea}', 491), ('\u{1ec}', 493), ('\u{1ee}', 495), ('\u{1f1}', 499), - ('\u{1f2}', 499), ('\u{1f4}', 501), ('\u{1f6}', 405), ('\u{1f7}', 447), ('\u{1f8}', 505), - ('\u{1fa}', 507), ('\u{1fc}', 509), ('\u{1fe}', 511), ('\u{200}', 513), ('\u{202}', 515), - ('\u{204}', 517), ('\u{206}', 519), ('\u{208}', 521), ('\u{20a}', 523), ('\u{20c}', 525), - ('\u{20e}', 527), ('\u{210}', 529), ('\u{212}', 531), ('\u{214}', 533), ('\u{216}', 535), - ('\u{218}', 537), ('\u{21a}', 539), ('\u{21c}', 541), ('\u{21e}', 543), ('\u{220}', 414), - ('\u{222}', 547), ('\u{224}', 549), ('\u{226}', 551), ('\u{228}', 553), ('\u{22a}', 555), - ('\u{22c}', 557), ('\u{22e}', 559), ('\u{230}', 561), ('\u{232}', 563), ('\u{23a}', 11365), - ('\u{23b}', 572), ('\u{23d}', 410), ('\u{23e}', 11366), ('\u{241}', 578), ('\u{243}', 384), - ('\u{244}', 649), ('\u{245}', 652), ('\u{246}', 583), ('\u{248}', 585), ('\u{24a}', 587), - ('\u{24c}', 589), ('\u{24e}', 591), ('\u{370}', 881), ('\u{372}', 883), ('\u{376}', 887), - ('\u{37f}', 1011), ('\u{386}', 940), ('\u{388}', 941), ('\u{389}', 942), ('\u{38a}', 943), - ('\u{38c}', 972), ('\u{38e}', 973), ('\u{38f}', 974), ('\u{391}', 945), ('\u{392}', 946), - ('\u{393}', 947), ('\u{394}', 948), ('\u{395}', 949), ('\u{396}', 950), ('\u{397}', 951), - ('\u{398}', 952), ('\u{399}', 953), ('\u{39a}', 954), ('\u{39b}', 955), ('\u{39c}', 956), - ('\u{39d}', 957), ('\u{39e}', 958), ('\u{39f}', 959), ('\u{3a0}', 960), ('\u{3a1}', 961), - ('\u{3a3}', 963), ('\u{3a4}', 964), ('\u{3a5}', 965), ('\u{3a6}', 966), ('\u{3a7}', 967), - ('\u{3a8}', 968), ('\u{3a9}', 969), ('\u{3aa}', 970), ('\u{3ab}', 971), ('\u{3cf}', 983), - ('\u{3d8}', 985), ('\u{3da}', 987), ('\u{3dc}', 989), ('\u{3de}', 991), ('\u{3e0}', 993), - ('\u{3e2}', 995), ('\u{3e4}', 997), ('\u{3e6}', 999), ('\u{3e8}', 1001), ('\u{3ea}', 1003), - ('\u{3ec}', 1005), ('\u{3ee}', 1007), ('\u{3f4}', 952), ('\u{3f7}', 1016), - ('\u{3f9}', 1010), ('\u{3fa}', 1019), ('\u{3fd}', 891), ('\u{3fe}', 892), ('\u{3ff}', 893), - ('\u{400}', 1104), ('\u{401}', 1105), ('\u{402}', 1106), ('\u{403}', 1107), - ('\u{404}', 1108), ('\u{405}', 1109), ('\u{406}', 1110), ('\u{407}', 1111), - ('\u{408}', 1112), ('\u{409}', 1113), ('\u{40a}', 1114), ('\u{40b}', 1115), - ('\u{40c}', 1116), ('\u{40d}', 1117), ('\u{40e}', 1118), ('\u{40f}', 1119), - ('\u{410}', 1072), ('\u{411}', 1073), ('\u{412}', 1074), ('\u{413}', 1075), - ('\u{414}', 1076), ('\u{415}', 1077), ('\u{416}', 1078), ('\u{417}', 1079), - ('\u{418}', 1080), ('\u{419}', 1081), ('\u{41a}', 1082), ('\u{41b}', 1083), - ('\u{41c}', 1084), ('\u{41d}', 1085), ('\u{41e}', 1086), ('\u{41f}', 1087), - ('\u{420}', 1088), ('\u{421}', 1089), ('\u{422}', 1090), ('\u{423}', 1091), - ('\u{424}', 1092), ('\u{425}', 1093), ('\u{426}', 1094), ('\u{427}', 1095), - ('\u{428}', 1096), ('\u{429}', 1097), ('\u{42a}', 1098), ('\u{42b}', 1099), - ('\u{42c}', 1100), ('\u{42d}', 1101), ('\u{42e}', 1102), ('\u{42f}', 1103), - ('\u{460}', 1121), ('\u{462}', 1123), ('\u{464}', 1125), ('\u{466}', 1127), - ('\u{468}', 1129), ('\u{46a}', 1131), ('\u{46c}', 1133), ('\u{46e}', 1135), - ('\u{470}', 1137), ('\u{472}', 1139), ('\u{474}', 1141), ('\u{476}', 1143), - ('\u{478}', 1145), ('\u{47a}', 1147), ('\u{47c}', 1149), ('\u{47e}', 1151), - ('\u{480}', 1153), ('\u{48a}', 1163), ('\u{48c}', 1165), ('\u{48e}', 1167), - ('\u{490}', 1169), ('\u{492}', 1171), ('\u{494}', 1173), ('\u{496}', 1175), - ('\u{498}', 1177), ('\u{49a}', 1179), ('\u{49c}', 1181), ('\u{49e}', 1183), - ('\u{4a0}', 1185), ('\u{4a2}', 1187), ('\u{4a4}', 1189), ('\u{4a6}', 1191), - ('\u{4a8}', 1193), ('\u{4aa}', 1195), ('\u{4ac}', 1197), ('\u{4ae}', 1199), - ('\u{4b0}', 1201), ('\u{4b2}', 1203), ('\u{4b4}', 1205), ('\u{4b6}', 1207), - ('\u{4b8}', 1209), ('\u{4ba}', 1211), ('\u{4bc}', 1213), ('\u{4be}', 1215), - ('\u{4c0}', 1231), ('\u{4c1}', 1218), ('\u{4c3}', 1220), ('\u{4c5}', 1222), - ('\u{4c7}', 1224), ('\u{4c9}', 1226), ('\u{4cb}', 1228), ('\u{4cd}', 1230), - ('\u{4d0}', 1233), ('\u{4d2}', 1235), ('\u{4d4}', 1237), ('\u{4d6}', 1239), - ('\u{4d8}', 1241), ('\u{4da}', 1243), ('\u{4dc}', 1245), ('\u{4de}', 1247), - ('\u{4e0}', 1249), ('\u{4e2}', 1251), ('\u{4e4}', 1253), ('\u{4e6}', 1255), - ('\u{4e8}', 1257), ('\u{4ea}', 1259), ('\u{4ec}', 1261), ('\u{4ee}', 1263), - ('\u{4f0}', 1265), ('\u{4f2}', 1267), ('\u{4f4}', 1269), ('\u{4f6}', 1271), - ('\u{4f8}', 1273), ('\u{4fa}', 1275), ('\u{4fc}', 1277), ('\u{4fe}', 1279), - ('\u{500}', 1281), ('\u{502}', 1283), ('\u{504}', 1285), ('\u{506}', 1287), - ('\u{508}', 1289), ('\u{50a}', 1291), ('\u{50c}', 1293), ('\u{50e}', 1295), - ('\u{510}', 1297), ('\u{512}', 1299), ('\u{514}', 1301), ('\u{516}', 1303), - ('\u{518}', 1305), ('\u{51a}', 1307), ('\u{51c}', 1309), ('\u{51e}', 1311), - ('\u{520}', 1313), ('\u{522}', 1315), ('\u{524}', 1317), ('\u{526}', 1319), - ('\u{528}', 1321), ('\u{52a}', 1323), ('\u{52c}', 1325), ('\u{52e}', 1327), - ('\u{531}', 1377), ('\u{532}', 1378), ('\u{533}', 1379), ('\u{534}', 1380), - ('\u{535}', 1381), ('\u{536}', 1382), ('\u{537}', 1383), ('\u{538}', 1384), - ('\u{539}', 1385), ('\u{53a}', 1386), ('\u{53b}', 1387), ('\u{53c}', 1388), - ('\u{53d}', 1389), ('\u{53e}', 1390), ('\u{53f}', 1391), ('\u{540}', 1392), - ('\u{541}', 1393), ('\u{542}', 1394), ('\u{543}', 1395), ('\u{544}', 1396), - ('\u{545}', 1397), ('\u{546}', 1398), ('\u{547}', 1399), ('\u{548}', 1400), - ('\u{549}', 1401), ('\u{54a}', 1402), ('\u{54b}', 1403), ('\u{54c}', 1404), - ('\u{54d}', 1405), ('\u{54e}', 1406), ('\u{54f}', 1407), ('\u{550}', 1408), - ('\u{551}', 1409), ('\u{552}', 1410), ('\u{553}', 1411), ('\u{554}', 1412), - ('\u{555}', 1413), ('\u{556}', 1414), ('\u{10a0}', 11520), ('\u{10a1}', 11521), - ('\u{10a2}', 11522), ('\u{10a3}', 11523), ('\u{10a4}', 11524), ('\u{10a5}', 11525), - ('\u{10a6}', 11526), ('\u{10a7}', 11527), ('\u{10a8}', 11528), ('\u{10a9}', 11529), - ('\u{10aa}', 11530), ('\u{10ab}', 11531), ('\u{10ac}', 11532), ('\u{10ad}', 11533), - ('\u{10ae}', 11534), ('\u{10af}', 11535), ('\u{10b0}', 11536), ('\u{10b1}', 11537), - ('\u{10b2}', 11538), ('\u{10b3}', 11539), ('\u{10b4}', 11540), ('\u{10b5}', 11541), - ('\u{10b6}', 11542), ('\u{10b7}', 11543), ('\u{10b8}', 11544), ('\u{10b9}', 11545), - ('\u{10ba}', 11546), ('\u{10bb}', 11547), ('\u{10bc}', 11548), ('\u{10bd}', 11549), - ('\u{10be}', 11550), ('\u{10bf}', 11551), ('\u{10c0}', 11552), ('\u{10c1}', 11553), - ('\u{10c2}', 11554), ('\u{10c3}', 11555), ('\u{10c4}', 11556), ('\u{10c5}', 11557), - ('\u{10c7}', 11559), ('\u{10cd}', 11565), ('\u{13a0}', 43888), ('\u{13a1}', 43889), - ('\u{13a2}', 43890), ('\u{13a3}', 43891), ('\u{13a4}', 43892), ('\u{13a5}', 43893), - ('\u{13a6}', 43894), ('\u{13a7}', 43895), ('\u{13a8}', 43896), ('\u{13a9}', 43897), - ('\u{13aa}', 43898), ('\u{13ab}', 43899), ('\u{13ac}', 43900), ('\u{13ad}', 43901), - ('\u{13ae}', 43902), ('\u{13af}', 43903), ('\u{13b0}', 43904), ('\u{13b1}', 43905), - ('\u{13b2}', 43906), ('\u{13b3}', 43907), ('\u{13b4}', 43908), ('\u{13b5}', 43909), - ('\u{13b6}', 43910), ('\u{13b7}', 43911), ('\u{13b8}', 43912), ('\u{13b9}', 43913), - ('\u{13ba}', 43914), ('\u{13bb}', 43915), ('\u{13bc}', 43916), ('\u{13bd}', 43917), - ('\u{13be}', 43918), ('\u{13bf}', 43919), ('\u{13c0}', 43920), ('\u{13c1}', 43921), - ('\u{13c2}', 43922), ('\u{13c3}', 43923), ('\u{13c4}', 43924), ('\u{13c5}', 43925), - ('\u{13c6}', 43926), ('\u{13c7}', 43927), ('\u{13c8}', 43928), ('\u{13c9}', 43929), - ('\u{13ca}', 43930), ('\u{13cb}', 43931), ('\u{13cc}', 43932), ('\u{13cd}', 43933), - ('\u{13ce}', 43934), ('\u{13cf}', 43935), ('\u{13d0}', 43936), ('\u{13d1}', 43937), - ('\u{13d2}', 43938), ('\u{13d3}', 43939), ('\u{13d4}', 43940), ('\u{13d5}', 43941), - ('\u{13d6}', 43942), ('\u{13d7}', 43943), ('\u{13d8}', 43944), ('\u{13d9}', 43945), - ('\u{13da}', 43946), ('\u{13db}', 43947), ('\u{13dc}', 43948), ('\u{13dd}', 43949), - ('\u{13de}', 43950), ('\u{13df}', 43951), ('\u{13e0}', 43952), ('\u{13e1}', 43953), - ('\u{13e2}', 43954), ('\u{13e3}', 43955), ('\u{13e4}', 43956), ('\u{13e5}', 43957), - ('\u{13e6}', 43958), ('\u{13e7}', 43959), ('\u{13e8}', 43960), ('\u{13e9}', 43961), - ('\u{13ea}', 43962), ('\u{13eb}', 43963), ('\u{13ec}', 43964), ('\u{13ed}', 43965), - ('\u{13ee}', 43966), ('\u{13ef}', 43967), ('\u{13f0}', 5112), ('\u{13f1}', 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('\u{104d0}', 66808), ('\u{104d1}', 66809), - ('\u{104d2}', 66810), ('\u{104d3}', 66811), ('\u{10570}', 66967), ('\u{10571}', 66968), - ('\u{10572}', 66969), ('\u{10573}', 66970), ('\u{10574}', 66971), ('\u{10575}', 66972), - ('\u{10576}', 66973), ('\u{10577}', 66974), ('\u{10578}', 66975), ('\u{10579}', 66976), - ('\u{1057a}', 66977), ('\u{1057c}', 66979), ('\u{1057d}', 66980), ('\u{1057e}', 66981), - ('\u{1057f}', 66982), ('\u{10580}', 66983), ('\u{10581}', 66984), ('\u{10582}', 66985), - ('\u{10583}', 66986), ('\u{10584}', 66987), ('\u{10585}', 66988), ('\u{10586}', 66989), - ('\u{10587}', 66990), ('\u{10588}', 66991), ('\u{10589}', 66992), ('\u{1058a}', 66993), - ('\u{1058c}', 66995), ('\u{1058d}', 66996), ('\u{1058e}', 66997), ('\u{1058f}', 66998), - ('\u{10590}', 66999), ('\u{10591}', 67000), ('\u{10592}', 67001), ('\u{10594}', 67003), - ('\u{10595}', 67004), ('\u{10c80}', 68800), ('\u{10c81}', 68801), ('\u{10c82}', 68802), - ('\u{10c83}', 68803), ('\u{10c84}', 68804), ('\u{10c85}', 68805), ('\u{10c86}', 68806), - ('\u{10c87}', 68807), ('\u{10c88}', 68808), ('\u{10c89}', 68809), ('\u{10c8a}', 68810), - ('\u{10c8b}', 68811), ('\u{10c8c}', 68812), ('\u{10c8d}', 68813), ('\u{10c8e}', 68814), - ('\u{10c8f}', 68815), ('\u{10c90}', 68816), ('\u{10c91}', 68817), ('\u{10c92}', 68818), - ('\u{10c93}', 68819), ('\u{10c94}', 68820), ('\u{10c95}', 68821), ('\u{10c96}', 68822), - ('\u{10c97}', 68823), ('\u{10c98}', 68824), ('\u{10c99}', 68825), ('\u{10c9a}', 68826), - ('\u{10c9b}', 68827), ('\u{10c9c}', 68828), ('\u{10c9d}', 68829), ('\u{10c9e}', 68830), - ('\u{10c9f}', 68831), ('\u{10ca0}', 68832), ('\u{10ca1}', 68833), ('\u{10ca2}', 68834), - ('\u{10ca3}', 68835), ('\u{10ca4}', 68836), ('\u{10ca5}', 68837), ('\u{10ca6}', 68838), - ('\u{10ca7}', 68839), ('\u{10ca8}', 68840), ('\u{10ca9}', 68841), ('\u{10caa}', 68842), - ('\u{10cab}', 68843), ('\u{10cac}', 68844), ('\u{10cad}', 68845), ('\u{10cae}', 68846), - ('\u{10caf}', 68847), ('\u{10cb0}', 68848), ('\u{10cb1}', 68849), ('\u{10cb2}', 68850), - ('\u{10d50}', 68976), ('\u{10d51}', 68977), ('\u{10d52}', 68978), ('\u{10d53}', 68979), - ('\u{10d54}', 68980), ('\u{10d55}', 68981), ('\u{10d56}', 68982), ('\u{10d57}', 68983), - ('\u{10d58}', 68984), ('\u{10d59}', 68985), ('\u{10d5a}', 68986), ('\u{10d5b}', 68987), - ('\u{10d5c}', 68988), ('\u{10d5d}', 68989), ('\u{10d5e}', 68990), ('\u{10d5f}', 68991), - ('\u{10d60}', 68992), ('\u{10d61}', 68993), ('\u{10d62}', 68994), ('\u{10d63}', 68995), - ('\u{10d64}', 68996), ('\u{10d65}', 68997), ('\u{118a0}', 71872), ('\u{118a1}', 71873), - ('\u{118a2}', 71874), ('\u{118a3}', 71875), ('\u{118a4}', 71876), ('\u{118a5}', 71877), - ('\u{118a6}', 71878), ('\u{118a7}', 71879), ('\u{118a8}', 71880), ('\u{118a9}', 71881), - ('\u{118aa}', 71882), ('\u{118ab}', 71883), ('\u{118ac}', 71884), ('\u{118ad}', 71885), - ('\u{118ae}', 71886), ('\u{118af}', 71887), ('\u{118b0}', 71888), ('\u{118b1}', 71889), - ('\u{118b2}', 71890), ('\u{118b3}', 71891), ('\u{118b4}', 71892), ('\u{118b5}', 71893), - ('\u{118b6}', 71894), ('\u{118b7}', 71895), ('\u{118b8}', 71896), ('\u{118b9}', 71897), - ('\u{118ba}', 71898), ('\u{118bb}', 71899), ('\u{118bc}', 71900), ('\u{118bd}', 71901), - ('\u{118be}', 71902), ('\u{118bf}', 71903), ('\u{16e40}', 93792), ('\u{16e41}', 93793), - ('\u{16e42}', 93794), ('\u{16e43}', 93795), ('\u{16e44}', 93796), ('\u{16e45}', 93797), - ('\u{16e46}', 93798), ('\u{16e47}', 93799), ('\u{16e48}', 93800), ('\u{16e49}', 93801), - ('\u{16e4a}', 93802), ('\u{16e4b}', 93803), ('\u{16e4c}', 93804), ('\u{16e4d}', 93805), - ('\u{16e4e}', 93806), ('\u{16e4f}', 93807), ('\u{16e50}', 93808), ('\u{16e51}', 93809), - ('\u{16e52}', 93810), ('\u{16e53}', 93811), ('\u{16e54}', 93812), ('\u{16e55}', 93813), - ('\u{16e56}', 93814), ('\u{16e57}', 93815), ('\u{16e58}', 93816), ('\u{16e59}', 93817), - ('\u{16e5a}', 93818), ('\u{16e5b}', 93819), ('\u{16e5c}', 93820), ('\u{16e5d}', 93821), - ('\u{16e5e}', 93822), ('\u{16e5f}', 93823), ('\u{16ea0}', 93883), ('\u{16ea1}', 93884), - ('\u{16ea2}', 93885), ('\u{16ea3}', 93886), ('\u{16ea4}', 93887), ('\u{16ea5}', 93888), - ('\u{16ea6}', 93889), ('\u{16ea7}', 93890), ('\u{16ea8}', 93891), ('\u{16ea9}', 93892), - ('\u{16eaa}', 93893), ('\u{16eab}', 93894), ('\u{16eac}', 93895), ('\u{16ead}', 93896), - ('\u{16eae}', 93897), ('\u{16eaf}', 93898), ('\u{16eb0}', 93899), ('\u{16eb1}', 93900), - ('\u{16eb2}', 93901), ('\u{16eb3}', 93902), ('\u{16eb4}', 93903), ('\u{16eb5}', 93904), - ('\u{16eb6}', 93905), ('\u{16eb7}', 93906), ('\u{16eb8}', 93907), ('\u{1e900}', 125218), - ('\u{1e901}', 125219), ('\u{1e902}', 125220), ('\u{1e903}', 125221), ('\u{1e904}', 125222), - ('\u{1e905}', 125223), ('\u{1e906}', 125224), ('\u{1e907}', 125225), ('\u{1e908}', 125226), - ('\u{1e909}', 125227), ('\u{1e90a}', 125228), ('\u{1e90b}', 125229), ('\u{1e90c}', 125230), - ('\u{1e90d}', 125231), ('\u{1e90e}', 125232), ('\u{1e90f}', 125233), ('\u{1e910}', 125234), - ('\u{1e911}', 125235), ('\u{1e912}', 125236), ('\u{1e913}', 125237), ('\u{1e914}', 125238), - ('\u{1e915}', 125239), ('\u{1e916}', 125240), ('\u{1e917}', 125241), ('\u{1e918}', 125242), - ('\u{1e919}', 125243), ('\u{1e91a}', 125244), ('\u{1e91b}', 125245), ('\u{1e91c}', 125246), - ('\u{1e91d}', 125247), ('\u{1e91e}', 125248), ('\u{1e91f}', 125249), ('\u{1e920}', 125250), - ('\u{1e921}', 125251), - ]; + pub fn to_title(c: char) -> [char; 3] { + // https://util.unicode.org/UnicodeJsps/list-unicodeset.jsp?a=%5B%253AChanges_When_Titlecased%253A%5D-%5B%253AASCII%253A%5D&abb=on + if c < '\u{B5}' { + return [c.to_ascii_uppercase(), '\0', '\0']; + } - static LOWERCASE_TABLE_MULTI: &[[char; 3]; 1] = &[ - ['i', '\u{307}', '\u{0}'], - ]; + lookup(c, &TITLECASE_LUT).or_else(|| lookup(c, &UPPERCASE_LUT)).unwrap_or([c, '\0', '\0']) + } - static UPPERCASE_TABLE: &[(char, u32); 1554] = &[ - ('\u{b5}', 924), ('\u{df}', 4194304), ('\u{e0}', 192), ('\u{e1}', 193), ('\u{e2}', 194), - ('\u{e3}', 195), ('\u{e4}', 196), ('\u{e5}', 197), ('\u{e6}', 198), ('\u{e7}', 199), - ('\u{e8}', 200), ('\u{e9}', 201), ('\u{ea}', 202), ('\u{eb}', 203), ('\u{ec}', 204), - ('\u{ed}', 205), ('\u{ee}', 206), ('\u{ef}', 207), ('\u{f0}', 208), ('\u{f1}', 209), - ('\u{f2}', 210), ('\u{f3}', 211), ('\u{f4}', 212), ('\u{f5}', 213), ('\u{f6}', 214), - ('\u{f8}', 216), ('\u{f9}', 217), ('\u{fa}', 218), ('\u{fb}', 219), ('\u{fc}', 220), - ('\u{fd}', 221), ('\u{fe}', 222), ('\u{ff}', 376), ('\u{101}', 256), ('\u{103}', 258), - ('\u{105}', 260), ('\u{107}', 262), ('\u{109}', 264), ('\u{10b}', 266), ('\u{10d}', 268), - ('\u{10f}', 270), ('\u{111}', 272), ('\u{113}', 274), ('\u{115}', 276), ('\u{117}', 278), - ('\u{119}', 280), ('\u{11b}', 282), ('\u{11d}', 284), ('\u{11f}', 286), ('\u{121}', 288), - ('\u{123}', 290), ('\u{125}', 292), ('\u{127}', 294), ('\u{129}', 296), ('\u{12b}', 298), - ('\u{12d}', 300), ('\u{12f}', 302), ('\u{131}', 73), ('\u{133}', 306), ('\u{135}', 308), - ('\u{137}', 310), ('\u{13a}', 313), ('\u{13c}', 315), ('\u{13e}', 317), ('\u{140}', 319), - ('\u{142}', 321), ('\u{144}', 323), ('\u{146}', 325), ('\u{148}', 327), - ('\u{149}', 4194305), ('\u{14b}', 330), ('\u{14d}', 332), ('\u{14f}', 334), - ('\u{151}', 336), ('\u{153}', 338), ('\u{155}', 340), ('\u{157}', 342), ('\u{159}', 344), - ('\u{15b}', 346), ('\u{15d}', 348), ('\u{15f}', 350), ('\u{161}', 352), ('\u{163}', 354), - ('\u{165}', 356), ('\u{167}', 358), ('\u{169}', 360), ('\u{16b}', 362), ('\u{16d}', 364), - ('\u{16f}', 366), ('\u{171}', 368), ('\u{173}', 370), ('\u{175}', 372), ('\u{177}', 374), - ('\u{17a}', 377), ('\u{17c}', 379), ('\u{17e}', 381), ('\u{17f}', 83), ('\u{180}', 579), - ('\u{183}', 386), ('\u{185}', 388), ('\u{188}', 391), ('\u{18c}', 395), ('\u{192}', 401), - ('\u{195}', 502), ('\u{199}', 408), ('\u{19a}', 573), ('\u{19b}', 42972), ('\u{19e}', 544), - ('\u{1a1}', 416), ('\u{1a3}', 418), ('\u{1a5}', 420), ('\u{1a8}', 423), ('\u{1ad}', 428), - ('\u{1b0}', 431), ('\u{1b4}', 435), ('\u{1b6}', 437), ('\u{1b9}', 440), ('\u{1bd}', 444), - ('\u{1bf}', 503), ('\u{1c5}', 452), ('\u{1c6}', 452), ('\u{1c8}', 455), ('\u{1c9}', 455), - ('\u{1cb}', 458), ('\u{1cc}', 458), ('\u{1ce}', 461), ('\u{1d0}', 463), ('\u{1d2}', 465), - ('\u{1d4}', 467), ('\u{1d6}', 469), ('\u{1d8}', 471), ('\u{1da}', 473), ('\u{1dc}', 475), - ('\u{1dd}', 398), ('\u{1df}', 478), ('\u{1e1}', 480), ('\u{1e3}', 482), ('\u{1e5}', 484), - ('\u{1e7}', 486), ('\u{1e9}', 488), ('\u{1eb}', 490), ('\u{1ed}', 492), ('\u{1ef}', 494), - ('\u{1f0}', 4194306), ('\u{1f2}', 497), ('\u{1f3}', 497), ('\u{1f5}', 500), - ('\u{1f9}', 504), ('\u{1fb}', 506), ('\u{1fd}', 508), ('\u{1ff}', 510), ('\u{201}', 512), - ('\u{203}', 514), ('\u{205}', 516), ('\u{207}', 518), ('\u{209}', 520), ('\u{20b}', 522), - ('\u{20d}', 524), ('\u{20f}', 526), ('\u{211}', 528), ('\u{213}', 530), ('\u{215}', 532), - ('\u{217}', 534), ('\u{219}', 536), ('\u{21b}', 538), ('\u{21d}', 540), ('\u{21f}', 542), - ('\u{223}', 546), ('\u{225}', 548), ('\u{227}', 550), ('\u{229}', 552), ('\u{22b}', 554), - ('\u{22d}', 556), ('\u{22f}', 558), ('\u{231}', 560), ('\u{233}', 562), ('\u{23c}', 571), - ('\u{23f}', 11390), ('\u{240}', 11391), ('\u{242}', 577), ('\u{247}', 582), - ('\u{249}', 584), ('\u{24b}', 586), ('\u{24d}', 588), ('\u{24f}', 590), ('\u{250}', 11375), - ('\u{251}', 11373), ('\u{252}', 11376), ('\u{253}', 385), ('\u{254}', 390), - ('\u{256}', 393), ('\u{257}', 394), ('\u{259}', 399), ('\u{25b}', 400), ('\u{25c}', 42923), - ('\u{260}', 403), ('\u{261}', 42924), ('\u{263}', 404), ('\u{264}', 42955), - ('\u{265}', 42893), ('\u{266}', 42922), ('\u{268}', 407), ('\u{269}', 406), - ('\u{26a}', 42926), ('\u{26b}', 11362), ('\u{26c}', 42925), ('\u{26f}', 412), - ('\u{271}', 11374), ('\u{272}', 413), ('\u{275}', 415), ('\u{27d}', 11364), - ('\u{280}', 422), ('\u{282}', 42949), ('\u{283}', 425), ('\u{287}', 42929), - ('\u{288}', 430), ('\u{289}', 580), ('\u{28a}', 433), ('\u{28b}', 434), ('\u{28c}', 581), - ('\u{292}', 439), ('\u{29d}', 42930), ('\u{29e}', 42928), ('\u{345}', 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('\u{10cc9}', 68745), ('\u{10cca}', 68746), ('\u{10ccb}', 68747), ('\u{10ccc}', 68748), - ('\u{10ccd}', 68749), ('\u{10cce}', 68750), ('\u{10ccf}', 68751), ('\u{10cd0}', 68752), - ('\u{10cd1}', 68753), ('\u{10cd2}', 68754), ('\u{10cd3}', 68755), ('\u{10cd4}', 68756), - ('\u{10cd5}', 68757), ('\u{10cd6}', 68758), ('\u{10cd7}', 68759), ('\u{10cd8}', 68760), - ('\u{10cd9}', 68761), ('\u{10cda}', 68762), ('\u{10cdb}', 68763), ('\u{10cdc}', 68764), - ('\u{10cdd}', 68765), ('\u{10cde}', 68766), ('\u{10cdf}', 68767), ('\u{10ce0}', 68768), - ('\u{10ce1}', 68769), ('\u{10ce2}', 68770), ('\u{10ce3}', 68771), ('\u{10ce4}', 68772), - ('\u{10ce5}', 68773), ('\u{10ce6}', 68774), ('\u{10ce7}', 68775), ('\u{10ce8}', 68776), - ('\u{10ce9}', 68777), ('\u{10cea}', 68778), ('\u{10ceb}', 68779), ('\u{10cec}', 68780), - ('\u{10ced}', 68781), ('\u{10cee}', 68782), ('\u{10cef}', 68783), ('\u{10cf0}', 68784), - ('\u{10cf1}', 68785), ('\u{10cf2}', 68786), ('\u{10d70}', 68944), ('\u{10d71}', 68945), - ('\u{10d72}', 68946), ('\u{10d73}', 68947), ('\u{10d74}', 68948), ('\u{10d75}', 68949), - ('\u{10d76}', 68950), ('\u{10d77}', 68951), ('\u{10d78}', 68952), ('\u{10d79}', 68953), - ('\u{10d7a}', 68954), ('\u{10d7b}', 68955), ('\u{10d7c}', 68956), ('\u{10d7d}', 68957), - ('\u{10d7e}', 68958), ('\u{10d7f}', 68959), ('\u{10d80}', 68960), ('\u{10d81}', 68961), - ('\u{10d82}', 68962), ('\u{10d83}', 68963), ('\u{10d84}', 68964), ('\u{10d85}', 68965), - ('\u{118c0}', 71840), ('\u{118c1}', 71841), ('\u{118c2}', 71842), ('\u{118c3}', 71843), - ('\u{118c4}', 71844), ('\u{118c5}', 71845), ('\u{118c6}', 71846), ('\u{118c7}', 71847), - ('\u{118c8}', 71848), ('\u{118c9}', 71849), ('\u{118ca}', 71850), ('\u{118cb}', 71851), - ('\u{118cc}', 71852), ('\u{118cd}', 71853), ('\u{118ce}', 71854), ('\u{118cf}', 71855), - ('\u{118d0}', 71856), ('\u{118d1}', 71857), ('\u{118d2}', 71858), ('\u{118d3}', 71859), - ('\u{118d4}', 71860), ('\u{118d5}', 71861), ('\u{118d6}', 71862), ('\u{118d7}', 71863), - ('\u{118d8}', 71864), ('\u{118d9}', 71865), ('\u{118da}', 71866), ('\u{118db}', 71867), - ('\u{118dc}', 71868), ('\u{118dd}', 71869), ('\u{118de}', 71870), ('\u{118df}', 71871), - ('\u{16e60}', 93760), ('\u{16e61}', 93761), ('\u{16e62}', 93762), ('\u{16e63}', 93763), - ('\u{16e64}', 93764), ('\u{16e65}', 93765), ('\u{16e66}', 93766), ('\u{16e67}', 93767), - ('\u{16e68}', 93768), ('\u{16e69}', 93769), ('\u{16e6a}', 93770), ('\u{16e6b}', 93771), - ('\u{16e6c}', 93772), ('\u{16e6d}', 93773), ('\u{16e6e}', 93774), ('\u{16e6f}', 93775), - ('\u{16e70}', 93776), ('\u{16e71}', 93777), ('\u{16e72}', 93778), ('\u{16e73}', 93779), - ('\u{16e74}', 93780), ('\u{16e75}', 93781), ('\u{16e76}', 93782), ('\u{16e77}', 93783), - ('\u{16e78}', 93784), ('\u{16e79}', 93785), ('\u{16e7a}', 93786), ('\u{16e7b}', 93787), - ('\u{16e7c}', 93788), ('\u{16e7d}', 93789), ('\u{16e7e}', 93790), ('\u{16e7f}', 93791), - ('\u{16ebb}', 93856), ('\u{16ebc}', 93857), ('\u{16ebd}', 93858), ('\u{16ebe}', 93859), - ('\u{16ebf}', 93860), ('\u{16ec0}', 93861), ('\u{16ec1}', 93862), ('\u{16ec2}', 93863), - ('\u{16ec3}', 93864), ('\u{16ec4}', 93865), ('\u{16ec5}', 93866), ('\u{16ec6}', 93867), - ('\u{16ec7}', 93868), ('\u{16ec8}', 93869), ('\u{16ec9}', 93870), ('\u{16eca}', 93871), - ('\u{16ecb}', 93872), ('\u{16ecc}', 93873), ('\u{16ecd}', 93874), ('\u{16ece}', 93875), - ('\u{16ecf}', 93876), ('\u{16ed0}', 93877), ('\u{16ed1}', 93878), ('\u{16ed2}', 93879), - ('\u{16ed3}', 93880), ('\u{1e922}', 125184), ('\u{1e923}', 125185), ('\u{1e924}', 125186), - ('\u{1e925}', 125187), ('\u{1e926}', 125188), ('\u{1e927}', 125189), ('\u{1e928}', 125190), - ('\u{1e929}', 125191), ('\u{1e92a}', 125192), ('\u{1e92b}', 125193), ('\u{1e92c}', 125194), - ('\u{1e92d}', 125195), ('\u{1e92e}', 125196), ('\u{1e92f}', 125197), ('\u{1e930}', 125198), - ('\u{1e931}', 125199), ('\u{1e932}', 125200), ('\u{1e933}', 125201), ('\u{1e934}', 125202), - ('\u{1e935}', 125203), ('\u{1e936}', 125204), ('\u{1e937}', 125205), ('\u{1e938}', 125206), - ('\u{1e939}', 125207), ('\u{1e93a}', 125208), ('\u{1e93b}', 125209), ('\u{1e93c}', 125210), - ('\u{1e93d}', 125211), ('\u{1e93e}', 125212), ('\u{1e93f}', 125213), ('\u{1e940}', 125214), - ('\u{1e941}', 125215), ('\u{1e942}', 125216), ('\u{1e943}', 125217), - ]; + static LOWERCASE_LUT: L1Lut = L1Lut { + l2_luts: [ + L2Lut { + singles: &[ // 172 entries, 1032 bytes + (Range::step_by_1(0x00c0..=0x00d6), 32), (Range::step_by_1(0x00d8..=0x00de), 32), + (Range::step_by_2(0x0100..=0x012e), 1), (Range::step_by_2(0x0132..=0x0136), 1), + (Range::step_by_2(0x0139..=0x0147), 1), (Range::step_by_2(0x014a..=0x0176), 1), + (Range::singleton(0x0178), -121), (Range::step_by_2(0x0179..=0x017d), 1), + (Range::singleton(0x0181), 210), (Range::step_by_2(0x0182..=0x0184), 1), + (Range::singleton(0x0186), 206), (Range::singleton(0x0187), 1), + (Range::step_by_1(0x0189..=0x018a), 205), (Range::singleton(0x018b), 1), + (Range::singleton(0x018e), 79), (Range::singleton(0x018f), 202), + (Range::singleton(0x0190), 203), (Range::singleton(0x0191), 1), + (Range::singleton(0x0193), 205), (Range::singleton(0x0194), 207), + (Range::singleton(0x0196), 211), (Range::singleton(0x0197), 209), + (Range::singleton(0x0198), 1), (Range::singleton(0x019c), 211), + (Range::singleton(0x019d), 213), (Range::singleton(0x019f), 214), + (Range::step_by_2(0x01a0..=0x01a4), 1), (Range::singleton(0x01a6), 218), + (Range::singleton(0x01a7), 1), (Range::singleton(0x01a9), 218), + (Range::singleton(0x01ac), 1), (Range::singleton(0x01ae), 218), + (Range::singleton(0x01af), 1), (Range::step_by_1(0x01b1..=0x01b2), 217), + (Range::step_by_2(0x01b3..=0x01b5), 1), (Range::singleton(0x01b7), 219), + (Range::singleton(0x01b8), 1), (Range::singleton(0x01bc), 1), (Range::singleton(0x01c4), 2), + (Range::singleton(0x01c5), 1), (Range::singleton(0x01c7), 2), (Range::singleton(0x01c8), 1), + (Range::singleton(0x01ca), 2), (Range::step_by_2(0x01cb..=0x01db), 1), + (Range::step_by_2(0x01de..=0x01ee), 1), (Range::singleton(0x01f1), 2), + (Range::step_by_2(0x01f2..=0x01f4), 1), (Range::singleton(0x01f6), -97), + (Range::singleton(0x01f7), -56), (Range::step_by_2(0x01f8..=0x021e), 1), + (Range::singleton(0x0220), -130), (Range::step_by_2(0x0222..=0x0232), 1), + (Range::singleton(0x023a), 10795), (Range::singleton(0x023b), 1), + (Range::singleton(0x023d), -163), (Range::singleton(0x023e), 10792), + (Range::singleton(0x0241), 1), (Range::singleton(0x0243), -195), + (Range::singleton(0x0244), 69), (Range::singleton(0x0245), 71), + (Range::step_by_2(0x0246..=0x024e), 1), (Range::step_by_2(0x0370..=0x0372), 1), + (Range::singleton(0x0376), 1), (Range::singleton(0x037f), 116), + (Range::singleton(0x0386), 38), (Range::step_by_1(0x0388..=0x038a), 37), + (Range::singleton(0x038c), 64), (Range::step_by_1(0x038e..=0x038f), 63), + (Range::step_by_1(0x0391..=0x03a1), 32), (Range::step_by_1(0x03a3..=0x03ab), 32), + (Range::singleton(0x03cf), 8), (Range::step_by_2(0x03d8..=0x03ee), 1), + (Range::singleton(0x03f4), -60), (Range::singleton(0x03f7), 1), + (Range::singleton(0x03f9), -7), (Range::singleton(0x03fa), 1), + (Range::step_by_1(0x03fd..=0x03ff), -130), (Range::step_by_1(0x0400..=0x040f), 80), + (Range::step_by_1(0x0410..=0x042f), 32), (Range::step_by_2(0x0460..=0x0480), 1), + (Range::step_by_2(0x048a..=0x04be), 1), (Range::singleton(0x04c0), 15), + (Range::step_by_2(0x04c1..=0x04cd), 1), (Range::step_by_2(0x04d0..=0x052e), 1), + (Range::step_by_1(0x0531..=0x0556), 48), (Range::step_by_1(0x10a0..=0x10c5), 7264), + (Range::singleton(0x10c7), 7264), (Range::singleton(0x10cd), 7264), + (Range::step_by_1(0x13a0..=0x13ef), -26672), (Range::step_by_1(0x13f0..=0x13f5), 8), + (Range::singleton(0x1c89), 1), (Range::step_by_1(0x1c90..=0x1cba), -3008), + (Range::step_by_1(0x1cbd..=0x1cbf), -3008), (Range::step_by_2(0x1e00..=0x1e94), 1), + (Range::singleton(0x1e9e), -7615), (Range::step_by_2(0x1ea0..=0x1efe), 1), + (Range::step_by_1(0x1f08..=0x1f0f), -8), (Range::step_by_1(0x1f18..=0x1f1d), -8), + (Range::step_by_1(0x1f28..=0x1f2f), -8), (Range::step_by_1(0x1f38..=0x1f3f), -8), + (Range::step_by_1(0x1f48..=0x1f4d), -8), (Range::step_by_2(0x1f59..=0x1f5f), -8), + (Range::step_by_1(0x1f68..=0x1f6f), -8), (Range::step_by_1(0x1f88..=0x1f8f), -8), + (Range::step_by_1(0x1f98..=0x1f9f), -8), (Range::step_by_1(0x1fa8..=0x1faf), -8), + (Range::step_by_1(0x1fb8..=0x1fb9), -8), (Range::step_by_1(0x1fba..=0x1fbb), -74), + (Range::singleton(0x1fbc), -9), (Range::step_by_1(0x1fc8..=0x1fcb), -86), + (Range::singleton(0x1fcc), -9), (Range::step_by_1(0x1fd8..=0x1fd9), -8), + (Range::step_by_1(0x1fda..=0x1fdb), -100), (Range::step_by_1(0x1fe8..=0x1fe9), -8), + (Range::step_by_1(0x1fea..=0x1feb), -112), (Range::singleton(0x1fec), -7), + (Range::step_by_1(0x1ff8..=0x1ff9), -128), (Range::step_by_1(0x1ffa..=0x1ffb), -126), + (Range::singleton(0x1ffc), -9), (Range::singleton(0x2126), -7517), + (Range::singleton(0x212a), -8383), (Range::singleton(0x212b), -8262), + (Range::singleton(0x2132), 28), (Range::step_by_1(0x2160..=0x216f), 16), + (Range::singleton(0x2183), 1), (Range::step_by_1(0x24b6..=0x24cf), 26), + (Range::step_by_1(0x2c00..=0x2c2f), 48), (Range::singleton(0x2c60), 1), + (Range::singleton(0x2c62), -10743), (Range::singleton(0x2c63), -3814), + (Range::singleton(0x2c64), -10727), (Range::step_by_2(0x2c67..=0x2c6b), 1), + (Range::singleton(0x2c6d), -10780), (Range::singleton(0x2c6e), -10749), + (Range::singleton(0x2c6f), -10783), (Range::singleton(0x2c70), -10782), + (Range::singleton(0x2c72), 1), (Range::singleton(0x2c75), 1), + (Range::step_by_1(0x2c7e..=0x2c7f), -10815), (Range::step_by_2(0x2c80..=0x2ce2), 1), + (Range::step_by_2(0x2ceb..=0x2ced), 1), (Range::singleton(0x2cf2), 1), + (Range::step_by_2(0xa640..=0xa66c), 1), (Range::step_by_2(0xa680..=0xa69a), 1), + (Range::step_by_2(0xa722..=0xa72e), 1), (Range::step_by_2(0xa732..=0xa76e), 1), + (Range::step_by_2(0xa779..=0xa77b), 1), (Range::singleton(0xa77d), 30204), + (Range::step_by_2(0xa77e..=0xa786), 1), (Range::singleton(0xa78b), 1), + (Range::singleton(0xa78d), 23256), (Range::step_by_2(0xa790..=0xa792), 1), + (Range::step_by_2(0xa796..=0xa7a8), 1), (Range::singleton(0xa7aa), 23228), + (Range::singleton(0xa7ab), 23217), (Range::singleton(0xa7ac), 23221), + (Range::singleton(0xa7ad), 23231), (Range::singleton(0xa7ae), 23228), + (Range::singleton(0xa7b0), 23278), (Range::singleton(0xa7b1), 23254), + (Range::singleton(0xa7b2), 23275), (Range::singleton(0xa7b3), 928), + (Range::step_by_2(0xa7b4..=0xa7c2), 1), (Range::singleton(0xa7c4), -48), + (Range::singleton(0xa7c5), 23229), (Range::singleton(0xa7c6), 30152), + (Range::step_by_2(0xa7c7..=0xa7c9), 1), (Range::singleton(0xa7cb), 23193), + (Range::step_by_2(0xa7cc..=0xa7da), 1), (Range::singleton(0xa7dc), 22975), + (Range::singleton(0xa7f5), 1), (Range::step_by_1(0xff21..=0xff3a), 32), + ], + multis: &[ // 1 entries, 8 bytes + (0x0130, [0x0069, 0x0307, 0x0000]), + ], + }, + L2Lut { + singles: &[ // 12 entries, 72 bytes + (Range::step_by_1(0x0400..=0x0427), 40), (Range::step_by_1(0x04b0..=0x04d3), 40), + (Range::step_by_1(0x0570..=0x057a), 39), (Range::step_by_1(0x057c..=0x058a), 39), + (Range::step_by_1(0x058c..=0x0592), 39), (Range::step_by_1(0x0594..=0x0595), 39), + (Range::step_by_1(0x0c80..=0x0cb2), 64), (Range::step_by_1(0x0d50..=0x0d65), 32), + (Range::step_by_1(0x18a0..=0x18bf), 32), (Range::step_by_1(0x6e40..=0x6e5f), 32), + (Range::step_by_1(0x6ea0..=0x6eb8), 27), (Range::step_by_1(0xe900..=0xe921), 34), + ], + multis: &[ // 0 entries, 0 bytes + ], + }, + ], + }; - static UPPERCASE_TABLE_MULTI: &[[char; 3]; 102] = &[ - ['S', 'S', '\u{0}'], ['\u{2bc}', 'N', '\u{0}'], ['J', '\u{30c}', '\u{0}'], - ['\u{399}', '\u{308}', '\u{301}'], ['\u{3a5}', '\u{308}', '\u{301}'], - ['\u{535}', '\u{552}', '\u{0}'], ['H', '\u{331}', '\u{0}'], ['T', '\u{308}', '\u{0}'], - ['W', '\u{30a}', '\u{0}'], ['Y', '\u{30a}', '\u{0}'], ['A', '\u{2be}', '\u{0}'], - ['\u{3a5}', '\u{313}', '\u{0}'], ['\u{3a5}', '\u{313}', '\u{300}'], - ['\u{3a5}', '\u{313}', '\u{301}'], ['\u{3a5}', '\u{313}', '\u{342}'], - ['\u{1f08}', '\u{399}', '\u{0}'], ['\u{1f09}', '\u{399}', '\u{0}'], - ['\u{1f0a}', '\u{399}', '\u{0}'], ['\u{1f0b}', '\u{399}', '\u{0}'], - ['\u{1f0c}', '\u{399}', '\u{0}'], ['\u{1f0d}', '\u{399}', '\u{0}'], - ['\u{1f0e}', '\u{399}', '\u{0}'], ['\u{1f0f}', '\u{399}', '\u{0}'], - ['\u{1f08}', '\u{399}', '\u{0}'], ['\u{1f09}', '\u{399}', '\u{0}'], - ['\u{1f0a}', '\u{399}', '\u{0}'], ['\u{1f0b}', '\u{399}', '\u{0}'], - ['\u{1f0c}', '\u{399}', '\u{0}'], ['\u{1f0d}', '\u{399}', '\u{0}'], - ['\u{1f0e}', '\u{399}', '\u{0}'], ['\u{1f0f}', '\u{399}', '\u{0}'], - ['\u{1f28}', '\u{399}', '\u{0}'], ['\u{1f29}', '\u{399}', '\u{0}'], - ['\u{1f2a}', '\u{399}', '\u{0}'], ['\u{1f2b}', '\u{399}', '\u{0}'], - ['\u{1f2c}', '\u{399}', '\u{0}'], ['\u{1f2d}', '\u{399}', '\u{0}'], - ['\u{1f2e}', '\u{399}', '\u{0}'], ['\u{1f2f}', '\u{399}', '\u{0}'], - ['\u{1f28}', '\u{399}', '\u{0}'], ['\u{1f29}', '\u{399}', '\u{0}'], - ['\u{1f2a}', '\u{399}', '\u{0}'], ['\u{1f2b}', '\u{399}', '\u{0}'], - ['\u{1f2c}', '\u{399}', '\u{0}'], ['\u{1f2d}', '\u{399}', '\u{0}'], - ['\u{1f2e}', '\u{399}', '\u{0}'], ['\u{1f2f}', '\u{399}', '\u{0}'], - ['\u{1f68}', '\u{399}', '\u{0}'], ['\u{1f69}', '\u{399}', '\u{0}'], - ['\u{1f6a}', '\u{399}', '\u{0}'], ['\u{1f6b}', '\u{399}', '\u{0}'], - ['\u{1f6c}', '\u{399}', '\u{0}'], ['\u{1f6d}', '\u{399}', '\u{0}'], - ['\u{1f6e}', '\u{399}', '\u{0}'], ['\u{1f6f}', '\u{399}', '\u{0}'], - ['\u{1f68}', '\u{399}', '\u{0}'], ['\u{1f69}', '\u{399}', '\u{0}'], - ['\u{1f6a}', '\u{399}', '\u{0}'], ['\u{1f6b}', '\u{399}', '\u{0}'], - ['\u{1f6c}', '\u{399}', '\u{0}'], ['\u{1f6d}', '\u{399}', '\u{0}'], - ['\u{1f6e}', '\u{399}', '\u{0}'], ['\u{1f6f}', '\u{399}', '\u{0}'], - ['\u{1fba}', '\u{399}', '\u{0}'], ['\u{391}', '\u{399}', '\u{0}'], - ['\u{386}', '\u{399}', '\u{0}'], ['\u{391}', '\u{342}', '\u{0}'], - ['\u{391}', '\u{342}', '\u{399}'], ['\u{391}', '\u{399}', '\u{0}'], - ['\u{1fca}', '\u{399}', '\u{0}'], ['\u{397}', '\u{399}', '\u{0}'], - ['\u{389}', '\u{399}', '\u{0}'], ['\u{397}', '\u{342}', '\u{0}'], - ['\u{397}', '\u{342}', '\u{399}'], ['\u{397}', '\u{399}', '\u{0}'], - ['\u{399}', '\u{308}', '\u{300}'], ['\u{399}', '\u{308}', '\u{301}'], - ['\u{399}', '\u{342}', '\u{0}'], ['\u{399}', '\u{308}', '\u{342}'], - ['\u{3a5}', '\u{308}', '\u{300}'], ['\u{3a5}', '\u{308}', '\u{301}'], - ['\u{3a1}', '\u{313}', '\u{0}'], ['\u{3a5}', '\u{342}', '\u{0}'], - ['\u{3a5}', '\u{308}', '\u{342}'], ['\u{1ffa}', '\u{399}', '\u{0}'], - ['\u{3a9}', '\u{399}', '\u{0}'], ['\u{38f}', '\u{399}', '\u{0}'], - ['\u{3a9}', '\u{342}', '\u{0}'], ['\u{3a9}', '\u{342}', '\u{399}'], - ['\u{3a9}', '\u{399}', '\u{0}'], ['F', 'F', '\u{0}'], ['F', 'I', '\u{0}'], - ['F', 'L', '\u{0}'], ['F', 'F', 'I'], ['F', 'F', 'L'], ['S', 'T', '\u{0}'], - ['S', 'T', '\u{0}'], ['\u{544}', '\u{546}', '\u{0}'], ['\u{544}', '\u{535}', '\u{0}'], - ['\u{544}', '\u{53b}', '\u{0}'], ['\u{54e}', '\u{546}', '\u{0}'], - ['\u{544}', '\u{53d}', '\u{0}'], - ]; + static UPPERCASE_LUT: L1Lut = L1Lut { + l2_luts: [ + L2Lut { + singles: &[ // 185 entries, 1110 bytes + (Range::singleton(0x00b5), 743), (Range::step_by_1(0x00e0..=0x00f6), -32), + (Range::step_by_1(0x00f8..=0x00fe), -32), (Range::singleton(0x00ff), 121), + (Range::step_by_2(0x0101..=0x012f), -1), (Range::singleton(0x0131), -232), + (Range::step_by_2(0x0133..=0x0137), -1), (Range::step_by_2(0x013a..=0x0148), -1), + (Range::step_by_2(0x014b..=0x0177), -1), (Range::step_by_2(0x017a..=0x017e), -1), + (Range::singleton(0x017f), -300), (Range::singleton(0x0180), 195), + (Range::step_by_2(0x0183..=0x0185), -1), (Range::singleton(0x0188), -1), + (Range::singleton(0x018c), -1), (Range::singleton(0x0192), -1), + (Range::singleton(0x0195), 97), (Range::singleton(0x0199), -1), + (Range::singleton(0x019a), 163), (Range::singleton(0x019b), -22975), + (Range::singleton(0x019e), 130), (Range::step_by_2(0x01a1..=0x01a5), -1), + (Range::singleton(0x01a8), -1), (Range::singleton(0x01ad), -1), + (Range::singleton(0x01b0), -1), (Range::step_by_2(0x01b4..=0x01b6), -1), + (Range::singleton(0x01b9), -1), (Range::singleton(0x01bd), -1), + (Range::singleton(0x01bf), 56), (Range::singleton(0x01c5), -1), + (Range::singleton(0x01c6), -2), (Range::singleton(0x01c8), -1), + (Range::singleton(0x01c9), -2), (Range::singleton(0x01cb), -1), + (Range::singleton(0x01cc), -2), (Range::step_by_2(0x01ce..=0x01dc), -1), + (Range::singleton(0x01dd), -79), (Range::step_by_2(0x01df..=0x01ef), -1), + (Range::singleton(0x01f2), -1), (Range::singleton(0x01f3), -2), + (Range::singleton(0x01f5), -1), (Range::step_by_2(0x01f9..=0x021f), -1), + (Range::step_by_2(0x0223..=0x0233), -1), (Range::singleton(0x023c), -1), + (Range::step_by_1(0x023f..=0x0240), 10815), (Range::singleton(0x0242), -1), + (Range::step_by_2(0x0247..=0x024f), -1), (Range::singleton(0x0250), 10783), + (Range::singleton(0x0251), 10780), (Range::singleton(0x0252), 10782), + (Range::singleton(0x0253), -210), (Range::singleton(0x0254), -206), + (Range::step_by_1(0x0256..=0x0257), -205), (Range::singleton(0x0259), -202), + (Range::singleton(0x025b), -203), (Range::singleton(0x025c), -23217), + (Range::singleton(0x0260), -205), (Range::singleton(0x0261), -23221), + (Range::singleton(0x0263), -207), (Range::singleton(0x0264), -23193), + (Range::singleton(0x0265), -23256), (Range::singleton(0x0266), -23228), + (Range::singleton(0x0268), -209), (Range::singleton(0x0269), -211), + (Range::singleton(0x026a), -23228), (Range::singleton(0x026b), 10743), + (Range::singleton(0x026c), -23231), (Range::singleton(0x026f), -211), + (Range::singleton(0x0271), 10749), (Range::singleton(0x0272), -213), + (Range::singleton(0x0275), -214), (Range::singleton(0x027d), 10727), + (Range::singleton(0x0280), -218), (Range::singleton(0x0282), -23229), + (Range::singleton(0x0283), -218), (Range::singleton(0x0287), -23254), + (Range::singleton(0x0288), -218), (Range::singleton(0x0289), -69), + (Range::step_by_1(0x028a..=0x028b), -217), (Range::singleton(0x028c), -71), + (Range::singleton(0x0292), -219), (Range::singleton(0x029d), -23275), + (Range::singleton(0x029e), -23278), (Range::singleton(0x0345), 84), + (Range::step_by_2(0x0371..=0x0373), -1), (Range::singleton(0x0377), -1), + (Range::step_by_1(0x037b..=0x037d), 130), (Range::singleton(0x03ac), -38), + (Range::step_by_1(0x03ad..=0x03af), -37), (Range::step_by_1(0x03b1..=0x03c1), -32), + (Range::singleton(0x03c2), -31), (Range::step_by_1(0x03c3..=0x03cb), -32), + (Range::singleton(0x03cc), -64), (Range::step_by_1(0x03cd..=0x03ce), -63), + (Range::singleton(0x03d0), -62), (Range::singleton(0x03d1), -57), + (Range::singleton(0x03d5), -47), (Range::singleton(0x03d6), -54), + (Range::singleton(0x03d7), -8), (Range::step_by_2(0x03d9..=0x03ef), -1), + (Range::singleton(0x03f0), -86), (Range::singleton(0x03f1), -80), + (Range::singleton(0x03f2), 7), (Range::singleton(0x03f3), -116), + (Range::singleton(0x03f5), -96), (Range::singleton(0x03f8), -1), + (Range::singleton(0x03fb), -1), (Range::step_by_1(0x0430..=0x044f), -32), + (Range::step_by_1(0x0450..=0x045f), -80), (Range::step_by_2(0x0461..=0x0481), -1), + (Range::step_by_2(0x048b..=0x04bf), -1), (Range::step_by_2(0x04c2..=0x04ce), -1), + (Range::singleton(0x04cf), -15), (Range::step_by_2(0x04d1..=0x052f), -1), + (Range::step_by_1(0x0561..=0x0586), -48), (Range::step_by_1(0x10d0..=0x10fa), 3008), + (Range::step_by_1(0x10fd..=0x10ff), 3008), (Range::step_by_1(0x13f8..=0x13fd), -8), + (Range::singleton(0x1c80), -6254), (Range::singleton(0x1c81), -6253), + (Range::singleton(0x1c82), -6244), (Range::step_by_1(0x1c83..=0x1c84), -6242), + (Range::singleton(0x1c85), -6243), (Range::singleton(0x1c86), -6236), + (Range::singleton(0x1c87), -6181), (Range::singleton(0x1c88), -30270), + (Range::singleton(0x1c8a), -1), (Range::singleton(0x1d79), -30204), + (Range::singleton(0x1d7d), 3814), (Range::singleton(0x1d8e), -30152), + (Range::step_by_2(0x1e01..=0x1e95), -1), (Range::singleton(0x1e9b), -59), + (Range::step_by_2(0x1ea1..=0x1eff), -1), (Range::step_by_1(0x1f00..=0x1f07), 8), + (Range::step_by_1(0x1f10..=0x1f15), 8), (Range::step_by_1(0x1f20..=0x1f27), 8), + (Range::step_by_1(0x1f30..=0x1f37), 8), (Range::step_by_1(0x1f40..=0x1f45), 8), + (Range::step_by_2(0x1f51..=0x1f57), 8), (Range::step_by_1(0x1f60..=0x1f67), 8), + (Range::step_by_1(0x1f70..=0x1f71), 74), (Range::step_by_1(0x1f72..=0x1f75), 86), + (Range::step_by_1(0x1f76..=0x1f77), 100), (Range::step_by_1(0x1f78..=0x1f79), 128), + (Range::step_by_1(0x1f7a..=0x1f7b), 112), (Range::step_by_1(0x1f7c..=0x1f7d), 126), + (Range::step_by_1(0x1fb0..=0x1fb1), 8), (Range::singleton(0x1fbe), -7205), + (Range::step_by_1(0x1fd0..=0x1fd1), 8), (Range::step_by_1(0x1fe0..=0x1fe1), 8), + (Range::singleton(0x1fe5), 7), (Range::singleton(0x214e), -28), + (Range::step_by_1(0x2170..=0x217f), -16), (Range::singleton(0x2184), -1), + (Range::step_by_1(0x24d0..=0x24e9), -26), (Range::step_by_1(0x2c30..=0x2c5f), -48), + (Range::singleton(0x2c61), -1), (Range::singleton(0x2c65), -10795), + (Range::singleton(0x2c66), -10792), (Range::step_by_2(0x2c68..=0x2c6c), -1), + (Range::singleton(0x2c73), -1), (Range::singleton(0x2c76), -1), + (Range::step_by_2(0x2c81..=0x2ce3), -1), (Range::step_by_2(0x2cec..=0x2cee), -1), + (Range::singleton(0x2cf3), -1), (Range::step_by_1(0x2d00..=0x2d25), -7264), + (Range::singleton(0x2d27), -7264), (Range::singleton(0x2d2d), -7264), + (Range::step_by_2(0xa641..=0xa66d), -1), (Range::step_by_2(0xa681..=0xa69b), -1), + (Range::step_by_2(0xa723..=0xa72f), -1), (Range::step_by_2(0xa733..=0xa76f), -1), + (Range::step_by_2(0xa77a..=0xa77c), -1), (Range::step_by_2(0xa77f..=0xa787), -1), + (Range::singleton(0xa78c), -1), (Range::step_by_2(0xa791..=0xa793), -1), + (Range::singleton(0xa794), 48), (Range::step_by_2(0xa797..=0xa7a9), -1), + (Range::step_by_2(0xa7b5..=0xa7c3), -1), (Range::step_by_2(0xa7c8..=0xa7ca), -1), + (Range::step_by_2(0xa7cd..=0xa7db), -1), (Range::singleton(0xa7f6), -1), + (Range::singleton(0xab53), -928), (Range::step_by_1(0xab70..=0xabbf), 26672), + (Range::step_by_1(0xff41..=0xff5a), -32), + ], + multis: &[ // 102 entries, 816 bytes + (0x00df, [0x0053, 0x0053, 0x0000]), (0x0149, [0x02bc, 0x004e, 0x0000]), + (0x01f0, [0x004a, 0x030c, 0x0000]), (0x0390, [0x0399, 0x0308, 0x0301]), + (0x03b0, [0x03a5, 0x0308, 0x0301]), (0x0587, [0x0535, 0x0552, 0x0000]), + (0x1e96, [0x0048, 0x0331, 0x0000]), (0x1e97, [0x0054, 0x0308, 0x0000]), + (0x1e98, [0x0057, 0x030a, 0x0000]), (0x1e99, [0x0059, 0x030a, 0x0000]), + (0x1e9a, [0x0041, 0x02be, 0x0000]), (0x1f50, [0x03a5, 0x0313, 0x0000]), + (0x1f52, [0x03a5, 0x0313, 0x0300]), (0x1f54, [0x03a5, 0x0313, 0x0301]), + (0x1f56, [0x03a5, 0x0313, 0x0342]), (0x1f80, [0x1f08, 0x0399, 0x0000]), + (0x1f81, [0x1f09, 0x0399, 0x0000]), (0x1f82, [0x1f0a, 0x0399, 0x0000]), + (0x1f83, [0x1f0b, 0x0399, 0x0000]), (0x1f84, [0x1f0c, 0x0399, 0x0000]), + (0x1f85, [0x1f0d, 0x0399, 0x0000]), (0x1f86, [0x1f0e, 0x0399, 0x0000]), + (0x1f87, [0x1f0f, 0x0399, 0x0000]), (0x1f88, [0x1f08, 0x0399, 0x0000]), + (0x1f89, [0x1f09, 0x0399, 0x0000]), (0x1f8a, [0x1f0a, 0x0399, 0x0000]), + (0x1f8b, [0x1f0b, 0x0399, 0x0000]), (0x1f8c, [0x1f0c, 0x0399, 0x0000]), + (0x1f8d, [0x1f0d, 0x0399, 0x0000]), (0x1f8e, [0x1f0e, 0x0399, 0x0000]), + (0x1f8f, [0x1f0f, 0x0399, 0x0000]), (0x1f90, [0x1f28, 0x0399, 0x0000]), + (0x1f91, [0x1f29, 0x0399, 0x0000]), (0x1f92, [0x1f2a, 0x0399, 0x0000]), + (0x1f93, [0x1f2b, 0x0399, 0x0000]), (0x1f94, [0x1f2c, 0x0399, 0x0000]), + (0x1f95, [0x1f2d, 0x0399, 0x0000]), (0x1f96, [0x1f2e, 0x0399, 0x0000]), + (0x1f97, [0x1f2f, 0x0399, 0x0000]), (0x1f98, [0x1f28, 0x0399, 0x0000]), + (0x1f99, [0x1f29, 0x0399, 0x0000]), (0x1f9a, [0x1f2a, 0x0399, 0x0000]), + (0x1f9b, [0x1f2b, 0x0399, 0x0000]), (0x1f9c, [0x1f2c, 0x0399, 0x0000]), + (0x1f9d, [0x1f2d, 0x0399, 0x0000]), (0x1f9e, [0x1f2e, 0x0399, 0x0000]), + (0x1f9f, [0x1f2f, 0x0399, 0x0000]), (0x1fa0, [0x1f68, 0x0399, 0x0000]), + (0x1fa1, [0x1f69, 0x0399, 0x0000]), (0x1fa2, [0x1f6a, 0x0399, 0x0000]), + (0x1fa3, [0x1f6b, 0x0399, 0x0000]), (0x1fa4, [0x1f6c, 0x0399, 0x0000]), + (0x1fa5, [0x1f6d, 0x0399, 0x0000]), (0x1fa6, [0x1f6e, 0x0399, 0x0000]), + (0x1fa7, [0x1f6f, 0x0399, 0x0000]), (0x1fa8, [0x1f68, 0x0399, 0x0000]), + (0x1fa9, [0x1f69, 0x0399, 0x0000]), (0x1faa, [0x1f6a, 0x0399, 0x0000]), + (0x1fab, [0x1f6b, 0x0399, 0x0000]), (0x1fac, [0x1f6c, 0x0399, 0x0000]), + (0x1fad, [0x1f6d, 0x0399, 0x0000]), (0x1fae, [0x1f6e, 0x0399, 0x0000]), + (0x1faf, [0x1f6f, 0x0399, 0x0000]), (0x1fb2, [0x1fba, 0x0399, 0x0000]), + (0x1fb3, [0x0391, 0x0399, 0x0000]), (0x1fb4, [0x0386, 0x0399, 0x0000]), + (0x1fb6, [0x0391, 0x0342, 0x0000]), (0x1fb7, [0x0391, 0x0342, 0x0399]), + (0x1fbc, [0x0391, 0x0399, 0x0000]), (0x1fc2, [0x1fca, 0x0399, 0x0000]), + (0x1fc3, [0x0397, 0x0399, 0x0000]), (0x1fc4, [0x0389, 0x0399, 0x0000]), + (0x1fc6, [0x0397, 0x0342, 0x0000]), (0x1fc7, [0x0397, 0x0342, 0x0399]), + (0x1fcc, [0x0397, 0x0399, 0x0000]), (0x1fd2, [0x0399, 0x0308, 0x0300]), + (0x1fd3, [0x0399, 0x0308, 0x0301]), (0x1fd6, [0x0399, 0x0342, 0x0000]), + (0x1fd7, [0x0399, 0x0308, 0x0342]), (0x1fe2, [0x03a5, 0x0308, 0x0300]), + (0x1fe3, [0x03a5, 0x0308, 0x0301]), (0x1fe4, [0x03a1, 0x0313, 0x0000]), + (0x1fe6, [0x03a5, 0x0342, 0x0000]), (0x1fe7, [0x03a5, 0x0308, 0x0342]), + (0x1ff2, [0x1ffa, 0x0399, 0x0000]), (0x1ff3, [0x03a9, 0x0399, 0x0000]), + (0x1ff4, [0x038f, 0x0399, 0x0000]), (0x1ff6, [0x03a9, 0x0342, 0x0000]), + (0x1ff7, [0x03a9, 0x0342, 0x0399]), (0x1ffc, [0x03a9, 0x0399, 0x0000]), + (0xfb00, [0x0046, 0x0046, 0x0000]), (0xfb01, [0x0046, 0x0049, 0x0000]), + (0xfb02, [0x0046, 0x004c, 0x0000]), (0xfb03, [0x0046, 0x0046, 0x0049]), + (0xfb04, [0x0046, 0x0046, 0x004c]), (0xfb05, [0x0053, 0x0054, 0x0000]), + (0xfb06, [0x0053, 0x0054, 0x0000]), (0xfb13, [0x0544, 0x0546, 0x0000]), + (0xfb14, [0x0544, 0x0535, 0x0000]), (0xfb15, [0x0544, 0x053b, 0x0000]), + (0xfb16, [0x054e, 0x0546, 0x0000]), (0xfb17, [0x0544, 0x053d, 0x0000]), + ], + }, + L2Lut { + singles: &[ // 12 entries, 72 bytes + (Range::step_by_1(0x0428..=0x044f), -40), (Range::step_by_1(0x04d8..=0x04fb), -40), + (Range::step_by_1(0x0597..=0x05a1), -39), (Range::step_by_1(0x05a3..=0x05b1), -39), + (Range::step_by_1(0x05b3..=0x05b9), -39), (Range::step_by_1(0x05bb..=0x05bc), -39), + (Range::step_by_1(0x0cc0..=0x0cf2), -64), (Range::step_by_1(0x0d70..=0x0d85), -32), + (Range::step_by_1(0x18c0..=0x18df), -32), (Range::step_by_1(0x6e60..=0x6e7f), -32), + (Range::step_by_1(0x6ebb..=0x6ed3), -27), (Range::step_by_1(0xe922..=0xe943), -34), + ], + multis: &[ // 0 entries, 0 bytes + ], + }, + ], + }; + + static TITLECASE_LUT: L1Lut = L1Lut { + l2_luts: [ + L2Lut { + singles: &[ // 26 entries, 156 bytes + (Range::singleton(0x01c4), 1), (Range::singleton(0x01c5), 0), + (Range::singleton(0x01c6), -1), (Range::singleton(0x01c7), 1), + (Range::singleton(0x01c8), 0), (Range::singleton(0x01c9), -1), + (Range::singleton(0x01ca), 1), (Range::singleton(0x01cb), 0), + (Range::singleton(0x01cc), -1), (Range::singleton(0x01f1), 1), + (Range::singleton(0x01f2), 0), (Range::singleton(0x01f3), -1), + (Range::step_by_1(0x10d0..=0x10fa), 0), (Range::step_by_1(0x10fd..=0x10ff), 0), + (Range::step_by_1(0x1f80..=0x1f87), 8), (Range::step_by_1(0x1f88..=0x1f8f), 0), + (Range::step_by_1(0x1f90..=0x1f97), 8), (Range::step_by_1(0x1f98..=0x1f9f), 0), + (Range::step_by_1(0x1fa0..=0x1fa7), 8), (Range::step_by_1(0x1fa8..=0x1faf), 0), + (Range::singleton(0x1fb3), 9), (Range::singleton(0x1fbc), 0), (Range::singleton(0x1fc3), 9), + (Range::singleton(0x1fcc), 0), (Range::singleton(0x1ff3), 9), (Range::singleton(0x1ffc), 0), + ], + multis: &[ // 23 entries, 184 bytes + (0x00df, [0x0053, 0x0073, 0x0000]), (0x0587, [0x0535, 0x0582, 0x0000]), + (0x1fb2, [0x1fba, 0x0345, 0x0000]), (0x1fb4, [0x0386, 0x0345, 0x0000]), + (0x1fb7, [0x0391, 0x0342, 0x0345]), (0x1fc2, [0x1fca, 0x0345, 0x0000]), + (0x1fc4, [0x0389, 0x0345, 0x0000]), (0x1fc7, [0x0397, 0x0342, 0x0345]), + (0x1ff2, [0x1ffa, 0x0345, 0x0000]), (0x1ff4, [0x038f, 0x0345, 0x0000]), + (0x1ff7, [0x03a9, 0x0342, 0x0345]), (0xfb00, [0x0046, 0x0066, 0x0000]), + (0xfb01, [0x0046, 0x0069, 0x0000]), (0xfb02, [0x0046, 0x006c, 0x0000]), + (0xfb03, [0x0046, 0x0066, 0x0069]), (0xfb04, [0x0046, 0x0066, 0x006c]), + (0xfb05, [0x0053, 0x0074, 0x0000]), (0xfb06, [0x0053, 0x0074, 0x0000]), + (0xfb13, [0x0544, 0x0576, 0x0000]), (0xfb14, [0x0544, 0x0565, 0x0000]), + (0xfb15, [0x0544, 0x056b, 0x0000]), (0xfb16, [0x054e, 0x0576, 0x0000]), + (0xfb17, [0x0544, 0x056d, 0x0000]), + ], + }, + L2Lut { + singles: &[ // 0 entries, 0 bytes + ], + multis: &[ // 0 entries, 0 bytes + ], + }, + ], + }; } diff --git a/core/src/wtf8.rs b/core/src/wtf8.rs index 7214918db6c39..a0978c3dafb48 100644 --- a/core/src/wtf8.rs +++ b/core/src/wtf8.rs @@ -484,11 +484,22 @@ unsafe fn slice_unchecked(s: &Wtf8, begin: usize, end: usize) -> &Wtf8 { } } -/// Copied from core::str::raw::slice_error_fail #[inline(never)] fn slice_error_fail(s: &Wtf8, begin: usize, end: usize) -> ! { - assert!(begin <= end); - panic!("index {begin} and/or {end} in `{s:?}` do not lie on character boundary"); + let len = s.len(); + if begin > len { + panic!("start byte index {begin} is out of bounds for string of length {len}"); + } + if end > len { + panic!("end byte index {end} is out of bounds for string of length {len}"); + } + if begin > end { + panic!("byte range starts at {begin} but ends at {end}"); + } + if !s.is_code_point_boundary(begin) { + panic!("byte index {begin} is not a code point boundary"); + } + panic!("byte index {end} is not a code point boundary"); } /// Iterator for the code points of a WTF-8 string. diff --git a/coretests/benches/lib.rs b/coretests/benches/lib.rs index 150b9b33f4578..e8dc815a7dd0f 100644 --- a/coretests/benches/lib.rs +++ b/coretests/benches/lib.rs @@ -1,6 +1,6 @@ // wasm32 does not support benches (no time). #![cfg(not(target_arch = "wasm32"))] -// Disabling in Miri as these would take too long. +// This is marked as `test = true` and hence picked up by `./x miri`, but that would be too slow. #![cfg(not(miri))] #![feature(flt2dec)] #![feature(test)] @@ -8,7 +8,9 @@ #![feature(iter_array_chunks)] #![feature(iter_next_chunk)] #![feature(iter_advance_by)] +#![feature(num_internals)] #![feature(uint_gather_scatter_bits)] +#![allow(internal_features)] extern crate test; diff --git a/coretests/benches/num/flt2dec/mod.rs b/coretests/benches/num/flt2dec/mod.rs index 428d0bbbbfbfa..0cd94ec5e1cfe 100644 --- a/coretests/benches/num/flt2dec/mod.rs +++ b/coretests/benches/num/flt2dec/mod.rs @@ -3,7 +3,7 @@ mod strategy { mod grisu; } -use core::num::flt2dec::{DecodableFloat, Decoded, FullDecoded, MAX_SIG_DIGITS, decode}; +use core::num::imp::flt2dec::{DecodableFloat, Decoded, FullDecoded, MAX_SIG_DIGITS, decode}; use std::io::Write; use test::{Bencher, black_box}; diff --git a/coretests/benches/num/flt2dec/strategy/dragon.rs b/coretests/benches/num/flt2dec/strategy/dragon.rs index 4526697140365..d98b3df9b2f35 100644 --- a/coretests/benches/num/flt2dec/strategy/dragon.rs +++ b/coretests/benches/num/flt2dec/strategy/dragon.rs @@ -1,4 +1,4 @@ -use core::num::flt2dec::strategy::dragon::*; +use core::num::imp::flt2dec::strategy::dragon::*; use std::mem::MaybeUninit; use super::super::*; diff --git a/coretests/benches/num/flt2dec/strategy/grisu.rs b/coretests/benches/num/flt2dec/strategy/grisu.rs index d20f9b02f7e74..5f73fdebf5e77 100644 --- a/coretests/benches/num/flt2dec/strategy/grisu.rs +++ b/coretests/benches/num/flt2dec/strategy/grisu.rs @@ -1,4 +1,4 @@ -use core::num::flt2dec::strategy::grisu::*; +use core::num::imp::flt2dec::strategy::grisu::*; use std::mem::MaybeUninit; use super::super::*; diff --git a/coretests/tests/array.rs b/coretests/tests/array.rs index 2b4429092e98b..43fed944e9280 100644 --- a/coretests/tests/array.rs +++ b/coretests/tests/array.rs @@ -646,7 +646,7 @@ fn array_mixed_equality_integers() { #[test] fn array_mixed_equality_nans() { - let array3: [f32; 3] = [1.0, std::f32::NAN, 3.0]; + let array3: [f32; 3] = [1.0, f32::NAN, 3.0]; let slice3: &[f32] = &{ array3 }; assert!(!(array3 == slice3)); @@ -741,3 +741,18 @@ fn const_array_ops() { struct Zst; assert_eq!([(); 10].try_map(|()| Some(Zst)), Some([const { Zst }; 10])); } + +#[test] +const fn extra_const_array_ops() { + let x: [u8; 4] = + { std::array::from_fn(const |i| i + 4).map(const |x| x * 2).map(const |x| x as _) }; + let y = 4; + struct Z(u16); + impl const Drop for Z { + fn drop(&mut self) {} + } + let w = Z(2); + let _x: [u8; 4] = { + std::array::from_fn(const |_| x[0] + y).map(const |x| x * (w.0 as u8)).map(const |x| x as _) + }; +} diff --git a/coretests/tests/bstr.rs b/coretests/tests/bstr.rs index cd4d69d6b337d..dffc7e3f03494 100644 --- a/coretests/tests/bstr.rs +++ b/coretests/tests/bstr.rs @@ -49,4 +49,19 @@ fn test_display() { assert_eq!(&format!("{b2:->3}!"), "�(��!"); assert_eq!(&format!("{b2:-^3}!"), "�(��!"); assert_eq!(&format!("{b2:-^2}!"), "�(��!"); + + assert_eq!(&format!("{b1:.1}!"), &format!("{:.1}!", "abc")); + assert_eq!(&format!("{b1:.2}!"), &format!("{:.2}!", "abc")); + assert_eq!(&format!("{b1:.3}!"), &format!("{:.3}!", "abc")); + assert_eq!(&format!("{b1:-<5.2}!"), &format!("{:-<5.2}!", "abc")); + assert_eq!(&format!("{b1:-^5.2}!"), &format!("{:-^5.2}!", "abc")); + assert_eq!(&format!("{b1:->5.2}!"), &format!("{:->5.2}!", "abc")); + + assert_eq!(&format!("{b2:.1}!"), "�!"); + assert_eq!(&format!("{b2:.2}!"), "�(!"); + assert_eq!(&format!("{b2:.3}!"), "�(�!"); + assert_eq!(&format!("{b2:.4}!"), "�(��!"); + assert_eq!(&format!("{b2:-<6.3}!"), "�(�---!"); + assert_eq!(&format!("{b2:-^6.3}!"), "-�(�--!"); + assert_eq!(&format!("{b2:->6.3}!"), "---�(�!"); } diff --git a/coretests/tests/char.rs b/coretests/tests/char.rs index f0f6a24429284..877017f682c97 100644 --- a/coretests/tests/char.rs +++ b/coretests/tests/char.rs @@ -1,5 +1,6 @@ +use std::char::{self, CharCase}; +use std::str; use std::str::FromStr; -use std::{char, str}; #[test] fn test_convert() { @@ -39,6 +40,30 @@ fn test_from_str() { assert!(char::from_str("abc").is_err()); } +#[test] +fn test_is_cased() { + assert!('a'.is_cased()); + assert!('ö'.is_cased()); + assert!('ß'.is_cased()); + assert!('Ü'.is_cased()); + assert!('P'.is_cased()); + assert!('ª'.is_cased()); + assert!(!'攂'.is_cased()); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn test_char_case() { + for c in '\0'..='\u{10FFFF}' { + match c.case() { + None => assert!(!c.is_cased()), + Some(CharCase::Lower) => assert!(c.is_lowercase()), + Some(CharCase::Upper) => assert!(c.is_uppercase()), + Some(CharCase::Title) => assert!(c.is_titlecase()), + } + } +} + #[test] fn test_is_lowercase() { assert!('a'.is_lowercase()); @@ -48,6 +73,17 @@ fn test_is_lowercase() { assert!(!'P'.is_lowercase()); } +#[test] +fn test_is_titlecase() { + assert!('Dž'.is_titlecase()); + assert!('ᾨ'.is_titlecase()); + assert!(!'h'.is_titlecase()); + assert!(!'ä'.is_titlecase()); + assert!(!'ß'.is_titlecase()); + assert!(!'Ö'.is_titlecase()); + assert!(!'T'.is_titlecase()); +} + #[test] fn test_is_uppercase() { assert!(!'h'.is_uppercase()); @@ -57,6 +93,27 @@ fn test_is_uppercase() { assert!('T'.is_uppercase()); } +#[test] +fn titlecase_fast_path() { + for c in '\0'..='\u{01C4}' { + assert!(!(c.is_cased() && !c.is_lowercase() && !c.is_uppercase())) + } +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn at_most_one_case() { + for c in '\0'..='\u{10FFFF}' { + assert_eq!( + !c.is_cased() as u8 + + c.is_lowercase() as u8 + + c.is_uppercase() as u8 + + c.is_titlecase() as u8, + 1 + ); + } +} + #[test] fn test_is_whitespace() { assert!(' '.is_whitespace()); diff --git a/coretests/tests/cmp.rs b/coretests/tests/cmp.rs index 55e35a4a7250e..0a14470060c3d 100644 --- a/coretests/tests/cmp.rs +++ b/coretests/tests/cmp.rs @@ -1,5 +1,5 @@ +use core::cmp; use core::cmp::Ordering::{self, *}; -use core::cmp::{self}; #[test] fn test_int_totalord() { diff --git a/coretests/tests/intrinsics.rs b/coretests/tests/intrinsics.rs index c6d841b8383a8..e562f49b0a2fc 100644 --- a/coretests/tests/intrinsics.rs +++ b/coretests/tests/intrinsics.rs @@ -1,6 +1,7 @@ use core::any::TypeId; -use core::intrinsics::{assume, vtable_for}; +use core::intrinsics::assume; use std::fmt::Debug; +use std::intrinsics::type_id_vtable; use std::option::Option; use std::ptr::DynMetadata; @@ -198,15 +199,17 @@ fn carrying_mul_add_fallback_i128() { } #[test] -fn test_vtable_for() { +fn test_type_id_vtable() { #[derive(Debug)] struct A {} struct B {} - const A_VTABLE: Option> = vtable_for::(); + const A_VTABLE: Option> = + type_id_vtable(TypeId::of::(), TypeId::of::()); assert!(A_VTABLE.is_some()); - const B_VTABLE: Option> = vtable_for::(); + const B_VTABLE: Option> = + type_id_vtable(TypeId::of::(), TypeId::of::()); assert!(B_VTABLE.is_none()); } diff --git a/coretests/tests/iter/adapters/array_chunks.rs b/coretests/tests/iter/adapters/array_chunks.rs index e6e279b14e626..480d3138bdb35 100644 --- a/coretests/tests/iter/adapters/array_chunks.rs +++ b/coretests/tests/iter/adapters/array_chunks.rs @@ -1,4 +1,4 @@ -use core::iter::{self}; +use core::iter; use super::*; diff --git a/coretests/tests/iter/adapters/intersperse.rs b/coretests/tests/iter/adapters/intersperse.rs index 72ae59b6b2f5f..bcb7709077cd7 100644 --- a/coretests/tests/iter/adapters/intersperse.rs +++ b/coretests/tests/iter/adapters/intersperse.rs @@ -152,3 +152,189 @@ fn test_try_fold_specialization_intersperse_err() { iter.try_for_each(|item| if item == "b" { None } else { Some(()) }); assert_eq!(iter.next(), None); } + +#[test] +fn test_non_fused_iterator_intersperse() { + #[derive(Debug)] + struct TestCounter { + counter: usize, + } + + /// Given a counter of 0, this produces: + /// `None` -> `Some(2)` -> `None` -> `Some(4)` -> `None` -> `Some(6)` + /// -> and then `None` endlessly + impl Iterator for TestCounter { + type Item = usize; + fn next(&mut self) -> Option { + if self.counter > 6 { + None + } else if self.counter % 2 == 0 { + self.counter += 1; + None + } else { + self.counter += 1; + Some(self.counter) + } + } + } + + let counter = 0; + // places a 1 between `Some(_)` items + let non_fused_iter = TestCounter { counter }; + let mut intersperse_iter = non_fused_iter.intersperse(1); + // Interspersed iter produces: + // `None` -> `Some(2)` -> `None` -> `Some(1)` -> Some(4)` -> `None` -> `Some(1)` -> + // `Some(6)` -> and then `None` endlessly + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(2)); + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(1)); + assert_eq!(intersperse_iter.next(), Some(4)); + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(1)); + assert_eq!(intersperse_iter.next(), Some(6)); + assert_eq!(intersperse_iter.next(), None); + + // Extra check to make sure it is `None` after processing all items + assert_eq!(intersperse_iter.next(), None); +} + +#[test] +fn test_non_fused_iterator_intersperse_2() { + #[derive(Debug)] + struct TestCounter { + counter: usize, + } + + // Given a counter of 0, this produces: + // `Some(1)` -> `Some(2)` -> `None` -> `Some(4)` -> `Some(5)` -> + // and then `None` endlessly + impl Iterator for TestCounter { + type Item = usize; + fn next(&mut self) -> Option { + if self.counter < 5 { + self.counter += 1; + if self.counter % 3 != 0 { + return Some(self.counter); + } else { + return None; + } + } + self.counter += 1; + None + } + } + + let counter = 0; + // places a 100 between `Some(_)` items + let non_fused_iter = TestCounter { counter }; + let mut intersperse_iter = non_fused_iter.intersperse(100); + // Interspersed iter produces: + // `Some(1)` -> `Some(100)` -> `Some(2)` -> `None` -> `Some(100)` + // -> `Some(4)` -> `Some(100)` -> `Some(5)` -> `None` endlessly + assert_eq!(intersperse_iter.next(), Some(1)); + assert_eq!(intersperse_iter.next(), Some(100)); + assert_eq!(intersperse_iter.next(), Some(2)); + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(100)); + assert_eq!(intersperse_iter.next(), Some(4)); + assert_eq!(intersperse_iter.next(), Some(100)); + assert_eq!(intersperse_iter.next(), Some(5)); + assert_eq!(intersperse_iter.next(), None); + + // Extra check to make sure it is `None` after processing 6 items + assert_eq!(intersperse_iter.next(), None); +} + +#[test] +fn test_non_fused_iterator_intersperse_with() { + #[derive(Debug)] + struct TestCounter { + counter: usize, + } + + // Given a counter of 0, this produces: + // `None` -> `Some(2)` -> `None` -> `Some(4)` -> `None` -> `Some(6)` + // -> and then `None` endlessly + impl Iterator for TestCounter { + type Item = usize; + fn next(&mut self) -> Option { + if self.counter > 6 { + None + } else if self.counter % 2 == 0 { + self.counter += 1; + None + } else { + self.counter += 1; + Some(self.counter) + } + } + } + + let counter = 0; + let non_fused_iter = TestCounter { counter }; + // places a 2 between `Some(_)` items + let mut intersperse_iter = non_fused_iter.intersperse_with(|| 1); + // Interspersed iter produces: + // `None` -> `Some(2)` -> `None` -> `Some(1)` -> Some(4)` -> `None` -> `Some(1)` -> + // `Some(6)` -> and then `None` endlessly + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(2)); + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(1)); + assert_eq!(intersperse_iter.next(), Some(4)); + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(1)); + assert_eq!(intersperse_iter.next(), Some(6)); + assert_eq!(intersperse_iter.next(), None); + + // Extra check to make sure it is `None` after processing 6 items + assert_eq!(intersperse_iter.next(), None); +} + +#[test] +fn test_non_fused_iterator_intersperse_with_2() { + #[derive(Debug)] + struct TestCounter { + counter: usize, + } + + // Given a counter of 0, this produces: + // `Some(1)` -> `Some(2)` -> `None` -> `Some(4)` -> `Some(5)` -> + // and then `None` endlessly + impl Iterator for TestCounter { + type Item = usize; + fn next(&mut self) -> Option { + if self.counter < 5 { + self.counter += 1; + if self.counter % 3 != 0 { + return Some(self.counter); + } else { + return None; + } + } + self.counter += 1; + None + } + } + + let counter = 0; + // places a 100 between `Some(_)` items + let non_fused_iter = TestCounter { counter }; + let mut intersperse_iter = non_fused_iter.intersperse_with(|| 100); + // Interspersed iter produces: + // `Some(1)` -> `Some(100)` -> `Some(2)` -> `None` -> `Some(100)` + // -> `Some(4)` -> `Some(100)` -> `Some(5)` -> `None` endlessly + assert_eq!(intersperse_iter.next(), Some(1)); + assert_eq!(intersperse_iter.next(), Some(100)); + assert_eq!(intersperse_iter.next(), Some(2)); + assert_eq!(intersperse_iter.next(), None); + assert_eq!(intersperse_iter.next(), Some(100)); + assert_eq!(intersperse_iter.next(), Some(4)); + assert_eq!(intersperse_iter.next(), Some(100)); + assert_eq!(intersperse_iter.next(), Some(5)); + assert_eq!(intersperse_iter.next(), None); + + // Extra check to make sure it is `None` after processing 6 items + assert_eq!(intersperse_iter.next(), None); +} diff --git a/coretests/tests/iter/adapters/map_windows.rs b/coretests/tests/iter/adapters/map_windows.rs index 01cebc9b27fd8..994ec087e5e8b 100644 --- a/coretests/tests/iter/adapters/map_windows.rs +++ b/coretests/tests/iter/adapters/map_windows.rs @@ -284,3 +284,29 @@ fn test_size_hint() { check_size_hint::<5>((5, Some(5)), (1, Some(1))); check_size_hint::<5>((5, Some(10)), (1, Some(6))); } + +#[test] +fn test_unfused() { + #[derive(Default)] + struct UnfusedIter(usize); + impl Iterator for UnfusedIter { + type Item = usize; + + fn next(&mut self) -> Option { + let curr = self.0; + self.0 += 1; + if curr % 7 == 0 { None } else { Some(curr) } + } + } + + let mut iter = UnfusedIter(1).map_windows(|a: &[_; 3]| *a); + assert_eq!(iter.by_ref().collect::>(), vec![[1, 2, 3], [2, 3, 4], [3, 4, 5], [4, 5, 6]]); + assert_eq!( + iter.by_ref().collect::>(), + vec![[8, 9, 10], [9, 10, 11], [10, 11, 12], [11, 12, 13]] + ); + assert_eq!( + iter.by_ref().collect::>(), + vec![[15, 16, 17], [16, 17, 18], [17, 18, 19], [18, 19, 20]] + ); +} diff --git a/coretests/tests/lib.rs b/coretests/tests/lib.rs index d085e4ad1a8fe..90a33aeead150 100644 --- a/coretests/tests/lib.rs +++ b/coretests/tests/lib.rs @@ -1,6 +1,5 @@ // tidy-alphabetical-start #![cfg_attr(target_has_atomic = "128", feature(integer_atomics))] -#![cfg_attr(test, feature(cfg_select))] #![feature(array_ptr_get)] #![feature(array_try_from_fn)] #![feature(array_try_map)] @@ -13,12 +12,12 @@ #![feature(cfg_target_has_reliable_f16_f128)] #![feature(char_internals)] #![feature(char_max_len)] -#![feature(clamp_magnitude)] #![feature(clone_to_uninit)] #![feature(const_array)] #![feature(const_bool)] #![feature(const_cell_traits)] #![feature(const_clone)] +#![feature(const_closures)] #![feature(const_cmp)] #![feature(const_convert)] #![feature(const_default)] @@ -34,8 +33,6 @@ #![feature(const_select_unpredictable)] #![feature(const_trait_impl)] #![feature(const_unsigned_bigint_helpers)] -#![feature(control_flow_ok)] -#![feature(core_float_math)] #![feature(core_intrinsics)] #![feature(core_intrinsics_fallbacks)] #![feature(core_io_borrowed_buf)] @@ -47,7 +44,6 @@ #![feature(drop_guard)] #![feature(duration_constants)] #![feature(duration_constructors)] -#![feature(error_generic_member_access)] #![feature(exact_div)] #![feature(exact_size_is_empty)] #![feature(extend_one)] @@ -55,6 +51,7 @@ #![feature(f16)] #![feature(f128)] #![feature(float_algebraic)] +#![feature(float_exact_integer_constants)] #![feature(float_gamma)] #![feature(float_minimum_maximum)] #![feature(flt2dec)] @@ -66,6 +63,7 @@ #![feature(generic_assert_internals)] #![feature(hasher_prefixfree_extras)] #![feature(hashmap_internals)] +#![feature(int_from_ascii)] #![feature(int_lowest_highest_one)] #![feature(int_roundings)] #![feature(ip)] @@ -87,17 +85,19 @@ #![feature(maybe_uninit_uninit_array_transpose)] #![feature(min_specialization)] #![feature(never_type)] -#![feature(new_range_api)] #![feature(next_index)] #![feature(non_exhaustive_omitted_patterns_lint)] +#![feature(nonzero_from_str_radix)] +#![feature(num_internals)] #![feature(numfmt)] #![feature(one_sided_range)] -#![feature(option_reduce)] +#![feature(panic_internals)] #![feature(pattern)] #![feature(pointer_is_aligned_to)] #![feature(portable_simd)] #![feature(ptr_metadata)] #![feature(result_option_map_or_default)] +#![feature(rustc_attrs)] #![feature(signed_bigint_helpers)] #![feature(slice_from_ptr_range)] #![feature(slice_index_methods)] @@ -112,7 +112,7 @@ #![feature(step_trait)] #![feature(str_internals)] #![feature(strict_provenance_lints)] -#![feature(test)] +#![feature(titlecase)] #![feature(trusted_len)] #![feature(trusted_random_access)] #![feature(try_blocks)] @@ -120,7 +120,9 @@ #![feature(try_trait_v2)] #![feature(type_info)] #![feature(uint_bit_width)] +#![feature(uint_carryless_mul)] #![feature(uint_gather_scatter_bits)] +#![feature(unicode_internals)] #![feature(unsize)] #![feature(unwrap_infallible)] #![feature(widening_mul)] @@ -181,7 +183,6 @@ mod cmp; mod const_ptr; mod convert; mod ffi; -mod floats; mod fmt; mod future; mod hash; diff --git a/coretests/tests/mem.rs b/coretests/tests/mem.rs index 193d5416b06a7..b95e6e13063f5 100644 --- a/coretests/tests/mem.rs +++ b/coretests/tests/mem.rs @@ -1,3 +1,5 @@ +mod fn_ptr; +mod trait_info_of; mod type_info; use core::mem::*; diff --git a/coretests/tests/mem/fn_ptr.rs b/coretests/tests/mem/fn_ptr.rs new file mode 100644 index 0000000000000..1d50a2552a193 --- /dev/null +++ b/coretests/tests/mem/fn_ptr.rs @@ -0,0 +1,169 @@ +use std::any::TypeId; +use std::mem::type_info::{Abi, FnPtr, Type, TypeKind}; + +const STRING_TY: TypeId = const { TypeId::of::() }; +const U8_TY: TypeId = const { TypeId::of::() }; +const _U8_REF_TY: TypeId = const { TypeId::of::<&u8>() }; +const UNIT_TY: TypeId = const { TypeId::of::<()>() }; + +#[test] +fn test_fn_ptrs() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); +} +#[test] +fn test_ref() { + const { + // references are tricky because the lifetimes give the references different type ids + // so we check the pointees instead + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[ty1, ty2], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + if output != UNIT_TY { + panic!(); + } + let TypeKind::Reference(reference) = ty1.info().kind else { + panic!(); + }; + if reference.pointee != U8_TY { + panic!(); + } + let TypeKind::Reference(reference) = ty2.info().kind else { + panic!(); + }; + if reference.pointee != U8_TY { + panic!(); + } + } +} + +#[test] +fn test_unsafe() { + let TypeKind::FnPtr(FnPtr { + unsafety: true, + abi: Abi::ExternRust, + inputs: &[], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); +} +#[test] +fn test_abi() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); + + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternC, + inputs: &[], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); + + let TypeKind::FnPtr(FnPtr { + unsafety: true, + abi: Abi::Named("system"), + inputs: &[], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); +} + +#[test] +fn test_inputs() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[ty1, ty2], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); + assert_eq!(ty1, STRING_TY); + assert_eq!(ty2, U8_TY); + + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[ty1, ty2], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); + assert_eq!(ty1, STRING_TY); + assert_eq!(ty2, U8_TY); +} + +#[test] +fn test_output() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[], + output, + variadic: false, + }) = (const { Type::of:: u8>().kind }) + else { + panic!(); + }; + assert_eq!(output, U8_TY); +} + +#[test] +fn test_variadic() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternC, + inputs: [ty1], + output, + variadic: true, + }) = &(const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, &UNIT_TY); + assert_eq!(*ty1, U8_TY); +} diff --git a/coretests/tests/mem/trait_info_of.rs b/coretests/tests/mem/trait_info_of.rs new file mode 100644 index 0000000000000..c723a96095815 --- /dev/null +++ b/coretests/tests/mem/trait_info_of.rs @@ -0,0 +1,70 @@ +use std::any::TypeId; +use std::ptr::DynMetadata; + +struct Garlic(i32); +trait Blah { + fn get_truth(&self) -> i32; +} +impl Blah for Garlic { + fn get_truth(&self) -> i32 { + self.0 * 21 + } +} + +#[test] +fn test_implements_trait() { + const { + assert!(TypeId::of::().trait_info_of::().is_some()); + assert!(TypeId::of::().trait_info_of::().is_some()); + assert!(TypeId::of::<*const Box>().trait_info_of::().is_none()); + assert!(TypeId::of::().trait_info_of_trait_type_id(TypeId::of::()).is_none()); + } +} + +#[test] +fn test_dyn_creation() { + let garlic = Garlic(2); + unsafe { + assert_eq!( + std::ptr::from_raw_parts::( + &raw const garlic, + const { TypeId::of::().trait_info_of::() }.unwrap().get_vtable() + ) + .as_ref() + .unwrap() + .get_truth(), + 42 + ); + } + + assert_eq!( + const { + TypeId::of::() + .trait_info_of_trait_type_id(TypeId::of::()) + .unwrap() + }.get_vtable(), + unsafe { + crate::mem::transmute::<_, DynMetadata<*const ()>>( + const { + TypeId::of::().trait_info_of::() + }.unwrap().get_vtable(), + ) + } + ); +} + +#[test] +fn test_incorrect_use() { + assert_eq!( + const { TypeId::of::().trait_info_of_trait_type_id(TypeId::of::()) }, + None + ); +} + +trait DstTrait {} +impl DstTrait for [i32] {} + +#[test] +fn dst_ice() { + assert!(const { TypeId::of::<[i32]>().trait_info_of::() }.is_none()); +} diff --git a/coretests/tests/mem/type_info.rs b/coretests/tests/mem/type_info.rs index 87f2d5dd8289c..2483b4c2aacd7 100644 --- a/coretests/tests/mem/type_info.rs +++ b/coretests/tests/mem/type_info.rs @@ -1,5 +1,8 @@ +#![allow(dead_code)] + use std::any::{Any, TypeId}; -use std::mem::type_info::{Type, TypeKind}; +use std::mem::offset_of; +use std::mem::type_info::{Const, Generic, GenericType, Type, TypeKind}; #[test] fn test_arrays() { @@ -66,6 +69,155 @@ fn test_tuples() { } } +#[test] +fn test_structs() { + use TypeKind::*; + + const { + struct TestStruct { + first: u8, + second: u16, + reference: &'static u16, + } + + let Type { kind: Struct(ty), size, .. } = Type::of::() else { panic!() }; + assert!(size == Some(size_of::())); + assert!(!ty.non_exhaustive); + assert!(ty.fields.len() == 3); + assert!(ty.fields[0].name == "first"); + assert!(ty.fields[0].ty == TypeId::of::()); + assert!(ty.fields[0].offset == offset_of!(TestStruct, first)); + assert!(ty.fields[1].name == "second"); + assert!(ty.fields[1].ty == TypeId::of::()); + assert!(ty.fields[1].offset == offset_of!(TestStruct, second)); + assert!(ty.fields[2].name == "reference"); + assert!(ty.fields[2].ty == TypeId::of::<&'static u16>()); + assert!(ty.fields[2].offset == offset_of!(TestStruct, reference)); + } + + const { + #[non_exhaustive] + struct NonExhaustive { + a: u8, + } + + let Type { kind: Struct(ty), .. } = Type::of::() else { panic!() }; + assert!(ty.non_exhaustive); + } + + const { + struct TupleStruct(u8, u16); + + let Type { kind: Struct(ty), .. } = Type::of::() else { panic!() }; + assert!(ty.fields.len() == 2); + assert!(ty.fields[0].name == "0"); + assert!(ty.fields[0].ty == TypeId::of::()); + assert!(ty.fields[1].name == "1"); + assert!(ty.fields[1].ty == TypeId::of::()); + } + + const { + struct Generics<'a, T, const C: u64> { + a: &'a T, + } + + let Type { kind: Struct(ty), .. } = Type::of::>() else { + panic!() + }; + assert!(ty.fields.len() == 1); + assert!(ty.generics.len() == 3); + + let Generic::Lifetime(_) = ty.generics[0] else { panic!() }; + let Generic::Type(GenericType { ty: generic_ty, .. }) = ty.generics[1] else { panic!() }; + assert!(generic_ty == TypeId::of::()); + let Generic::Const(Const { ty: const_ty, .. }) = ty.generics[2] else { panic!() }; + assert!(const_ty == TypeId::of::()); + } +} + +#[test] +fn test_unions() { + use TypeKind::*; + + const { + union TestUnion { + first: i16, + second: u16, + } + + let Type { kind: Union(ty), size, .. } = Type::of::() else { panic!() }; + assert!(size == Some(size_of::())); + assert!(ty.fields.len() == 2); + assert!(ty.fields[0].name == "first"); + assert!(ty.fields[0].offset == offset_of!(TestUnion, first)); + assert!(ty.fields[1].name == "second"); + assert!(ty.fields[1].offset == offset_of!(TestUnion, second)); + } + + const { + union Generics<'a, T: Copy, const C: u64> { + a: T, + z: &'a (), + } + + let Type { kind: Union(ty), .. } = Type::of::>() else { + panic!() + }; + assert!(ty.fields.len() == 2); + assert!(ty.fields[0].offset == offset_of!(Generics<'static, i32, 1_u64>, a)); + assert!(ty.fields[1].offset == offset_of!(Generics<'static, i32, 1_u64>, z)); + + assert!(ty.generics.len() == 3); + let Generic::Lifetime(_) = ty.generics[0] else { panic!() }; + let Generic::Type(GenericType { ty: generic_ty, .. }) = ty.generics[1] else { panic!() }; + assert!(generic_ty == TypeId::of::()); + let Generic::Const(Const { ty: const_ty, .. }) = ty.generics[2] else { panic!() }; + assert!(const_ty == TypeId::of::()); + } +} + +#[test] +fn test_enums() { + use TypeKind::*; + + const { + enum E { + Some(u32), + None, + #[non_exhaustive] + Foomp { + a: (), + b: &'static str, + }, + } + + let Type { kind: Enum(ty), size, .. } = Type::of::() else { panic!() }; + assert!(size == Some(size_of::())); + assert!(ty.variants.len() == 3); + + assert!(ty.variants[0].name == "Some"); + assert!(!ty.variants[0].non_exhaustive); + assert!(ty.variants[0].fields.len() == 1); + + assert!(ty.variants[1].name == "None"); + assert!(!ty.variants[1].non_exhaustive); + assert!(ty.variants[1].fields.len() == 0); + + assert!(ty.variants[2].name == "Foomp"); + assert!(ty.variants[2].non_exhaustive); + assert!(ty.variants[2].fields.len() == 2); + } + + const { + let Type { kind: Enum(ty), size, .. } = Type::of::>() else { panic!() }; + assert!(size == Some(size_of::>())); + assert!(ty.variants.len() == 2); + assert!(ty.generics.len() == 1); + let Generic::Type(GenericType { ty: generic_ty, .. }) = ty.generics[0] else { panic!() }; + assert!(generic_ty == TypeId::of::()); + } +} + #[test] fn test_primitives() { use TypeKind::*; diff --git a/coretests/tests/nonzero.rs b/coretests/tests/nonzero.rs index c368a2621740b..861e9e05081fc 100644 --- a/coretests/tests/nonzero.rs +++ b/coretests/tests/nonzero.rs @@ -124,6 +124,97 @@ fn test_from_signed_nonzero() { assert_eq!(num, 1i32); } +#[test] +fn test_from_ascii_radix() { + assert_eq!(NonZero::::from_ascii_radix(b"123", 10), Ok(NonZero::new(123).unwrap())); + assert_eq!(NonZero::::from_ascii_radix(b"1001", 2), Ok(NonZero::new(9).unwrap())); + assert_eq!(NonZero::::from_ascii_radix(b"123", 8), Ok(NonZero::new(83).unwrap())); + assert_eq!(NonZero::::from_ascii_radix(b"123", 16), Ok(NonZero::new(291).unwrap())); + assert_eq!(NonZero::::from_ascii_radix(b"ffff", 16), Ok(NonZero::new(65535).unwrap())); + assert_eq!(NonZero::::from_ascii_radix(b"z", 36), Ok(NonZero::new(35).unwrap())); + assert_eq!( + NonZero::::from_ascii_radix(b"0", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::Zero) + ); + assert_eq!( + NonZero::::from_ascii_radix(b"-1", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_ascii_radix(b"-129", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::NegOverflow) + ); + assert_eq!( + NonZero::::from_ascii_radix(b"257", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::PosOverflow) + ); + + assert_eq!( + NonZero::::from_ascii_radix(b"Z", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_ascii_radix(b"_", 2).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); +} + +#[test] +fn test_from_ascii() { + assert_eq!(NonZero::::from_ascii(b"123"), Ok(NonZero::new(123).unwrap())); + assert_eq!( + NonZero::::from_ascii(b"0").err().map(|e| e.kind().clone()), + Some(IntErrorKind::Zero) + ); + assert_eq!( + NonZero::::from_ascii(b"-1").err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_ascii(b"-129").err().map(|e| e.kind().clone()), + Some(IntErrorKind::NegOverflow) + ); + assert_eq!( + NonZero::::from_ascii(b"257").err().map(|e| e.kind().clone()), + Some(IntErrorKind::PosOverflow) + ); +} + +#[test] +fn test_from_str_radix() { + assert_eq!(NonZero::::from_str_radix("123", 10), Ok(NonZero::new(123).unwrap())); + assert_eq!(NonZero::::from_str_radix("1001", 2), Ok(NonZero::new(9).unwrap())); + assert_eq!(NonZero::::from_str_radix("123", 8), Ok(NonZero::new(83).unwrap())); + assert_eq!(NonZero::::from_str_radix("123", 16), Ok(NonZero::new(291).unwrap())); + assert_eq!(NonZero::::from_str_radix("ffff", 16), Ok(NonZero::new(65535).unwrap())); + assert_eq!(NonZero::::from_str_radix("z", 36), Ok(NonZero::new(35).unwrap())); + assert_eq!( + NonZero::::from_str_radix("0", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::Zero) + ); + assert_eq!( + NonZero::::from_str_radix("-1", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_str_radix("-129", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::NegOverflow) + ); + assert_eq!( + NonZero::::from_str_radix("257", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::PosOverflow) + ); + + assert_eq!( + NonZero::::from_str_radix("Z", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_str_radix("_", 2).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); +} + #[test] fn test_from_str() { assert_eq!("123".parse::>(), Ok(NonZero::new(123).unwrap())); diff --git a/coretests/tests/num/bignum.rs b/coretests/tests/num/bignum.rs index 6dfa496e018bf..2b4c30cc261cb 100644 --- a/coretests/tests/num/bignum.rs +++ b/coretests/tests/num/bignum.rs @@ -1,5 +1,5 @@ -use core::num::bignum::Big32x40; -use core::num::bignum::tests::Big8x3 as Big; +use core::num::imp::bignum::Big32x40; +use core::num::imp::bignum::tests::Big8x3 as Big; #[test] #[should_panic] diff --git a/coretests/tests/num/carryless_mul.rs b/coretests/tests/num/carryless_mul.rs new file mode 100644 index 0000000000000..5d4690beaedea --- /dev/null +++ b/coretests/tests/num/carryless_mul.rs @@ -0,0 +1,254 @@ +//! Tests the `Unsigned::{carryless_mul, widening_carryless_mul, carrying_carryless_mul}` methods. + +#[test] +fn carryless_mul_u128() { + assert_eq_const_safe!(u128: ::carryless_mul(0, 0), 0); + assert_eq_const_safe!(u128: ::carryless_mul(1, 1), 1); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0x0123456789ABCDEF_FEDCBA9876543210, + 1u128 << 64, + ), + 0xFEDCBA9876543210_0000000000000000 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0x0123456789ABCDEF_FEDCBA9876543210, + (1u128 << 64) | 1, + ), + 0xFFFFFFFFFFFFFFFF_FEDCBA9876543210 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0x0123456789ABCDEF_FEDCBA9876543211, + 1u128 << 127, + ), + 0x8000000000000000_0000000000000000 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0xAAAAAAAAAAAAAAAA_AAAAAAAAAAAAAAAA, + 0x5555555555555555_5555555555555555, + ), + 0x2222222222222222_2222222222222222 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + (1 << 127) | (1 << 64) | 1, + (1 << 63) | 1 + ), + (1 << 64) | (1 << 63) | 1 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0x8000000000000000_0000000000000001, + 0x7FFFFFFFFFFFFFFF_FFFFFFFFFFFFFFFF, + ), + 0xFFFFFFFFFFFFFFFF_FFFFFFFFFFFFFFFF + ); +} + +#[test] +fn carryless_mul_u64() { + assert_eq_const_safe!(u64: ::carryless_mul(0, 0), 0); + assert_eq_const_safe!(u64: ::carryless_mul(1, 1), 1); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0x0123_4567_89AB_CDEF, + 1u64 << 32, + ), + 0x89AB_CDEF_0000_0000 + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0x0123_4567_89AB_CDEF, + (1u64 << 32) | 1, + ), + 0x8888_8888_89AB_CDEF + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0x0123_4567_89AB_CDEF, + 1u64 << 63, + ), + 0x8000_0000_0000_0000 + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0xAAAA_AAAA_AAAA_AAAA, + 0x5555_5555_5555_5555, + ), + 0x2222_2222_2222_2222 + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + (1u64 << 63) | (1u64 << 32) | 1, + (1u64 << 31) | 1, + ), + (1u64 << 32) | (1u64 << 31) | 1 + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0x8000_0000_0000_0001, + 0x7FFF_FFFF_FFFF_FFFF, + ), + 0xFFFF_FFFF_FFFF_FFFF + ); +} + +#[test] +fn carryless_mul_u32() { + assert_eq_const_safe!( + u32: ::carryless_mul(0x0123_4567, 1u32 << 16), + 0x4567_0000 + ); + + assert_eq_const_safe!( + u32: ::carryless_mul(0xAAAA_AAAA, 0x5555_5555), + 0x2222_2222 + ); +} + +#[test] +fn carryless_mul_u16() { + assert_eq_const_safe!( + u16: ::carryless_mul(0x0123, 1u16 << 8), + 0x2300 + ); + + assert_eq_const_safe!( + u16: ::carryless_mul(0xAAAA, 0x5555), + 0x2222 + ); +} + +#[test] +fn carryless_mul_u8() { + assert_eq_const_safe!( + u8: ::carryless_mul(0x01, 1u8 << 4), + 0x10 + ); + + assert_eq_const_safe!( + u8: ::carryless_mul(0xAA, 0x55), + 0x22 + ); +} + +#[test] +fn widening_carryless_mul() { + assert_eq_const_safe!( + u16: ::widening_carryless_mul(0xEFu8, 1u8 << 7), + 0x7780u16 + ); + assert_eq_const_safe!( + u16: ::widening_carryless_mul(0xEFu8, (1u8 << 7) | 1), + 0x776Fu16 + ); + + assert_eq_const_safe!( + u32: ::widening_carryless_mul(0xBEEFu16, 1u16 << 15), + 0x5F77_8000u32 + ); + assert_eq_const_safe!( + u32: ::widening_carryless_mul(0xBEEFu16, (1u16 << 15) | 1), + 0x5F77_3EEFu32 + ); + + assert_eq_const_safe!( + u64: ::widening_carryless_mul(0xDEAD_BEEFu32, 1u32 << 31), + 0x6F56_DF77_8000_0000u64 + ); + assert_eq_const_safe!( + u64: ::widening_carryless_mul(0xDEAD_BEEFu32, (1u32 << 31) | 1), + 0x6F56_DF77_5EAD_BEEFu64 + ); + + assert_eq_const_safe!( + u128: ::widening_carryless_mul(0xDEAD_BEEF_FACE_FEEDu64, 1u64 << 63), + 147995377545877439359040026616086396928 + + ); + assert_eq_const_safe!( + u128: ::widening_carryless_mul(0xDEAD_BEEF_FACE_FEEDu64, (1u64 << 63) | 1), + 147995377545877439356638973527682121453 + ); +} + +#[test] +fn carrying_carryless_mul() { + assert_eq_const_safe!( + (u8, u8): ::carrying_carryless_mul(0xEFu8, 1u8 << 7, 0), + (0x80u8, 0x77u8) + ); + assert_eq_const_safe!( + (u8, u8): ::carrying_carryless_mul(0xEFu8, (1u8 << 7) | 1, 0xEF), + (0x80u8, 0x77u8) + ); + + assert_eq_const_safe!( + (u16, u16): ::carrying_carryless_mul(0xBEEFu16, 1u16 << 15, 0), + (0x8000u16, 0x5F77u16) + ); + assert_eq_const_safe!( + (u16, u16): ::carrying_carryless_mul(0xBEEFu16, (1u16 << 15) | 1, 0xBEEF), + (0x8000u16, 0x5F77u16) + ); + + assert_eq_const_safe!( + (u32, u32): ::carrying_carryless_mul(0xDEAD_BEEFu32, 1u32 << 31, 0), + (0x8000_0000u32, 0x6F56_DF77u32) + ); + assert_eq_const_safe!( + (u32, u32): ::carrying_carryless_mul(0xDEAD_BEEFu32, (1u32 << 31) | 1, 0xDEAD_BEEF), + (0x8000_0000u32, 0x6F56_DF77u32) + ); + + assert_eq_const_safe!( + (u64, u64): ::carrying_carryless_mul(0xDEAD_BEEF_FACE_FEEDu64, 1u64 << 63, 0), + (9223372036854775808, 8022845492652638070) + ); + assert_eq_const_safe!( + (u64, u64): ::carrying_carryless_mul( + 0xDEAD_BEEF_FACE_FEEDu64, + (1u64 << 63) | 1, + 0xDEAD_BEEF_FACE_FEED, + ), + (9223372036854775808, 8022845492652638070) + ); + + assert_eq_const_safe!( + (u128, u128): ::carrying_carryless_mul( + 0xDEAD_BEEF_FACE_FEED_0123_4567_89AB_CDEFu128, + 1u128 << 127, + 0, + ), + ( + 0x8000_0000_0000_0000_0000_0000_0000_0000u128, + 147995377545877439359081019380694640375, + ) + ); + assert_eq_const_safe!( + (u128, u128): ::carrying_carryless_mul( + 0xDEAD_BEEF_FACE_FEED_0123_4567_89AB_CDEFu128, + (1u128 << 127) | 1, + 0xDEAD_BEEF_FACE_FEED_0123_4567_89AB_CDEF, + ), + ( + 0x8000_0000_0000_0000_0000_0000_0000_0000u128, + 147995377545877439359081019380694640375, + ) + ); +} diff --git a/coretests/tests/num/dec2flt/decimal.rs b/coretests/tests/num/dec2flt/decimal.rs index f5ecc604a99a1..8611310850be7 100644 --- a/coretests/tests/num/dec2flt/decimal.rs +++ b/coretests/tests/num/dec2flt/decimal.rs @@ -1,4 +1,4 @@ -use core::num::dec2flt::decimal::Decimal; +use core::num::imp::dec2flt::decimal::Decimal; type FPath = ((i64, u64, bool, bool), Option); diff --git a/coretests/tests/num/dec2flt/decimal_seq.rs b/coretests/tests/num/dec2flt/decimal_seq.rs index f46ba7c465a6e..f2fee3a0d8e85 100644 --- a/coretests/tests/num/dec2flt/decimal_seq.rs +++ b/coretests/tests/num/dec2flt/decimal_seq.rs @@ -1,4 +1,4 @@ -use core::num::dec2flt::decimal_seq::{DecimalSeq, parse_decimal_seq}; +use core::num::imp::dec2flt::decimal_seq::{DecimalSeq, parse_decimal_seq}; #[test] fn test_trim() { diff --git a/coretests/tests/num/dec2flt/float.rs b/coretests/tests/num/dec2flt/float.rs index 734cb7e4f7dbd..0713c5c651fb3 100644 --- a/coretests/tests/num/dec2flt/float.rs +++ b/coretests/tests/num/dec2flt/float.rs @@ -1,4 +1,5 @@ -use core::num::dec2flt::float::RawFloat; +use core::num::imp::dec2flt::Lemire; +use core::num::imp::{Float, FloatExt}; use crate::num::{ldexp_f32, ldexp_f64}; @@ -56,57 +57,60 @@ fn test_f64_integer_decode() { #[test] #[cfg(target_has_reliable_f16)] fn test_f16_consts() { - assert_eq!(::INFINITY, f16::INFINITY); - assert_eq!(::NEG_INFINITY, -f16::INFINITY); - assert_eq!(::NAN.to_bits(), f16::NAN.to_bits()); - assert_eq!(::NEG_NAN.to_bits(), (-f16::NAN).to_bits()); - assert_eq!(::SIG_BITS, 10); - assert_eq!(::MIN_EXPONENT_ROUND_TO_EVEN, -22); - assert_eq!(::MAX_EXPONENT_ROUND_TO_EVEN, 5); - assert_eq!(::MIN_EXPONENT_FAST_PATH, -4); - assert_eq!(::MAX_EXPONENT_FAST_PATH, 4); - assert_eq!(::MAX_EXPONENT_DISGUISED_FAST_PATH, 7); - assert_eq!(::EXP_MIN, -14); - assert_eq!(::EXP_SAT, 0x1f); - assert_eq!(::SMALLEST_POWER_OF_TEN, -27); - assert_eq!(::LARGEST_POWER_OF_TEN, 4); - assert_eq!(::MAX_MANTISSA_FAST_PATH, 2048); + assert_eq!(::INFINITY, f16::INFINITY); + assert_eq!(::NEG_INFINITY, -f16::INFINITY); + assert_eq!(::NAN.to_bits(), f16::NAN.to_bits()); + assert_eq!(::NEG_NAN.to_bits(), (-f16::NAN).to_bits()); + assert_eq!(::SIG_BITS, 10); + assert_eq!(::MIN_EXPONENT_ROUND_TO_EVEN, -22); + assert_eq!(::MAX_EXPONENT_ROUND_TO_EVEN, 5); + assert_eq!(::EXP_MIN, -14); + assert_eq!(::EXP_SAT, 0x1f); + assert_eq!(::SMALLEST_POWER_OF_TEN, -27); + assert_eq!(::LARGEST_POWER_OF_TEN, 4); + + assert_eq!(::MIN_EXPONENT_FAST_PATH, -4); + assert_eq!(::MAX_EXPONENT_FAST_PATH, 4); + assert_eq!(::MAX_EXPONENT_DISGUISED_FAST_PATH, 7); + assert_eq!(::MAX_MANTISSA_FAST_PATH, 2048); } #[test] fn test_f32_consts() { - assert_eq!(::INFINITY, f32::INFINITY); - assert_eq!(::NEG_INFINITY, -f32::INFINITY); - assert_eq!(::NAN.to_bits(), f32::NAN.to_bits()); - assert_eq!(::NEG_NAN.to_bits(), (-f32::NAN).to_bits()); - assert_eq!(::SIG_BITS, 23); - assert_eq!(::MIN_EXPONENT_ROUND_TO_EVEN, -17); - assert_eq!(::MAX_EXPONENT_ROUND_TO_EVEN, 10); - assert_eq!(::MIN_EXPONENT_FAST_PATH, -10); - assert_eq!(::MAX_EXPONENT_FAST_PATH, 10); - assert_eq!(::MAX_EXPONENT_DISGUISED_FAST_PATH, 17); - assert_eq!(::EXP_MIN, -126); - assert_eq!(::EXP_SAT, 0xff); - assert_eq!(::SMALLEST_POWER_OF_TEN, -65); - assert_eq!(::LARGEST_POWER_OF_TEN, 38); - assert_eq!(::MAX_MANTISSA_FAST_PATH, 16777216); + assert_eq!(::INFINITY, f32::INFINITY); + assert_eq!(::NEG_INFINITY, -f32::INFINITY); + assert_eq!(::NAN.to_bits(), f32::NAN.to_bits()); + assert_eq!(::NEG_NAN.to_bits(), (-f32::NAN).to_bits()); + assert_eq!(::SIG_BITS, 23); + assert_eq!(::MIN_EXPONENT_ROUND_TO_EVEN, -17); + assert_eq!(::MAX_EXPONENT_ROUND_TO_EVEN, 10); + assert_eq!(::EXP_MIN, -126); + assert_eq!(::EXP_SAT, 0xff); + assert_eq!(::SMALLEST_POWER_OF_TEN, -65); + assert_eq!(::LARGEST_POWER_OF_TEN, 38); + + assert_eq!(::MIN_EXPONENT_FAST_PATH, -10); + assert_eq!(::MAX_EXPONENT_FAST_PATH, 10); + assert_eq!(::MAX_EXPONENT_DISGUISED_FAST_PATH, 17); + assert_eq!(::MAX_MANTISSA_FAST_PATH, 16777216); } #[test] fn test_f64_consts() { - assert_eq!(::INFINITY, f64::INFINITY); - assert_eq!(::NEG_INFINITY, -f64::INFINITY); - assert_eq!(::NAN.to_bits(), f64::NAN.to_bits()); - assert_eq!(::NEG_NAN.to_bits(), (-f64::NAN).to_bits()); - assert_eq!(::SIG_BITS, 52); - assert_eq!(::MIN_EXPONENT_ROUND_TO_EVEN, -4); - assert_eq!(::MAX_EXPONENT_ROUND_TO_EVEN, 23); - assert_eq!(::MIN_EXPONENT_FAST_PATH, -22); - assert_eq!(::MAX_EXPONENT_FAST_PATH, 22); - assert_eq!(::MAX_EXPONENT_DISGUISED_FAST_PATH, 37); - assert_eq!(::EXP_MIN, -1022); - assert_eq!(::EXP_SAT, 0x7ff); - assert_eq!(::SMALLEST_POWER_OF_TEN, -342); - assert_eq!(::LARGEST_POWER_OF_TEN, 308); - assert_eq!(::MAX_MANTISSA_FAST_PATH, 9007199254740992); + assert_eq!(::INFINITY, f64::INFINITY); + assert_eq!(::NEG_INFINITY, -f64::INFINITY); + assert_eq!(::NAN.to_bits(), f64::NAN.to_bits()); + assert_eq!(::NEG_NAN.to_bits(), (-f64::NAN).to_bits()); + assert_eq!(::SIG_BITS, 52); + assert_eq!(::MIN_EXPONENT_ROUND_TO_EVEN, -4); + assert_eq!(::MAX_EXPONENT_ROUND_TO_EVEN, 23); + assert_eq!(::EXP_MIN, -1022); + assert_eq!(::EXP_SAT, 0x7ff); + assert_eq!(::SMALLEST_POWER_OF_TEN, -342); + assert_eq!(::LARGEST_POWER_OF_TEN, 308); + + assert_eq!(::MIN_EXPONENT_FAST_PATH, -22); + assert_eq!(::MAX_EXPONENT_FAST_PATH, 22); + assert_eq!(::MAX_EXPONENT_DISGUISED_FAST_PATH, 37); + assert_eq!(::MAX_MANTISSA_FAST_PATH, 9007199254740992); } diff --git a/coretests/tests/num/dec2flt/lemire.rs b/coretests/tests/num/dec2flt/lemire.rs index ba359a0495fef..e5a7ae346f425 100644 --- a/coretests/tests/num/dec2flt/lemire.rs +++ b/coretests/tests/num/dec2flt/lemire.rs @@ -1,5 +1,6 @@ -use core::num::dec2flt::float::RawFloat; -use core::num::dec2flt::lemire::compute_float; +use core::num::imp::{Float, dec2flt}; + +use dec2flt::lemire::compute_float; #[cfg(target_has_reliable_f16)] fn compute_float16(q: i64, w: u64) -> (i32, u64) { diff --git a/coretests/tests/num/dec2flt/parse.rs b/coretests/tests/num/dec2flt/parse.rs index 65f1289d531b3..a63cdb3873762 100644 --- a/coretests/tests/num/dec2flt/parse.rs +++ b/coretests/tests/num/dec2flt/parse.rs @@ -1,6 +1,8 @@ -use core::num::dec2flt::decimal::Decimal; -use core::num::dec2flt::parse::parse_number; -use core::num::dec2flt::{dec2flt, pfe_invalid}; +use core::num::imp::dec2flt; + +use dec2flt::decimal::Decimal; +use dec2flt::parse::parse_number; +use dec2flt::{dec2flt, pfe_invalid}; fn new_dec(e: i64, m: u64) -> Decimal { Decimal { exponent: e, mantissa: m, negative: false, many_digits: false } diff --git a/coretests/tests/num/float_ieee754_flt2dec_dec2flt.rs b/coretests/tests/num/float_ieee754_flt2dec_dec2flt.rs new file mode 100644 index 0000000000000..2a82ae326c223 --- /dev/null +++ b/coretests/tests/num/float_ieee754_flt2dec_dec2flt.rs @@ -0,0 +1,166 @@ +//! IEEE 754 floating point compliance tests +//! +//! To understand IEEE 754's requirements on a programming language, one must understand that the +//! requirements of IEEE 754 rest on the total programming environment, and not entirely on any +//! one component. That means the hardware, language, and even libraries are considered part of +//! conforming floating point support in a programming environment. +//! +//! A programming language's duty, accordingly, is: +//! 1. offer access to the hardware where the hardware offers support +//! 2. provide operations that fulfill the remaining requirements of the standard +//! 3. provide the ability to write additional software that can fulfill those requirements +//! +//! This may be fulfilled in any combination that the language sees fit. However, to claim that +//! a language supports IEEE 754 is to suggest that it has fulfilled requirements 1 and 2, without +//! deferring minimum requirements to libraries. This is because support for IEEE 754 is defined +//! as complete support for at least one specified floating point type as an "arithmetic" and +//! "interchange" format, plus specified type conversions to "external character sequences" and +//! integer types. +//! +//! For our purposes, +//! "interchange format" => f16, f32, f64, f128 +//! "arithmetic format" => f16, f32, f64, f128, and any "soft floats" +//! "external character sequence" => str from any float +//! "integer format" => {i,u}{8,16,32,64,128} +//! +//! None of these tests are against Rust's own implementation. They are only tests against the +//! standard. That is why they accept wildly diverse inputs or may seem to duplicate other tests. +//! Please consider this carefully when adding, removing, or reorganizing these tests. They are +//! here so that it is clear what tests are required by the standard and what can be changed. + +use core::fmt; +use core::str::FromStr; + +use crate::num::{assert_biteq, float_test}; + +/// ToString uses the default fmt::Display impl without special concerns, and bypasses other parts +/// of the formatting infrastructure, which makes it ideal for testing here. +#[track_caller] +fn string_roundtrip(x: T) -> T +where + T: FromStr + fmt::Display, +{ + x.to_string().parse::().unwrap() +} + +// FIXME(f128): Tests are disabled while we don't have parsing / printing + +// We must preserve signs on all numbers. That includes zero. +// -0 and 0 are == normally, so test bit equality. +float_test! { + name: preserve_signed_zero, + attrs: { + const: #[cfg(false)], + f16: #[cfg(any(miri, target_has_reliable_f16))], + f128: #[cfg(false)], + }, + test { + let neg0 = flt(-0.0); + let pos0 = flt(0.0); + assert_biteq!(neg0, string_roundtrip(neg0)); + assert_biteq!(pos0, string_roundtrip(pos0)); + assert_ne!(neg0.to_bits(), pos0.to_bits()); + } +} + +float_test! { + name: preserve_signed_infinity, + attrs: { + const: #[cfg(false)], + f16: #[cfg(any(miri, target_has_reliable_f16))], + f128: #[cfg(false)], + }, + test { + let neg_inf = Float::NEG_INFINITY; + let pos_inf = Float::INFINITY; + assert_biteq!(neg_inf, string_roundtrip(neg_inf)); + assert_biteq!(pos_inf, string_roundtrip(pos_inf)); + assert_ne!(neg_inf.to_bits(), pos_inf.to_bits()); + } +} + +float_test! { + name: infinity_to_str, + attrs: { + const: #[cfg(false)], + f16: #[cfg(any(miri, target_has_reliable_f16))], + f128: #[cfg(false)], + }, + test { + assert!( + match Float::INFINITY.to_string().to_lowercase().as_str() { + "+infinity" | "infinity" => true, + "+inf" | "inf" => true, + _ => false, + }, + "Infinity must write to a string as some casing of inf or infinity, with an optional +." + ); + assert!( + match Float::NEG_INFINITY.to_string().to_lowercase().as_str() { + "-infinity" | "-inf" => true, + _ => false, + }, + "Negative Infinity must write to a string as some casing of -inf or -infinity" + ); + } +} + +float_test! { + name: nan_to_str, + attrs: { + const: #[cfg(false)], + f16: #[cfg(any(miri, target_has_reliable_f16))], + f128: #[cfg(false)], + }, + test { + assert!( + match Float::NAN.to_string().to_lowercase().as_str() { + "nan" | "+nan" | "-nan" => true, + _ => false, + }, + "NaNs must write to a string as some casing of nan." + ) + } +} + +float_test! { + name: infinity_from_str, + attrs: { + const: #[cfg(false)], + f16: #[cfg(any(miri, target_has_reliable_f16))], + f128: #[cfg(false)], + }, + test { + // "+"?("inf"|"infinity") in any case => Infinity + assert_biteq!(Float::INFINITY, Float::from_str("infinity").unwrap()); + assert_biteq!(Float::INFINITY, Float::from_str("inf").unwrap()); + assert_biteq!(Float::INFINITY, Float::from_str("+infinity").unwrap()); + assert_biteq!(Float::INFINITY, Float::from_str("+inf").unwrap()); + // yes! this means you are weLcOmE tO mY iNfInItElY tWiStEd MiNd + assert_biteq!(Float::INFINITY, Float::from_str("+iNfInItY").unwrap()); + + // "-inf"|"-infinity" in any case => Negative Infinity + assert_biteq!(Float::NEG_INFINITY, Float::from_str("-infinity").unwrap()); + assert_biteq!(Float::NEG_INFINITY, Float::from_str("-inf").unwrap()); + assert_biteq!(Float::NEG_INFINITY, Float::from_str("-INF").unwrap()); + assert_biteq!(Float::NEG_INFINITY, Float::from_str("-INFinity").unwrap()); + + } +} + +float_test! { + name: qnan_from_str, + attrs: { + const: #[cfg(false)], + f16: #[cfg(any(miri, target_has_reliable_f16))], + f128: #[cfg(false)], + }, + test { + // ("+"|"-"")?"s"?"nan" in any case => qNaN + assert!("nan".parse::().unwrap().is_nan()); + assert!("-nan".parse::().unwrap().is_nan()); + assert!("+nan".parse::().unwrap().is_nan()); + assert!("+NAN".parse::().unwrap().is_nan()); + assert!("-NaN".parse::().unwrap().is_nan()); + } +} diff --git a/coretests/tests/floats/mod.rs b/coretests/tests/num/floats.rs similarity index 60% rename from coretests/tests/floats/mod.rs rename to coretests/tests/num/floats.rs index 06fc3c96eafc8..d87f850944503 100644 --- a/coretests/tests/floats/mod.rs +++ b/coretests/tests/num/floats.rs @@ -1,20 +1,39 @@ +use std::hint::black_box; use std::num::FpCategory as Fp; use std::ops::{Add, Div, Mul, Rem, Sub}; -trait TestableFloat: Sized { +pub(crate) trait TestableFloat: Sized { + const BITS: u32; /// Unsigned int with the same size, for converting to/from bits. type Int; + /// Signed int with the same size. + type SInt; /// Set the default tolerance for float comparison based on the type. const APPROX: Self; /// Allow looser tolerance for f32 on miri const POWI_APPROX: Self = Self::APPROX; + /// Tolerance for `powf` tests; some types need looser bounds + const POWF_APPROX: Self = Self::APPROX; /// Allow looser tolerance for f16 const _180_TO_RADIANS_APPROX: Self = Self::APPROX; /// Allow for looser tolerance for f16 const PI_TO_DEGREES_APPROX: Self = Self::APPROX; + /// Tolerance for math tests + const EXP_APPROX: Self = Self::APPROX; + const LN_APPROX: Self = Self::APPROX; + const LOG_APPROX: Self = Self::APPROX; + const LOG2_APPROX: Self = Self::APPROX; + const LOG10_APPROX: Self = Self::APPROX; + const ASINH_APPROX: Self = Self::APPROX; + const ACOSH_APPROX: Self = Self::APPROX; + const ATANH_APPROX: Self = Self::APPROX; + const GAMMA_APPROX: Self = Self::APPROX; + const GAMMA_APPROX_LOOSE: Self = Self::APPROX; + const LNGAMMA_APPROX: Self = Self::APPROX; + const LNGAMMA_APPROX_LOOSE: Self = Self::APPROX; const ZERO: Self; const ONE: Self; - const PI: Self; + const SNAN: Self; const MIN_POSITIVE_NORMAL: Self; const MAX_SUBNORMAL: Self; /// Smallest number @@ -43,13 +62,30 @@ trait TestableFloat: Sized { } impl TestableFloat for f16 { + const BITS: u32 = 16; type Int = u16; + type SInt = i16; const APPROX: Self = 1e-3; + const POWF_APPROX: Self = 5e-1; const _180_TO_RADIANS_APPROX: Self = 1e-2; const PI_TO_DEGREES_APPROX: Self = 0.125; + const EXP_APPROX: Self = 1e-2; + const LN_APPROX: Self = 1e-2; + const LOG_APPROX: Self = 1e-2; + const LOG2_APPROX: Self = 1e-2; + const LOG10_APPROX: Self = 1e-2; + const ASINH_APPROX: Self = 1e-2; + const ACOSH_APPROX: Self = 1e-2; + const ATANH_APPROX: Self = 1e-2; + const GAMMA_APPROX: Self = 1e-2; + const GAMMA_APPROX_LOOSE: Self = 1e-1; + const LNGAMMA_APPROX: Self = 1e-2; + const LNGAMMA_APPROX_LOOSE: Self = 1e-1; const ZERO: Self = 0.0; const ONE: Self = 1.0; - const PI: Self = std::f16::consts::PI; + // We rely on NAN having an all-0 payload, so the signaling bit is the least significant + // non-0 bit, and that gets toggled by the "-1". + const SNAN: Self = Self::from_bits(Self::NAN.to_bits() - 1); const MIN_POSITIVE_NORMAL: Self = Self::MIN_POSITIVE; const MAX_SUBNORMAL: Self = Self::MIN_POSITIVE.next_down(); const TINY: Self = Self::from_bits(0x1); @@ -70,15 +106,32 @@ impl TestableFloat for f16 { } impl TestableFloat for f32 { + const BITS: u32 = 32; type Int = u32; + type SInt = i32; const APPROX: Self = 1e-6; /// Miri adds some extra errors to float functions; make sure the tests still pass. /// These values are purely used as a canary to test against and are thus not a stable guarantee Rust provides. /// They serve as a way to get an idea of the real precision of floating point operations on different platforms. const POWI_APPROX: Self = if cfg!(miri) { 1e-4 } else { Self::APPROX }; + const POWF_APPROX: Self = if cfg!(miri) { 1e-3 } else { 1e-4 }; + const EXP_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LN_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LOG_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LOG2_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LOG10_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const ASINH_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const ACOSH_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const ATANH_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const GAMMA_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const GAMMA_APPROX_LOOSE: Self = if cfg!(miri) { 1e-2 } else { 1e-4 }; + const LNGAMMA_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LNGAMMA_APPROX_LOOSE: Self = if cfg!(miri) { 1e-2 } else { 1e-4 }; const ZERO: Self = 0.0; const ONE: Self = 1.0; - const PI: Self = std::f32::consts::PI; + // We rely on NAN having an all-0 payload, so the signaling bit is the least significant + // non-0 bit, and that gets toggled by the "-1". + const SNAN: Self = Self::from_bits(Self::NAN.to_bits() - 1); const MIN_POSITIVE_NORMAL: Self = Self::MIN_POSITIVE; const MAX_SUBNORMAL: Self = Self::MIN_POSITIVE.next_down(); const TINY: Self = Self::from_bits(0x1); @@ -99,11 +152,17 @@ impl TestableFloat for f32 { } impl TestableFloat for f64 { + const BITS: u32 = 64; type Int = u64; + type SInt = i64; const APPROX: Self = 1e-6; + const GAMMA_APPROX_LOOSE: Self = 1e-4; + const LNGAMMA_APPROX_LOOSE: Self = 1e-4; const ZERO: Self = 0.0; const ONE: Self = 1.0; - const PI: Self = std::f64::consts::PI; + // We rely on NAN having an all-0 payload, so the signaling bit is the least significant + // non-0 bit, and that gets toggled by the "-1". + const SNAN: Self = Self::from_bits(Self::NAN.to_bits() - 1); const MIN_POSITIVE_NORMAL: Self = Self::MIN_POSITIVE; const MAX_SUBNORMAL: Self = Self::MIN_POSITIVE.next_down(); const TINY: Self = Self::from_bits(0x1); @@ -124,11 +183,27 @@ impl TestableFloat for f64 { } impl TestableFloat for f128 { + const BITS: u32 = 128; type Int = u128; + type SInt = i128; const APPROX: Self = 1e-9; + const EXP_APPROX: Self = 1e-12; + const LN_APPROX: Self = 1e-12; + const LOG_APPROX: Self = 1e-12; + const LOG2_APPROX: Self = 1e-12; + const LOG10_APPROX: Self = 1e-12; + const ASINH_APPROX: Self = 1e-10; + const ACOSH_APPROX: Self = 1e-10; + const ATANH_APPROX: Self = 1e-10; + const GAMMA_APPROX: Self = 1e-12; + const GAMMA_APPROX_LOOSE: Self = 1e-10; + const LNGAMMA_APPROX: Self = 1e-12; + const LNGAMMA_APPROX_LOOSE: Self = 1e-10; const ZERO: Self = 0.0; const ONE: Self = 1.0; - const PI: Self = std::f128::consts::PI; + // We rely on NAN having an all-0 payload, so the signaling bit is the least significant + // non-0 bit, and that gets toggled by the "-1". + const SNAN: Self = Self::from_bits(Self::NAN.to_bits() - 1); const MIN_POSITIVE_NORMAL: Self = Self::MIN_POSITIVE; const MAX_SUBNORMAL: Self = Self::MIN_POSITIVE.next_down(); const TINY: Self = Self::from_bits(0x1); @@ -149,38 +224,37 @@ impl TestableFloat for f128 { } /// Determine the tolerance for values of the argument type. -const fn lim_for_ty(_x: T) -> T { +pub(crate) const fn lim_for_ty(_x: T) -> T { T::APPROX } // We have runtime ("rt") and const versions of these macros. /// Verify that floats are within a tolerance of each other. -macro_rules! assert_approx_eq_rt { - ($a:expr, $b:expr) => {{ assert_approx_eq_rt!($a, $b, $crate::floats::lim_for_ty($a)) }}; +macro_rules! assert_approx_eq { + ($a:expr, $b:expr $(,)?) => {{ + assert_approx_eq!($a, $b, $crate::num::floats::lim_for_ty($a)) + }}; ($a:expr, $b:expr, $lim:expr) => {{ let (a, b) = (&$a, &$b); let diff = (*a - *b).abs(); - assert!( + core::panic::const_assert!( diff <= $lim, + "actual value is not approximately equal to expected value", "{a:?} is not approximately equal to {b:?} (threshold {lim:?}, difference {diff:?})", - lim = $lim + // We rely on the `Float` type being brought in scope by the macros below. + a: Float = *a, + b: Float = *b, + diff: Float = diff, + lim: Float = $lim, ); }}; } -macro_rules! assert_approx_eq_const { - ($a:expr, $b:expr) => {{ assert_approx_eq_const!($a, $b, $crate::floats::lim_for_ty($a)) }}; - ($a:expr, $b:expr, $lim:expr) => {{ - let (a, b) = (&$a, &$b); - let diff = (*a - *b).abs(); - assert!(diff <= $lim); - }}; -} /// Verify that floats have the same bitwise representation. Used to avoid the default `0.0 == -0.0` /// behavior, as well as to ensure exact NaN bitpatterns. -macro_rules! assert_biteq_rt { - (@inner $left:expr, $right:expr, $msg_sep:literal, $($tt:tt)*) => {{ +macro_rules! assert_biteq { + ($left:expr, $right:expr $(,)?) => {{ let l = $left; let r = $right; @@ -190,62 +264,20 @@ macro_rules! assert_biteq_rt { // Hack to get the width from a value let bits = (l.to_bits() - l.to_bits()).leading_zeros(); - assert!( + core::panic::const_assert!( l.to_bits() == r.to_bits(), - "{msg}{nl}l: {l:?} ({lb:#0width$x})\nr: {r:?} ({rb:#0width$x})", - msg = format_args!($($tt)*), - nl = $msg_sep, - lb = l.to_bits(), - rb = r.to_bits(), - width = ((bits / 4) + 2) as usize, + "actual value and expected value are not bit-equal", + "actual value and expected value are not bit-equal\n\ + l: {l:?} ({lb:#0width$x})\nr: {r:?} ({rb:#0width$x})", + // We rely on the `Float` type being brought in scope by the macros below. + l: Float = l, + r: Float = r, + lb: ::Int = l.to_bits(), + rb: ::Int = r.to_bits(), + width: usize = ((bits / 4) + 2) as usize, ); - - if !l.is_nan() && !r.is_nan() { - // Also check that standard equality holds, since most tests use `assert_biteq` rather - // than `assert_eq`. - assert_eq!(l, r); - } }}; - ($left:expr, $right:expr , $($tt:tt)*) => { - assert_biteq_rt!(@inner $left, $right, "\n", $($tt)*) - }; - ($left:expr, $right:expr $(,)?) => { - assert_biteq_rt!(@inner $left, $right, "", "") - }; } -macro_rules! assert_biteq_const { - (@inner $left:expr, $right:expr, $msg_sep:literal, $($tt:tt)*) => {{ - let l = $left; - let r = $right; - - // Hack to coerce left and right to the same type - let mut _eq_ty = l; - _eq_ty = r; - - assert!(l.to_bits() == r.to_bits()); - - if !l.is_nan() && !r.is_nan() { - // Also check that standard equality holds, since most tests use `assert_biteq` rather - // than `assert_eq`. - assert!(l == r); - } - }}; - ($left:expr, $right:expr , $($tt:tt)*) => { - assert_biteq_const!(@inner $left, $right, "\n", $($tt)*) - }; - ($left:expr, $right:expr $(,)?) => { - assert_biteq_const!(@inner $left, $right, "", "") - }; -} - -// Use the runtime version by default. -// This way, they can be shadowed by the const versions. -pub(crate) use {assert_approx_eq_rt as assert_approx_eq, assert_biteq_rt as assert_biteq}; - -// Also make the const version available for re-exports. -#[rustfmt::skip] -pub(crate) use assert_biteq_const; -pub(crate) use assert_approx_eq_const; /// Generate float tests for all our float types, for compile-time and run-time behavior. /// @@ -279,95 +311,102 @@ macro_rules! float_test { $(f128: #[ $($f128_meta:meta),+ ] ,)? $(const f128: #[ $($f128_const_meta:meta),+ ] ,)? }, - test<$fty:ident> $test:block + test $test:block ) => { mod $name { + #[allow(unused_imports)] use super::*; #[test] $( $( #[$f16_meta] )+ )? fn test_f16() { - type $fty = f16; + #[allow(unused_imports)] + use core::f16::consts; + type Float = f16; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } $test } #[test] $( $( #[$f32_meta] )+ )? fn test_f32() { - type $fty = f32; + #[allow(unused_imports)] + use core::f32::consts; + type Float = f32; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } $test } #[test] $( $( #[$f64_meta] )+ )? fn test_f64() { - type $fty = f64; + #[allow(unused_imports)] + use core::f64::consts; + type Float = f64; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } $test } #[test] $( $( #[$f128_meta] )+ )? fn test_f128() { - type $fty = f128; + #[allow(unused_imports)] + use core::f128::consts; + type Float = f128; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } $test } $( $( #[$const_meta] )+ )? mod const_ { - #[allow(unused)] - use super::TestableFloat; - #[allow(unused)] - use std::num::FpCategory as Fp; - #[allow(unused)] - use std::ops::{Add, Div, Mul, Rem, Sub}; - // Shadow the runtime versions of the macro with const-compatible versions. - #[allow(unused)] - use $crate::floats::{ - assert_approx_eq_const as assert_approx_eq, - assert_biteq_const as assert_biteq, - }; + #[allow(unused_imports)] + use super::*; #[test] $( $( #[$f16_const_meta] )+ )? fn test_f16() { - type $fty = f16; + #[allow(unused_imports)] + use core::f16::consts; + type Float = f16; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } const { $test } } #[test] $( $( #[$f32_const_meta] )+ )? fn test_f32() { - type $fty = f32; + #[allow(unused_imports)] + use core::f32::consts; + type Float = f32; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } const { $test } } #[test] $( $( #[$f64_const_meta] )+ )? fn test_f64() { - type $fty = f64; + #[allow(unused_imports)] + use core::f64::consts; + type Float = f64; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } const { $test } } #[test] $( $( #[$f128_const_meta] )+ )? fn test_f128() { - type $fty = f128; + #[allow(unused_imports)] + use core::f128::consts; + type Float = f128; #[allow(unused)] - const fn flt (x: $fty) -> $fty { x } + const fn flt (x: Float) -> Float { x } const { $test } } } @@ -375,13 +414,16 @@ macro_rules! float_test { }; } +pub(crate) use assert_biteq; +pub(crate) use float_test; + float_test! { name: num, attrs: { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let two: Float = 2.0; let ten: Float = 10.0; assert_biteq!(ten.add(two), ten + two); @@ -399,7 +441,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { let two: Float = 2.0; let ten: Float = 10.0; assert_biteq!(ten.rem(two), ten % two); @@ -412,7 +454,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let nan: Float = Float::NAN; assert!(nan.is_nan()); assert!(!nan.is_infinite()); @@ -432,7 +474,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let inf: Float = Float::INFINITY; assert!(inf.is_infinite()); assert!(!inf.is_finite()); @@ -450,7 +492,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let neg_inf: Float = Float::NEG_INFINITY; assert!(neg_inf.is_infinite()); assert!(!neg_inf.is_finite()); @@ -468,7 +510,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { assert_biteq!(0.0, Float::ZERO); assert!(!Float::ZERO.is_infinite()); assert!(Float::ZERO.is_finite()); @@ -486,7 +528,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let neg_zero: Float = -0.0; assert!(0.0 == neg_zero); assert_biteq!(-0.0, neg_zero); @@ -506,7 +548,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { assert_biteq!(1.0, Float::ONE); assert!(!Float::ONE.is_infinite()); assert!(Float::ONE.is_finite()); @@ -524,7 +566,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; @@ -545,7 +587,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; @@ -566,7 +608,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; @@ -587,7 +629,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; @@ -608,7 +650,7 @@ float_test! { attrs: { f16: #[cfg(any(miri, target_has_reliable_f16))], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; @@ -630,27 +672,38 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((0.0 as Float).min(0.0), 0.0); - assert_biteq!((-0.0 as Float).min(-0.0), -0.0); - assert_biteq!((9.0 as Float).min(9.0), 9.0); - assert_biteq!((-9.0 as Float).min(0.0), -9.0); - assert_biteq!((0.0 as Float).min(9.0), 0.0); - assert_biteq!((-0.0 as Float).min(9.0), -0.0); - assert_biteq!((-0.0 as Float).min(-9.0), -9.0); + test { + assert_biteq!(flt(0.0).min(0.0), 0.0); + assert_biteq!(flt(-0.0).min(-0.0), -0.0); + assert_biteq!(flt(9.0).min(9.0), 9.0); + assert_biteq!(flt(-9.0).min(0.0), -9.0); + assert_biteq!(flt(0.0).min(9.0), 0.0); + assert_biteq!(flt(-0.0).min(9.0), -0.0); + assert_biteq!(flt(-0.0).min(-9.0), -9.0); assert_biteq!(Float::INFINITY.min(9.0), 9.0); - assert_biteq!((9.0 as Float).min(Float::INFINITY), 9.0); + assert_biteq!(flt(9.0).min(Float::INFINITY), 9.0); assert_biteq!(Float::INFINITY.min(-9.0), -9.0); - assert_biteq!((-9.0 as Float).min(Float::INFINITY), -9.0); + assert_biteq!(flt(-9.0).min(Float::INFINITY), -9.0); assert_biteq!(Float::NEG_INFINITY.min(9.0), Float::NEG_INFINITY); - assert_biteq!((9.0 as Float).min(Float::NEG_INFINITY), Float::NEG_INFINITY); + assert_biteq!(flt(9.0).min(Float::NEG_INFINITY), Float::NEG_INFINITY); assert_biteq!(Float::NEG_INFINITY.min(-9.0), Float::NEG_INFINITY); - assert_biteq!((-9.0 as Float).min(Float::NEG_INFINITY), Float::NEG_INFINITY); - assert_biteq!(Float::NAN.min(9.0), 9.0); - assert_biteq!(Float::NAN.min(-9.0), -9.0); - assert_biteq!((9.0 as Float).min(Float::NAN), 9.0); - assert_biteq!((-9.0 as Float).min(Float::NAN), -9.0); + assert_biteq!(flt(-9.0).min(Float::NEG_INFINITY), Float::NEG_INFINITY); + // We add black_box for the NAN tests as that used to be able to trigger miscompilations. + assert_biteq!(Float::NAN.min(black_box(9.0)), 9.0); + assert_biteq!(black_box(Float::NAN).min(-9.0), -9.0); + assert_biteq!(flt(9.0).min(black_box(Float::NAN)), 9.0); + assert_biteq!(black_box(flt(-9.0)).min(Float::NAN), -9.0); assert!(Float::NAN.min(Float::NAN).is_nan()); + // FIXME(llvm21): LLVM miscompiles the fallback impl on aarch64 and likely other targets + // (https://github.com/llvm/llvm-project/issues/176624). When we require LLVM 22, + // remove the ui test `tests/ui/float/minmax.rs` and unconditionally enable the test here. + if cfg!(miri) { + assert_biteq!(Float::SNAN.min(black_box(9.0)), 9.0); + assert_biteq!(black_box(Float::SNAN).min(-9.0), -9.0); + assert_biteq!(flt(9.0).min(black_box(Float::SNAN)), 9.0); + assert_biteq!(black_box(flt(-9.0)).min(Float::SNAN), -9.0); + } + assert!(Float::SNAN.min(Float::SNAN).is_nan()); } } @@ -660,28 +713,39 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((0.0 as Float).max(0.0), 0.0); - assert_biteq!((-0.0 as Float).max(-0.0), -0.0); - assert_biteq!((9.0 as Float).max(9.0), 9.0); - assert_biteq!((-9.0 as Float).max(0.0), 0.0); - assert_biteq!((-9.0 as Float).max(-0.0), -0.0); - assert_biteq!((0.0 as Float).max(9.0), 9.0); - assert_biteq!((0.0 as Float).max(-9.0), 0.0); - assert_biteq!((-0.0 as Float).max(-9.0), -0.0); + test { + assert_biteq!(flt(0.0).max(0.0), 0.0); + assert_biteq!(flt(-0.0).max(-0.0), -0.0); + assert_biteq!(flt(9.0).max(9.0), 9.0); + assert_biteq!(flt(-9.0).max(0.0), 0.0); + assert_biteq!(flt(-9.0).max(-0.0), -0.0); + assert_biteq!(flt(0.0).max(9.0), 9.0); + assert_biteq!(flt(0.0).max(-9.0), 0.0); + assert_biteq!(flt(-0.0).max(-9.0), -0.0); assert_biteq!(Float::INFINITY.max(9.0), Float::INFINITY); - assert_biteq!((9.0 as Float).max(Float::INFINITY), Float::INFINITY); + assert_biteq!(flt(9.0).max(Float::INFINITY), Float::INFINITY); assert_biteq!(Float::INFINITY.max(-9.0), Float::INFINITY); - assert_biteq!((-9.0 as Float).max(Float::INFINITY), Float::INFINITY); + assert_biteq!(flt(-9.0).max(Float::INFINITY), Float::INFINITY); assert_biteq!(Float::NEG_INFINITY.max(9.0), 9.0); - assert_biteq!((9.0 as Float).max(Float::NEG_INFINITY), 9.0); + assert_biteq!(flt(9.0).max(Float::NEG_INFINITY), 9.0); assert_biteq!(Float::NEG_INFINITY.max(-9.0), -9.0); - assert_biteq!((-9.0 as Float).max(Float::NEG_INFINITY), -9.0); - assert_biteq!(Float::NAN.max(9.0), 9.0); - assert_biteq!(Float::NAN.max(-9.0), -9.0); - assert_biteq!((9.0 as Float).max(Float::NAN), 9.0); - assert_biteq!((-9.0 as Float).max(Float::NAN), -9.0); + assert_biteq!(flt(-9.0).max(Float::NEG_INFINITY), -9.0); + // We add black_box for the NAN tests as that used to be able to trigger miscompilations. + assert_biteq!(Float::NAN.max(black_box(9.0)), 9.0); + assert_biteq!(black_box(Float::NAN).max(-9.0), -9.0); + assert_biteq!(flt(9.0).max(black_box(Float::NAN)), 9.0); + assert_biteq!(black_box(flt(-9.0)).max(Float::NAN), -9.0); assert!(Float::NAN.max(Float::NAN).is_nan()); + // FIXME(llvm21): LLVM miscompiles the fallback impl on aarch64 and likely other targets + // (https://github.com/llvm/llvm-project/issues/176624). When we require LLVM 22, + // remove the ui test `tests/ui/float/minmax.rs` and unconditionally enable the test here. + if cfg!(miri) { + assert_biteq!(Float::SNAN.max(black_box(9.0)), 9.0); + assert_biteq!(black_box(Float::SNAN).max(-9.0), -9.0); + assert_biteq!(flt(9.0).max(black_box(Float::SNAN)), 9.0); + assert_biteq!(black_box(flt(-9.0)).max(Float::SNAN), -9.0); + } + assert!(Float::SNAN.max(Float::SNAN).is_nan()); } } @@ -691,27 +755,27 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((0.0 as Float).minimum(0.0), 0.0); - assert_biteq!((-0.0 as Float).minimum(0.0), -0.0); - assert_biteq!((-0.0 as Float).minimum(-0.0), -0.0); - assert_biteq!((9.0 as Float).minimum(9.0), 9.0); - assert_biteq!((-9.0 as Float).minimum(0.0), -9.0); - assert_biteq!((0.0 as Float).minimum(9.0), 0.0); - assert_biteq!((-0.0 as Float).minimum(9.0), -0.0); - assert_biteq!((-0.0 as Float).minimum(-9.0), -9.0); + test { + assert_biteq!(flt(0.0).minimum(0.0), 0.0); + assert_biteq!(flt(-0.0).minimum(0.0), -0.0); + assert_biteq!(flt(-0.0).minimum(-0.0), -0.0); + assert_biteq!(flt(9.0).minimum(9.0), 9.0); + assert_biteq!(flt(-9.0).minimum(0.0), -9.0); + assert_biteq!(flt(0.0).minimum(9.0), 0.0); + assert_biteq!(flt(-0.0).minimum(9.0), -0.0); + assert_biteq!(flt(-0.0).minimum(-9.0), -9.0); assert_biteq!(Float::INFINITY.minimum(9.0), 9.0); - assert_biteq!((9.0 as Float).minimum(Float::INFINITY), 9.0); + assert_biteq!(flt(9.0).minimum(Float::INFINITY), 9.0); assert_biteq!(Float::INFINITY.minimum(-9.0), -9.0); - assert_biteq!((-9.0 as Float).minimum(Float::INFINITY), -9.0); + assert_biteq!(flt(-9.0).minimum(Float::INFINITY), -9.0); assert_biteq!(Float::NEG_INFINITY.minimum(9.0), Float::NEG_INFINITY); - assert_biteq!((9.0 as Float).minimum(Float::NEG_INFINITY), Float::NEG_INFINITY); + assert_biteq!(flt(9.0).minimum(Float::NEG_INFINITY), Float::NEG_INFINITY); assert_biteq!(Float::NEG_INFINITY.minimum(-9.0), Float::NEG_INFINITY); - assert_biteq!((-9.0 as Float).minimum(Float::NEG_INFINITY), Float::NEG_INFINITY); + assert_biteq!(flt(-9.0).minimum(Float::NEG_INFINITY), Float::NEG_INFINITY); assert!(Float::NAN.minimum(9.0).is_nan()); assert!(Float::NAN.minimum(-9.0).is_nan()); - assert!((9.0 as Float).minimum(Float::NAN).is_nan()); - assert!((-9.0 as Float).minimum(Float::NAN).is_nan()); + assert!(flt(9.0).minimum(Float::NAN).is_nan()); + assert!(flt(-9.0).minimum(Float::NAN).is_nan()); assert!(Float::NAN.minimum(Float::NAN).is_nan()); } } @@ -722,28 +786,28 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((0.0 as Float).maximum(0.0), 0.0); - assert_biteq!((-0.0 as Float).maximum(0.0), 0.0); - assert_biteq!((-0.0 as Float).maximum(-0.0), -0.0); - assert_biteq!((9.0 as Float).maximum(9.0), 9.0); - assert_biteq!((-9.0 as Float).maximum(0.0), 0.0); - assert_biteq!((-9.0 as Float).maximum(-0.0), -0.0); - assert_biteq!((0.0 as Float).maximum(9.0), 9.0); - assert_biteq!((0.0 as Float).maximum(-9.0), 0.0); - assert_biteq!((-0.0 as Float).maximum(-9.0), -0.0); + test { + assert_biteq!(flt(0.0).maximum(0.0), 0.0); + assert_biteq!(flt(-0.0).maximum(0.0), 0.0); + assert_biteq!(flt(-0.0).maximum(-0.0), -0.0); + assert_biteq!(flt(9.0).maximum(9.0), 9.0); + assert_biteq!(flt(-9.0).maximum(0.0), 0.0); + assert_biteq!(flt(-9.0).maximum(-0.0), -0.0); + assert_biteq!(flt(0.0).maximum(9.0), 9.0); + assert_biteq!(flt(0.0).maximum(-9.0), 0.0); + assert_biteq!(flt(-0.0).maximum(-9.0), -0.0); assert_biteq!(Float::INFINITY.maximum(9.0), Float::INFINITY); - assert_biteq!((9.0 as Float).maximum(Float::INFINITY), Float::INFINITY); + assert_biteq!(flt(9.0).maximum(Float::INFINITY), Float::INFINITY); assert_biteq!(Float::INFINITY.maximum(-9.0), Float::INFINITY); - assert_biteq!((-9.0 as Float).maximum(Float::INFINITY), Float::INFINITY); + assert_biteq!(flt(-9.0).maximum(Float::INFINITY), Float::INFINITY); assert_biteq!(Float::NEG_INFINITY.maximum(9.0), 9.0); - assert_biteq!((9.0 as Float).maximum(Float::NEG_INFINITY), 9.0); + assert_biteq!(flt(9.0).maximum(Float::NEG_INFINITY), 9.0); assert_biteq!(Float::NEG_INFINITY.maximum(-9.0), -9.0); - assert_biteq!((-9.0 as Float).maximum(Float::NEG_INFINITY), -9.0); + assert_biteq!(flt(-9.0).maximum(Float::NEG_INFINITY), -9.0); assert!(Float::NAN.maximum(9.0).is_nan()); assert!(Float::NAN.maximum(-9.0).is_nan()); - assert!((9.0 as Float).maximum(Float::NAN).is_nan()); - assert!((-9.0 as Float).maximum(Float::NAN).is_nan()); + assert!(flt(9.0).maximum(Float::NAN).is_nan()); + assert!(flt(-9.0).maximum(Float::NAN).is_nan()); assert!(Float::NAN.maximum(Float::NAN).is_nan()); } } @@ -754,16 +818,16 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((0.5 as Float).midpoint(0.5), 0.5); - assert_biteq!((0.5 as Float).midpoint(2.5), 1.5); - assert_biteq!((3.0 as Float).midpoint(4.0), 3.5); - assert_biteq!((-3.0 as Float).midpoint(4.0), 0.5); - assert_biteq!((3.0 as Float).midpoint(-4.0), -0.5); - assert_biteq!((-3.0 as Float).midpoint(-4.0), -3.5); - assert_biteq!((0.0 as Float).midpoint(0.0), 0.0); - assert_biteq!((-0.0 as Float).midpoint(-0.0), -0.0); - assert_biteq!((-5.0 as Float).midpoint(5.0), 0.0); + test { + assert_biteq!(flt(0.5).midpoint(0.5), 0.5); + assert_biteq!(flt(0.5).midpoint(2.5), 1.5); + assert_biteq!(flt(3.0).midpoint(4.0), 3.5); + assert_biteq!(flt(-3.0).midpoint(4.0), 0.5); + assert_biteq!(flt(3.0).midpoint(-4.0), -0.5); + assert_biteq!(flt(-3.0).midpoint(-4.0), -3.5); + assert_biteq!(flt(0.0).midpoint(0.0), 0.0); + assert_biteq!(flt(-0.0).midpoint(-0.0), -0.0); + assert_biteq!(flt(-5.0).midpoint(5.0), 0.0); assert_biteq!(Float::MAX.midpoint(Float::MIN), 0.0); assert_biteq!(Float::MIN.midpoint(Float::MAX), 0.0); assert_biteq!(Float::MAX.midpoint(Float::MIN_POSITIVE), Float::MAX / 2.); @@ -793,7 +857,7 @@ float_test! { assert!(Float::NEG_INFINITY.midpoint(Float::INFINITY).is_nan()); assert!(Float::INFINITY.midpoint(Float::NEG_INFINITY).is_nan()); assert!(Float::NAN.midpoint(1.0).is_nan()); - assert!((1.0 as Float).midpoint(Float::NAN).is_nan()); + assert!(flt(1.0).midpoint(Float::NAN).is_nan()); assert!(Float::NAN.midpoint(Float::NAN).is_nan()); } } @@ -807,7 +871,7 @@ float_test! { f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], }, - test { + test { // test if large differences in magnitude are still correctly computed. // NOTE: that because of how small x and y are, x + y can never overflow // so (x + y) / 2.0 is always correct @@ -815,10 +879,10 @@ float_test! { // be safely doubled, while j is significantly smaller. for i in Float::MAX_EXP.saturating_sub(64)..Float::MAX_EXP { for j in 0..64u8 { - let large = (2.0 as Float).powi(i); + let large = flt(2.0).powi(i); // a much smaller number, such that there is no chance of overflow to test // potential double rounding in midpoint's implementation. - let small = (2.0 as Float).powi(Float::MAX_EXP - 1) + let small = flt(2.0).powi(Float::MAX_EXP - 1) * Float::EPSILON * Float::from(j); @@ -837,7 +901,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { assert_biteq!(Float::INFINITY.abs(), Float::INFINITY); assert_biteq!(Float::ONE.abs(), Float::ONE); assert_biteq!(Float::ZERO.abs(), Float::ZERO); @@ -855,9 +919,9 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((1.0 as Float).copysign(-2.0), -1.0); - assert_biteq!((-1.0 as Float).copysign(2.0), 1.0); + test { + assert_biteq!(flt(1.0).copysign(-2.0), -1.0); + assert_biteq!(flt(-1.0).copysign(2.0), 1.0); assert_biteq!(Float::INFINITY.copysign(-0.0), Float::NEG_INFINITY); assert_biteq!(Float::NEG_INFINITY.copysign(0.0), Float::INFINITY); } @@ -870,10 +934,10 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert!(Float::INFINITY.rem_euclid(42.0 as Float).is_nan()); - assert_biteq!((42.0 as Float).rem_euclid(Float::INFINITY), 42.0 as Float); - assert!((42.0 as Float).rem_euclid(Float::NAN).is_nan()); + test { + assert!(Float::INFINITY.rem_euclid(42.0).is_nan()); + assert_biteq!(flt(42.0).rem_euclid(Float::INFINITY), 42.0); + assert!(flt(42.0).rem_euclid(Float::NAN).is_nan()); assert!(Float::INFINITY.rem_euclid(Float::INFINITY).is_nan()); assert!(Float::INFINITY.rem_euclid(Float::NAN).is_nan()); assert!(Float::NAN.rem_euclid(Float::INFINITY).is_nan()); @@ -887,9 +951,9 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((42.0 as Float).div_euclid(Float::INFINITY), 0.0); - assert!((42.0 as Float).div_euclid(Float::NAN).is_nan()); + test { + assert_biteq!(flt(42.0).div_euclid(Float::INFINITY), 0.0); + assert!(flt(42.0).div_euclid(Float::NAN).is_nan()); assert!(Float::INFINITY.div_euclid(Float::INFINITY).is_nan()); assert!(Float::INFINITY.div_euclid(Float::NAN).is_nan()); assert!(Float::NAN.div_euclid(Float::INFINITY).is_nan()); @@ -902,19 +966,19 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((1.0 as Float).floor(), 1.0); - assert_biteq!((1.3 as Float).floor(), 1.0); - assert_biteq!((1.5 as Float).floor(), 1.0); - assert_biteq!((1.7 as Float).floor(), 1.0); - assert_biteq!((0.5 as Float).floor(), 0.0); - assert_biteq!((0.0 as Float).floor(), 0.0); - assert_biteq!((-0.0 as Float).floor(), -0.0); - assert_biteq!((-0.5 as Float).floor(), -1.0); - assert_biteq!((-1.0 as Float).floor(), -1.0); - assert_biteq!((-1.3 as Float).floor(), -2.0); - assert_biteq!((-1.5 as Float).floor(), -2.0); - assert_biteq!((-1.7 as Float).floor(), -2.0); + test { + assert_biteq!(flt(1.0).floor(), 1.0); + assert_biteq!(flt(1.3).floor(), 1.0); + assert_biteq!(flt(1.5).floor(), 1.0); + assert_biteq!(flt(1.7).floor(), 1.0); + assert_biteq!(flt(0.5).floor(), 0.0); + assert_biteq!(flt(0.0).floor(), 0.0); + assert_biteq!(flt(-0.0).floor(), -0.0); + assert_biteq!(flt(-0.5).floor(), -1.0); + assert_biteq!(flt(-1.0).floor(), -1.0); + assert_biteq!(flt(-1.3).floor(), -2.0); + assert_biteq!(flt(-1.5).floor(), -2.0); + assert_biteq!(flt(-1.7).floor(), -2.0); assert_biteq!(Float::MAX.floor(), Float::MAX); assert_biteq!(Float::MIN.floor(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.floor(), 0.0); @@ -931,19 +995,19 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((1.0 as Float).ceil(), 1.0); - assert_biteq!((1.3 as Float).ceil(), 2.0); - assert_biteq!((1.5 as Float).ceil(), 2.0); - assert_biteq!((1.7 as Float).ceil(), 2.0); - assert_biteq!((0.5 as Float).ceil(), 1.0); - assert_biteq!((0.0 as Float).ceil(), 0.0); - assert_biteq!((-0.0 as Float).ceil(), -0.0); - assert_biteq!((-0.5 as Float).ceil(), -0.0); - assert_biteq!((-1.0 as Float).ceil(), -1.0); - assert_biteq!((-1.3 as Float).ceil(), -1.0); - assert_biteq!((-1.5 as Float).ceil(), -1.0); - assert_biteq!((-1.7 as Float).ceil(), -1.0); + test { + assert_biteq!(flt(1.0).ceil(), 1.0); + assert_biteq!(flt(1.3).ceil(), 2.0); + assert_biteq!(flt(1.5).ceil(), 2.0); + assert_biteq!(flt(1.7).ceil(), 2.0); + assert_biteq!(flt(0.5).ceil(), 1.0); + assert_biteq!(flt(0.0).ceil(), 0.0); + assert_biteq!(flt(-0.0).ceil(), -0.0); + assert_biteq!(flt(-0.5).ceil(), -0.0); + assert_biteq!(flt(-1.0).ceil(), -1.0); + assert_biteq!(flt(-1.3).ceil(), -1.0); + assert_biteq!(flt(-1.5).ceil(), -1.0); + assert_biteq!(flt(-1.7).ceil(), -1.0); assert_biteq!(Float::MAX.ceil(), Float::MAX); assert_biteq!(Float::MIN.ceil(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.ceil(), 1.0); @@ -960,20 +1024,20 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((2.5 as Float).round(), 3.0); - assert_biteq!((1.0 as Float).round(), 1.0); - assert_biteq!((1.3 as Float).round(), 1.0); - assert_biteq!((1.5 as Float).round(), 2.0); - assert_biteq!((1.7 as Float).round(), 2.0); - assert_biteq!((0.5 as Float).round(), 1.0); - assert_biteq!((0.0 as Float).round(), 0.0); - assert_biteq!((-0.0 as Float).round(), -0.0); - assert_biteq!((-0.5 as Float).round(), -1.0); - assert_biteq!((-1.0 as Float).round(), -1.0); - assert_biteq!((-1.3 as Float).round(), -1.0); - assert_biteq!((-1.5 as Float).round(), -2.0); - assert_biteq!((-1.7 as Float).round(), -2.0); + test { + assert_biteq!(flt(2.5).round(), 3.0); + assert_biteq!(flt(1.0).round(), 1.0); + assert_biteq!(flt(1.3).round(), 1.0); + assert_biteq!(flt(1.5).round(), 2.0); + assert_biteq!(flt(1.7).round(), 2.0); + assert_biteq!(flt(0.5).round(), 1.0); + assert_biteq!(flt(0.0).round(), 0.0); + assert_biteq!(flt(-0.0).round(), -0.0); + assert_biteq!(flt(-0.5).round(), -1.0); + assert_biteq!(flt(-1.0).round(), -1.0); + assert_biteq!(flt(-1.3).round(), -1.0); + assert_biteq!(flt(-1.5).round(), -2.0); + assert_biteq!(flt(-1.7).round(), -2.0); assert_biteq!(Float::MAX.round(), Float::MAX); assert_biteq!(Float::MIN.round(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.round(), 0.0); @@ -990,20 +1054,20 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((2.5 as Float).round_ties_even(), 2.0); - assert_biteq!((1.0 as Float).round_ties_even(), 1.0); - assert_biteq!((1.3 as Float).round_ties_even(), 1.0); - assert_biteq!((1.5 as Float).round_ties_even(), 2.0); - assert_biteq!((1.7 as Float).round_ties_even(), 2.0); - assert_biteq!((0.5 as Float).round_ties_even(), 0.0); - assert_biteq!((0.0 as Float).round_ties_even(), 0.0); - assert_biteq!((-0.0 as Float).round_ties_even(), -0.0); - assert_biteq!((-0.5 as Float).round_ties_even(), -0.0); - assert_biteq!((-1.0 as Float).round_ties_even(), -1.0); - assert_biteq!((-1.3 as Float).round_ties_even(), -1.0); - assert_biteq!((-1.5 as Float).round_ties_even(), -2.0); - assert_biteq!((-1.7 as Float).round_ties_even(), -2.0); + test { + assert_biteq!(flt(2.5).round_ties_even(), 2.0); + assert_biteq!(flt(1.0).round_ties_even(), 1.0); + assert_biteq!(flt(1.3).round_ties_even(), 1.0); + assert_biteq!(flt(1.5).round_ties_even(), 2.0); + assert_biteq!(flt(1.7).round_ties_even(), 2.0); + assert_biteq!(flt(0.5).round_ties_even(), 0.0); + assert_biteq!(flt(0.0).round_ties_even(), 0.0); + assert_biteq!(flt(-0.0).round_ties_even(), -0.0); + assert_biteq!(flt(-0.5).round_ties_even(), -0.0); + assert_biteq!(flt(-1.0).round_ties_even(), -1.0); + assert_biteq!(flt(-1.3).round_ties_even(), -1.0); + assert_biteq!(flt(-1.5).round_ties_even(), -2.0); + assert_biteq!(flt(-1.7).round_ties_even(), -2.0); assert_biteq!(Float::MAX.round_ties_even(), Float::MAX); assert_biteq!(Float::MIN.round_ties_even(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.round_ties_even(), 0.0); @@ -1020,19 +1084,19 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((1.0 as Float).trunc(), 1.0); - assert_biteq!((1.3 as Float).trunc(), 1.0); - assert_biteq!((1.5 as Float).trunc(), 1.0); - assert_biteq!((1.7 as Float).trunc(), 1.0); - assert_biteq!((0.5 as Float).trunc(), 0.0); - assert_biteq!((0.0 as Float).trunc(), 0.0); - assert_biteq!((-0.0 as Float).trunc(), -0.0); - assert_biteq!((-0.5 as Float).trunc(), -0.0); - assert_biteq!((-1.0 as Float).trunc(), -1.0); - assert_biteq!((-1.3 as Float).trunc(), -1.0); - assert_biteq!((-1.5 as Float).trunc(), -1.0); - assert_biteq!((-1.7 as Float).trunc(), -1.0); + test { + assert_biteq!(flt(1.0).trunc(), 1.0); + assert_biteq!(flt(1.3).trunc(), 1.0); + assert_biteq!(flt(1.5).trunc(), 1.0); + assert_biteq!(flt(1.7).trunc(), 1.0); + assert_biteq!(flt(0.5).trunc(), 0.0); + assert_biteq!(flt(0.0).trunc(), 0.0); + assert_biteq!(flt(-0.0).trunc(), -0.0); + assert_biteq!(flt(-0.5).trunc(), -0.0); + assert_biteq!(flt(-1.0).trunc(), -1.0); + assert_biteq!(flt(-1.3).trunc(), -1.0); + assert_biteq!(flt(-1.5).trunc(), -1.0); + assert_biteq!(flt(-1.7).trunc(), -1.0); assert_biteq!(Float::MAX.trunc(), Float::MAX); assert_biteq!(Float::MIN.trunc(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.trunc(), 0.0); @@ -1049,19 +1113,19 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { - assert_biteq!((1.0 as Float).fract(), 0.0); - assert_approx_eq!((1.3 as Float).fract(), 0.3); // rounding differs between float types - assert_biteq!((1.5 as Float).fract(), 0.5); - assert_approx_eq!((1.7 as Float).fract(), 0.7); - assert_biteq!((0.5 as Float).fract(), 0.5); - assert_biteq!((0.0 as Float).fract(), 0.0); - assert_biteq!((-0.0 as Float).fract(), 0.0); - assert_biteq!((-0.5 as Float).fract(), -0.5); - assert_biteq!((-1.0 as Float).fract(), 0.0); - assert_approx_eq!((-1.3 as Float).fract(), -0.3); // rounding differs between float types - assert_biteq!((-1.5 as Float).fract(), -0.5); - assert_approx_eq!((-1.7 as Float).fract(), -0.7); + test { + assert_biteq!(flt(1.0).fract(), 0.0); + assert_approx_eq!(flt(1.3).fract(), 0.3); // rounding differs between float types + assert_biteq!(flt(1.5).fract(), 0.5); + assert_approx_eq!(flt(1.7).fract(), 0.7); + assert_biteq!(flt(0.5).fract(), 0.5); + assert_biteq!(flt(0.0).fract(), 0.0); + assert_biteq!(flt(-0.0).fract(), 0.0); + assert_biteq!(flt(-0.5).fract(), -0.5); + assert_biteq!(flt(-1.0).fract(), 0.0); + assert_approx_eq!(flt(-1.3).fract(), -0.3); // rounding differs between float types + assert_biteq!(flt(-1.5).fract(), -0.5); + assert_approx_eq!(flt(-1.7).fract(), -0.7); assert_biteq!(Float::MAX.fract(), 0.0); assert_biteq!(Float::MIN.fract(), 0.0); assert_biteq!(Float::MIN_POSITIVE.fract(), Float::MIN_POSITIVE); @@ -1080,7 +1144,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { assert_biteq!(Float::INFINITY.signum(), Float::ONE); assert_biteq!(Float::ONE.signum(), Float::ONE); assert_biteq!(Float::ZERO.signum(), Float::ONE); @@ -1098,7 +1162,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { assert!(Float::INFINITY.is_sign_positive()); assert!(Float::ONE.is_sign_positive()); assert!(Float::ZERO.is_sign_positive()); @@ -1117,7 +1181,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { assert!(!Float::INFINITY.is_sign_negative()); assert!(!Float::ONE.is_sign_negative()); assert!(!Float::ZERO.is_sign_negative()); @@ -1136,7 +1200,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { assert_biteq!(Float::NEG_INFINITY.next_up(), Float::MIN); assert_biteq!(Float::MIN.next_up(), -Float::MAX_DOWN); assert_biteq!((-Float::ONE - Float::EPSILON).next_up(), -Float::ONE); @@ -1167,7 +1231,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { assert_biteq!(Float::NEG_INFINITY.next_down(), Float::NEG_INFINITY); assert_biteq!(Float::MIN.next_down(), Float::NEG_INFINITY); assert_biteq!((-Float::MAX_DOWN).next_down(), Float::MIN); @@ -1200,7 +1264,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { assert!(Float::NAN.sqrt().is_nan()); assert!(Float::NEG_INFINITY.sqrt().is_nan()); assert!((-Float::ONE).sqrt().is_nan()); @@ -1220,7 +1284,7 @@ float_test! { f64: #[should_panic], f128: #[should_panic, cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let _ = Float::ONE.clamp(3.0, 1.0); } } @@ -1234,7 +1298,7 @@ float_test! { f64: #[should_panic], f128: #[should_panic, cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let _ = Float::ONE.clamp(Float::NAN, 1.0); } } @@ -1248,7 +1312,7 @@ float_test! { f64: #[should_panic], f128: #[should_panic, cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let _ = Float::ONE.clamp(3.0, Float::NAN); } } @@ -1259,7 +1323,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { use core::cmp::Ordering; const fn quiet_bit_mask() -> ::Int { @@ -1364,7 +1428,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { use core::cmp::Ordering; fn quiet_bit_mask() -> ::Int { @@ -1420,15 +1484,15 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16_math))], f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; let max: Float = Float::MAX; - assert_biteq!((1.0 as Float).recip(), 1.0); - assert_biteq!((2.0 as Float).recip(), 0.5); - assert_biteq!((-0.4 as Float).recip(), -2.5); - assert_biteq!((0.0 as Float).recip(), inf); + assert_biteq!(flt(1.0).recip(), 1.0); + assert_biteq!(flt(2.0).recip(), 0.5); + assert_biteq!(flt(-0.4).recip(), -2.5); + assert_biteq!(flt(0.0).recip(), inf); assert!(nan.recip().is_nan()); assert_biteq!(inf.recip(), 0.0); assert_biteq!(neg_inf.recip(), -0.0); @@ -1444,38 +1508,337 @@ float_test! { f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; assert_approx_eq!(Float::ONE.powi(1), Float::ONE); - assert_approx_eq!((-3.1 as Float).powi(2), 9.6100000000000005506706202140776519387, Float::POWI_APPROX); - assert_approx_eq!((5.9 as Float).powi(-2), 0.028727377190462507313100483690639638451); - assert_biteq!((8.3 as Float).powi(0), Float::ONE); + assert_approx_eq!(flt(-3.1).powi(2), 9.6100000000000005506706202140776519387, Float::POWI_APPROX); + assert_approx_eq!(flt(5.9).powi(-2), 0.028727377190462507313100483690639638451); + assert_biteq!(flt(8.3).powi(0), Float::ONE); assert!(nan.powi(2).is_nan()); assert_biteq!(inf.powi(3), inf); assert_biteq!(neg_inf.powi(2), inf); } } +float_test! { + name: powf, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_biteq!(flt(1.0).powf(1.0), 1.0); + assert_approx_eq!(flt(3.4).powf(4.5), 246.40818323761892815995637964326426756, Float::POWF_APPROX); + assert_approx_eq!(flt(2.7).powf(-3.2), 0.041652009108526178281070304373500889273, Float::POWF_APPROX); + assert_approx_eq!(flt(-3.1).powf(2.0), 9.6100000000000005506706202140776519387, Float::POWF_APPROX); + assert_approx_eq!(flt(5.9).powf(-2.0), 0.028727377190462507313100483690639638451, Float::POWF_APPROX); + assert_biteq!(flt(8.3).powf(0.0), 1.0); + assert!(nan.powf(2.0).is_nan()); + assert_biteq!(inf.powf(2.0), inf); + assert_biteq!(neg_inf.powf(3.0), neg_inf); + } +} + +float_test! { + name: exp, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_biteq!(1.0, flt(0.0).exp()); + assert_approx_eq!(consts::E, flt(1.0).exp(), Float::EXP_APPROX); + assert_approx_eq!(148.41315910257660342111558004055227962348775, flt(5.0).exp(), Float::EXP_APPROX); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + let nan: Float = Float::NAN; + assert_biteq!(inf, inf.exp()); + assert_biteq!(0.0, neg_inf.exp()); + assert!(nan.exp().is_nan()); + } +} + +float_test! { + name: exp2, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_approx_eq!(32.0, flt(5.0).exp2(), Float::EXP_APPROX); + assert_biteq!(1.0, flt(0.0).exp2()); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + let nan: Float = Float::NAN; + assert_biteq!(inf, inf.exp2()); + assert_biteq!(0.0, neg_inf.exp2()); + assert!(nan.exp2().is_nan()); + } +} + +float_test! { + name: ln, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_approx_eq!(flt(1.0).exp().ln(), 1.0, Float::LN_APPROX); + assert!(nan.ln().is_nan()); + assert_biteq!(inf.ln(), inf); + assert!(neg_inf.ln().is_nan()); + assert!(flt(-2.3).ln().is_nan()); + assert_biteq!(flt(-0.0).ln(), neg_inf); + assert_biteq!(flt(0.0).ln(), neg_inf); + assert_approx_eq!(flt(4.0).ln(), 1.3862943611198906188344642429163531366, Float::LN_APPROX); + } +} + +float_test! { + name: log, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_approx_eq!(flt(10.0).log(10.0), 1.0, Float::LOG_APPROX); + assert_approx_eq!(flt(2.3).log(3.5), 0.66485771361478710036766645911922010272, Float::LOG_APPROX); + assert_approx_eq!(flt(1.0).exp().log(flt(1.0).exp()), 1.0, Float::LOG_APPROX); + assert!(flt(1.0).log(1.0).is_nan()); + assert!(flt(1.0).log(-13.9).is_nan()); + assert!(nan.log(2.3).is_nan()); + assert_biteq!(inf.log(10.0), inf); + assert!(neg_inf.log(8.8).is_nan()); + assert!(flt(-2.3).log(0.1).is_nan()); + assert_biteq!(flt(-0.0).log(2.0), neg_inf); + assert_biteq!(flt(0.0).log(7.0), neg_inf); + } +} + +float_test! { + name: log2, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_approx_eq!(flt(10.0).log2(), 3.32192809488736234787031942948939017, Float::LOG2_APPROX); + assert_approx_eq!(flt(2.3).log2(), 1.2016338611696504130002982471978765921, Float::LOG2_APPROX); + assert_approx_eq!(flt(1.0).exp().log2(), 1.4426950408889634073599246810018921381, Float::LOG2_APPROX); + assert!(nan.log2().is_nan()); + assert_biteq!(inf.log2(), inf); + assert!(neg_inf.log2().is_nan()); + assert!(flt(-2.3).log2().is_nan()); + assert_biteq!(flt(-0.0).log2(), neg_inf); + assert_biteq!(flt(0.0).log2(), neg_inf); + } +} + +float_test! { + name: log10, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_approx_eq!(flt(10.0).log10(), 1.0, Float::LOG10_APPROX); + assert_approx_eq!(flt(2.3).log10(), 0.36172783601759284532595218865859309898, Float::LOG10_APPROX); + assert_approx_eq!(flt(1.0).exp().log10(), 0.43429448190325182765112891891660508222, Float::LOG10_APPROX); + assert_biteq!(flt(1.0).log10(), 0.0); + assert!(nan.log10().is_nan()); + assert_biteq!(inf.log10(), inf); + assert!(neg_inf.log10().is_nan()); + assert!(flt(-2.3).log10().is_nan()); + assert_biteq!(flt(-0.0).log10(), neg_inf); + assert_biteq!(flt(0.0).log10(), neg_inf); + } +} + +float_test! { + name: asinh, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_biteq!(flt(0.0).asinh(), 0.0); + assert_biteq!(flt(-0.0).asinh(), -0.0); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + let nan: Float = Float::NAN; + assert_biteq!(inf.asinh(), inf); + assert_biteq!(neg_inf.asinh(), neg_inf); + assert!(nan.asinh().is_nan()); + assert!(flt(-0.0).asinh().is_sign_negative()); + + // issue 63271 + assert_approx_eq!(flt(2.0).asinh(), 1.443635475178810342493276740273105, Float::ASINH_APPROX); + assert_approx_eq!(flt(-2.0).asinh(), -1.443635475178810342493276740273105, Float::ASINH_APPROX); + + assert_approx_eq!(flt(-200.0).asinh(), -5.991470797049389, Float::ASINH_APPROX); + + #[allow(overflowing_literals)] + if Float::MAX > flt(66000.0) { + // regression test for the catastrophic cancellation fixed in 72486 + assert_approx_eq!(flt(-67452098.07139316).asinh(), -18.720075426274544393985484294000831757220, Float::ASINH_APPROX); + } + } +} + +float_test! { + name: acosh, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_biteq!(flt(1.0).acosh(), 0.0); + assert!(flt(0.999).acosh().is_nan()); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + let nan: Float = Float::NAN; + assert_biteq!(inf.acosh(), inf); + assert!(neg_inf.acosh().is_nan()); + assert!(nan.acosh().is_nan()); + assert_approx_eq!(flt(2.0).acosh(), 1.31695789692481670862504634730796844, Float::ACOSH_APPROX); + assert_approx_eq!(flt(3.0).acosh(), 1.76274717403908605046521864995958461, Float::ACOSH_APPROX); + + #[allow(overflowing_literals)] + if Float::MAX > flt(66000.0) { + // test for low accuracy from issue 104548 + assert_approx_eq!(flt(60.0), flt(60.0).cosh().acosh(), Float::ACOSH_APPROX); + } + } +} + +float_test! { + name: atanh, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_biteq!(flt(0.0).atanh(), 0.0); + assert_biteq!(flt(-0.0).atanh(), -0.0); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_biteq!(flt(1.0).atanh(), inf); + assert_biteq!(flt(-1.0).atanh(), neg_inf); + + let nan: Float = Float::NAN; + assert!(inf.atanh().is_nan()); + assert!(neg_inf.atanh().is_nan()); + assert!(nan.atanh().is_nan()); + + assert_approx_eq!(flt(0.5).atanh(), 0.54930614433405484569762261846126285, Float::ATANH_APPROX); + assert_approx_eq!(flt(-0.5).atanh(), -0.54930614433405484569762261846126285, Float::ATANH_APPROX); + } +} + +float_test! { + name: gamma, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_approx_eq!(flt(1.0).gamma(), 1.0, Float::GAMMA_APPROX); + assert_approx_eq!(flt(2.0).gamma(), 1.0, Float::GAMMA_APPROX); + assert_approx_eq!(flt(3.0).gamma(), 2.0, Float::GAMMA_APPROX); + assert_approx_eq!(flt(4.0).gamma(), 6.0, Float::GAMMA_APPROX); + assert_approx_eq!(flt(5.0).gamma(), 24.0, Float::GAMMA_APPROX_LOOSE); + assert_approx_eq!(flt(0.5).gamma(), consts::PI.sqrt(), Float::GAMMA_APPROX); + assert_approx_eq!(flt(-0.5).gamma(), flt(-2.0) * consts::PI.sqrt(), Float::GAMMA_APPROX_LOOSE); + assert_biteq!(flt(0.0).gamma(), Float::INFINITY); + assert_biteq!(flt(-0.0).gamma(), Float::NEG_INFINITY); + assert!(flt(-1.0).gamma().is_nan()); + assert!(flt(-2.0).gamma().is_nan()); + assert!(Float::NAN.gamma().is_nan()); + assert!(Float::NEG_INFINITY.gamma().is_nan()); + assert_biteq!(Float::INFINITY.gamma(), Float::INFINITY); + + // FIXME: there is a bug in the MinGW gamma implementation that causes this to + // return NaN. https://sourceforge.net/p/mingw-w64/bugs/517/ + if !cfg!(all(target_os = "windows", target_env = "gnu", not(target_abi = "llvm"))) { + assert_biteq!(flt(1760.9).gamma(), Float::INFINITY); + } + + if ::BITS <= 64 { + assert_biteq!(flt(171.71).gamma(), Float::INFINITY); + } + } +} + +float_test! { + name: ln_gamma, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_approx_eq!(flt(1.0).ln_gamma().0, 0.0, Float::LNGAMMA_APPROX); + assert_eq!(flt(1.0).ln_gamma().1, 1); + assert_approx_eq!(flt(2.0).ln_gamma().0, 0.0, Float::LNGAMMA_APPROX); + assert_eq!(flt(2.0).ln_gamma().1, 1); + assert_approx_eq!(flt(3.0).ln_gamma().0, flt(2.0).ln(), Float::LNGAMMA_APPROX); + assert_eq!(flt(3.0).ln_gamma().1, 1); + assert_approx_eq!(flt(-0.5).ln_gamma().0, (flt(2.0) * consts::PI.sqrt()).ln(), Float::LNGAMMA_APPROX_LOOSE); + assert_eq!(flt(-0.5).ln_gamma().1, -1); + } +} + float_test! { name: to_degrees, attrs: { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { - let pi: Float = Float::PI; + test { + let pi: Float = consts::PI; let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; - assert_biteq!((0.0 as Float).to_degrees(), 0.0); - assert_approx_eq!((-5.8 as Float).to_degrees(), -332.31552117587745090765431723855668471); + assert_biteq!(flt(0.0).to_degrees(), 0.0); + assert_approx_eq!(flt(-5.8).to_degrees(), -332.31552117587745090765431723855668471); assert_approx_eq!(pi.to_degrees(), 180.0, Float::PI_TO_DEGREES_APPROX); assert!(nan.to_degrees().is_nan()); assert_biteq!(inf.to_degrees(), inf); assert_biteq!(neg_inf.to_degrees(), neg_inf); - assert_biteq!((1.0 as Float).to_degrees(), 57.2957795130823208767981548141051703); + assert_biteq!(flt(1.0).to_degrees(), 57.2957795130823208767981548141051703); } } @@ -1485,15 +1848,15 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { - let pi: Float = Float::PI; + test { + let pi: Float = consts::PI; let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; - assert_biteq!((0.0 as Float).to_radians(), 0.0); - assert_approx_eq!((154.6 as Float).to_radians(), 2.6982790235832334267135442069489767804); - assert_approx_eq!((-332.31 as Float).to_radians(), -5.7999036373023566567593094812182763013); - assert_approx_eq!((180.0 as Float).to_radians(), pi, Float::_180_TO_RADIANS_APPROX); + assert_biteq!(flt(0.0).to_radians(), 0.0); + assert_approx_eq!(flt(154.6).to_radians(), 2.6982790235832334267135442069489767804); + assert_approx_eq!(flt(-332.31).to_radians(), -5.7999036373023566567593094812182763013); + assert_approx_eq!(flt(180.0).to_radians(), pi, Float::_180_TO_RADIANS_APPROX); assert!(nan.to_radians().is_nan()); assert_biteq!(inf.to_radians(), inf); assert_biteq!(neg_inf.to_radians(), neg_inf); @@ -1506,9 +1869,9 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { - let a: Float = 123.0; - let b: Float = 456.0; + test { + let a: Float = flt(123.0); + let b: Float = flt(456.0); // Check that individual operations match their primitive counterparts. // @@ -1530,7 +1893,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { assert_biteq!(flt(1.0), Float::RAW_1); assert_biteq!(flt(12.5), Float::RAW_12_DOT_5); assert_biteq!(flt(1337.0), Float::RAW_1337); @@ -1560,12 +1923,12 @@ float_test! { f64: #[cfg_attr(all(target_os = "windows", target_env = "gnu", not(target_abi = "llvm")), ignore)], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; - assert_biteq!(flt(12.3).mul_add(4.5, 6.7), Float::MUL_ADD_RESULT); - assert_biteq!((flt(-12.3)).mul_add(-4.5, -6.7), Float::NEG_MUL_ADD_RESULT); + assert_biteq!(flt(12.3).mul_add(flt(4.5), flt(6.7)), Float::MUL_ADD_RESULT); + assert_biteq!((flt(-12.3)).mul_add(flt(-4.5), flt(-6.7)), Float::NEG_MUL_ADD_RESULT); assert_biteq!(flt(0.0).mul_add(8.9, 1.2), 1.2); assert_biteq!(flt(3.4).mul_add(-0.0, 5.6), 5.6); assert!(nan.mul_add(7.8, 9.0).is_nan()); @@ -1582,7 +1945,7 @@ float_test! { f16: #[cfg(any(miri, target_has_reliable_f16))], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { assert_biteq!(Float::from(false), Float::ZERO); assert_biteq!(Float::from(true), Float::ONE); @@ -1603,7 +1966,7 @@ float_test! { const f16: #[cfg(false)], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { assert_biteq!(Float::from(u16::MIN), Float::ZERO); assert_biteq!(Float::from(42_u16), 42.0); assert_biteq!(Float::from(u16::MAX), 65535.0); @@ -1622,7 +1985,7 @@ float_test! { const f32: #[cfg(false)], f128: #[cfg(any(miri, target_has_reliable_f128))], }, - test { + test { assert_biteq!(Float::from(u32::MIN), Float::ZERO); assert_biteq!(Float::from(42_u32), 42.0); assert_biteq!(Float::from(u32::MAX), 4294967295.0); @@ -1632,6 +1995,93 @@ float_test! { } } +// Test the `float_exact_integer_constants` feature +float_test! { + name: max_exact_integer_constant, + attrs: { + f16: #[cfg(any(miri, target_has_reliable_f16))], + f128: #[cfg(any(miri, target_has_reliable_f128))], + }, + test { + // The maximum integer that converts to a unique floating point + // value. + const MAX_EXACT_INTEGER: ::SInt = Float::MAX_EXACT_INTEGER; + + let max_minus_one = (MAX_EXACT_INTEGER - 1) as Float as ::SInt; + let max_plus_one = (MAX_EXACT_INTEGER + 1) as Float as ::SInt; + let max_plus_two = (MAX_EXACT_INTEGER + 2) as Float as ::SInt; + + // This does an extra round trip back to float for the second operand in + // order to print the results if there is a mismatch + assert_biteq!((MAX_EXACT_INTEGER - 1) as Float, max_minus_one as Float); + assert_biteq!(MAX_EXACT_INTEGER as Float, MAX_EXACT_INTEGER as Float as ::SInt as Float); + assert_biteq!((MAX_EXACT_INTEGER + 1) as Float, max_plus_one as Float); + // The first non-unique conversion, where `max_plus_two` roundtrips to + // `max_plus_one` + assert_biteq!((MAX_EXACT_INTEGER + 1) as Float, (MAX_EXACT_INTEGER + 2) as Float); + assert_biteq!((MAX_EXACT_INTEGER + 2) as Float, max_plus_one as Float); + assert_biteq!((MAX_EXACT_INTEGER + 2) as Float, max_plus_two as Float); + + // Lossless roundtrips, for integers + assert!(MAX_EXACT_INTEGER - 1 == max_minus_one); + assert!(MAX_EXACT_INTEGER == MAX_EXACT_INTEGER as Float as ::SInt); + assert!(MAX_EXACT_INTEGER + 1 == max_plus_one); + // The first non-unique conversion, where `max_plus_two` roundtrips to + // one less than the starting value + assert!(MAX_EXACT_INTEGER + 2 != max_plus_two); + + // max-1 | max+0 | max+1 | max+2 + // After roundtripping, +1 and +2 will equal each other + assert!(max_minus_one != MAX_EXACT_INTEGER); + assert!(MAX_EXACT_INTEGER != max_plus_one); + assert!(max_plus_one == max_plus_two); + } +} + +float_test! { + name: min_exact_integer_constant, + attrs: { + f16: #[cfg(any(miri, target_has_reliable_f16))], + f128: #[cfg(any(miri, target_has_reliable_f128))], + }, + test { + // The minimum integer that converts to a unique floating point + // value. + const MIN_EXACT_INTEGER: ::SInt = Float::MIN_EXACT_INTEGER; + + // Same logic as the `max` test, but we work our way leftward + // across the number line from (min_exact + 1) to (min_exact - 2). + let min_plus_one = (MIN_EXACT_INTEGER + 1) as Float as ::SInt; + let min_minus_one = (MIN_EXACT_INTEGER - 1) as Float as ::SInt; + let min_minus_two = (MIN_EXACT_INTEGER - 2) as Float as ::SInt; + + // This does an extra round trip back to float for the second operand in + // order to print the results if there is a mismatch + assert_biteq!((MIN_EXACT_INTEGER + 1) as Float, min_plus_one as Float); + assert_biteq!(MIN_EXACT_INTEGER as Float, MIN_EXACT_INTEGER as Float as ::SInt as Float); + assert_biteq!((MIN_EXACT_INTEGER - 1) as Float, min_minus_one as Float); + // The first non-unique conversion, which roundtrips to one + // greater than the starting value. + assert_biteq!((MIN_EXACT_INTEGER - 1) as Float, (MIN_EXACT_INTEGER - 2) as Float); + assert_biteq!((MIN_EXACT_INTEGER - 2) as Float, min_minus_one as Float); + assert_biteq!((MIN_EXACT_INTEGER - 2) as Float, min_minus_two as Float); + + // Lossless roundtrips, for integers + assert!(MIN_EXACT_INTEGER + 1 == min_plus_one); + assert!(MIN_EXACT_INTEGER == MIN_EXACT_INTEGER as Float as ::SInt); + assert!(MIN_EXACT_INTEGER - 1 == min_minus_one); + // The first non-unique conversion, which roundtrips to one + // greater than the starting value. + assert!(MIN_EXACT_INTEGER - 2 != min_minus_two); + + // min-2 | min-1 | min | min+1 + // After roundtripping, -2 and -1 will equal each other. + assert!(min_plus_one != MIN_EXACT_INTEGER); + assert!(MIN_EXACT_INTEGER != min_minus_one); + assert!(min_minus_one == min_minus_two); + } +} + // FIXME(f128): Uncomment and adapt these tests once the From<{u64,i64}> impls are added. // float_test! { // name: from_u64_i64, @@ -1641,7 +2091,7 @@ float_test! { // f64: #[cfg(false)], // f128: #[cfg(any(miri, target_has_reliable_f128))], // }, -// test { +// test { // assert_biteq!(Float::from(u64::MIN), Float::ZERO); // assert_biteq!(Float::from(42_u64), 42.0); // assert_biteq!(Float::from(u64::MAX), 18446744073709551615.0); @@ -1650,3 +2100,30 @@ float_test! { // assert_biteq!(Float::from(i64::MAX), 9223372036854775807.0); // } // } + +float_test! { + name: real_consts, + attrs: { + // FIXME(f16_f128): add math tests when available + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + let pi: Float = consts::PI; + assert_approx_eq!(consts::FRAC_PI_2, pi / 2.0); + assert_approx_eq!(consts::FRAC_PI_3, pi / 3.0, Float::APPROX); + assert_approx_eq!(consts::FRAC_PI_4, pi / 4.0); + assert_approx_eq!(consts::FRAC_PI_6, pi / 6.0); + assert_approx_eq!(consts::FRAC_PI_8, pi / 8.0); + assert_approx_eq!(consts::FRAC_1_PI, 1.0 / pi); + assert_approx_eq!(consts::FRAC_2_PI, 2.0 / pi); + assert_approx_eq!(consts::FRAC_2_SQRT_PI, 2.0 / pi.sqrt()); + assert_approx_eq!(consts::SQRT_2, flt(2.0).sqrt()); + assert_approx_eq!(consts::FRAC_1_SQRT_2, 1.0 / flt(2.0).sqrt()); + assert_approx_eq!(consts::LOG2_E, consts::E.log2()); + assert_approx_eq!(consts::LOG10_E, consts::E.log10()); + assert_approx_eq!(consts::LN_2, flt(2.0).ln()); + assert_approx_eq!(consts::LN_10, flt(10.0).ln(), Float::APPROX); + } +} diff --git a/coretests/tests/num/flt2dec/estimator.rs b/coretests/tests/num/flt2dec/estimator.rs index f53282611f686..1e24048fa515a 100644 --- a/coretests/tests/num/flt2dec/estimator.rs +++ b/coretests/tests/num/flt2dec/estimator.rs @@ -1,4 +1,4 @@ -use core::num::flt2dec::estimator::*; +use core::num::imp::flt2dec::estimator::*; use crate::num::ldexp_f64; diff --git a/coretests/tests/num/flt2dec/mod.rs b/coretests/tests/num/flt2dec/mod.rs index be1bc6ac460ba..4888d9d1de06a 100644 --- a/coretests/tests/num/flt2dec/mod.rs +++ b/coretests/tests/num/flt2dec/mod.rs @@ -1,11 +1,13 @@ -use core::num::flt2dec::{ +use core::num::imp::flt2dec::{ DecodableFloat, Decoded, FullDecoded, MAX_SIG_DIGITS, Sign, decode, round_up, to_exact_exp_str, to_exact_fixed_str, to_shortest_exp_str, to_shortest_str, }; -use core::num::fmt::{Formatted, Part}; +use core::num::imp::fmt::{Formatted, Part}; use std::mem::MaybeUninit; use std::{fmt, str}; +use Sign::{Minus, MinusPlus}; + use crate::num::{ldexp_f32, ldexp_f64}; mod estimator; @@ -562,8 +564,6 @@ pub fn to_shortest_str_test(mut f_: F) where F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit]) -> (&'a [u8], i16), { - use core::num::flt2dec::Sign::*; - fn to_string(f: &mut F, v: T, sign: Sign, frac_digits: usize) -> String where T: DecodableFloat, @@ -672,8 +672,6 @@ pub fn to_shortest_exp_str_test(mut f_: F) where F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit]) -> (&'a [u8], i16), { - use core::num::flt2dec::Sign::*; - fn to_string(f: &mut F, v: T, sign: Sign, exp_bounds: (i16, i16), upper: bool) -> String where T: DecodableFloat, @@ -789,8 +787,6 @@ pub fn to_exact_exp_str_test(mut f_: F) where F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit], i16) -> (&'a [u8], i16), { - use core::num::flt2dec::Sign::*; - fn to_string(f: &mut F, v: T, sign: Sign, ndigits: usize, upper: bool) -> String where T: DecodableFloat, @@ -1065,8 +1061,6 @@ pub fn to_exact_fixed_str_test(mut f_: F) where F: for<'a> FnMut(&Decoded, &'a mut [MaybeUninit], i16) -> (&'a [u8], i16), { - use core::num::flt2dec::Sign::*; - fn to_string(f: &mut F, v: T, sign: Sign, frac_digits: usize) -> String where T: DecodableFloat, diff --git a/coretests/tests/num/flt2dec/random.rs b/coretests/tests/num/flt2dec/random.rs index 7386139aaced5..e47aa6d37a804 100644 --- a/coretests/tests/num/flt2dec/random.rs +++ b/coretests/tests/num/flt2dec/random.rs @@ -1,10 +1,11 @@ #![cfg(not(target_arch = "wasm32"))] -use core::num::flt2dec::strategy::grisu::{format_exact_opt, format_shortest_opt}; -use core::num::flt2dec::{DecodableFloat, Decoded, FullDecoded, MAX_SIG_DIGITS, decode}; +use core::num::imp::flt2dec; use std::mem::MaybeUninit; use std::str; +use flt2dec::strategy::grisu::{format_exact_opt, format_shortest_opt}; +use flt2dec::{DecodableFloat, Decoded, FullDecoded, MAX_SIG_DIGITS, decode}; use rand::distr::{Distribution, Uniform}; pub fn decode_finite(v: T) -> Decoded { @@ -159,7 +160,7 @@ where #[test] fn shortest_random_equivalence_test() { - use core::num::flt2dec::strategy::dragon::format_shortest as fallback; + use flt2dec::strategy::dragon::format_shortest as fallback; // Miri is too slow let n = if cfg!(miri) { 10 } else { 10_000 }; @@ -174,7 +175,7 @@ fn shortest_random_equivalence_test() { #[cfg(target_has_reliable_f16)] fn shortest_f16_exhaustive_equivalence_test() { // see the f32 version - use core::num::flt2dec::strategy::dragon::format_shortest as fallback; + use flt2dec::strategy::dragon::format_shortest as fallback; f16_exhaustive_equivalence_test(format_shortest_opt, fallback, MAX_SIG_DIGITS); } @@ -188,7 +189,7 @@ fn shortest_f32_exhaustive_equivalence_test() { // with `--nocapture` (and plenty of time and appropriate rustc flags), this should print: // `done, ignored=17643158 passed=2121451881 failed=0`. - use core::num::flt2dec::strategy::dragon::format_shortest as fallback; + use flt2dec::strategy::dragon::format_shortest as fallback; f32_exhaustive_equivalence_test(format_shortest_opt, fallback, MAX_SIG_DIGITS); } @@ -197,14 +198,14 @@ fn shortest_f32_exhaustive_equivalence_test() { fn shortest_f64_hard_random_equivalence_test() { // this again probably has to use appropriate rustc flags. - use core::num::flt2dec::strategy::dragon::format_shortest as fallback; + use flt2dec::strategy::dragon::format_shortest as fallback; f64_random_equivalence_test(format_shortest_opt, fallback, MAX_SIG_DIGITS, 100_000_000); } #[test] #[cfg(target_has_reliable_f16)] fn exact_f16_random_equivalence_test() { - use core::num::flt2dec::strategy::dragon::format_exact as fallback; + use flt2dec::strategy::dragon::format_exact as fallback; // Miri is too slow let n = if cfg!(miri) { 3 } else { 1_000 }; @@ -220,7 +221,7 @@ fn exact_f16_random_equivalence_test() { #[test] fn exact_f32_random_equivalence_test() { - use core::num::flt2dec::strategy::dragon::format_exact as fallback; + use flt2dec::strategy::dragon::format_exact as fallback; // Miri is too slow let n = if cfg!(miri) { 3 } else { 1_000 }; @@ -236,7 +237,7 @@ fn exact_f32_random_equivalence_test() { #[test] fn exact_f64_random_equivalence_test() { - use core::num::flt2dec::strategy::dragon::format_exact as fallback; + use flt2dec::strategy::dragon::format_exact as fallback; // Miri is too slow let n = if cfg!(miri) { 2 } else { 1_000 }; diff --git a/coretests/tests/num/flt2dec/strategy/dragon.rs b/coretests/tests/num/flt2dec/strategy/dragon.rs index 43bb6024f9cee..886f50064a503 100644 --- a/coretests/tests/num/flt2dec/strategy/dragon.rs +++ b/coretests/tests/num/flt2dec/strategy/dragon.rs @@ -1,5 +1,5 @@ -use core::num::bignum::Big32x40 as Big; -use core::num::flt2dec::strategy::dragon::*; +use core::num::imp::bignum::Big32x40 as Big; +use core::num::imp::flt2dec::strategy::dragon::*; use super::super::*; diff --git a/coretests/tests/num/flt2dec/strategy/grisu.rs b/coretests/tests/num/flt2dec/strategy/grisu.rs index 117191e0c8fdb..8350480333380 100644 --- a/coretests/tests/num/flt2dec/strategy/grisu.rs +++ b/coretests/tests/num/flt2dec/strategy/grisu.rs @@ -1,4 +1,4 @@ -use core::num::flt2dec::strategy::grisu::*; +use core::num::imp::flt2dec::strategy::grisu::*; use super::super::*; diff --git a/coretests/tests/num/ieee754.rs b/coretests/tests/num/ieee754.rs deleted file mode 100644 index b0f6a7545aa93..0000000000000 --- a/coretests/tests/num/ieee754.rs +++ /dev/null @@ -1,158 +0,0 @@ -//! IEEE 754 floating point compliance tests -//! -//! To understand IEEE 754's requirements on a programming language, one must understand that the -//! requirements of IEEE 754 rest on the total programming environment, and not entirely on any -//! one component. That means the hardware, language, and even libraries are considered part of -//! conforming floating point support in a programming environment. -//! -//! A programming language's duty, accordingly, is: -//! 1. offer access to the hardware where the hardware offers support -//! 2. provide operations that fulfill the remaining requirements of the standard -//! 3. provide the ability to write additional software that can fulfill those requirements -//! -//! This may be fulfilled in any combination that the language sees fit. However, to claim that -//! a language supports IEEE 754 is to suggest that it has fulfilled requirements 1 and 2, without -//! deferring minimum requirements to libraries. This is because support for IEEE 754 is defined -//! as complete support for at least one specified floating point type as an "arithmetic" and -//! "interchange" format, plus specified type conversions to "external character sequences" and -//! integer types. -//! -//! For our purposes, -//! "interchange format" => f32, f64 -//! "arithmetic format" => f32, f64, and any "soft floats" -//! "external character sequence" => str from any float -//! "integer format" => {i,u}{8,16,32,64,128} -//! -//! None of these tests are against Rust's own implementation. They are only tests against the -//! standard. That is why they accept wildly diverse inputs or may seem to duplicate other tests. -//! Please consider this carefully when adding, removing, or reorganizing these tests. They are -//! here so that it is clear what tests are required by the standard and what can be changed. - -use ::core::str::FromStr; - -// IEEE 754 for many tests is applied to specific bit patterns. -// These generally are not applicable to NaN, however. -macro_rules! assert_biteq { - ($lhs:expr, $rhs:expr) => { - assert_eq!($lhs.to_bits(), $rhs.to_bits()) - }; -} - -// ToString uses the default fmt::Display impl without special concerns, and bypasses other parts -// of the formatting infrastructure, which makes it ideal for testing here. -macro_rules! roundtrip { - ($f:expr => $t:ty) => { - ($f).to_string().parse::<$t>().unwrap() - }; -} - -macro_rules! assert_floats_roundtrip { - ($f:ident) => { - assert_biteq!(f32::$f, roundtrip!(f32::$f => f32)); - assert_biteq!(f64::$f, roundtrip!(f64::$f => f64)); - }; - ($f:expr) => { - assert_biteq!($f as f32, roundtrip!($f => f32)); - assert_biteq!($f as f64, roundtrip!($f => f64)); - } -} - -macro_rules! assert_floats_bitne { - ($lhs:ident, $rhs:ident) => { - assert_ne!(f32::$lhs.to_bits(), f32::$rhs.to_bits()); - assert_ne!(f64::$lhs.to_bits(), f64::$rhs.to_bits()); - }; - ($lhs:expr, $rhs:expr) => { - assert_ne!(f32::to_bits($lhs), f32::to_bits($rhs)); - assert_ne!(f64::to_bits($lhs), f64::to_bits($rhs)); - }; -} - -// We must preserve signs on all numbers. That includes zero. -// -0 and 0 are == normally, so test bit equality. -#[test] -fn preserve_signed_zero() { - assert_floats_roundtrip!(-0.0); - assert_floats_roundtrip!(0.0); - assert_floats_bitne!(0.0, -0.0); -} - -#[test] -fn preserve_signed_infinity() { - assert_floats_roundtrip!(INFINITY); - assert_floats_roundtrip!(NEG_INFINITY); - assert_floats_bitne!(INFINITY, NEG_INFINITY); -} - -#[test] -fn infinity_to_str() { - assert!(match f32::INFINITY.to_string().to_lowercase().as_str() { - "+infinity" | "infinity" => true, - "+inf" | "inf" => true, - _ => false, - }); - assert!( - match f64::INFINITY.to_string().to_lowercase().as_str() { - "+infinity" | "infinity" => true, - "+inf" | "inf" => true, - _ => false, - }, - "Infinity must write to a string as some casing of inf or infinity, with an optional +." - ); -} - -#[test] -fn neg_infinity_to_str() { - assert!(match f32::NEG_INFINITY.to_string().to_lowercase().as_str() { - "-infinity" | "-inf" => true, - _ => false, - }); - assert!( - match f64::NEG_INFINITY.to_string().to_lowercase().as_str() { - "-infinity" | "-inf" => true, - _ => false, - }, - "Negative Infinity must write to a string as some casing of -inf or -infinity" - ) -} - -#[test] -fn nan_to_str() { - assert!( - match f32::NAN.to_string().to_lowercase().as_str() { - "nan" | "+nan" | "-nan" => true, - _ => false, - }, - "NaNs must write to a string as some casing of nan." - ) -} - -// "+"?("inf"|"infinity") in any case => Infinity -#[test] -fn infinity_from_str() { - assert_biteq!(f32::INFINITY, f32::from_str("infinity").unwrap()); - assert_biteq!(f32::INFINITY, f32::from_str("inf").unwrap()); - assert_biteq!(f32::INFINITY, f32::from_str("+infinity").unwrap()); - assert_biteq!(f32::INFINITY, f32::from_str("+inf").unwrap()); - // yes! this means you are weLcOmE tO mY iNfInItElY tWiStEd MiNd - assert_biteq!(f32::INFINITY, f32::from_str("+iNfInItY").unwrap()); -} - -// "-inf"|"-infinity" in any case => Negative Infinity -#[test] -fn neg_infinity_from_str() { - assert_biteq!(f32::NEG_INFINITY, f32::from_str("-infinity").unwrap()); - assert_biteq!(f32::NEG_INFINITY, f32::from_str("-inf").unwrap()); - assert_biteq!(f32::NEG_INFINITY, f32::from_str("-INF").unwrap()); - assert_biteq!(f32::NEG_INFINITY, f32::from_str("-INFinity").unwrap()); -} - -// ("+"|"-"")?"s"?"nan" in any case => qNaN -#[test] -fn qnan_from_str() { - assert!("nan".parse::().unwrap().is_nan()); - assert!("-nan".parse::().unwrap().is_nan()); - assert!("+nan".parse::().unwrap().is_nan()); - assert!("+NAN".parse::().unwrap().is_nan()); - assert!("-NaN".parse::().unwrap().is_nan()); -} diff --git a/coretests/tests/num/int_macros.rs b/coretests/tests/num/int_macros.rs index 37336f49ef1b6..2b641f595eba4 100644 --- a/coretests/tests/num/int_macros.rs +++ b/coretests/tests/num/int_macros.rs @@ -2,7 +2,8 @@ macro_rules! int_module { ($T:ident, $U:ident) => { use core::num::ParseIntError; use core::ops::{BitAnd, BitOr, BitXor, Not, Shl, Shr}; - use core::$T::*; + const MAX: $T = $T::MAX; + const MIN: $T = $T::MIN; const UMAX: $U = $U::MAX; diff --git a/coretests/tests/num/mod.rs b/coretests/tests/num/mod.rs index 913f766ec1683..e0214c6ae6868 100644 --- a/coretests/tests/num/mod.rs +++ b/coretests/tests/num/mod.rs @@ -22,11 +22,13 @@ mod u64; mod u8; mod bignum; +mod carryless_mul; mod const_from; mod dec2flt; +mod float_ieee754_flt2dec_dec2flt; mod float_iter_sum_identity; +mod floats; mod flt2dec; -mod ieee754; mod int_log; mod int_sqrt; mod midpoint; @@ -35,6 +37,8 @@ mod niche_types; mod ops; mod wrapping; +use floats::{assert_biteq, float_test}; + /// Adds the attribute to all items in the block. macro_rules! cfg_block { ($(#[$attr:meta]{$($it:item)*})*) => {$($( diff --git a/coretests/tests/num/uint_macros.rs b/coretests/tests/num/uint_macros.rs index 7c4fb22599c03..8dfa0924bd369 100644 --- a/coretests/tests/num/uint_macros.rs +++ b/coretests/tests/num/uint_macros.rs @@ -2,15 +2,14 @@ macro_rules! uint_module { ($T:ident) => { use core::num::ParseIntError; use core::ops::{BitAnd, BitOr, BitXor, Not, Shl, Shr}; - use core::$T::*; use crate::num; #[test] fn test_overflows() { - assert!(MAX > 0); - assert!(MIN <= 0); - assert!((MIN + MAX).wrapping_add(1) == 0); + assert!($T::MAX > 0); + assert!($T::MIN <= 0); + assert!(($T::MIN + $T::MAX).wrapping_add(1) == 0); } #[test] @@ -25,7 +24,7 @@ macro_rules! uint_module { assert!(0b0110 as $T == (0b1100 as $T).bitxor(0b1010 as $T)); assert!(0b1110 as $T == (0b0111 as $T).shl(1)); assert!(0b0111 as $T == (0b1110 as $T).shr(1)); - assert!(MAX - (0b1011 as $T) == (0b1011 as $T).not()); + assert!($T::MAX - (0b1011 as $T) == (0b1011 as $T).not()); } const A: $T = 0b0101100; @@ -117,6 +116,13 @@ macro_rules! uint_module { assert_eq_const_safe!($T: <$T>::funnel_shr(_1, _1, 4), <$T>::rotate_right(_1, 4)); } + fn test_carryless_mul() { + assert_eq_const_safe!($T: <$T>::carryless_mul(0, 0), 0); + assert_eq_const_safe!($T: <$T>::carryless_mul(1, 1), 1); + + assert_eq_const_safe!($T: <$T>::carryless_mul(0b0100, 2), 0b1000); + } + fn test_swap_bytes() { assert_eq_const_safe!($T: A.swap_bytes().swap_bytes(), A); assert_eq_const_safe!($T: B.swap_bytes().swap_bytes(), B); @@ -354,7 +360,7 @@ macro_rules! uint_module { assert_eq_const_safe!($T: R.wrapping_pow(2), 1 as $T); assert_eq_const_safe!(Option<$T>: R.checked_pow(2), None); assert_eq_const_safe!(($T, bool): R.overflowing_pow(2), (1 as $T, true)); - assert_eq_const_safe!($T: R.saturating_pow(2), MAX); + assert_eq_const_safe!($T: R.saturating_pow(2), $T::MAX); } } @@ -461,14 +467,14 @@ macro_rules! uint_module { fn test_next_multiple_of() { assert_eq_const_safe!($T: (16 as $T).next_multiple_of(8), 16); assert_eq_const_safe!($T: (23 as $T).next_multiple_of(8), 24); - assert_eq_const_safe!($T: MAX.next_multiple_of(1), MAX); + assert_eq_const_safe!($T: $T::MAX.next_multiple_of(1), $T::MAX); } fn test_checked_next_multiple_of() { assert_eq_const_safe!(Option<$T>: (16 as $T).checked_next_multiple_of(8), Some(16)); assert_eq_const_safe!(Option<$T>: (23 as $T).checked_next_multiple_of(8), Some(24)); assert_eq_const_safe!(Option<$T>: (1 as $T).checked_next_multiple_of(0), None); - assert_eq_const_safe!(Option<$T>: MAX.checked_next_multiple_of(2), None); + assert_eq_const_safe!(Option<$T>: $T::MAX.checked_next_multiple_of(2), None); } fn test_is_next_multiple_of() { diff --git a/coretests/tests/option.rs b/coretests/tests/option.rs index fc0f82ad6bb38..3df7afb4f3bea 100644 --- a/coretests/tests/option.rs +++ b/coretests/tests/option.rs @@ -495,6 +495,30 @@ const fn option_const_mut() { */ } +/// Test that `Option::get_or_insert_default` is usable in const contexts, including with types that +/// do not satisfy `T: const Destruct`. +#[test] +fn const_get_or_insert_default() { + const OPT_DEFAULT: Option> = { + let mut x = None; + x.get_or_insert_default(); + x + }; + assert!(OPT_DEFAULT.is_some()); +} + +/// Test that `Option::get_or_insert_with` is usable in const contexts, including with types that +/// do not satisfy `T: const Destruct`. +#[test] +fn const_get_or_insert_with() { + const OPT_WITH: Option> = { + let mut x = None; + x.get_or_insert_with(Vec::new); + x + }; + assert!(OPT_WITH.is_some()); +} + #[test] fn test_unwrap_drop() { struct Dtor<'a> { diff --git a/coretests/tests/pin.rs b/coretests/tests/pin.rs index b3fb06e710d44..37a729ae4f1c4 100644 --- a/coretests/tests/pin.rs +++ b/coretests/tests/pin.rs @@ -45,22 +45,6 @@ mod pin_coerce_unsized { pub trait MyTrait {} impl MyTrait for String {} - // These Pins should continue to compile. - // Do note that these instances of Pin types cannot be used - // meaningfully because all methods require a Deref/DerefMut - // bounds on the pointer type and Cell, RefCell and UnsafeCell - // do not implement Deref/DerefMut. - - pub fn cell(arg: Pin>>) -> Pin>> { - arg - } - pub fn ref_cell(arg: Pin>>) -> Pin>> { - arg - } - pub fn unsafe_cell(arg: Pin>>) -> Pin>> { - arg - } - // These sensible Pin coercions are possible. pub fn pin_mut_ref(arg: Pin<&mut String>) -> Pin<&mut dyn MyTrait> { arg @@ -68,15 +52,6 @@ mod pin_coerce_unsized { pub fn pin_ref(arg: Pin<&String>) -> Pin<&dyn MyTrait> { arg } - pub fn pin_ptr(arg: Pin<*const String>) -> Pin<*const dyn MyTrait> { - arg - } - pub fn pin_ptr_mut(arg: Pin<*mut String>) -> Pin<*mut dyn MyTrait> { - arg - } - pub fn pin_non_null(arg: Pin>) -> Pin> { - arg - } pub fn nesting_pins(arg: Pin>) -> Pin> { arg } diff --git a/coretests/tests/time.rs b/coretests/tests/time.rs index ff80ff680943f..5877f662b7ddc 100644 --- a/coretests/tests/time.rs +++ b/coretests/tests/time.rs @@ -598,3 +598,100 @@ fn from_neg_zero() { assert_eq!(Duration::from_secs_f32(-0.0), Duration::ZERO); assert_eq!(Duration::from_secs_f64(-0.0), Duration::ZERO); } + +#[test] +#[should_panic(expected = "value is either too big or NaN")] +fn duration_fp_mul_nan() { + let _ = Duration::NANOSECOND.mul_f64(f64::NAN); +} + +#[test] +#[should_panic(expected = "value is either too big or NaN")] +fn duration_fp_mul_posinfinity() { + let _ = Duration::NANOSECOND.mul_f64(f64::INFINITY); +} + +#[test] +#[should_panic(expected = "value is negative")] +fn duration_fp_mul_neginfinity() { + let _ = Duration::NANOSECOND.mul_f64(f64::NEG_INFINITY); +} + +#[test] +#[should_panic(expected = "value is either too big or NaN")] +fn duration_fp_div_nan() { + let _ = Duration::NANOSECOND.div_f64(f64::NAN); +} + +#[test] +#[should_panic(expected = "value is either too big or NaN")] +fn duration_fp_div_poszero() { + let _ = Duration::NANOSECOND.div_f64(0.0); +} + +#[test] +#[should_panic(expected = "value is negative")] +fn duration_fp_div_negzero() { + let _ = Duration::NANOSECOND.div_f64(-0.0); +} + +#[test] +#[should_panic(expected = "value is negative")] +fn duration_fp_div_negative() { + let _ = Duration::NANOSECOND.div_f64(f64::MIN); +} + +const TOO_LARGE_FACTOR: f64 = Duration::MAX.as_nanos() as f64; +const TOO_LARGE_DIVISOR: f64 = (Duration::MAX.as_secs_f64() * 2e9).next_up(); +const SMALLEST_DIVISOR: f64 = (TOO_LARGE_DIVISOR.recip() * 2.0).next_up().next_up(); +const SMALLEST_FACTOR: f64 = TOO_LARGE_FACTOR.recip() / 2.0; +const SMALLEST_NEGFACTOR: f64 = (0.0f64.next_down() * 0.5e9).next_up(); + +#[test] +fn duration_fp_boundaries() { + const DURATION_BITS: u32 = Duration::MAX.as_nanos().ilog2() + 1; + const PRECISION: u32 = DURATION_BITS - f64::MANTISSA_DIGITS + 1; + + assert_eq!(Duration::MAX.mul_f64(0.0), Duration::ZERO); + assert_eq!(Duration::MAX.mul_f64(-0.0), Duration::ZERO); + + assert_eq!(Duration::MAX.mul_f64(SMALLEST_FACTOR), Duration::NANOSECOND); + assert_eq!(Duration::MAX.mul_f64(SMALLEST_FACTOR.next_down()), Duration::ZERO); + + assert_eq!(Duration::MAX.div_f64(TOO_LARGE_DIVISOR), Duration::ZERO); + assert_eq!(Duration::MAX.div_f64(TOO_LARGE_DIVISOR.next_down()), Duration::NANOSECOND); + + assert_eq!(Duration::MAX.div_f64(f64::INFINITY), Duration::ZERO); + assert_eq!(Duration::MAX.div_f64(f64::NEG_INFINITY), Duration::ZERO); + + // the following assertions pair with the subsequent (`should_panic`) tests + + assert_eq!(Duration::NANOSECOND.mul_f64(SMALLEST_NEGFACTOR), Duration::ZERO); + + assert!( + Duration::MAX - Duration::NANOSECOND.mul_f64(TOO_LARGE_FACTOR.next_down()) + < Duration::from_nanos(1 << PRECISION) + ); + assert!( + Duration::MAX - Duration::NANOSECOND.div_f64(SMALLEST_DIVISOR) + < Duration::from_nanos(1 << PRECISION) + ); +} + +#[test] +#[should_panic(expected = "value is negative")] +fn duration_fp_mul_negative() { + let _ = Duration::NANOSECOND.mul_f64(SMALLEST_NEGFACTOR.next_down()); +} + +#[test] +#[should_panic(expected = "value is either too big or NaN")] +fn duration_fp_mul_overflow() { + let _ = Duration::NANOSECOND.mul_f64(TOO_LARGE_FACTOR); +} + +#[test] +#[should_panic(expected = "value is either too big or NaN")] +fn duration_fp_div_overflow() { + let _ = Duration::NANOSECOND.div_f64(SMALLEST_DIVISOR.next_down()); +} diff --git a/coretests/tests/unicode.rs b/coretests/tests/unicode.rs index bbace0ef66ca3..a8a221db8f955 100644 --- a/coretests/tests/unicode.rs +++ b/coretests/tests/unicode.rs @@ -1,5 +1,126 @@ +use core::unicode::unicode_data; +use std::ops::RangeInclusive; + +mod test_data; + #[test] pub fn version() { let (major, _minor, _update) = core::char::UNICODE_VERSION; assert!(major >= 10); } + +#[track_caller] +fn test_boolean_property(ranges: &[RangeInclusive], lookup: fn(char) -> bool) { + let mut start = '\u{80}'; + for range in ranges { + for c in start..*range.start() { + assert!(!lookup(c), "{c:?}"); + } + for c in range.clone() { + assert!(lookup(c), "{c:?}"); + } + start = char::from_u32(*range.end() as u32 + 1).unwrap(); + } + for c in start..=char::MAX { + assert!(!lookup(c), "{c:?}"); + } +} + +#[track_caller] +fn test_case_mapping( + ranges: &[(char, [char; 3])], + lookup: fn(char) -> [char; 3], + fallback: fn(char) -> [char; 3], +) { + let mut start = '\u{80}'; + for &(key, val) in ranges { + for c in start..key { + assert_eq!(lookup(c), fallback(c), "{c:?}"); + } + assert_eq!(lookup(key), val, "{key:?}"); + start = char::from_u32(key as u32 + 1).unwrap(); + } + for c in start..=char::MAX { + assert_eq!(lookup(c), fallback(c), "{c:?}"); + } +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn alphabetic() { + test_boolean_property(test_data::ALPHABETIC, unicode_data::alphabetic::lookup); + test_boolean_property(test_data::ALPHABETIC, char::is_alphabetic); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn case_ignorable() { + test_boolean_property(test_data::CASE_IGNORABLE, unicode_data::case_ignorable::lookup); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn cased() { + test_boolean_property(test_data::CASED, unicode_data::cased::lookup); + test_boolean_property(test_data::CASED, char::is_cased); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn grapheme_extend() { + test_boolean_property(test_data::GRAPHEME_EXTEND, unicode_data::grapheme_extend::lookup); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn lowercase() { + test_boolean_property(test_data::LOWERCASE, unicode_data::lowercase::lookup); + test_boolean_property(test_data::LOWERCASE, char::is_lowercase); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn n() { + test_boolean_property(test_data::N, unicode_data::n::lookup); + test_boolean_property(test_data::N, char::is_numeric); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn uppercase() { + test_boolean_property(test_data::UPPERCASE, unicode_data::uppercase::lookup); + test_boolean_property(test_data::UPPERCASE, char::is_uppercase); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn white_space() { + test_boolean_property(test_data::WHITE_SPACE, unicode_data::white_space::lookup); + test_boolean_property(test_data::WHITE_SPACE, char::is_whitespace); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn to_lowercase() { + test_case_mapping(test_data::TO_LOWER, unicode_data::conversions::to_lower, |c| { + [c, '\0', '\0'] + }); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn to_uppercase() { + test_case_mapping(test_data::TO_UPPER, unicode_data::conversions::to_upper, |c| { + [c, '\0', '\0'] + }); +} + +#[test] +#[cfg_attr(miri, ignore)] // Miri is too slow +fn to_titlecase() { + test_case_mapping( + test_data::TO_TITLE, + unicode_data::conversions::to_title, + unicode_data::conversions::to_upper, + ); +} diff --git a/coretests/tests/unicode/test_data.rs b/coretests/tests/unicode/test_data.rs new file mode 100644 index 0000000000000..3071aedcae07a --- /dev/null +++ b/coretests/tests/unicode/test_data.rs @@ -0,0 +1,2980 @@ +//! This file is generated by `./x run src/tools/unicode-table-generator`; do not edit manually! +// ignore-tidy-filelength + +use std::ops::RangeInclusive; + +#[rustfmt::skip] +pub(super) static ALPHABETIC: &[RangeInclusive; 759] = &[ + '\u{aa}'..='\u{aa}', '\u{b5}'..='\u{b5}', '\u{ba}'..='\u{ba}', '\u{c0}'..='\u{d6}', + '\u{d8}'..='\u{f6}', '\u{f8}'..='\u{2c1}', '\u{2c6}'..='\u{2d1}', '\u{2e0}'..='\u{2e4}', + '\u{2ec}'..='\u{2ec}', '\u{2ee}'..='\u{2ee}', '\u{345}'..='\u{345}', '\u{363}'..='\u{374}', + '\u{376}'..='\u{377}', '\u{37a}'..='\u{37d}', '\u{37f}'..='\u{37f}', '\u{386}'..='\u{386}', + '\u{388}'..='\u{38a}', '\u{38c}'..='\u{38c}', '\u{38e}'..='\u{3a1}', '\u{3a3}'..='\u{3f5}', + '\u{3f7}'..='\u{481}', '\u{48a}'..='\u{52f}', '\u{531}'..='\u{556}', '\u{559}'..='\u{559}', + '\u{560}'..='\u{588}', '\u{5b0}'..='\u{5bd}', '\u{5bf}'..='\u{5bf}', '\u{5c1}'..='\u{5c2}', + '\u{5c4}'..='\u{5c5}', '\u{5c7}'..='\u{5c7}', '\u{5d0}'..='\u{5ea}', '\u{5ef}'..='\u{5f2}', + '\u{610}'..='\u{61a}', '\u{620}'..='\u{657}', '\u{659}'..='\u{65f}', '\u{66e}'..='\u{6d3}', + '\u{6d5}'..='\u{6dc}', '\u{6e1}'..='\u{6e8}', '\u{6ed}'..='\u{6ef}', '\u{6fa}'..='\u{6fc}', + '\u{6ff}'..='\u{6ff}', '\u{710}'..='\u{73f}', '\u{74d}'..='\u{7b1}', '\u{7ca}'..='\u{7ea}', + '\u{7f4}'..='\u{7f5}', '\u{7fa}'..='\u{7fa}', '\u{800}'..='\u{817}', '\u{81a}'..='\u{82c}', + '\u{840}'..='\u{858}', '\u{860}'..='\u{86a}', '\u{870}'..='\u{887}', '\u{889}'..='\u{88f}', + '\u{897}'..='\u{897}', '\u{8a0}'..='\u{8c9}', '\u{8d4}'..='\u{8df}', '\u{8e3}'..='\u{8e9}', + '\u{8f0}'..='\u{93b}', '\u{93d}'..='\u{94c}', '\u{94e}'..='\u{950}', '\u{955}'..='\u{963}', + '\u{971}'..='\u{983}', '\u{985}'..='\u{98c}', '\u{98f}'..='\u{990}', '\u{993}'..='\u{9a8}', + '\u{9aa}'..='\u{9b0}', '\u{9b2}'..='\u{9b2}', '\u{9b6}'..='\u{9b9}', '\u{9bd}'..='\u{9c4}', + '\u{9c7}'..='\u{9c8}', '\u{9cb}'..='\u{9cc}', '\u{9ce}'..='\u{9ce}', '\u{9d7}'..='\u{9d7}', + '\u{9dc}'..='\u{9dd}', '\u{9df}'..='\u{9e3}', '\u{9f0}'..='\u{9f1}', '\u{9fc}'..='\u{9fc}', + '\u{a01}'..='\u{a03}', '\u{a05}'..='\u{a0a}', '\u{a0f}'..='\u{a10}', '\u{a13}'..='\u{a28}', + '\u{a2a}'..='\u{a30}', '\u{a32}'..='\u{a33}', '\u{a35}'..='\u{a36}', '\u{a38}'..='\u{a39}', + '\u{a3e}'..='\u{a42}', '\u{a47}'..='\u{a48}', '\u{a4b}'..='\u{a4c}', '\u{a51}'..='\u{a51}', + '\u{a59}'..='\u{a5c}', '\u{a5e}'..='\u{a5e}', '\u{a70}'..='\u{a75}', '\u{a81}'..='\u{a83}', + '\u{a85}'..='\u{a8d}', '\u{a8f}'..='\u{a91}', '\u{a93}'..='\u{aa8}', '\u{aaa}'..='\u{ab0}', + '\u{ab2}'..='\u{ab3}', '\u{ab5}'..='\u{ab9}', '\u{abd}'..='\u{ac5}', '\u{ac7}'..='\u{ac9}', + '\u{acb}'..='\u{acc}', '\u{ad0}'..='\u{ad0}', '\u{ae0}'..='\u{ae3}', '\u{af9}'..='\u{afc}', + '\u{b01}'..='\u{b03}', '\u{b05}'..='\u{b0c}', '\u{b0f}'..='\u{b10}', '\u{b13}'..='\u{b28}', + '\u{b2a}'..='\u{b30}', '\u{b32}'..='\u{b33}', '\u{b35}'..='\u{b39}', '\u{b3d}'..='\u{b44}', + '\u{b47}'..='\u{b48}', '\u{b4b}'..='\u{b4c}', '\u{b56}'..='\u{b57}', '\u{b5c}'..='\u{b5d}', + '\u{b5f}'..='\u{b63}', '\u{b71}'..='\u{b71}', '\u{b82}'..='\u{b83}', '\u{b85}'..='\u{b8a}', + '\u{b8e}'..='\u{b90}', '\u{b92}'..='\u{b95}', '\u{b99}'..='\u{b9a}', '\u{b9c}'..='\u{b9c}', + '\u{b9e}'..='\u{b9f}', '\u{ba3}'..='\u{ba4}', '\u{ba8}'..='\u{baa}', '\u{bae}'..='\u{bb9}', + '\u{bbe}'..='\u{bc2}', '\u{bc6}'..='\u{bc8}', '\u{bca}'..='\u{bcc}', '\u{bd0}'..='\u{bd0}', + '\u{bd7}'..='\u{bd7}', '\u{c00}'..='\u{c0c}', '\u{c0e}'..='\u{c10}', '\u{c12}'..='\u{c28}', + '\u{c2a}'..='\u{c39}', '\u{c3d}'..='\u{c44}', '\u{c46}'..='\u{c48}', '\u{c4a}'..='\u{c4c}', + '\u{c55}'..='\u{c56}', '\u{c58}'..='\u{c5a}', '\u{c5c}'..='\u{c5d}', '\u{c60}'..='\u{c63}', + '\u{c80}'..='\u{c83}', '\u{c85}'..='\u{c8c}', '\u{c8e}'..='\u{c90}', '\u{c92}'..='\u{ca8}', + '\u{caa}'..='\u{cb3}', '\u{cb5}'..='\u{cb9}', '\u{cbd}'..='\u{cc4}', '\u{cc6}'..='\u{cc8}', + '\u{cca}'..='\u{ccc}', '\u{cd5}'..='\u{cd6}', '\u{cdc}'..='\u{cde}', '\u{ce0}'..='\u{ce3}', + '\u{cf1}'..='\u{cf3}', '\u{d00}'..='\u{d0c}', '\u{d0e}'..='\u{d10}', '\u{d12}'..='\u{d3a}', + '\u{d3d}'..='\u{d44}', '\u{d46}'..='\u{d48}', '\u{d4a}'..='\u{d4c}', '\u{d4e}'..='\u{d4e}', + '\u{d54}'..='\u{d57}', '\u{d5f}'..='\u{d63}', '\u{d7a}'..='\u{d7f}', '\u{d81}'..='\u{d83}', + '\u{d85}'..='\u{d96}', '\u{d9a}'..='\u{db1}', '\u{db3}'..='\u{dbb}', '\u{dbd}'..='\u{dbd}', + '\u{dc0}'..='\u{dc6}', '\u{dcf}'..='\u{dd4}', '\u{dd6}'..='\u{dd6}', '\u{dd8}'..='\u{ddf}', + '\u{df2}'..='\u{df3}', '\u{e01}'..='\u{e3a}', '\u{e40}'..='\u{e46}', '\u{e4d}'..='\u{e4d}', + '\u{e81}'..='\u{e82}', '\u{e84}'..='\u{e84}', '\u{e86}'..='\u{e8a}', '\u{e8c}'..='\u{ea3}', + '\u{ea5}'..='\u{ea5}', '\u{ea7}'..='\u{eb9}', '\u{ebb}'..='\u{ebd}', '\u{ec0}'..='\u{ec4}', + '\u{ec6}'..='\u{ec6}', '\u{ecd}'..='\u{ecd}', '\u{edc}'..='\u{edf}', '\u{f00}'..='\u{f00}', + '\u{f40}'..='\u{f47}', '\u{f49}'..='\u{f6c}', '\u{f71}'..='\u{f83}', '\u{f88}'..='\u{f97}', + '\u{f99}'..='\u{fbc}', '\u{1000}'..='\u{1036}', '\u{1038}'..='\u{1038}', + '\u{103b}'..='\u{103f}', '\u{1050}'..='\u{108f}', '\u{109a}'..='\u{109d}', + '\u{10a0}'..='\u{10c5}', '\u{10c7}'..='\u{10c7}', '\u{10cd}'..='\u{10cd}', + '\u{10d0}'..='\u{10fa}', '\u{10fc}'..='\u{1248}', '\u{124a}'..='\u{124d}', + '\u{1250}'..='\u{1256}', '\u{1258}'..='\u{1258}', '\u{125a}'..='\u{125d}', + '\u{1260}'..='\u{1288}', '\u{128a}'..='\u{128d}', '\u{1290}'..='\u{12b0}', + '\u{12b2}'..='\u{12b5}', '\u{12b8}'..='\u{12be}', '\u{12c0}'..='\u{12c0}', + '\u{12c2}'..='\u{12c5}', '\u{12c8}'..='\u{12d6}', '\u{12d8}'..='\u{1310}', + '\u{1312}'..='\u{1315}', '\u{1318}'..='\u{135a}', '\u{1380}'..='\u{138f}', + '\u{13a0}'..='\u{13f5}', '\u{13f8}'..='\u{13fd}', '\u{1401}'..='\u{166c}', + '\u{166f}'..='\u{167f}', '\u{1681}'..='\u{169a}', '\u{16a0}'..='\u{16ea}', + '\u{16ee}'..='\u{16f8}', '\u{1700}'..='\u{1713}', '\u{171f}'..='\u{1733}', + '\u{1740}'..='\u{1753}', '\u{1760}'..='\u{176c}', '\u{176e}'..='\u{1770}', + '\u{1772}'..='\u{1773}', '\u{1780}'..='\u{17b3}', '\u{17b6}'..='\u{17c8}', + '\u{17d7}'..='\u{17d7}', '\u{17dc}'..='\u{17dc}', '\u{1820}'..='\u{1878}', + '\u{1880}'..='\u{18aa}', '\u{18b0}'..='\u{18f5}', '\u{1900}'..='\u{191e}', + '\u{1920}'..='\u{192b}', '\u{1930}'..='\u{1938}', '\u{1950}'..='\u{196d}', + '\u{1970}'..='\u{1974}', '\u{1980}'..='\u{19ab}', '\u{19b0}'..='\u{19c9}', + '\u{1a00}'..='\u{1a1b}', '\u{1a20}'..='\u{1a5e}', '\u{1a61}'..='\u{1a74}', + '\u{1aa7}'..='\u{1aa7}', '\u{1abf}'..='\u{1ac0}', '\u{1acc}'..='\u{1ace}', + '\u{1b00}'..='\u{1b33}', '\u{1b35}'..='\u{1b43}', '\u{1b45}'..='\u{1b4c}', + '\u{1b80}'..='\u{1ba9}', '\u{1bac}'..='\u{1baf}', '\u{1bba}'..='\u{1be5}', + '\u{1be7}'..='\u{1bf1}', '\u{1c00}'..='\u{1c36}', '\u{1c4d}'..='\u{1c4f}', + '\u{1c5a}'..='\u{1c7d}', '\u{1c80}'..='\u{1c8a}', '\u{1c90}'..='\u{1cba}', + '\u{1cbd}'..='\u{1cbf}', '\u{1ce9}'..='\u{1cec}', '\u{1cee}'..='\u{1cf3}', + '\u{1cf5}'..='\u{1cf6}', '\u{1cfa}'..='\u{1cfa}', '\u{1d00}'..='\u{1dbf}', + '\u{1dd3}'..='\u{1df4}', '\u{1e00}'..='\u{1f15}', '\u{1f18}'..='\u{1f1d}', + '\u{1f20}'..='\u{1f45}', '\u{1f48}'..='\u{1f4d}', '\u{1f50}'..='\u{1f57}', + '\u{1f59}'..='\u{1f59}', '\u{1f5b}'..='\u{1f5b}', '\u{1f5d}'..='\u{1f5d}', + '\u{1f5f}'..='\u{1f7d}', '\u{1f80}'..='\u{1fb4}', '\u{1fb6}'..='\u{1fbc}', + '\u{1fbe}'..='\u{1fbe}', '\u{1fc2}'..='\u{1fc4}', '\u{1fc6}'..='\u{1fcc}', + '\u{1fd0}'..='\u{1fd3}', '\u{1fd6}'..='\u{1fdb}', '\u{1fe0}'..='\u{1fec}', + '\u{1ff2}'..='\u{1ff4}', '\u{1ff6}'..='\u{1ffc}', '\u{2071}'..='\u{2071}', + '\u{207f}'..='\u{207f}', '\u{2090}'..='\u{209c}', '\u{2102}'..='\u{2102}', + '\u{2107}'..='\u{2107}', '\u{210a}'..='\u{2113}', '\u{2115}'..='\u{2115}', + '\u{2119}'..='\u{211d}', '\u{2124}'..='\u{2124}', '\u{2126}'..='\u{2126}', + '\u{2128}'..='\u{2128}', '\u{212a}'..='\u{212d}', '\u{212f}'..='\u{2139}', + '\u{213c}'..='\u{213f}', '\u{2145}'..='\u{2149}', '\u{214e}'..='\u{214e}', + '\u{2160}'..='\u{2188}', '\u{24b6}'..='\u{24e9}', '\u{2c00}'..='\u{2ce4}', + '\u{2ceb}'..='\u{2cee}', '\u{2cf2}'..='\u{2cf3}', '\u{2d00}'..='\u{2d25}', + '\u{2d27}'..='\u{2d27}', '\u{2d2d}'..='\u{2d2d}', '\u{2d30}'..='\u{2d67}', + '\u{2d6f}'..='\u{2d6f}', '\u{2d80}'..='\u{2d96}', '\u{2da0}'..='\u{2da6}', + '\u{2da8}'..='\u{2dae}', '\u{2db0}'..='\u{2db6}', '\u{2db8}'..='\u{2dbe}', + '\u{2dc0}'..='\u{2dc6}', '\u{2dc8}'..='\u{2dce}', '\u{2dd0}'..='\u{2dd6}', + '\u{2dd8}'..='\u{2dde}', '\u{2de0}'..='\u{2dff}', '\u{2e2f}'..='\u{2e2f}', + '\u{3005}'..='\u{3007}', '\u{3021}'..='\u{3029}', '\u{3031}'..='\u{3035}', + '\u{3038}'..='\u{303c}', '\u{3041}'..='\u{3096}', '\u{309d}'..='\u{309f}', + '\u{30a1}'..='\u{30fa}', '\u{30fc}'..='\u{30ff}', '\u{3105}'..='\u{312f}', + '\u{3131}'..='\u{318e}', '\u{31a0}'..='\u{31bf}', '\u{31f0}'..='\u{31ff}', + '\u{3400}'..='\u{4dbf}', '\u{4e00}'..='\u{a48c}', '\u{a4d0}'..='\u{a4fd}', + '\u{a500}'..='\u{a60c}', '\u{a610}'..='\u{a61f}', '\u{a62a}'..='\u{a62b}', + '\u{a640}'..='\u{a66e}', '\u{a674}'..='\u{a67b}', '\u{a67f}'..='\u{a6ef}', + '\u{a717}'..='\u{a71f}', '\u{a722}'..='\u{a788}', '\u{a78b}'..='\u{a7dc}', + '\u{a7f1}'..='\u{a805}', '\u{a807}'..='\u{a827}', '\u{a840}'..='\u{a873}', + '\u{a880}'..='\u{a8c3}', '\u{a8c5}'..='\u{a8c5}', '\u{a8f2}'..='\u{a8f7}', + '\u{a8fb}'..='\u{a8fb}', '\u{a8fd}'..='\u{a8ff}', '\u{a90a}'..='\u{a92a}', + '\u{a930}'..='\u{a952}', '\u{a960}'..='\u{a97c}', '\u{a980}'..='\u{a9b2}', + '\u{a9b4}'..='\u{a9bf}', '\u{a9cf}'..='\u{a9cf}', '\u{a9e0}'..='\u{a9ef}', + '\u{a9fa}'..='\u{a9fe}', '\u{aa00}'..='\u{aa36}', '\u{aa40}'..='\u{aa4d}', + '\u{aa60}'..='\u{aa76}', '\u{aa7a}'..='\u{aabe}', '\u{aac0}'..='\u{aac0}', + '\u{aac2}'..='\u{aac2}', '\u{aadb}'..='\u{aadd}', '\u{aae0}'..='\u{aaef}', + '\u{aaf2}'..='\u{aaf5}', '\u{ab01}'..='\u{ab06}', '\u{ab09}'..='\u{ab0e}', + '\u{ab11}'..='\u{ab16}', '\u{ab20}'..='\u{ab26}', '\u{ab28}'..='\u{ab2e}', + '\u{ab30}'..='\u{ab5a}', '\u{ab5c}'..='\u{ab69}', '\u{ab70}'..='\u{abea}', + '\u{ac00}'..='\u{d7a3}', '\u{d7b0}'..='\u{d7c6}', '\u{d7cb}'..='\u{d7fb}', + '\u{f900}'..='\u{fa6d}', '\u{fa70}'..='\u{fad9}', '\u{fb00}'..='\u{fb06}', + '\u{fb13}'..='\u{fb17}', '\u{fb1d}'..='\u{fb28}', '\u{fb2a}'..='\u{fb36}', + '\u{fb38}'..='\u{fb3c}', '\u{fb3e}'..='\u{fb3e}', '\u{fb40}'..='\u{fb41}', + '\u{fb43}'..='\u{fb44}', '\u{fb46}'..='\u{fbb1}', '\u{fbd3}'..='\u{fd3d}', + '\u{fd50}'..='\u{fd8f}', '\u{fd92}'..='\u{fdc7}', '\u{fdf0}'..='\u{fdfb}', + '\u{fe70}'..='\u{fe74}', '\u{fe76}'..='\u{fefc}', '\u{ff21}'..='\u{ff3a}', + '\u{ff41}'..='\u{ff5a}', '\u{ff66}'..='\u{ffbe}', '\u{ffc2}'..='\u{ffc7}', + '\u{ffca}'..='\u{ffcf}', '\u{ffd2}'..='\u{ffd7}', '\u{ffda}'..='\u{ffdc}', + '\u{10000}'..='\u{1000b}', '\u{1000d}'..='\u{10026}', '\u{10028}'..='\u{1003a}', + '\u{1003c}'..='\u{1003d}', '\u{1003f}'..='\u{1004d}', '\u{10050}'..='\u{1005d}', + '\u{10080}'..='\u{100fa}', '\u{10140}'..='\u{10174}', '\u{10280}'..='\u{1029c}', + '\u{102a0}'..='\u{102d0}', '\u{10300}'..='\u{1031f}', '\u{1032d}'..='\u{1034a}', + '\u{10350}'..='\u{1037a}', '\u{10380}'..='\u{1039d}', '\u{103a0}'..='\u{103c3}', + '\u{103c8}'..='\u{103cf}', '\u{103d1}'..='\u{103d5}', '\u{10400}'..='\u{1049d}', + '\u{104b0}'..='\u{104d3}', '\u{104d8}'..='\u{104fb}', '\u{10500}'..='\u{10527}', + '\u{10530}'..='\u{10563}', '\u{10570}'..='\u{1057a}', '\u{1057c}'..='\u{1058a}', + '\u{1058c}'..='\u{10592}', '\u{10594}'..='\u{10595}', '\u{10597}'..='\u{105a1}', + '\u{105a3}'..='\u{105b1}', '\u{105b3}'..='\u{105b9}', '\u{105bb}'..='\u{105bc}', + '\u{105c0}'..='\u{105f3}', '\u{10600}'..='\u{10736}', '\u{10740}'..='\u{10755}', + '\u{10760}'..='\u{10767}', '\u{10780}'..='\u{10785}', '\u{10787}'..='\u{107b0}', + '\u{107b2}'..='\u{107ba}', '\u{10800}'..='\u{10805}', '\u{10808}'..='\u{10808}', + '\u{1080a}'..='\u{10835}', '\u{10837}'..='\u{10838}', '\u{1083c}'..='\u{1083c}', + '\u{1083f}'..='\u{10855}', '\u{10860}'..='\u{10876}', '\u{10880}'..='\u{1089e}', + '\u{108e0}'..='\u{108f2}', '\u{108f4}'..='\u{108f5}', '\u{10900}'..='\u{10915}', + '\u{10920}'..='\u{10939}', '\u{10940}'..='\u{10959}', '\u{10980}'..='\u{109b7}', + '\u{109be}'..='\u{109bf}', '\u{10a00}'..='\u{10a03}', '\u{10a05}'..='\u{10a06}', + '\u{10a0c}'..='\u{10a13}', '\u{10a15}'..='\u{10a17}', '\u{10a19}'..='\u{10a35}', + '\u{10a60}'..='\u{10a7c}', '\u{10a80}'..='\u{10a9c}', '\u{10ac0}'..='\u{10ac7}', + '\u{10ac9}'..='\u{10ae4}', '\u{10b00}'..='\u{10b35}', '\u{10b40}'..='\u{10b55}', + '\u{10b60}'..='\u{10b72}', '\u{10b80}'..='\u{10b91}', '\u{10c00}'..='\u{10c48}', + '\u{10c80}'..='\u{10cb2}', '\u{10cc0}'..='\u{10cf2}', '\u{10d00}'..='\u{10d27}', + '\u{10d4a}'..='\u{10d65}', '\u{10d69}'..='\u{10d69}', '\u{10d6f}'..='\u{10d85}', + '\u{10e80}'..='\u{10ea9}', '\u{10eab}'..='\u{10eac}', '\u{10eb0}'..='\u{10eb1}', + '\u{10ec2}'..='\u{10ec7}', '\u{10efa}'..='\u{10efc}', '\u{10f00}'..='\u{10f1c}', + '\u{10f27}'..='\u{10f27}', '\u{10f30}'..='\u{10f45}', '\u{10f70}'..='\u{10f81}', + '\u{10fb0}'..='\u{10fc4}', '\u{10fe0}'..='\u{10ff6}', '\u{11000}'..='\u{11045}', + '\u{11071}'..='\u{11075}', '\u{11080}'..='\u{110b8}', '\u{110c2}'..='\u{110c2}', + '\u{110d0}'..='\u{110e8}', '\u{11100}'..='\u{11132}', '\u{11144}'..='\u{11147}', + '\u{11150}'..='\u{11172}', '\u{11176}'..='\u{11176}', '\u{11180}'..='\u{111bf}', + '\u{111c1}'..='\u{111c4}', '\u{111ce}'..='\u{111cf}', '\u{111da}'..='\u{111da}', + '\u{111dc}'..='\u{111dc}', '\u{11200}'..='\u{11211}', '\u{11213}'..='\u{11234}', + '\u{11237}'..='\u{11237}', '\u{1123e}'..='\u{11241}', '\u{11280}'..='\u{11286}', + '\u{11288}'..='\u{11288}', '\u{1128a}'..='\u{1128d}', '\u{1128f}'..='\u{1129d}', + '\u{1129f}'..='\u{112a8}', '\u{112b0}'..='\u{112e8}', '\u{11300}'..='\u{11303}', + '\u{11305}'..='\u{1130c}', '\u{1130f}'..='\u{11310}', '\u{11313}'..='\u{11328}', + '\u{1132a}'..='\u{11330}', '\u{11332}'..='\u{11333}', '\u{11335}'..='\u{11339}', + '\u{1133d}'..='\u{11344}', '\u{11347}'..='\u{11348}', '\u{1134b}'..='\u{1134c}', + '\u{11350}'..='\u{11350}', '\u{11357}'..='\u{11357}', '\u{1135d}'..='\u{11363}', + '\u{11380}'..='\u{11389}', '\u{1138b}'..='\u{1138b}', '\u{1138e}'..='\u{1138e}', + '\u{11390}'..='\u{113b5}', '\u{113b7}'..='\u{113c0}', '\u{113c2}'..='\u{113c2}', + '\u{113c5}'..='\u{113c5}', '\u{113c7}'..='\u{113ca}', '\u{113cc}'..='\u{113cd}', + '\u{113d1}'..='\u{113d1}', '\u{113d3}'..='\u{113d3}', '\u{11400}'..='\u{11441}', + '\u{11443}'..='\u{11445}', '\u{11447}'..='\u{1144a}', '\u{1145f}'..='\u{11461}', + '\u{11480}'..='\u{114c1}', '\u{114c4}'..='\u{114c5}', '\u{114c7}'..='\u{114c7}', + '\u{11580}'..='\u{115b5}', '\u{115b8}'..='\u{115be}', '\u{115d8}'..='\u{115dd}', + '\u{11600}'..='\u{1163e}', '\u{11640}'..='\u{11640}', '\u{11644}'..='\u{11644}', + '\u{11680}'..='\u{116b5}', '\u{116b8}'..='\u{116b8}', '\u{11700}'..='\u{1171a}', + '\u{1171d}'..='\u{1172a}', '\u{11740}'..='\u{11746}', '\u{11800}'..='\u{11838}', + '\u{118a0}'..='\u{118df}', '\u{118ff}'..='\u{11906}', '\u{11909}'..='\u{11909}', + '\u{1190c}'..='\u{11913}', '\u{11915}'..='\u{11916}', '\u{11918}'..='\u{11935}', + '\u{11937}'..='\u{11938}', '\u{1193b}'..='\u{1193c}', '\u{1193f}'..='\u{11942}', + '\u{119a0}'..='\u{119a7}', '\u{119aa}'..='\u{119d7}', '\u{119da}'..='\u{119df}', + '\u{119e1}'..='\u{119e1}', '\u{119e3}'..='\u{119e4}', '\u{11a00}'..='\u{11a32}', + '\u{11a35}'..='\u{11a3e}', '\u{11a50}'..='\u{11a97}', '\u{11a9d}'..='\u{11a9d}', + '\u{11ab0}'..='\u{11af8}', '\u{11b60}'..='\u{11b67}', '\u{11bc0}'..='\u{11be0}', + '\u{11c00}'..='\u{11c08}', '\u{11c0a}'..='\u{11c36}', '\u{11c38}'..='\u{11c3e}', + '\u{11c40}'..='\u{11c40}', '\u{11c72}'..='\u{11c8f}', '\u{11c92}'..='\u{11ca7}', + '\u{11ca9}'..='\u{11cb6}', '\u{11d00}'..='\u{11d06}', '\u{11d08}'..='\u{11d09}', + '\u{11d0b}'..='\u{11d36}', '\u{11d3a}'..='\u{11d3a}', '\u{11d3c}'..='\u{11d3d}', + '\u{11d3f}'..='\u{11d41}', '\u{11d43}'..='\u{11d43}', '\u{11d46}'..='\u{11d47}', + '\u{11d60}'..='\u{11d65}', '\u{11d67}'..='\u{11d68}', '\u{11d6a}'..='\u{11d8e}', + '\u{11d90}'..='\u{11d91}', '\u{11d93}'..='\u{11d96}', '\u{11d98}'..='\u{11d98}', + '\u{11db0}'..='\u{11ddb}', '\u{11ee0}'..='\u{11ef6}', '\u{11f00}'..='\u{11f10}', + '\u{11f12}'..='\u{11f3a}', '\u{11f3e}'..='\u{11f40}', '\u{11fb0}'..='\u{11fb0}', + '\u{12000}'..='\u{12399}', '\u{12400}'..='\u{1246e}', '\u{12480}'..='\u{12543}', + '\u{12f90}'..='\u{12ff0}', '\u{13000}'..='\u{1342f}', '\u{13441}'..='\u{13446}', + '\u{13460}'..='\u{143fa}', '\u{14400}'..='\u{14646}', '\u{16100}'..='\u{1612e}', + '\u{16800}'..='\u{16a38}', '\u{16a40}'..='\u{16a5e}', '\u{16a70}'..='\u{16abe}', + '\u{16ad0}'..='\u{16aed}', '\u{16b00}'..='\u{16b2f}', '\u{16b40}'..='\u{16b43}', + '\u{16b63}'..='\u{16b77}', '\u{16b7d}'..='\u{16b8f}', '\u{16d40}'..='\u{16d6c}', + '\u{16e40}'..='\u{16e7f}', '\u{16ea0}'..='\u{16eb8}', '\u{16ebb}'..='\u{16ed3}', + '\u{16f00}'..='\u{16f4a}', '\u{16f4f}'..='\u{16f87}', '\u{16f8f}'..='\u{16f9f}', + '\u{16fe0}'..='\u{16fe1}', '\u{16fe3}'..='\u{16fe3}', '\u{16ff0}'..='\u{16ff6}', + '\u{17000}'..='\u{18cd5}', '\u{18cff}'..='\u{18d1e}', '\u{18d80}'..='\u{18df2}', + '\u{1aff0}'..='\u{1aff3}', '\u{1aff5}'..='\u{1affb}', '\u{1affd}'..='\u{1affe}', + '\u{1b000}'..='\u{1b122}', '\u{1b132}'..='\u{1b132}', '\u{1b150}'..='\u{1b152}', + '\u{1b155}'..='\u{1b155}', '\u{1b164}'..='\u{1b167}', '\u{1b170}'..='\u{1b2fb}', + '\u{1bc00}'..='\u{1bc6a}', '\u{1bc70}'..='\u{1bc7c}', '\u{1bc80}'..='\u{1bc88}', + '\u{1bc90}'..='\u{1bc99}', '\u{1bc9e}'..='\u{1bc9e}', '\u{1d400}'..='\u{1d454}', + '\u{1d456}'..='\u{1d49c}', '\u{1d49e}'..='\u{1d49f}', '\u{1d4a2}'..='\u{1d4a2}', + '\u{1d4a5}'..='\u{1d4a6}', '\u{1d4a9}'..='\u{1d4ac}', '\u{1d4ae}'..='\u{1d4b9}', + '\u{1d4bb}'..='\u{1d4bb}', '\u{1d4bd}'..='\u{1d4c3}', '\u{1d4c5}'..='\u{1d505}', + '\u{1d507}'..='\u{1d50a}', '\u{1d50d}'..='\u{1d514}', '\u{1d516}'..='\u{1d51c}', + '\u{1d51e}'..='\u{1d539}', '\u{1d53b}'..='\u{1d53e}', '\u{1d540}'..='\u{1d544}', + '\u{1d546}'..='\u{1d546}', '\u{1d54a}'..='\u{1d550}', '\u{1d552}'..='\u{1d6a5}', + '\u{1d6a8}'..='\u{1d6c0}', '\u{1d6c2}'..='\u{1d6da}', '\u{1d6dc}'..='\u{1d6fa}', + '\u{1d6fc}'..='\u{1d714}', '\u{1d716}'..='\u{1d734}', '\u{1d736}'..='\u{1d74e}', + '\u{1d750}'..='\u{1d76e}', '\u{1d770}'..='\u{1d788}', '\u{1d78a}'..='\u{1d7a8}', + '\u{1d7aa}'..='\u{1d7c2}', '\u{1d7c4}'..='\u{1d7cb}', '\u{1df00}'..='\u{1df1e}', + '\u{1df25}'..='\u{1df2a}', '\u{1e000}'..='\u{1e006}', '\u{1e008}'..='\u{1e018}', + '\u{1e01b}'..='\u{1e021}', '\u{1e023}'..='\u{1e024}', '\u{1e026}'..='\u{1e02a}', + '\u{1e030}'..='\u{1e06d}', '\u{1e08f}'..='\u{1e08f}', '\u{1e100}'..='\u{1e12c}', + '\u{1e137}'..='\u{1e13d}', '\u{1e14e}'..='\u{1e14e}', '\u{1e290}'..='\u{1e2ad}', + '\u{1e2c0}'..='\u{1e2eb}', '\u{1e4d0}'..='\u{1e4eb}', '\u{1e5d0}'..='\u{1e5ed}', + '\u{1e5f0}'..='\u{1e5f0}', '\u{1e6c0}'..='\u{1e6de}', '\u{1e6e0}'..='\u{1e6f5}', + '\u{1e6fe}'..='\u{1e6ff}', '\u{1e7e0}'..='\u{1e7e6}', '\u{1e7e8}'..='\u{1e7eb}', + '\u{1e7ed}'..='\u{1e7ee}', '\u{1e7f0}'..='\u{1e7fe}', '\u{1e800}'..='\u{1e8c4}', + '\u{1e900}'..='\u{1e943}', '\u{1e947}'..='\u{1e947}', '\u{1e94b}'..='\u{1e94b}', + '\u{1ee00}'..='\u{1ee03}', '\u{1ee05}'..='\u{1ee1f}', '\u{1ee21}'..='\u{1ee22}', + '\u{1ee24}'..='\u{1ee24}', '\u{1ee27}'..='\u{1ee27}', '\u{1ee29}'..='\u{1ee32}', + '\u{1ee34}'..='\u{1ee37}', '\u{1ee39}'..='\u{1ee39}', '\u{1ee3b}'..='\u{1ee3b}', + '\u{1ee42}'..='\u{1ee42}', '\u{1ee47}'..='\u{1ee47}', '\u{1ee49}'..='\u{1ee49}', + '\u{1ee4b}'..='\u{1ee4b}', '\u{1ee4d}'..='\u{1ee4f}', '\u{1ee51}'..='\u{1ee52}', + '\u{1ee54}'..='\u{1ee54}', '\u{1ee57}'..='\u{1ee57}', '\u{1ee59}'..='\u{1ee59}', + '\u{1ee5b}'..='\u{1ee5b}', '\u{1ee5d}'..='\u{1ee5d}', '\u{1ee5f}'..='\u{1ee5f}', + '\u{1ee61}'..='\u{1ee62}', '\u{1ee64}'..='\u{1ee64}', '\u{1ee67}'..='\u{1ee6a}', + '\u{1ee6c}'..='\u{1ee72}', '\u{1ee74}'..='\u{1ee77}', '\u{1ee79}'..='\u{1ee7c}', + '\u{1ee7e}'..='\u{1ee7e}', '\u{1ee80}'..='\u{1ee89}', '\u{1ee8b}'..='\u{1ee9b}', + '\u{1eea1}'..='\u{1eea3}', '\u{1eea5}'..='\u{1eea9}', '\u{1eeab}'..='\u{1eebb}', + '\u{1f130}'..='\u{1f149}', '\u{1f150}'..='\u{1f169}', '\u{1f170}'..='\u{1f189}', + '\u{20000}'..='\u{2a6df}', '\u{2a700}'..='\u{2b81d}', '\u{2b820}'..='\u{2cead}', + '\u{2ceb0}'..='\u{2ebe0}', '\u{2ebf0}'..='\u{2ee5d}', '\u{2f800}'..='\u{2fa1d}', + '\u{30000}'..='\u{3134a}', '\u{31350}'..='\u{33479}', +]; + +#[rustfmt::skip] +pub(super) static CASE_IGNORABLE: &[RangeInclusive; 459] = &[ + '\u{a8}'..='\u{a8}', '\u{ad}'..='\u{ad}', '\u{af}'..='\u{af}', '\u{b4}'..='\u{b4}', + '\u{b7}'..='\u{b8}', '\u{2b0}'..='\u{36f}', '\u{374}'..='\u{375}', '\u{37a}'..='\u{37a}', + '\u{384}'..='\u{385}', '\u{387}'..='\u{387}', '\u{483}'..='\u{489}', '\u{559}'..='\u{559}', + '\u{55f}'..='\u{55f}', '\u{591}'..='\u{5bd}', '\u{5bf}'..='\u{5bf}', '\u{5c1}'..='\u{5c2}', + '\u{5c4}'..='\u{5c5}', '\u{5c7}'..='\u{5c7}', '\u{5f4}'..='\u{5f4}', '\u{600}'..='\u{605}', + '\u{610}'..='\u{61a}', '\u{61c}'..='\u{61c}', '\u{640}'..='\u{640}', '\u{64b}'..='\u{65f}', + '\u{670}'..='\u{670}', '\u{6d6}'..='\u{6dd}', '\u{6df}'..='\u{6e8}', '\u{6ea}'..='\u{6ed}', + '\u{70f}'..='\u{70f}', '\u{711}'..='\u{711}', '\u{730}'..='\u{74a}', '\u{7a6}'..='\u{7b0}', + '\u{7eb}'..='\u{7f5}', '\u{7fa}'..='\u{7fa}', '\u{7fd}'..='\u{7fd}', '\u{816}'..='\u{82d}', + '\u{859}'..='\u{85b}', '\u{888}'..='\u{888}', '\u{890}'..='\u{891}', '\u{897}'..='\u{89f}', + '\u{8c9}'..='\u{902}', '\u{93a}'..='\u{93a}', '\u{93c}'..='\u{93c}', '\u{941}'..='\u{948}', + '\u{94d}'..='\u{94d}', '\u{951}'..='\u{957}', '\u{962}'..='\u{963}', '\u{971}'..='\u{971}', + '\u{981}'..='\u{981}', '\u{9bc}'..='\u{9bc}', '\u{9c1}'..='\u{9c4}', '\u{9cd}'..='\u{9cd}', + '\u{9e2}'..='\u{9e3}', '\u{9fe}'..='\u{9fe}', '\u{a01}'..='\u{a02}', '\u{a3c}'..='\u{a3c}', + '\u{a41}'..='\u{a42}', '\u{a47}'..='\u{a48}', '\u{a4b}'..='\u{a4d}', '\u{a51}'..='\u{a51}', + '\u{a70}'..='\u{a71}', '\u{a75}'..='\u{a75}', '\u{a81}'..='\u{a82}', '\u{abc}'..='\u{abc}', + '\u{ac1}'..='\u{ac5}', '\u{ac7}'..='\u{ac8}', '\u{acd}'..='\u{acd}', '\u{ae2}'..='\u{ae3}', + '\u{afa}'..='\u{aff}', '\u{b01}'..='\u{b01}', '\u{b3c}'..='\u{b3c}', '\u{b3f}'..='\u{b3f}', + '\u{b41}'..='\u{b44}', '\u{b4d}'..='\u{b4d}', '\u{b55}'..='\u{b56}', '\u{b62}'..='\u{b63}', + '\u{b82}'..='\u{b82}', '\u{bc0}'..='\u{bc0}', '\u{bcd}'..='\u{bcd}', '\u{c00}'..='\u{c00}', + '\u{c04}'..='\u{c04}', '\u{c3c}'..='\u{c3c}', '\u{c3e}'..='\u{c40}', '\u{c46}'..='\u{c48}', + '\u{c4a}'..='\u{c4d}', '\u{c55}'..='\u{c56}', '\u{c62}'..='\u{c63}', '\u{c81}'..='\u{c81}', + '\u{cbc}'..='\u{cbc}', '\u{cbf}'..='\u{cbf}', '\u{cc6}'..='\u{cc6}', '\u{ccc}'..='\u{ccd}', + '\u{ce2}'..='\u{ce3}', '\u{d00}'..='\u{d01}', '\u{d3b}'..='\u{d3c}', '\u{d41}'..='\u{d44}', + '\u{d4d}'..='\u{d4d}', '\u{d62}'..='\u{d63}', '\u{d81}'..='\u{d81}', '\u{dca}'..='\u{dca}', + '\u{dd2}'..='\u{dd4}', '\u{dd6}'..='\u{dd6}', '\u{e31}'..='\u{e31}', '\u{e34}'..='\u{e3a}', + '\u{e46}'..='\u{e4e}', '\u{eb1}'..='\u{eb1}', '\u{eb4}'..='\u{ebc}', '\u{ec6}'..='\u{ec6}', + '\u{ec8}'..='\u{ece}', '\u{f18}'..='\u{f19}', '\u{f35}'..='\u{f35}', '\u{f37}'..='\u{f37}', + '\u{f39}'..='\u{f39}', '\u{f71}'..='\u{f7e}', '\u{f80}'..='\u{f84}', '\u{f86}'..='\u{f87}', + '\u{f8d}'..='\u{f97}', '\u{f99}'..='\u{fbc}', '\u{fc6}'..='\u{fc6}', + '\u{102d}'..='\u{1030}', '\u{1032}'..='\u{1037}', '\u{1039}'..='\u{103a}', + '\u{103d}'..='\u{103e}', '\u{1058}'..='\u{1059}', '\u{105e}'..='\u{1060}', + '\u{1071}'..='\u{1074}', '\u{1082}'..='\u{1082}', '\u{1085}'..='\u{1086}', + '\u{108d}'..='\u{108d}', '\u{109d}'..='\u{109d}', '\u{10fc}'..='\u{10fc}', + '\u{135d}'..='\u{135f}', '\u{1712}'..='\u{1714}', '\u{1732}'..='\u{1733}', + '\u{1752}'..='\u{1753}', '\u{1772}'..='\u{1773}', '\u{17b4}'..='\u{17b5}', + '\u{17b7}'..='\u{17bd}', '\u{17c6}'..='\u{17c6}', '\u{17c9}'..='\u{17d3}', + '\u{17d7}'..='\u{17d7}', '\u{17dd}'..='\u{17dd}', '\u{180b}'..='\u{180f}', + '\u{1843}'..='\u{1843}', '\u{1885}'..='\u{1886}', '\u{18a9}'..='\u{18a9}', + '\u{1920}'..='\u{1922}', '\u{1927}'..='\u{1928}', '\u{1932}'..='\u{1932}', + '\u{1939}'..='\u{193b}', '\u{1a17}'..='\u{1a18}', '\u{1a1b}'..='\u{1a1b}', + '\u{1a56}'..='\u{1a56}', '\u{1a58}'..='\u{1a5e}', '\u{1a60}'..='\u{1a60}', + '\u{1a62}'..='\u{1a62}', '\u{1a65}'..='\u{1a6c}', '\u{1a73}'..='\u{1a7c}', + '\u{1a7f}'..='\u{1a7f}', '\u{1aa7}'..='\u{1aa7}', '\u{1ab0}'..='\u{1add}', + '\u{1ae0}'..='\u{1aeb}', '\u{1b00}'..='\u{1b03}', '\u{1b34}'..='\u{1b34}', + '\u{1b36}'..='\u{1b3a}', '\u{1b3c}'..='\u{1b3c}', '\u{1b42}'..='\u{1b42}', + '\u{1b6b}'..='\u{1b73}', '\u{1b80}'..='\u{1b81}', '\u{1ba2}'..='\u{1ba5}', + '\u{1ba8}'..='\u{1ba9}', '\u{1bab}'..='\u{1bad}', '\u{1be6}'..='\u{1be6}', + '\u{1be8}'..='\u{1be9}', '\u{1bed}'..='\u{1bed}', '\u{1bef}'..='\u{1bf1}', + '\u{1c2c}'..='\u{1c33}', '\u{1c36}'..='\u{1c37}', '\u{1c78}'..='\u{1c7d}', + '\u{1cd0}'..='\u{1cd2}', '\u{1cd4}'..='\u{1ce0}', '\u{1ce2}'..='\u{1ce8}', + '\u{1ced}'..='\u{1ced}', '\u{1cf4}'..='\u{1cf4}', '\u{1cf8}'..='\u{1cf9}', + '\u{1d2c}'..='\u{1d6a}', '\u{1d78}'..='\u{1d78}', '\u{1d9b}'..='\u{1dff}', + '\u{1fbd}'..='\u{1fbd}', '\u{1fbf}'..='\u{1fc1}', '\u{1fcd}'..='\u{1fcf}', + '\u{1fdd}'..='\u{1fdf}', '\u{1fed}'..='\u{1fef}', '\u{1ffd}'..='\u{1ffe}', + '\u{200b}'..='\u{200f}', '\u{2018}'..='\u{2019}', '\u{2024}'..='\u{2024}', + '\u{2027}'..='\u{2027}', '\u{202a}'..='\u{202e}', '\u{2060}'..='\u{2064}', + '\u{2066}'..='\u{206f}', '\u{2071}'..='\u{2071}', '\u{207f}'..='\u{207f}', + '\u{2090}'..='\u{209c}', '\u{20d0}'..='\u{20f0}', '\u{2c7c}'..='\u{2c7d}', + '\u{2cef}'..='\u{2cf1}', '\u{2d6f}'..='\u{2d6f}', '\u{2d7f}'..='\u{2d7f}', + '\u{2de0}'..='\u{2dff}', '\u{2e2f}'..='\u{2e2f}', '\u{3005}'..='\u{3005}', + '\u{302a}'..='\u{302d}', '\u{3031}'..='\u{3035}', '\u{303b}'..='\u{303b}', + '\u{3099}'..='\u{309e}', '\u{30fc}'..='\u{30fe}', '\u{a015}'..='\u{a015}', + '\u{a4f8}'..='\u{a4fd}', '\u{a60c}'..='\u{a60c}', '\u{a66f}'..='\u{a672}', + '\u{a674}'..='\u{a67d}', '\u{a67f}'..='\u{a67f}', '\u{a69c}'..='\u{a69f}', + '\u{a6f0}'..='\u{a6f1}', '\u{a700}'..='\u{a721}', '\u{a770}'..='\u{a770}', + '\u{a788}'..='\u{a78a}', '\u{a7f1}'..='\u{a7f4}', '\u{a7f8}'..='\u{a7f9}', + '\u{a802}'..='\u{a802}', '\u{a806}'..='\u{a806}', '\u{a80b}'..='\u{a80b}', + '\u{a825}'..='\u{a826}', '\u{a82c}'..='\u{a82c}', '\u{a8c4}'..='\u{a8c5}', + '\u{a8e0}'..='\u{a8f1}', '\u{a8ff}'..='\u{a8ff}', '\u{a926}'..='\u{a92d}', + '\u{a947}'..='\u{a951}', '\u{a980}'..='\u{a982}', '\u{a9b3}'..='\u{a9b3}', + '\u{a9b6}'..='\u{a9b9}', '\u{a9bc}'..='\u{a9bd}', '\u{a9cf}'..='\u{a9cf}', + '\u{a9e5}'..='\u{a9e6}', '\u{aa29}'..='\u{aa2e}', '\u{aa31}'..='\u{aa32}', + '\u{aa35}'..='\u{aa36}', '\u{aa43}'..='\u{aa43}', '\u{aa4c}'..='\u{aa4c}', + '\u{aa70}'..='\u{aa70}', '\u{aa7c}'..='\u{aa7c}', '\u{aab0}'..='\u{aab0}', + '\u{aab2}'..='\u{aab4}', '\u{aab7}'..='\u{aab8}', '\u{aabe}'..='\u{aabf}', + '\u{aac1}'..='\u{aac1}', '\u{aadd}'..='\u{aadd}', '\u{aaec}'..='\u{aaed}', + '\u{aaf3}'..='\u{aaf4}', '\u{aaf6}'..='\u{aaf6}', '\u{ab5b}'..='\u{ab5f}', + '\u{ab69}'..='\u{ab6b}', '\u{abe5}'..='\u{abe5}', '\u{abe8}'..='\u{abe8}', + '\u{abed}'..='\u{abed}', '\u{fb1e}'..='\u{fb1e}', '\u{fbb2}'..='\u{fbc2}', + '\u{fe00}'..='\u{fe0f}', '\u{fe13}'..='\u{fe13}', '\u{fe20}'..='\u{fe2f}', + '\u{fe52}'..='\u{fe52}', '\u{fe55}'..='\u{fe55}', '\u{feff}'..='\u{feff}', + '\u{ff07}'..='\u{ff07}', '\u{ff0e}'..='\u{ff0e}', '\u{ff1a}'..='\u{ff1a}', + '\u{ff3e}'..='\u{ff3e}', '\u{ff40}'..='\u{ff40}', '\u{ff70}'..='\u{ff70}', + '\u{ff9e}'..='\u{ff9f}', '\u{ffe3}'..='\u{ffe3}', '\u{fff9}'..='\u{fffb}', + '\u{101fd}'..='\u{101fd}', '\u{102e0}'..='\u{102e0}', '\u{10376}'..='\u{1037a}', + '\u{10780}'..='\u{10785}', '\u{10787}'..='\u{107b0}', '\u{107b2}'..='\u{107ba}', + '\u{10a01}'..='\u{10a03}', '\u{10a05}'..='\u{10a06}', '\u{10a0c}'..='\u{10a0f}', + '\u{10a38}'..='\u{10a3a}', '\u{10a3f}'..='\u{10a3f}', '\u{10ae5}'..='\u{10ae6}', + '\u{10d24}'..='\u{10d27}', '\u{10d4e}'..='\u{10d4e}', '\u{10d69}'..='\u{10d6d}', + '\u{10d6f}'..='\u{10d6f}', '\u{10eab}'..='\u{10eac}', '\u{10ec5}'..='\u{10ec5}', + '\u{10efa}'..='\u{10eff}', '\u{10f46}'..='\u{10f50}', '\u{10f82}'..='\u{10f85}', + '\u{11001}'..='\u{11001}', '\u{11038}'..='\u{11046}', '\u{11070}'..='\u{11070}', + '\u{11073}'..='\u{11074}', '\u{1107f}'..='\u{11081}', '\u{110b3}'..='\u{110b6}', + '\u{110b9}'..='\u{110ba}', '\u{110bd}'..='\u{110bd}', '\u{110c2}'..='\u{110c2}', + '\u{110cd}'..='\u{110cd}', '\u{11100}'..='\u{11102}', '\u{11127}'..='\u{1112b}', + '\u{1112d}'..='\u{11134}', '\u{11173}'..='\u{11173}', '\u{11180}'..='\u{11181}', + '\u{111b6}'..='\u{111be}', '\u{111c9}'..='\u{111cc}', '\u{111cf}'..='\u{111cf}', + '\u{1122f}'..='\u{11231}', '\u{11234}'..='\u{11234}', '\u{11236}'..='\u{11237}', + '\u{1123e}'..='\u{1123e}', '\u{11241}'..='\u{11241}', '\u{112df}'..='\u{112df}', + '\u{112e3}'..='\u{112ea}', '\u{11300}'..='\u{11301}', '\u{1133b}'..='\u{1133c}', + '\u{11340}'..='\u{11340}', '\u{11366}'..='\u{1136c}', '\u{11370}'..='\u{11374}', + '\u{113bb}'..='\u{113c0}', '\u{113ce}'..='\u{113ce}', '\u{113d0}'..='\u{113d0}', + '\u{113d2}'..='\u{113d2}', '\u{113e1}'..='\u{113e2}', '\u{11438}'..='\u{1143f}', + '\u{11442}'..='\u{11444}', '\u{11446}'..='\u{11446}', '\u{1145e}'..='\u{1145e}', + '\u{114b3}'..='\u{114b8}', '\u{114ba}'..='\u{114ba}', '\u{114bf}'..='\u{114c0}', + '\u{114c2}'..='\u{114c3}', '\u{115b2}'..='\u{115b5}', '\u{115bc}'..='\u{115bd}', + '\u{115bf}'..='\u{115c0}', '\u{115dc}'..='\u{115dd}', '\u{11633}'..='\u{1163a}', + '\u{1163d}'..='\u{1163d}', '\u{1163f}'..='\u{11640}', '\u{116ab}'..='\u{116ab}', + '\u{116ad}'..='\u{116ad}', '\u{116b0}'..='\u{116b5}', '\u{116b7}'..='\u{116b7}', + '\u{1171d}'..='\u{1171d}', '\u{1171f}'..='\u{1171f}', '\u{11722}'..='\u{11725}', + '\u{11727}'..='\u{1172b}', '\u{1182f}'..='\u{11837}', '\u{11839}'..='\u{1183a}', + '\u{1193b}'..='\u{1193c}', '\u{1193e}'..='\u{1193e}', '\u{11943}'..='\u{11943}', + '\u{119d4}'..='\u{119d7}', '\u{119da}'..='\u{119db}', '\u{119e0}'..='\u{119e0}', + '\u{11a01}'..='\u{11a0a}', '\u{11a33}'..='\u{11a38}', '\u{11a3b}'..='\u{11a3e}', + '\u{11a47}'..='\u{11a47}', '\u{11a51}'..='\u{11a56}', '\u{11a59}'..='\u{11a5b}', + '\u{11a8a}'..='\u{11a96}', '\u{11a98}'..='\u{11a99}', '\u{11b60}'..='\u{11b60}', + '\u{11b62}'..='\u{11b64}', '\u{11b66}'..='\u{11b66}', '\u{11c30}'..='\u{11c36}', + '\u{11c38}'..='\u{11c3d}', '\u{11c3f}'..='\u{11c3f}', '\u{11c92}'..='\u{11ca7}', + '\u{11caa}'..='\u{11cb0}', '\u{11cb2}'..='\u{11cb3}', '\u{11cb5}'..='\u{11cb6}', + '\u{11d31}'..='\u{11d36}', '\u{11d3a}'..='\u{11d3a}', '\u{11d3c}'..='\u{11d3d}', + '\u{11d3f}'..='\u{11d45}', '\u{11d47}'..='\u{11d47}', '\u{11d90}'..='\u{11d91}', + '\u{11d95}'..='\u{11d95}', '\u{11d97}'..='\u{11d97}', '\u{11dd9}'..='\u{11dd9}', + '\u{11ef3}'..='\u{11ef4}', '\u{11f00}'..='\u{11f01}', '\u{11f36}'..='\u{11f3a}', + '\u{11f40}'..='\u{11f40}', '\u{11f42}'..='\u{11f42}', '\u{11f5a}'..='\u{11f5a}', + '\u{13430}'..='\u{13440}', '\u{13447}'..='\u{13455}', '\u{1611e}'..='\u{16129}', + '\u{1612d}'..='\u{1612f}', '\u{16af0}'..='\u{16af4}', '\u{16b30}'..='\u{16b36}', + '\u{16b40}'..='\u{16b43}', '\u{16d40}'..='\u{16d42}', '\u{16d6b}'..='\u{16d6c}', + '\u{16f4f}'..='\u{16f4f}', '\u{16f8f}'..='\u{16f9f}', '\u{16fe0}'..='\u{16fe1}', + '\u{16fe3}'..='\u{16fe4}', '\u{16ff2}'..='\u{16ff3}', '\u{1aff0}'..='\u{1aff3}', + '\u{1aff5}'..='\u{1affb}', '\u{1affd}'..='\u{1affe}', '\u{1bc9d}'..='\u{1bc9e}', + '\u{1bca0}'..='\u{1bca3}', '\u{1cf00}'..='\u{1cf2d}', '\u{1cf30}'..='\u{1cf46}', + '\u{1d167}'..='\u{1d169}', '\u{1d173}'..='\u{1d182}', '\u{1d185}'..='\u{1d18b}', + '\u{1d1aa}'..='\u{1d1ad}', '\u{1d242}'..='\u{1d244}', '\u{1da00}'..='\u{1da36}', + '\u{1da3b}'..='\u{1da6c}', '\u{1da75}'..='\u{1da75}', '\u{1da84}'..='\u{1da84}', + '\u{1da9b}'..='\u{1da9f}', '\u{1daa1}'..='\u{1daaf}', '\u{1e000}'..='\u{1e006}', + '\u{1e008}'..='\u{1e018}', '\u{1e01b}'..='\u{1e021}', '\u{1e023}'..='\u{1e024}', + '\u{1e026}'..='\u{1e02a}', '\u{1e030}'..='\u{1e06d}', '\u{1e08f}'..='\u{1e08f}', + '\u{1e130}'..='\u{1e13d}', '\u{1e2ae}'..='\u{1e2ae}', '\u{1e2ec}'..='\u{1e2ef}', + '\u{1e4eb}'..='\u{1e4ef}', '\u{1e5ee}'..='\u{1e5ef}', '\u{1e6e3}'..='\u{1e6e3}', + '\u{1e6e6}'..='\u{1e6e6}', '\u{1e6ee}'..='\u{1e6ef}', '\u{1e6f5}'..='\u{1e6f5}', + '\u{1e6ff}'..='\u{1e6ff}', '\u{1e8d0}'..='\u{1e8d6}', '\u{1e944}'..='\u{1e94b}', + '\u{1f3fb}'..='\u{1f3ff}', '\u{e0001}'..='\u{e0001}', '\u{e0020}'..='\u{e007f}', + '\u{e0100}'..='\u{e01ef}', +]; + +#[rustfmt::skip] +pub(super) static CASED: &[RangeInclusive; 156] = &[ + '\u{aa}'..='\u{aa}', '\u{b5}'..='\u{b5}', '\u{ba}'..='\u{ba}', '\u{c0}'..='\u{d6}', + '\u{d8}'..='\u{f6}', '\u{f8}'..='\u{1ba}', '\u{1bc}'..='\u{1bf}', '\u{1c4}'..='\u{293}', + '\u{296}'..='\u{2b8}', '\u{2c0}'..='\u{2c1}', '\u{2e0}'..='\u{2e4}', '\u{345}'..='\u{345}', + '\u{370}'..='\u{373}', '\u{376}'..='\u{377}', '\u{37a}'..='\u{37d}', '\u{37f}'..='\u{37f}', + '\u{386}'..='\u{386}', '\u{388}'..='\u{38a}', '\u{38c}'..='\u{38c}', '\u{38e}'..='\u{3a1}', + '\u{3a3}'..='\u{3f5}', '\u{3f7}'..='\u{481}', '\u{48a}'..='\u{52f}', '\u{531}'..='\u{556}', + '\u{560}'..='\u{588}', '\u{10a0}'..='\u{10c5}', '\u{10c7}'..='\u{10c7}', + '\u{10cd}'..='\u{10cd}', '\u{10d0}'..='\u{10fa}', '\u{10fc}'..='\u{10ff}', + '\u{13a0}'..='\u{13f5}', '\u{13f8}'..='\u{13fd}', '\u{1c80}'..='\u{1c8a}', + '\u{1c90}'..='\u{1cba}', '\u{1cbd}'..='\u{1cbf}', '\u{1d00}'..='\u{1dbf}', + '\u{1e00}'..='\u{1f15}', '\u{1f18}'..='\u{1f1d}', '\u{1f20}'..='\u{1f45}', + '\u{1f48}'..='\u{1f4d}', '\u{1f50}'..='\u{1f57}', '\u{1f59}'..='\u{1f59}', + '\u{1f5b}'..='\u{1f5b}', '\u{1f5d}'..='\u{1f5d}', '\u{1f5f}'..='\u{1f7d}', + '\u{1f80}'..='\u{1fb4}', '\u{1fb6}'..='\u{1fbc}', '\u{1fbe}'..='\u{1fbe}', + '\u{1fc2}'..='\u{1fc4}', '\u{1fc6}'..='\u{1fcc}', '\u{1fd0}'..='\u{1fd3}', + '\u{1fd6}'..='\u{1fdb}', '\u{1fe0}'..='\u{1fec}', '\u{1ff2}'..='\u{1ff4}', + '\u{1ff6}'..='\u{1ffc}', '\u{2071}'..='\u{2071}', '\u{207f}'..='\u{207f}', + '\u{2090}'..='\u{209c}', '\u{2102}'..='\u{2102}', '\u{2107}'..='\u{2107}', + '\u{210a}'..='\u{2113}', '\u{2115}'..='\u{2115}', '\u{2119}'..='\u{211d}', + '\u{2124}'..='\u{2124}', '\u{2126}'..='\u{2126}', '\u{2128}'..='\u{2128}', + '\u{212a}'..='\u{212d}', '\u{212f}'..='\u{2134}', '\u{2139}'..='\u{2139}', + '\u{213c}'..='\u{213f}', '\u{2145}'..='\u{2149}', '\u{214e}'..='\u{214e}', + '\u{2160}'..='\u{217f}', '\u{2183}'..='\u{2184}', '\u{24b6}'..='\u{24e9}', + '\u{2c00}'..='\u{2ce4}', '\u{2ceb}'..='\u{2cee}', '\u{2cf2}'..='\u{2cf3}', + '\u{2d00}'..='\u{2d25}', '\u{2d27}'..='\u{2d27}', '\u{2d2d}'..='\u{2d2d}', + '\u{a640}'..='\u{a66d}', '\u{a680}'..='\u{a69d}', '\u{a722}'..='\u{a787}', + '\u{a78b}'..='\u{a78e}', '\u{a790}'..='\u{a7dc}', '\u{a7f1}'..='\u{a7f6}', + '\u{a7f8}'..='\u{a7fa}', '\u{ab30}'..='\u{ab5a}', '\u{ab5c}'..='\u{ab69}', + '\u{ab70}'..='\u{abbf}', '\u{fb00}'..='\u{fb06}', '\u{fb13}'..='\u{fb17}', + '\u{ff21}'..='\u{ff3a}', '\u{ff41}'..='\u{ff5a}', '\u{10400}'..='\u{1044f}', + '\u{104b0}'..='\u{104d3}', '\u{104d8}'..='\u{104fb}', '\u{10570}'..='\u{1057a}', + '\u{1057c}'..='\u{1058a}', '\u{1058c}'..='\u{10592}', '\u{10594}'..='\u{10595}', + '\u{10597}'..='\u{105a1}', '\u{105a3}'..='\u{105b1}', '\u{105b3}'..='\u{105b9}', + '\u{105bb}'..='\u{105bc}', '\u{10780}'..='\u{10780}', '\u{10783}'..='\u{10785}', + '\u{10787}'..='\u{107b0}', '\u{107b2}'..='\u{107ba}', '\u{10c80}'..='\u{10cb2}', + '\u{10cc0}'..='\u{10cf2}', '\u{10d50}'..='\u{10d65}', '\u{10d70}'..='\u{10d85}', + '\u{118a0}'..='\u{118df}', '\u{16e40}'..='\u{16e7f}', '\u{16ea0}'..='\u{16eb8}', + '\u{16ebb}'..='\u{16ed3}', '\u{1d400}'..='\u{1d454}', '\u{1d456}'..='\u{1d49c}', + '\u{1d49e}'..='\u{1d49f}', '\u{1d4a2}'..='\u{1d4a2}', '\u{1d4a5}'..='\u{1d4a6}', + '\u{1d4a9}'..='\u{1d4ac}', '\u{1d4ae}'..='\u{1d4b9}', '\u{1d4bb}'..='\u{1d4bb}', + '\u{1d4bd}'..='\u{1d4c3}', '\u{1d4c5}'..='\u{1d505}', '\u{1d507}'..='\u{1d50a}', + '\u{1d50d}'..='\u{1d514}', '\u{1d516}'..='\u{1d51c}', '\u{1d51e}'..='\u{1d539}', + '\u{1d53b}'..='\u{1d53e}', '\u{1d540}'..='\u{1d544}', '\u{1d546}'..='\u{1d546}', + '\u{1d54a}'..='\u{1d550}', '\u{1d552}'..='\u{1d6a5}', '\u{1d6a8}'..='\u{1d6c0}', + '\u{1d6c2}'..='\u{1d6da}', '\u{1d6dc}'..='\u{1d6fa}', '\u{1d6fc}'..='\u{1d714}', + '\u{1d716}'..='\u{1d734}', '\u{1d736}'..='\u{1d74e}', '\u{1d750}'..='\u{1d76e}', + '\u{1d770}'..='\u{1d788}', '\u{1d78a}'..='\u{1d7a8}', '\u{1d7aa}'..='\u{1d7c2}', + '\u{1d7c4}'..='\u{1d7cb}', '\u{1df00}'..='\u{1df09}', '\u{1df0b}'..='\u{1df1e}', + '\u{1df25}'..='\u{1df2a}', '\u{1e030}'..='\u{1e06d}', '\u{1e900}'..='\u{1e943}', + '\u{1f130}'..='\u{1f149}', '\u{1f150}'..='\u{1f169}', '\u{1f170}'..='\u{1f189}', +]; + +#[rustfmt::skip] +pub(super) static GRAPHEME_EXTEND: &[RangeInclusive; 383] = &[ + '\u{300}'..='\u{36f}', '\u{483}'..='\u{489}', '\u{591}'..='\u{5bd}', '\u{5bf}'..='\u{5bf}', + '\u{5c1}'..='\u{5c2}', '\u{5c4}'..='\u{5c5}', '\u{5c7}'..='\u{5c7}', '\u{610}'..='\u{61a}', + '\u{64b}'..='\u{65f}', '\u{670}'..='\u{670}', '\u{6d6}'..='\u{6dc}', '\u{6df}'..='\u{6e4}', + '\u{6e7}'..='\u{6e8}', '\u{6ea}'..='\u{6ed}', '\u{711}'..='\u{711}', '\u{730}'..='\u{74a}', + '\u{7a6}'..='\u{7b0}', '\u{7eb}'..='\u{7f3}', '\u{7fd}'..='\u{7fd}', '\u{816}'..='\u{819}', + '\u{81b}'..='\u{823}', '\u{825}'..='\u{827}', '\u{829}'..='\u{82d}', '\u{859}'..='\u{85b}', + '\u{897}'..='\u{89f}', '\u{8ca}'..='\u{8e1}', '\u{8e3}'..='\u{902}', '\u{93a}'..='\u{93a}', + '\u{93c}'..='\u{93c}', '\u{941}'..='\u{948}', '\u{94d}'..='\u{94d}', '\u{951}'..='\u{957}', + '\u{962}'..='\u{963}', '\u{981}'..='\u{981}', '\u{9bc}'..='\u{9bc}', '\u{9be}'..='\u{9be}', + '\u{9c1}'..='\u{9c4}', '\u{9cd}'..='\u{9cd}', '\u{9d7}'..='\u{9d7}', '\u{9e2}'..='\u{9e3}', + '\u{9fe}'..='\u{9fe}', '\u{a01}'..='\u{a02}', '\u{a3c}'..='\u{a3c}', '\u{a41}'..='\u{a42}', + '\u{a47}'..='\u{a48}', '\u{a4b}'..='\u{a4d}', '\u{a51}'..='\u{a51}', '\u{a70}'..='\u{a71}', + '\u{a75}'..='\u{a75}', '\u{a81}'..='\u{a82}', '\u{abc}'..='\u{abc}', '\u{ac1}'..='\u{ac5}', + '\u{ac7}'..='\u{ac8}', '\u{acd}'..='\u{acd}', '\u{ae2}'..='\u{ae3}', '\u{afa}'..='\u{aff}', + '\u{b01}'..='\u{b01}', '\u{b3c}'..='\u{b3c}', '\u{b3e}'..='\u{b3f}', '\u{b41}'..='\u{b44}', + '\u{b4d}'..='\u{b4d}', '\u{b55}'..='\u{b57}', '\u{b62}'..='\u{b63}', '\u{b82}'..='\u{b82}', + '\u{bbe}'..='\u{bbe}', '\u{bc0}'..='\u{bc0}', '\u{bcd}'..='\u{bcd}', '\u{bd7}'..='\u{bd7}', + '\u{c00}'..='\u{c00}', '\u{c04}'..='\u{c04}', '\u{c3c}'..='\u{c3c}', '\u{c3e}'..='\u{c40}', + '\u{c46}'..='\u{c48}', '\u{c4a}'..='\u{c4d}', '\u{c55}'..='\u{c56}', '\u{c62}'..='\u{c63}', + '\u{c81}'..='\u{c81}', '\u{cbc}'..='\u{cbc}', '\u{cbf}'..='\u{cc0}', '\u{cc2}'..='\u{cc2}', + '\u{cc6}'..='\u{cc8}', '\u{cca}'..='\u{ccd}', '\u{cd5}'..='\u{cd6}', '\u{ce2}'..='\u{ce3}', + '\u{d00}'..='\u{d01}', '\u{d3b}'..='\u{d3c}', '\u{d3e}'..='\u{d3e}', '\u{d41}'..='\u{d44}', + '\u{d4d}'..='\u{d4d}', '\u{d57}'..='\u{d57}', '\u{d62}'..='\u{d63}', '\u{d81}'..='\u{d81}', + '\u{dca}'..='\u{dca}', '\u{dcf}'..='\u{dcf}', '\u{dd2}'..='\u{dd4}', '\u{dd6}'..='\u{dd6}', + '\u{ddf}'..='\u{ddf}', '\u{e31}'..='\u{e31}', '\u{e34}'..='\u{e3a}', '\u{e47}'..='\u{e4e}', + '\u{eb1}'..='\u{eb1}', '\u{eb4}'..='\u{ebc}', '\u{ec8}'..='\u{ece}', '\u{f18}'..='\u{f19}', + '\u{f35}'..='\u{f35}', '\u{f37}'..='\u{f37}', '\u{f39}'..='\u{f39}', '\u{f71}'..='\u{f7e}', + '\u{f80}'..='\u{f84}', '\u{f86}'..='\u{f87}', '\u{f8d}'..='\u{f97}', '\u{f99}'..='\u{fbc}', + '\u{fc6}'..='\u{fc6}', '\u{102d}'..='\u{1030}', '\u{1032}'..='\u{1037}', + '\u{1039}'..='\u{103a}', '\u{103d}'..='\u{103e}', '\u{1058}'..='\u{1059}', + '\u{105e}'..='\u{1060}', '\u{1071}'..='\u{1074}', '\u{1082}'..='\u{1082}', + '\u{1085}'..='\u{1086}', '\u{108d}'..='\u{108d}', '\u{109d}'..='\u{109d}', + '\u{135d}'..='\u{135f}', '\u{1712}'..='\u{1715}', '\u{1732}'..='\u{1734}', + '\u{1752}'..='\u{1753}', '\u{1772}'..='\u{1773}', '\u{17b4}'..='\u{17b5}', + '\u{17b7}'..='\u{17bd}', '\u{17c6}'..='\u{17c6}', '\u{17c9}'..='\u{17d3}', + '\u{17dd}'..='\u{17dd}', '\u{180b}'..='\u{180d}', '\u{180f}'..='\u{180f}', + '\u{1885}'..='\u{1886}', '\u{18a9}'..='\u{18a9}', '\u{1920}'..='\u{1922}', + '\u{1927}'..='\u{1928}', '\u{1932}'..='\u{1932}', '\u{1939}'..='\u{193b}', + '\u{1a17}'..='\u{1a18}', '\u{1a1b}'..='\u{1a1b}', '\u{1a56}'..='\u{1a56}', + '\u{1a58}'..='\u{1a5e}', '\u{1a60}'..='\u{1a60}', '\u{1a62}'..='\u{1a62}', + '\u{1a65}'..='\u{1a6c}', '\u{1a73}'..='\u{1a7c}', '\u{1a7f}'..='\u{1a7f}', + '\u{1ab0}'..='\u{1add}', '\u{1ae0}'..='\u{1aeb}', '\u{1b00}'..='\u{1b03}', + '\u{1b34}'..='\u{1b3d}', '\u{1b42}'..='\u{1b44}', '\u{1b6b}'..='\u{1b73}', + '\u{1b80}'..='\u{1b81}', '\u{1ba2}'..='\u{1ba5}', '\u{1ba8}'..='\u{1bad}', + '\u{1be6}'..='\u{1be6}', '\u{1be8}'..='\u{1be9}', '\u{1bed}'..='\u{1bed}', + '\u{1bef}'..='\u{1bf3}', '\u{1c2c}'..='\u{1c33}', '\u{1c36}'..='\u{1c37}', + '\u{1cd0}'..='\u{1cd2}', '\u{1cd4}'..='\u{1ce0}', '\u{1ce2}'..='\u{1ce8}', + '\u{1ced}'..='\u{1ced}', '\u{1cf4}'..='\u{1cf4}', '\u{1cf8}'..='\u{1cf9}', + '\u{1dc0}'..='\u{1dff}', '\u{200c}'..='\u{200c}', '\u{20d0}'..='\u{20f0}', + '\u{2cef}'..='\u{2cf1}', '\u{2d7f}'..='\u{2d7f}', '\u{2de0}'..='\u{2dff}', + '\u{302a}'..='\u{302f}', '\u{3099}'..='\u{309a}', '\u{a66f}'..='\u{a672}', + '\u{a674}'..='\u{a67d}', '\u{a69e}'..='\u{a69f}', '\u{a6f0}'..='\u{a6f1}', + '\u{a802}'..='\u{a802}', '\u{a806}'..='\u{a806}', '\u{a80b}'..='\u{a80b}', + '\u{a825}'..='\u{a826}', '\u{a82c}'..='\u{a82c}', '\u{a8c4}'..='\u{a8c5}', + '\u{a8e0}'..='\u{a8f1}', '\u{a8ff}'..='\u{a8ff}', '\u{a926}'..='\u{a92d}', + '\u{a947}'..='\u{a951}', '\u{a953}'..='\u{a953}', '\u{a980}'..='\u{a982}', + '\u{a9b3}'..='\u{a9b3}', '\u{a9b6}'..='\u{a9b9}', '\u{a9bc}'..='\u{a9bd}', + '\u{a9c0}'..='\u{a9c0}', '\u{a9e5}'..='\u{a9e5}', '\u{aa29}'..='\u{aa2e}', + '\u{aa31}'..='\u{aa32}', '\u{aa35}'..='\u{aa36}', '\u{aa43}'..='\u{aa43}', + '\u{aa4c}'..='\u{aa4c}', '\u{aa7c}'..='\u{aa7c}', '\u{aab0}'..='\u{aab0}', + '\u{aab2}'..='\u{aab4}', '\u{aab7}'..='\u{aab8}', '\u{aabe}'..='\u{aabf}', + '\u{aac1}'..='\u{aac1}', '\u{aaec}'..='\u{aaed}', '\u{aaf6}'..='\u{aaf6}', + '\u{abe5}'..='\u{abe5}', '\u{abe8}'..='\u{abe8}', '\u{abed}'..='\u{abed}', + '\u{fb1e}'..='\u{fb1e}', '\u{fe00}'..='\u{fe0f}', '\u{fe20}'..='\u{fe2f}', + '\u{ff9e}'..='\u{ff9f}', '\u{101fd}'..='\u{101fd}', '\u{102e0}'..='\u{102e0}', + '\u{10376}'..='\u{1037a}', '\u{10a01}'..='\u{10a03}', '\u{10a05}'..='\u{10a06}', + '\u{10a0c}'..='\u{10a0f}', '\u{10a38}'..='\u{10a3a}', '\u{10a3f}'..='\u{10a3f}', + '\u{10ae5}'..='\u{10ae6}', '\u{10d24}'..='\u{10d27}', '\u{10d69}'..='\u{10d6d}', + '\u{10eab}'..='\u{10eac}', '\u{10efa}'..='\u{10eff}', '\u{10f46}'..='\u{10f50}', + '\u{10f82}'..='\u{10f85}', '\u{11001}'..='\u{11001}', '\u{11038}'..='\u{11046}', + '\u{11070}'..='\u{11070}', '\u{11073}'..='\u{11074}', '\u{1107f}'..='\u{11081}', + '\u{110b3}'..='\u{110b6}', '\u{110b9}'..='\u{110ba}', '\u{110c2}'..='\u{110c2}', + '\u{11100}'..='\u{11102}', '\u{11127}'..='\u{1112b}', '\u{1112d}'..='\u{11134}', + '\u{11173}'..='\u{11173}', '\u{11180}'..='\u{11181}', '\u{111b6}'..='\u{111be}', + '\u{111c0}'..='\u{111c0}', '\u{111c9}'..='\u{111cc}', '\u{111cf}'..='\u{111cf}', + '\u{1122f}'..='\u{11231}', '\u{11234}'..='\u{11237}', '\u{1123e}'..='\u{1123e}', + '\u{11241}'..='\u{11241}', '\u{112df}'..='\u{112df}', '\u{112e3}'..='\u{112ea}', + '\u{11300}'..='\u{11301}', '\u{1133b}'..='\u{1133c}', '\u{1133e}'..='\u{1133e}', + '\u{11340}'..='\u{11340}', '\u{1134d}'..='\u{1134d}', '\u{11357}'..='\u{11357}', + '\u{11366}'..='\u{1136c}', '\u{11370}'..='\u{11374}', '\u{113b8}'..='\u{113b8}', + '\u{113bb}'..='\u{113c0}', '\u{113c2}'..='\u{113c2}', '\u{113c5}'..='\u{113c5}', + '\u{113c7}'..='\u{113c9}', '\u{113ce}'..='\u{113d0}', '\u{113d2}'..='\u{113d2}', + '\u{113e1}'..='\u{113e2}', '\u{11438}'..='\u{1143f}', '\u{11442}'..='\u{11444}', + '\u{11446}'..='\u{11446}', '\u{1145e}'..='\u{1145e}', '\u{114b0}'..='\u{114b0}', + '\u{114b3}'..='\u{114b8}', '\u{114ba}'..='\u{114ba}', '\u{114bd}'..='\u{114bd}', + '\u{114bf}'..='\u{114c0}', '\u{114c2}'..='\u{114c3}', '\u{115af}'..='\u{115af}', + '\u{115b2}'..='\u{115b5}', '\u{115bc}'..='\u{115bd}', '\u{115bf}'..='\u{115c0}', + '\u{115dc}'..='\u{115dd}', '\u{11633}'..='\u{1163a}', '\u{1163d}'..='\u{1163d}', + '\u{1163f}'..='\u{11640}', '\u{116ab}'..='\u{116ab}', '\u{116ad}'..='\u{116ad}', + '\u{116b0}'..='\u{116b7}', '\u{1171d}'..='\u{1171d}', '\u{1171f}'..='\u{1171f}', + '\u{11722}'..='\u{11725}', '\u{11727}'..='\u{1172b}', '\u{1182f}'..='\u{11837}', + '\u{11839}'..='\u{1183a}', '\u{11930}'..='\u{11930}', '\u{1193b}'..='\u{1193e}', + '\u{11943}'..='\u{11943}', '\u{119d4}'..='\u{119d7}', '\u{119da}'..='\u{119db}', + '\u{119e0}'..='\u{119e0}', '\u{11a01}'..='\u{11a0a}', '\u{11a33}'..='\u{11a38}', + '\u{11a3b}'..='\u{11a3e}', '\u{11a47}'..='\u{11a47}', '\u{11a51}'..='\u{11a56}', + '\u{11a59}'..='\u{11a5b}', '\u{11a8a}'..='\u{11a96}', '\u{11a98}'..='\u{11a99}', + '\u{11b60}'..='\u{11b60}', '\u{11b62}'..='\u{11b64}', '\u{11b66}'..='\u{11b66}', + '\u{11c30}'..='\u{11c36}', '\u{11c38}'..='\u{11c3d}', '\u{11c3f}'..='\u{11c3f}', + '\u{11c92}'..='\u{11ca7}', '\u{11caa}'..='\u{11cb0}', '\u{11cb2}'..='\u{11cb3}', + '\u{11cb5}'..='\u{11cb6}', '\u{11d31}'..='\u{11d36}', '\u{11d3a}'..='\u{11d3a}', + '\u{11d3c}'..='\u{11d3d}', '\u{11d3f}'..='\u{11d45}', '\u{11d47}'..='\u{11d47}', + '\u{11d90}'..='\u{11d91}', '\u{11d95}'..='\u{11d95}', '\u{11d97}'..='\u{11d97}', + '\u{11ef3}'..='\u{11ef4}', '\u{11f00}'..='\u{11f01}', '\u{11f36}'..='\u{11f3a}', + '\u{11f40}'..='\u{11f42}', '\u{11f5a}'..='\u{11f5a}', '\u{13440}'..='\u{13440}', + '\u{13447}'..='\u{13455}', '\u{1611e}'..='\u{16129}', '\u{1612d}'..='\u{1612f}', + '\u{16af0}'..='\u{16af4}', '\u{16b30}'..='\u{16b36}', '\u{16f4f}'..='\u{16f4f}', + '\u{16f8f}'..='\u{16f92}', '\u{16fe4}'..='\u{16fe4}', '\u{16ff0}'..='\u{16ff1}', + '\u{1bc9d}'..='\u{1bc9e}', '\u{1cf00}'..='\u{1cf2d}', '\u{1cf30}'..='\u{1cf46}', + '\u{1d165}'..='\u{1d169}', '\u{1d16d}'..='\u{1d172}', '\u{1d17b}'..='\u{1d182}', + '\u{1d185}'..='\u{1d18b}', '\u{1d1aa}'..='\u{1d1ad}', '\u{1d242}'..='\u{1d244}', + '\u{1da00}'..='\u{1da36}', '\u{1da3b}'..='\u{1da6c}', '\u{1da75}'..='\u{1da75}', + '\u{1da84}'..='\u{1da84}', '\u{1da9b}'..='\u{1da9f}', '\u{1daa1}'..='\u{1daaf}', + '\u{1e000}'..='\u{1e006}', '\u{1e008}'..='\u{1e018}', '\u{1e01b}'..='\u{1e021}', + '\u{1e023}'..='\u{1e024}', '\u{1e026}'..='\u{1e02a}', '\u{1e08f}'..='\u{1e08f}', + '\u{1e130}'..='\u{1e136}', '\u{1e2ae}'..='\u{1e2ae}', '\u{1e2ec}'..='\u{1e2ef}', + '\u{1e4ec}'..='\u{1e4ef}', '\u{1e5ee}'..='\u{1e5ef}', '\u{1e6e3}'..='\u{1e6e3}', + '\u{1e6e6}'..='\u{1e6e6}', '\u{1e6ee}'..='\u{1e6ef}', '\u{1e6f5}'..='\u{1e6f5}', + '\u{1e8d0}'..='\u{1e8d6}', '\u{1e944}'..='\u{1e94a}', '\u{e0020}'..='\u{e007f}', + '\u{e0100}'..='\u{e01ef}', +]; + +#[rustfmt::skip] +pub(super) static LOWERCASE: &[RangeInclusive; 676] = &[ + '\u{aa}'..='\u{aa}', '\u{b5}'..='\u{b5}', '\u{ba}'..='\u{ba}', '\u{df}'..='\u{f6}', + '\u{f8}'..='\u{ff}', '\u{101}'..='\u{101}', '\u{103}'..='\u{103}', '\u{105}'..='\u{105}', + '\u{107}'..='\u{107}', '\u{109}'..='\u{109}', '\u{10b}'..='\u{10b}', '\u{10d}'..='\u{10d}', + '\u{10f}'..='\u{10f}', '\u{111}'..='\u{111}', '\u{113}'..='\u{113}', '\u{115}'..='\u{115}', + '\u{117}'..='\u{117}', '\u{119}'..='\u{119}', '\u{11b}'..='\u{11b}', '\u{11d}'..='\u{11d}', + '\u{11f}'..='\u{11f}', '\u{121}'..='\u{121}', '\u{123}'..='\u{123}', '\u{125}'..='\u{125}', + '\u{127}'..='\u{127}', '\u{129}'..='\u{129}', '\u{12b}'..='\u{12b}', '\u{12d}'..='\u{12d}', + '\u{12f}'..='\u{12f}', '\u{131}'..='\u{131}', '\u{133}'..='\u{133}', '\u{135}'..='\u{135}', + '\u{137}'..='\u{138}', '\u{13a}'..='\u{13a}', '\u{13c}'..='\u{13c}', '\u{13e}'..='\u{13e}', + '\u{140}'..='\u{140}', '\u{142}'..='\u{142}', '\u{144}'..='\u{144}', '\u{146}'..='\u{146}', + '\u{148}'..='\u{149}', '\u{14b}'..='\u{14b}', '\u{14d}'..='\u{14d}', '\u{14f}'..='\u{14f}', + '\u{151}'..='\u{151}', '\u{153}'..='\u{153}', '\u{155}'..='\u{155}', '\u{157}'..='\u{157}', + '\u{159}'..='\u{159}', '\u{15b}'..='\u{15b}', '\u{15d}'..='\u{15d}', '\u{15f}'..='\u{15f}', + '\u{161}'..='\u{161}', '\u{163}'..='\u{163}', '\u{165}'..='\u{165}', '\u{167}'..='\u{167}', + '\u{169}'..='\u{169}', '\u{16b}'..='\u{16b}', '\u{16d}'..='\u{16d}', '\u{16f}'..='\u{16f}', + '\u{171}'..='\u{171}', '\u{173}'..='\u{173}', '\u{175}'..='\u{175}', '\u{177}'..='\u{177}', + '\u{17a}'..='\u{17a}', '\u{17c}'..='\u{17c}', '\u{17e}'..='\u{180}', '\u{183}'..='\u{183}', + '\u{185}'..='\u{185}', '\u{188}'..='\u{188}', '\u{18c}'..='\u{18d}', '\u{192}'..='\u{192}', + '\u{195}'..='\u{195}', '\u{199}'..='\u{19b}', '\u{19e}'..='\u{19e}', '\u{1a1}'..='\u{1a1}', + '\u{1a3}'..='\u{1a3}', '\u{1a5}'..='\u{1a5}', '\u{1a8}'..='\u{1a8}', '\u{1aa}'..='\u{1ab}', + '\u{1ad}'..='\u{1ad}', '\u{1b0}'..='\u{1b0}', '\u{1b4}'..='\u{1b4}', '\u{1b6}'..='\u{1b6}', + '\u{1b9}'..='\u{1ba}', '\u{1bd}'..='\u{1bf}', '\u{1c6}'..='\u{1c6}', '\u{1c9}'..='\u{1c9}', + '\u{1cc}'..='\u{1cc}', '\u{1ce}'..='\u{1ce}', '\u{1d0}'..='\u{1d0}', '\u{1d2}'..='\u{1d2}', + '\u{1d4}'..='\u{1d4}', '\u{1d6}'..='\u{1d6}', '\u{1d8}'..='\u{1d8}', '\u{1da}'..='\u{1da}', + '\u{1dc}'..='\u{1dd}', '\u{1df}'..='\u{1df}', '\u{1e1}'..='\u{1e1}', '\u{1e3}'..='\u{1e3}', + '\u{1e5}'..='\u{1e5}', '\u{1e7}'..='\u{1e7}', '\u{1e9}'..='\u{1e9}', '\u{1eb}'..='\u{1eb}', + '\u{1ed}'..='\u{1ed}', '\u{1ef}'..='\u{1f0}', '\u{1f3}'..='\u{1f3}', '\u{1f5}'..='\u{1f5}', + '\u{1f9}'..='\u{1f9}', '\u{1fb}'..='\u{1fb}', '\u{1fd}'..='\u{1fd}', '\u{1ff}'..='\u{1ff}', + '\u{201}'..='\u{201}', '\u{203}'..='\u{203}', '\u{205}'..='\u{205}', '\u{207}'..='\u{207}', + '\u{209}'..='\u{209}', '\u{20b}'..='\u{20b}', '\u{20d}'..='\u{20d}', '\u{20f}'..='\u{20f}', + '\u{211}'..='\u{211}', '\u{213}'..='\u{213}', '\u{215}'..='\u{215}', '\u{217}'..='\u{217}', + '\u{219}'..='\u{219}', '\u{21b}'..='\u{21b}', '\u{21d}'..='\u{21d}', '\u{21f}'..='\u{21f}', + '\u{221}'..='\u{221}', '\u{223}'..='\u{223}', '\u{225}'..='\u{225}', '\u{227}'..='\u{227}', + '\u{229}'..='\u{229}', '\u{22b}'..='\u{22b}', '\u{22d}'..='\u{22d}', '\u{22f}'..='\u{22f}', + '\u{231}'..='\u{231}', '\u{233}'..='\u{239}', '\u{23c}'..='\u{23c}', '\u{23f}'..='\u{240}', + '\u{242}'..='\u{242}', '\u{247}'..='\u{247}', '\u{249}'..='\u{249}', '\u{24b}'..='\u{24b}', + '\u{24d}'..='\u{24d}', '\u{24f}'..='\u{293}', '\u{296}'..='\u{2b8}', '\u{2c0}'..='\u{2c1}', + '\u{2e0}'..='\u{2e4}', '\u{345}'..='\u{345}', '\u{371}'..='\u{371}', '\u{373}'..='\u{373}', + '\u{377}'..='\u{377}', '\u{37a}'..='\u{37d}', '\u{390}'..='\u{390}', '\u{3ac}'..='\u{3ce}', + '\u{3d0}'..='\u{3d1}', '\u{3d5}'..='\u{3d7}', '\u{3d9}'..='\u{3d9}', '\u{3db}'..='\u{3db}', + '\u{3dd}'..='\u{3dd}', '\u{3df}'..='\u{3df}', '\u{3e1}'..='\u{3e1}', '\u{3e3}'..='\u{3e3}', + '\u{3e5}'..='\u{3e5}', '\u{3e7}'..='\u{3e7}', '\u{3e9}'..='\u{3e9}', '\u{3eb}'..='\u{3eb}', + '\u{3ed}'..='\u{3ed}', '\u{3ef}'..='\u{3f3}', '\u{3f5}'..='\u{3f5}', '\u{3f8}'..='\u{3f8}', + '\u{3fb}'..='\u{3fc}', '\u{430}'..='\u{45f}', '\u{461}'..='\u{461}', '\u{463}'..='\u{463}', + '\u{465}'..='\u{465}', '\u{467}'..='\u{467}', '\u{469}'..='\u{469}', '\u{46b}'..='\u{46b}', + '\u{46d}'..='\u{46d}', '\u{46f}'..='\u{46f}', '\u{471}'..='\u{471}', '\u{473}'..='\u{473}', + '\u{475}'..='\u{475}', '\u{477}'..='\u{477}', '\u{479}'..='\u{479}', '\u{47b}'..='\u{47b}', + '\u{47d}'..='\u{47d}', '\u{47f}'..='\u{47f}', '\u{481}'..='\u{481}', '\u{48b}'..='\u{48b}', + '\u{48d}'..='\u{48d}', '\u{48f}'..='\u{48f}', '\u{491}'..='\u{491}', '\u{493}'..='\u{493}', + '\u{495}'..='\u{495}', '\u{497}'..='\u{497}', '\u{499}'..='\u{499}', '\u{49b}'..='\u{49b}', + '\u{49d}'..='\u{49d}', '\u{49f}'..='\u{49f}', '\u{4a1}'..='\u{4a1}', '\u{4a3}'..='\u{4a3}', + '\u{4a5}'..='\u{4a5}', '\u{4a7}'..='\u{4a7}', '\u{4a9}'..='\u{4a9}', '\u{4ab}'..='\u{4ab}', + '\u{4ad}'..='\u{4ad}', '\u{4af}'..='\u{4af}', '\u{4b1}'..='\u{4b1}', '\u{4b3}'..='\u{4b3}', + '\u{4b5}'..='\u{4b5}', '\u{4b7}'..='\u{4b7}', '\u{4b9}'..='\u{4b9}', '\u{4bb}'..='\u{4bb}', + '\u{4bd}'..='\u{4bd}', '\u{4bf}'..='\u{4bf}', '\u{4c2}'..='\u{4c2}', '\u{4c4}'..='\u{4c4}', + '\u{4c6}'..='\u{4c6}', '\u{4c8}'..='\u{4c8}', '\u{4ca}'..='\u{4ca}', '\u{4cc}'..='\u{4cc}', + '\u{4ce}'..='\u{4cf}', '\u{4d1}'..='\u{4d1}', '\u{4d3}'..='\u{4d3}', '\u{4d5}'..='\u{4d5}', + '\u{4d7}'..='\u{4d7}', '\u{4d9}'..='\u{4d9}', '\u{4db}'..='\u{4db}', '\u{4dd}'..='\u{4dd}', + '\u{4df}'..='\u{4df}', '\u{4e1}'..='\u{4e1}', '\u{4e3}'..='\u{4e3}', '\u{4e5}'..='\u{4e5}', + '\u{4e7}'..='\u{4e7}', '\u{4e9}'..='\u{4e9}', '\u{4eb}'..='\u{4eb}', '\u{4ed}'..='\u{4ed}', + '\u{4ef}'..='\u{4ef}', '\u{4f1}'..='\u{4f1}', '\u{4f3}'..='\u{4f3}', '\u{4f5}'..='\u{4f5}', + '\u{4f7}'..='\u{4f7}', '\u{4f9}'..='\u{4f9}', '\u{4fb}'..='\u{4fb}', '\u{4fd}'..='\u{4fd}', + '\u{4ff}'..='\u{4ff}', '\u{501}'..='\u{501}', '\u{503}'..='\u{503}', '\u{505}'..='\u{505}', + '\u{507}'..='\u{507}', '\u{509}'..='\u{509}', '\u{50b}'..='\u{50b}', '\u{50d}'..='\u{50d}', + '\u{50f}'..='\u{50f}', '\u{511}'..='\u{511}', '\u{513}'..='\u{513}', '\u{515}'..='\u{515}', + '\u{517}'..='\u{517}', '\u{519}'..='\u{519}', '\u{51b}'..='\u{51b}', '\u{51d}'..='\u{51d}', + '\u{51f}'..='\u{51f}', '\u{521}'..='\u{521}', '\u{523}'..='\u{523}', '\u{525}'..='\u{525}', + '\u{527}'..='\u{527}', '\u{529}'..='\u{529}', '\u{52b}'..='\u{52b}', '\u{52d}'..='\u{52d}', + '\u{52f}'..='\u{52f}', '\u{560}'..='\u{588}', '\u{10d0}'..='\u{10fa}', + '\u{10fc}'..='\u{10ff}', '\u{13f8}'..='\u{13fd}', '\u{1c80}'..='\u{1c88}', + '\u{1c8a}'..='\u{1c8a}', '\u{1d00}'..='\u{1dbf}', '\u{1e01}'..='\u{1e01}', + '\u{1e03}'..='\u{1e03}', '\u{1e05}'..='\u{1e05}', '\u{1e07}'..='\u{1e07}', + '\u{1e09}'..='\u{1e09}', '\u{1e0b}'..='\u{1e0b}', '\u{1e0d}'..='\u{1e0d}', + '\u{1e0f}'..='\u{1e0f}', '\u{1e11}'..='\u{1e11}', '\u{1e13}'..='\u{1e13}', + '\u{1e15}'..='\u{1e15}', '\u{1e17}'..='\u{1e17}', '\u{1e19}'..='\u{1e19}', + '\u{1e1b}'..='\u{1e1b}', '\u{1e1d}'..='\u{1e1d}', '\u{1e1f}'..='\u{1e1f}', + '\u{1e21}'..='\u{1e21}', '\u{1e23}'..='\u{1e23}', '\u{1e25}'..='\u{1e25}', + '\u{1e27}'..='\u{1e27}', '\u{1e29}'..='\u{1e29}', '\u{1e2b}'..='\u{1e2b}', + '\u{1e2d}'..='\u{1e2d}', '\u{1e2f}'..='\u{1e2f}', '\u{1e31}'..='\u{1e31}', + '\u{1e33}'..='\u{1e33}', '\u{1e35}'..='\u{1e35}', '\u{1e37}'..='\u{1e37}', + '\u{1e39}'..='\u{1e39}', '\u{1e3b}'..='\u{1e3b}', '\u{1e3d}'..='\u{1e3d}', + '\u{1e3f}'..='\u{1e3f}', '\u{1e41}'..='\u{1e41}', '\u{1e43}'..='\u{1e43}', + '\u{1e45}'..='\u{1e45}', '\u{1e47}'..='\u{1e47}', '\u{1e49}'..='\u{1e49}', + '\u{1e4b}'..='\u{1e4b}', '\u{1e4d}'..='\u{1e4d}', '\u{1e4f}'..='\u{1e4f}', + '\u{1e51}'..='\u{1e51}', '\u{1e53}'..='\u{1e53}', '\u{1e55}'..='\u{1e55}', + '\u{1e57}'..='\u{1e57}', '\u{1e59}'..='\u{1e59}', '\u{1e5b}'..='\u{1e5b}', + '\u{1e5d}'..='\u{1e5d}', '\u{1e5f}'..='\u{1e5f}', '\u{1e61}'..='\u{1e61}', + '\u{1e63}'..='\u{1e63}', '\u{1e65}'..='\u{1e65}', '\u{1e67}'..='\u{1e67}', + '\u{1e69}'..='\u{1e69}', '\u{1e6b}'..='\u{1e6b}', '\u{1e6d}'..='\u{1e6d}', + '\u{1e6f}'..='\u{1e6f}', '\u{1e71}'..='\u{1e71}', '\u{1e73}'..='\u{1e73}', + '\u{1e75}'..='\u{1e75}', '\u{1e77}'..='\u{1e77}', '\u{1e79}'..='\u{1e79}', + '\u{1e7b}'..='\u{1e7b}', '\u{1e7d}'..='\u{1e7d}', '\u{1e7f}'..='\u{1e7f}', + '\u{1e81}'..='\u{1e81}', '\u{1e83}'..='\u{1e83}', '\u{1e85}'..='\u{1e85}', + '\u{1e87}'..='\u{1e87}', '\u{1e89}'..='\u{1e89}', '\u{1e8b}'..='\u{1e8b}', + '\u{1e8d}'..='\u{1e8d}', '\u{1e8f}'..='\u{1e8f}', '\u{1e91}'..='\u{1e91}', + '\u{1e93}'..='\u{1e93}', '\u{1e95}'..='\u{1e9d}', '\u{1e9f}'..='\u{1e9f}', + '\u{1ea1}'..='\u{1ea1}', '\u{1ea3}'..='\u{1ea3}', '\u{1ea5}'..='\u{1ea5}', + '\u{1ea7}'..='\u{1ea7}', '\u{1ea9}'..='\u{1ea9}', '\u{1eab}'..='\u{1eab}', + '\u{1ead}'..='\u{1ead}', '\u{1eaf}'..='\u{1eaf}', '\u{1eb1}'..='\u{1eb1}', + '\u{1eb3}'..='\u{1eb3}', '\u{1eb5}'..='\u{1eb5}', '\u{1eb7}'..='\u{1eb7}', + '\u{1eb9}'..='\u{1eb9}', '\u{1ebb}'..='\u{1ebb}', '\u{1ebd}'..='\u{1ebd}', + '\u{1ebf}'..='\u{1ebf}', '\u{1ec1}'..='\u{1ec1}', '\u{1ec3}'..='\u{1ec3}', + '\u{1ec5}'..='\u{1ec5}', '\u{1ec7}'..='\u{1ec7}', '\u{1ec9}'..='\u{1ec9}', + '\u{1ecb}'..='\u{1ecb}', '\u{1ecd}'..='\u{1ecd}', '\u{1ecf}'..='\u{1ecf}', + '\u{1ed1}'..='\u{1ed1}', '\u{1ed3}'..='\u{1ed3}', '\u{1ed5}'..='\u{1ed5}', + '\u{1ed7}'..='\u{1ed7}', '\u{1ed9}'..='\u{1ed9}', '\u{1edb}'..='\u{1edb}', + '\u{1edd}'..='\u{1edd}', '\u{1edf}'..='\u{1edf}', '\u{1ee1}'..='\u{1ee1}', + '\u{1ee3}'..='\u{1ee3}', '\u{1ee5}'..='\u{1ee5}', '\u{1ee7}'..='\u{1ee7}', + '\u{1ee9}'..='\u{1ee9}', '\u{1eeb}'..='\u{1eeb}', '\u{1eed}'..='\u{1eed}', + '\u{1eef}'..='\u{1eef}', '\u{1ef1}'..='\u{1ef1}', '\u{1ef3}'..='\u{1ef3}', + '\u{1ef5}'..='\u{1ef5}', '\u{1ef7}'..='\u{1ef7}', '\u{1ef9}'..='\u{1ef9}', + '\u{1efb}'..='\u{1efb}', '\u{1efd}'..='\u{1efd}', '\u{1eff}'..='\u{1f07}', + '\u{1f10}'..='\u{1f15}', '\u{1f20}'..='\u{1f27}', '\u{1f30}'..='\u{1f37}', + '\u{1f40}'..='\u{1f45}', '\u{1f50}'..='\u{1f57}', '\u{1f60}'..='\u{1f67}', + '\u{1f70}'..='\u{1f7d}', '\u{1f80}'..='\u{1f87}', '\u{1f90}'..='\u{1f97}', + '\u{1fa0}'..='\u{1fa7}', '\u{1fb0}'..='\u{1fb4}', '\u{1fb6}'..='\u{1fb7}', + '\u{1fbe}'..='\u{1fbe}', '\u{1fc2}'..='\u{1fc4}', '\u{1fc6}'..='\u{1fc7}', + '\u{1fd0}'..='\u{1fd3}', '\u{1fd6}'..='\u{1fd7}', '\u{1fe0}'..='\u{1fe7}', + '\u{1ff2}'..='\u{1ff4}', '\u{1ff6}'..='\u{1ff7}', '\u{2071}'..='\u{2071}', + '\u{207f}'..='\u{207f}', '\u{2090}'..='\u{209c}', '\u{210a}'..='\u{210a}', + '\u{210e}'..='\u{210f}', '\u{2113}'..='\u{2113}', '\u{212f}'..='\u{212f}', + '\u{2134}'..='\u{2134}', '\u{2139}'..='\u{2139}', '\u{213c}'..='\u{213d}', + '\u{2146}'..='\u{2149}', '\u{214e}'..='\u{214e}', '\u{2170}'..='\u{217f}', + '\u{2184}'..='\u{2184}', '\u{24d0}'..='\u{24e9}', '\u{2c30}'..='\u{2c5f}', + '\u{2c61}'..='\u{2c61}', '\u{2c65}'..='\u{2c66}', '\u{2c68}'..='\u{2c68}', + '\u{2c6a}'..='\u{2c6a}', '\u{2c6c}'..='\u{2c6c}', '\u{2c71}'..='\u{2c71}', + '\u{2c73}'..='\u{2c74}', '\u{2c76}'..='\u{2c7d}', '\u{2c81}'..='\u{2c81}', + '\u{2c83}'..='\u{2c83}', '\u{2c85}'..='\u{2c85}', '\u{2c87}'..='\u{2c87}', + '\u{2c89}'..='\u{2c89}', '\u{2c8b}'..='\u{2c8b}', '\u{2c8d}'..='\u{2c8d}', + '\u{2c8f}'..='\u{2c8f}', '\u{2c91}'..='\u{2c91}', '\u{2c93}'..='\u{2c93}', + '\u{2c95}'..='\u{2c95}', '\u{2c97}'..='\u{2c97}', '\u{2c99}'..='\u{2c99}', + '\u{2c9b}'..='\u{2c9b}', '\u{2c9d}'..='\u{2c9d}', '\u{2c9f}'..='\u{2c9f}', + '\u{2ca1}'..='\u{2ca1}', '\u{2ca3}'..='\u{2ca3}', '\u{2ca5}'..='\u{2ca5}', + '\u{2ca7}'..='\u{2ca7}', '\u{2ca9}'..='\u{2ca9}', '\u{2cab}'..='\u{2cab}', + '\u{2cad}'..='\u{2cad}', '\u{2caf}'..='\u{2caf}', '\u{2cb1}'..='\u{2cb1}', + '\u{2cb3}'..='\u{2cb3}', '\u{2cb5}'..='\u{2cb5}', '\u{2cb7}'..='\u{2cb7}', + '\u{2cb9}'..='\u{2cb9}', '\u{2cbb}'..='\u{2cbb}', '\u{2cbd}'..='\u{2cbd}', + '\u{2cbf}'..='\u{2cbf}', '\u{2cc1}'..='\u{2cc1}', '\u{2cc3}'..='\u{2cc3}', + '\u{2cc5}'..='\u{2cc5}', '\u{2cc7}'..='\u{2cc7}', '\u{2cc9}'..='\u{2cc9}', + '\u{2ccb}'..='\u{2ccb}', '\u{2ccd}'..='\u{2ccd}', '\u{2ccf}'..='\u{2ccf}', + '\u{2cd1}'..='\u{2cd1}', '\u{2cd3}'..='\u{2cd3}', '\u{2cd5}'..='\u{2cd5}', + '\u{2cd7}'..='\u{2cd7}', '\u{2cd9}'..='\u{2cd9}', '\u{2cdb}'..='\u{2cdb}', + '\u{2cdd}'..='\u{2cdd}', '\u{2cdf}'..='\u{2cdf}', '\u{2ce1}'..='\u{2ce1}', + '\u{2ce3}'..='\u{2ce4}', '\u{2cec}'..='\u{2cec}', '\u{2cee}'..='\u{2cee}', + '\u{2cf3}'..='\u{2cf3}', '\u{2d00}'..='\u{2d25}', '\u{2d27}'..='\u{2d27}', + '\u{2d2d}'..='\u{2d2d}', '\u{a641}'..='\u{a641}', '\u{a643}'..='\u{a643}', + '\u{a645}'..='\u{a645}', '\u{a647}'..='\u{a647}', '\u{a649}'..='\u{a649}', + '\u{a64b}'..='\u{a64b}', '\u{a64d}'..='\u{a64d}', '\u{a64f}'..='\u{a64f}', + '\u{a651}'..='\u{a651}', '\u{a653}'..='\u{a653}', '\u{a655}'..='\u{a655}', + '\u{a657}'..='\u{a657}', '\u{a659}'..='\u{a659}', '\u{a65b}'..='\u{a65b}', + '\u{a65d}'..='\u{a65d}', '\u{a65f}'..='\u{a65f}', '\u{a661}'..='\u{a661}', + '\u{a663}'..='\u{a663}', '\u{a665}'..='\u{a665}', '\u{a667}'..='\u{a667}', + '\u{a669}'..='\u{a669}', '\u{a66b}'..='\u{a66b}', '\u{a66d}'..='\u{a66d}', + '\u{a681}'..='\u{a681}', '\u{a683}'..='\u{a683}', '\u{a685}'..='\u{a685}', + '\u{a687}'..='\u{a687}', '\u{a689}'..='\u{a689}', '\u{a68b}'..='\u{a68b}', + '\u{a68d}'..='\u{a68d}', '\u{a68f}'..='\u{a68f}', '\u{a691}'..='\u{a691}', + '\u{a693}'..='\u{a693}', '\u{a695}'..='\u{a695}', '\u{a697}'..='\u{a697}', + '\u{a699}'..='\u{a699}', '\u{a69b}'..='\u{a69d}', '\u{a723}'..='\u{a723}', + '\u{a725}'..='\u{a725}', '\u{a727}'..='\u{a727}', '\u{a729}'..='\u{a729}', + '\u{a72b}'..='\u{a72b}', '\u{a72d}'..='\u{a72d}', '\u{a72f}'..='\u{a731}', + '\u{a733}'..='\u{a733}', '\u{a735}'..='\u{a735}', '\u{a737}'..='\u{a737}', + '\u{a739}'..='\u{a739}', '\u{a73b}'..='\u{a73b}', '\u{a73d}'..='\u{a73d}', + '\u{a73f}'..='\u{a73f}', '\u{a741}'..='\u{a741}', '\u{a743}'..='\u{a743}', + '\u{a745}'..='\u{a745}', '\u{a747}'..='\u{a747}', '\u{a749}'..='\u{a749}', + '\u{a74b}'..='\u{a74b}', '\u{a74d}'..='\u{a74d}', '\u{a74f}'..='\u{a74f}', + '\u{a751}'..='\u{a751}', '\u{a753}'..='\u{a753}', '\u{a755}'..='\u{a755}', + '\u{a757}'..='\u{a757}', '\u{a759}'..='\u{a759}', '\u{a75b}'..='\u{a75b}', + '\u{a75d}'..='\u{a75d}', '\u{a75f}'..='\u{a75f}', '\u{a761}'..='\u{a761}', + '\u{a763}'..='\u{a763}', '\u{a765}'..='\u{a765}', '\u{a767}'..='\u{a767}', + '\u{a769}'..='\u{a769}', '\u{a76b}'..='\u{a76b}', '\u{a76d}'..='\u{a76d}', + '\u{a76f}'..='\u{a778}', '\u{a77a}'..='\u{a77a}', '\u{a77c}'..='\u{a77c}', + '\u{a77f}'..='\u{a77f}', '\u{a781}'..='\u{a781}', '\u{a783}'..='\u{a783}', + '\u{a785}'..='\u{a785}', '\u{a787}'..='\u{a787}', '\u{a78c}'..='\u{a78c}', + '\u{a78e}'..='\u{a78e}', '\u{a791}'..='\u{a791}', '\u{a793}'..='\u{a795}', + '\u{a797}'..='\u{a797}', '\u{a799}'..='\u{a799}', '\u{a79b}'..='\u{a79b}', + '\u{a79d}'..='\u{a79d}', '\u{a79f}'..='\u{a79f}', '\u{a7a1}'..='\u{a7a1}', + '\u{a7a3}'..='\u{a7a3}', '\u{a7a5}'..='\u{a7a5}', '\u{a7a7}'..='\u{a7a7}', + '\u{a7a9}'..='\u{a7a9}', '\u{a7af}'..='\u{a7af}', '\u{a7b5}'..='\u{a7b5}', + '\u{a7b7}'..='\u{a7b7}', '\u{a7b9}'..='\u{a7b9}', '\u{a7bb}'..='\u{a7bb}', + '\u{a7bd}'..='\u{a7bd}', '\u{a7bf}'..='\u{a7bf}', '\u{a7c1}'..='\u{a7c1}', + '\u{a7c3}'..='\u{a7c3}', '\u{a7c8}'..='\u{a7c8}', '\u{a7ca}'..='\u{a7ca}', + '\u{a7cd}'..='\u{a7cd}', '\u{a7cf}'..='\u{a7cf}', '\u{a7d1}'..='\u{a7d1}', + '\u{a7d3}'..='\u{a7d3}', '\u{a7d5}'..='\u{a7d5}', '\u{a7d7}'..='\u{a7d7}', + '\u{a7d9}'..='\u{a7d9}', '\u{a7db}'..='\u{a7db}', '\u{a7f1}'..='\u{a7f4}', + '\u{a7f6}'..='\u{a7f6}', '\u{a7f8}'..='\u{a7fa}', '\u{ab30}'..='\u{ab5a}', + '\u{ab5c}'..='\u{ab69}', '\u{ab70}'..='\u{abbf}', '\u{fb00}'..='\u{fb06}', + '\u{fb13}'..='\u{fb17}', '\u{ff41}'..='\u{ff5a}', '\u{10428}'..='\u{1044f}', + '\u{104d8}'..='\u{104fb}', '\u{10597}'..='\u{105a1}', '\u{105a3}'..='\u{105b1}', + '\u{105b3}'..='\u{105b9}', '\u{105bb}'..='\u{105bc}', '\u{10780}'..='\u{10780}', + '\u{10783}'..='\u{10785}', '\u{10787}'..='\u{107b0}', '\u{107b2}'..='\u{107ba}', + '\u{10cc0}'..='\u{10cf2}', '\u{10d70}'..='\u{10d85}', '\u{118c0}'..='\u{118df}', + '\u{16e60}'..='\u{16e7f}', '\u{16ebb}'..='\u{16ed3}', '\u{1d41a}'..='\u{1d433}', + '\u{1d44e}'..='\u{1d454}', '\u{1d456}'..='\u{1d467}', '\u{1d482}'..='\u{1d49b}', + '\u{1d4b6}'..='\u{1d4b9}', '\u{1d4bb}'..='\u{1d4bb}', '\u{1d4bd}'..='\u{1d4c3}', + '\u{1d4c5}'..='\u{1d4cf}', '\u{1d4ea}'..='\u{1d503}', '\u{1d51e}'..='\u{1d537}', + '\u{1d552}'..='\u{1d56b}', '\u{1d586}'..='\u{1d59f}', '\u{1d5ba}'..='\u{1d5d3}', + '\u{1d5ee}'..='\u{1d607}', '\u{1d622}'..='\u{1d63b}', '\u{1d656}'..='\u{1d66f}', + '\u{1d68a}'..='\u{1d6a5}', '\u{1d6c2}'..='\u{1d6da}', '\u{1d6dc}'..='\u{1d6e1}', + '\u{1d6fc}'..='\u{1d714}', '\u{1d716}'..='\u{1d71b}', '\u{1d736}'..='\u{1d74e}', + '\u{1d750}'..='\u{1d755}', '\u{1d770}'..='\u{1d788}', '\u{1d78a}'..='\u{1d78f}', + '\u{1d7aa}'..='\u{1d7c2}', '\u{1d7c4}'..='\u{1d7c9}', '\u{1d7cb}'..='\u{1d7cb}', + '\u{1df00}'..='\u{1df09}', '\u{1df0b}'..='\u{1df1e}', '\u{1df25}'..='\u{1df2a}', + '\u{1e030}'..='\u{1e06d}', '\u{1e922}'..='\u{1e943}', +]; + +#[rustfmt::skip] +pub(super) static N: &[RangeInclusive; 145] = &[ + '\u{b2}'..='\u{b3}', '\u{b9}'..='\u{b9}', '\u{bc}'..='\u{be}', '\u{660}'..='\u{669}', + '\u{6f0}'..='\u{6f9}', '\u{7c0}'..='\u{7c9}', '\u{966}'..='\u{96f}', '\u{9e6}'..='\u{9ef}', + '\u{9f4}'..='\u{9f9}', '\u{a66}'..='\u{a6f}', '\u{ae6}'..='\u{aef}', '\u{b66}'..='\u{b6f}', + '\u{b72}'..='\u{b77}', '\u{be6}'..='\u{bf2}', '\u{c66}'..='\u{c6f}', '\u{c78}'..='\u{c7e}', + '\u{ce6}'..='\u{cef}', '\u{d58}'..='\u{d5e}', '\u{d66}'..='\u{d78}', '\u{de6}'..='\u{def}', + '\u{e50}'..='\u{e59}', '\u{ed0}'..='\u{ed9}', '\u{f20}'..='\u{f33}', + '\u{1040}'..='\u{1049}', '\u{1090}'..='\u{1099}', '\u{1369}'..='\u{137c}', + '\u{16ee}'..='\u{16f0}', '\u{17e0}'..='\u{17e9}', '\u{17f0}'..='\u{17f9}', + '\u{1810}'..='\u{1819}', '\u{1946}'..='\u{194f}', '\u{19d0}'..='\u{19da}', + '\u{1a80}'..='\u{1a89}', '\u{1a90}'..='\u{1a99}', '\u{1b50}'..='\u{1b59}', + '\u{1bb0}'..='\u{1bb9}', '\u{1c40}'..='\u{1c49}', '\u{1c50}'..='\u{1c59}', + '\u{2070}'..='\u{2070}', '\u{2074}'..='\u{2079}', '\u{2080}'..='\u{2089}', + '\u{2150}'..='\u{2182}', '\u{2185}'..='\u{2189}', '\u{2460}'..='\u{249b}', + '\u{24ea}'..='\u{24ff}', '\u{2776}'..='\u{2793}', '\u{2cfd}'..='\u{2cfd}', + '\u{3007}'..='\u{3007}', '\u{3021}'..='\u{3029}', '\u{3038}'..='\u{303a}', + '\u{3192}'..='\u{3195}', '\u{3220}'..='\u{3229}', '\u{3248}'..='\u{324f}', + '\u{3251}'..='\u{325f}', '\u{3280}'..='\u{3289}', '\u{32b1}'..='\u{32bf}', + '\u{a620}'..='\u{a629}', '\u{a6e6}'..='\u{a6ef}', '\u{a830}'..='\u{a835}', + '\u{a8d0}'..='\u{a8d9}', '\u{a900}'..='\u{a909}', '\u{a9d0}'..='\u{a9d9}', + '\u{a9f0}'..='\u{a9f9}', '\u{aa50}'..='\u{aa59}', '\u{abf0}'..='\u{abf9}', + '\u{ff10}'..='\u{ff19}', '\u{10107}'..='\u{10133}', '\u{10140}'..='\u{10178}', + '\u{1018a}'..='\u{1018b}', '\u{102e1}'..='\u{102fb}', '\u{10320}'..='\u{10323}', + '\u{10341}'..='\u{10341}', '\u{1034a}'..='\u{1034a}', '\u{103d1}'..='\u{103d5}', + '\u{104a0}'..='\u{104a9}', '\u{10858}'..='\u{1085f}', '\u{10879}'..='\u{1087f}', + '\u{108a7}'..='\u{108af}', '\u{108fb}'..='\u{108ff}', '\u{10916}'..='\u{1091b}', + '\u{109bc}'..='\u{109bd}', '\u{109c0}'..='\u{109cf}', '\u{109d2}'..='\u{109ff}', + '\u{10a40}'..='\u{10a48}', '\u{10a7d}'..='\u{10a7e}', '\u{10a9d}'..='\u{10a9f}', + '\u{10aeb}'..='\u{10aef}', '\u{10b58}'..='\u{10b5f}', '\u{10b78}'..='\u{10b7f}', + '\u{10ba9}'..='\u{10baf}', '\u{10cfa}'..='\u{10cff}', '\u{10d30}'..='\u{10d39}', + '\u{10d40}'..='\u{10d49}', '\u{10e60}'..='\u{10e7e}', '\u{10f1d}'..='\u{10f26}', + '\u{10f51}'..='\u{10f54}', '\u{10fc5}'..='\u{10fcb}', '\u{11052}'..='\u{1106f}', + '\u{110f0}'..='\u{110f9}', '\u{11136}'..='\u{1113f}', '\u{111d0}'..='\u{111d9}', + '\u{111e1}'..='\u{111f4}', '\u{112f0}'..='\u{112f9}', '\u{11450}'..='\u{11459}', + '\u{114d0}'..='\u{114d9}', '\u{11650}'..='\u{11659}', '\u{116c0}'..='\u{116c9}', + '\u{116d0}'..='\u{116e3}', '\u{11730}'..='\u{1173b}', '\u{118e0}'..='\u{118f2}', + '\u{11950}'..='\u{11959}', '\u{11bf0}'..='\u{11bf9}', '\u{11c50}'..='\u{11c6c}', + '\u{11d50}'..='\u{11d59}', '\u{11da0}'..='\u{11da9}', '\u{11de0}'..='\u{11de9}', + '\u{11f50}'..='\u{11f59}', '\u{11fc0}'..='\u{11fd4}', '\u{12400}'..='\u{1246e}', + '\u{16130}'..='\u{16139}', '\u{16a60}'..='\u{16a69}', '\u{16ac0}'..='\u{16ac9}', + '\u{16b50}'..='\u{16b59}', '\u{16b5b}'..='\u{16b61}', '\u{16d70}'..='\u{16d79}', + '\u{16e80}'..='\u{16e96}', '\u{16ff4}'..='\u{16ff6}', '\u{1ccf0}'..='\u{1ccf9}', + '\u{1d2c0}'..='\u{1d2d3}', '\u{1d2e0}'..='\u{1d2f3}', '\u{1d360}'..='\u{1d378}', + '\u{1d7ce}'..='\u{1d7ff}', '\u{1e140}'..='\u{1e149}', '\u{1e2f0}'..='\u{1e2f9}', + '\u{1e4f0}'..='\u{1e4f9}', '\u{1e5f1}'..='\u{1e5fa}', '\u{1e8c7}'..='\u{1e8cf}', + '\u{1e950}'..='\u{1e959}', '\u{1ec71}'..='\u{1ecab}', '\u{1ecad}'..='\u{1ecaf}', + '\u{1ecb1}'..='\u{1ecb4}', '\u{1ed01}'..='\u{1ed2d}', '\u{1ed2f}'..='\u{1ed3d}', + '\u{1f100}'..='\u{1f10c}', '\u{1fbf0}'..='\u{1fbf9}', +]; + +#[rustfmt::skip] +pub(super) static UPPERCASE: &[RangeInclusive; 659] = &[ + '\u{c0}'..='\u{d6}', '\u{d8}'..='\u{de}', '\u{100}'..='\u{100}', '\u{102}'..='\u{102}', + '\u{104}'..='\u{104}', '\u{106}'..='\u{106}', '\u{108}'..='\u{108}', '\u{10a}'..='\u{10a}', + '\u{10c}'..='\u{10c}', '\u{10e}'..='\u{10e}', '\u{110}'..='\u{110}', '\u{112}'..='\u{112}', + '\u{114}'..='\u{114}', '\u{116}'..='\u{116}', '\u{118}'..='\u{118}', '\u{11a}'..='\u{11a}', + '\u{11c}'..='\u{11c}', '\u{11e}'..='\u{11e}', '\u{120}'..='\u{120}', '\u{122}'..='\u{122}', + '\u{124}'..='\u{124}', '\u{126}'..='\u{126}', '\u{128}'..='\u{128}', '\u{12a}'..='\u{12a}', + '\u{12c}'..='\u{12c}', '\u{12e}'..='\u{12e}', '\u{130}'..='\u{130}', '\u{132}'..='\u{132}', + '\u{134}'..='\u{134}', '\u{136}'..='\u{136}', '\u{139}'..='\u{139}', '\u{13b}'..='\u{13b}', + '\u{13d}'..='\u{13d}', '\u{13f}'..='\u{13f}', '\u{141}'..='\u{141}', '\u{143}'..='\u{143}', + '\u{145}'..='\u{145}', '\u{147}'..='\u{147}', '\u{14a}'..='\u{14a}', '\u{14c}'..='\u{14c}', + '\u{14e}'..='\u{14e}', '\u{150}'..='\u{150}', '\u{152}'..='\u{152}', '\u{154}'..='\u{154}', + '\u{156}'..='\u{156}', '\u{158}'..='\u{158}', '\u{15a}'..='\u{15a}', '\u{15c}'..='\u{15c}', + '\u{15e}'..='\u{15e}', '\u{160}'..='\u{160}', '\u{162}'..='\u{162}', '\u{164}'..='\u{164}', + '\u{166}'..='\u{166}', '\u{168}'..='\u{168}', '\u{16a}'..='\u{16a}', '\u{16c}'..='\u{16c}', + '\u{16e}'..='\u{16e}', '\u{170}'..='\u{170}', '\u{172}'..='\u{172}', '\u{174}'..='\u{174}', + '\u{176}'..='\u{176}', '\u{178}'..='\u{179}', '\u{17b}'..='\u{17b}', '\u{17d}'..='\u{17d}', + '\u{181}'..='\u{182}', '\u{184}'..='\u{184}', '\u{186}'..='\u{187}', '\u{189}'..='\u{18b}', + '\u{18e}'..='\u{191}', '\u{193}'..='\u{194}', '\u{196}'..='\u{198}', '\u{19c}'..='\u{19d}', + '\u{19f}'..='\u{1a0}', '\u{1a2}'..='\u{1a2}', '\u{1a4}'..='\u{1a4}', '\u{1a6}'..='\u{1a7}', + '\u{1a9}'..='\u{1a9}', '\u{1ac}'..='\u{1ac}', '\u{1ae}'..='\u{1af}', '\u{1b1}'..='\u{1b3}', + '\u{1b5}'..='\u{1b5}', '\u{1b7}'..='\u{1b8}', '\u{1bc}'..='\u{1bc}', '\u{1c4}'..='\u{1c4}', + '\u{1c7}'..='\u{1c7}', '\u{1ca}'..='\u{1ca}', '\u{1cd}'..='\u{1cd}', '\u{1cf}'..='\u{1cf}', + '\u{1d1}'..='\u{1d1}', '\u{1d3}'..='\u{1d3}', '\u{1d5}'..='\u{1d5}', '\u{1d7}'..='\u{1d7}', + '\u{1d9}'..='\u{1d9}', '\u{1db}'..='\u{1db}', '\u{1de}'..='\u{1de}', '\u{1e0}'..='\u{1e0}', + '\u{1e2}'..='\u{1e2}', '\u{1e4}'..='\u{1e4}', '\u{1e6}'..='\u{1e6}', '\u{1e8}'..='\u{1e8}', + '\u{1ea}'..='\u{1ea}', '\u{1ec}'..='\u{1ec}', '\u{1ee}'..='\u{1ee}', '\u{1f1}'..='\u{1f1}', + '\u{1f4}'..='\u{1f4}', '\u{1f6}'..='\u{1f8}', '\u{1fa}'..='\u{1fa}', '\u{1fc}'..='\u{1fc}', + '\u{1fe}'..='\u{1fe}', '\u{200}'..='\u{200}', '\u{202}'..='\u{202}', '\u{204}'..='\u{204}', + '\u{206}'..='\u{206}', '\u{208}'..='\u{208}', '\u{20a}'..='\u{20a}', '\u{20c}'..='\u{20c}', + '\u{20e}'..='\u{20e}', '\u{210}'..='\u{210}', '\u{212}'..='\u{212}', '\u{214}'..='\u{214}', + '\u{216}'..='\u{216}', '\u{218}'..='\u{218}', '\u{21a}'..='\u{21a}', '\u{21c}'..='\u{21c}', + '\u{21e}'..='\u{21e}', '\u{220}'..='\u{220}', '\u{222}'..='\u{222}', '\u{224}'..='\u{224}', + '\u{226}'..='\u{226}', '\u{228}'..='\u{228}', '\u{22a}'..='\u{22a}', '\u{22c}'..='\u{22c}', + '\u{22e}'..='\u{22e}', '\u{230}'..='\u{230}', '\u{232}'..='\u{232}', '\u{23a}'..='\u{23b}', + '\u{23d}'..='\u{23e}', '\u{241}'..='\u{241}', '\u{243}'..='\u{246}', '\u{248}'..='\u{248}', + '\u{24a}'..='\u{24a}', '\u{24c}'..='\u{24c}', '\u{24e}'..='\u{24e}', '\u{370}'..='\u{370}', + '\u{372}'..='\u{372}', '\u{376}'..='\u{376}', '\u{37f}'..='\u{37f}', '\u{386}'..='\u{386}', + '\u{388}'..='\u{38a}', '\u{38c}'..='\u{38c}', '\u{38e}'..='\u{38f}', '\u{391}'..='\u{3a1}', + '\u{3a3}'..='\u{3ab}', '\u{3cf}'..='\u{3cf}', '\u{3d2}'..='\u{3d4}', '\u{3d8}'..='\u{3d8}', + '\u{3da}'..='\u{3da}', '\u{3dc}'..='\u{3dc}', '\u{3de}'..='\u{3de}', '\u{3e0}'..='\u{3e0}', + '\u{3e2}'..='\u{3e2}', '\u{3e4}'..='\u{3e4}', '\u{3e6}'..='\u{3e6}', '\u{3e8}'..='\u{3e8}', + '\u{3ea}'..='\u{3ea}', '\u{3ec}'..='\u{3ec}', '\u{3ee}'..='\u{3ee}', '\u{3f4}'..='\u{3f4}', + '\u{3f7}'..='\u{3f7}', '\u{3f9}'..='\u{3fa}', '\u{3fd}'..='\u{42f}', '\u{460}'..='\u{460}', + '\u{462}'..='\u{462}', '\u{464}'..='\u{464}', '\u{466}'..='\u{466}', '\u{468}'..='\u{468}', + '\u{46a}'..='\u{46a}', '\u{46c}'..='\u{46c}', '\u{46e}'..='\u{46e}', '\u{470}'..='\u{470}', + '\u{472}'..='\u{472}', '\u{474}'..='\u{474}', '\u{476}'..='\u{476}', '\u{478}'..='\u{478}', + '\u{47a}'..='\u{47a}', '\u{47c}'..='\u{47c}', '\u{47e}'..='\u{47e}', '\u{480}'..='\u{480}', + '\u{48a}'..='\u{48a}', '\u{48c}'..='\u{48c}', '\u{48e}'..='\u{48e}', '\u{490}'..='\u{490}', + '\u{492}'..='\u{492}', '\u{494}'..='\u{494}', '\u{496}'..='\u{496}', '\u{498}'..='\u{498}', + '\u{49a}'..='\u{49a}', '\u{49c}'..='\u{49c}', '\u{49e}'..='\u{49e}', '\u{4a0}'..='\u{4a0}', + '\u{4a2}'..='\u{4a2}', '\u{4a4}'..='\u{4a4}', '\u{4a6}'..='\u{4a6}', '\u{4a8}'..='\u{4a8}', + '\u{4aa}'..='\u{4aa}', '\u{4ac}'..='\u{4ac}', '\u{4ae}'..='\u{4ae}', '\u{4b0}'..='\u{4b0}', + '\u{4b2}'..='\u{4b2}', '\u{4b4}'..='\u{4b4}', '\u{4b6}'..='\u{4b6}', '\u{4b8}'..='\u{4b8}', + '\u{4ba}'..='\u{4ba}', '\u{4bc}'..='\u{4bc}', '\u{4be}'..='\u{4be}', '\u{4c0}'..='\u{4c1}', + '\u{4c3}'..='\u{4c3}', '\u{4c5}'..='\u{4c5}', '\u{4c7}'..='\u{4c7}', '\u{4c9}'..='\u{4c9}', + '\u{4cb}'..='\u{4cb}', '\u{4cd}'..='\u{4cd}', '\u{4d0}'..='\u{4d0}', '\u{4d2}'..='\u{4d2}', + '\u{4d4}'..='\u{4d4}', '\u{4d6}'..='\u{4d6}', '\u{4d8}'..='\u{4d8}', '\u{4da}'..='\u{4da}', + '\u{4dc}'..='\u{4dc}', '\u{4de}'..='\u{4de}', '\u{4e0}'..='\u{4e0}', '\u{4e2}'..='\u{4e2}', + '\u{4e4}'..='\u{4e4}', '\u{4e6}'..='\u{4e6}', '\u{4e8}'..='\u{4e8}', '\u{4ea}'..='\u{4ea}', + '\u{4ec}'..='\u{4ec}', '\u{4ee}'..='\u{4ee}', '\u{4f0}'..='\u{4f0}', '\u{4f2}'..='\u{4f2}', + '\u{4f4}'..='\u{4f4}', '\u{4f6}'..='\u{4f6}', '\u{4f8}'..='\u{4f8}', '\u{4fa}'..='\u{4fa}', + '\u{4fc}'..='\u{4fc}', '\u{4fe}'..='\u{4fe}', '\u{500}'..='\u{500}', '\u{502}'..='\u{502}', + '\u{504}'..='\u{504}', '\u{506}'..='\u{506}', '\u{508}'..='\u{508}', '\u{50a}'..='\u{50a}', + '\u{50c}'..='\u{50c}', '\u{50e}'..='\u{50e}', '\u{510}'..='\u{510}', '\u{512}'..='\u{512}', + '\u{514}'..='\u{514}', '\u{516}'..='\u{516}', '\u{518}'..='\u{518}', '\u{51a}'..='\u{51a}', + '\u{51c}'..='\u{51c}', '\u{51e}'..='\u{51e}', '\u{520}'..='\u{520}', '\u{522}'..='\u{522}', + '\u{524}'..='\u{524}', '\u{526}'..='\u{526}', '\u{528}'..='\u{528}', '\u{52a}'..='\u{52a}', + '\u{52c}'..='\u{52c}', '\u{52e}'..='\u{52e}', '\u{531}'..='\u{556}', + '\u{10a0}'..='\u{10c5}', '\u{10c7}'..='\u{10c7}', '\u{10cd}'..='\u{10cd}', + '\u{13a0}'..='\u{13f5}', '\u{1c89}'..='\u{1c89}', '\u{1c90}'..='\u{1cba}', + '\u{1cbd}'..='\u{1cbf}', '\u{1e00}'..='\u{1e00}', '\u{1e02}'..='\u{1e02}', + '\u{1e04}'..='\u{1e04}', '\u{1e06}'..='\u{1e06}', '\u{1e08}'..='\u{1e08}', + '\u{1e0a}'..='\u{1e0a}', '\u{1e0c}'..='\u{1e0c}', '\u{1e0e}'..='\u{1e0e}', + '\u{1e10}'..='\u{1e10}', '\u{1e12}'..='\u{1e12}', '\u{1e14}'..='\u{1e14}', + '\u{1e16}'..='\u{1e16}', '\u{1e18}'..='\u{1e18}', '\u{1e1a}'..='\u{1e1a}', + '\u{1e1c}'..='\u{1e1c}', '\u{1e1e}'..='\u{1e1e}', '\u{1e20}'..='\u{1e20}', + '\u{1e22}'..='\u{1e22}', '\u{1e24}'..='\u{1e24}', '\u{1e26}'..='\u{1e26}', + '\u{1e28}'..='\u{1e28}', '\u{1e2a}'..='\u{1e2a}', '\u{1e2c}'..='\u{1e2c}', + '\u{1e2e}'..='\u{1e2e}', '\u{1e30}'..='\u{1e30}', '\u{1e32}'..='\u{1e32}', + '\u{1e34}'..='\u{1e34}', '\u{1e36}'..='\u{1e36}', '\u{1e38}'..='\u{1e38}', + '\u{1e3a}'..='\u{1e3a}', '\u{1e3c}'..='\u{1e3c}', '\u{1e3e}'..='\u{1e3e}', + '\u{1e40}'..='\u{1e40}', '\u{1e42}'..='\u{1e42}', '\u{1e44}'..='\u{1e44}', + '\u{1e46}'..='\u{1e46}', '\u{1e48}'..='\u{1e48}', '\u{1e4a}'..='\u{1e4a}', + '\u{1e4c}'..='\u{1e4c}', '\u{1e4e}'..='\u{1e4e}', '\u{1e50}'..='\u{1e50}', + '\u{1e52}'..='\u{1e52}', '\u{1e54}'..='\u{1e54}', '\u{1e56}'..='\u{1e56}', + '\u{1e58}'..='\u{1e58}', '\u{1e5a}'..='\u{1e5a}', '\u{1e5c}'..='\u{1e5c}', + '\u{1e5e}'..='\u{1e5e}', '\u{1e60}'..='\u{1e60}', '\u{1e62}'..='\u{1e62}', + '\u{1e64}'..='\u{1e64}', '\u{1e66}'..='\u{1e66}', '\u{1e68}'..='\u{1e68}', + '\u{1e6a}'..='\u{1e6a}', '\u{1e6c}'..='\u{1e6c}', '\u{1e6e}'..='\u{1e6e}', + '\u{1e70}'..='\u{1e70}', '\u{1e72}'..='\u{1e72}', '\u{1e74}'..='\u{1e74}', + '\u{1e76}'..='\u{1e76}', '\u{1e78}'..='\u{1e78}', '\u{1e7a}'..='\u{1e7a}', + '\u{1e7c}'..='\u{1e7c}', '\u{1e7e}'..='\u{1e7e}', '\u{1e80}'..='\u{1e80}', + '\u{1e82}'..='\u{1e82}', '\u{1e84}'..='\u{1e84}', '\u{1e86}'..='\u{1e86}', + '\u{1e88}'..='\u{1e88}', '\u{1e8a}'..='\u{1e8a}', '\u{1e8c}'..='\u{1e8c}', + '\u{1e8e}'..='\u{1e8e}', '\u{1e90}'..='\u{1e90}', '\u{1e92}'..='\u{1e92}', + '\u{1e94}'..='\u{1e94}', '\u{1e9e}'..='\u{1e9e}', '\u{1ea0}'..='\u{1ea0}', + '\u{1ea2}'..='\u{1ea2}', '\u{1ea4}'..='\u{1ea4}', '\u{1ea6}'..='\u{1ea6}', + '\u{1ea8}'..='\u{1ea8}', '\u{1eaa}'..='\u{1eaa}', '\u{1eac}'..='\u{1eac}', + '\u{1eae}'..='\u{1eae}', '\u{1eb0}'..='\u{1eb0}', '\u{1eb2}'..='\u{1eb2}', + '\u{1eb4}'..='\u{1eb4}', '\u{1eb6}'..='\u{1eb6}', '\u{1eb8}'..='\u{1eb8}', + '\u{1eba}'..='\u{1eba}', '\u{1ebc}'..='\u{1ebc}', '\u{1ebe}'..='\u{1ebe}', + '\u{1ec0}'..='\u{1ec0}', '\u{1ec2}'..='\u{1ec2}', '\u{1ec4}'..='\u{1ec4}', + '\u{1ec6}'..='\u{1ec6}', '\u{1ec8}'..='\u{1ec8}', '\u{1eca}'..='\u{1eca}', + '\u{1ecc}'..='\u{1ecc}', '\u{1ece}'..='\u{1ece}', '\u{1ed0}'..='\u{1ed0}', + '\u{1ed2}'..='\u{1ed2}', '\u{1ed4}'..='\u{1ed4}', '\u{1ed6}'..='\u{1ed6}', + '\u{1ed8}'..='\u{1ed8}', '\u{1eda}'..='\u{1eda}', '\u{1edc}'..='\u{1edc}', + '\u{1ede}'..='\u{1ede}', '\u{1ee0}'..='\u{1ee0}', '\u{1ee2}'..='\u{1ee2}', + '\u{1ee4}'..='\u{1ee4}', '\u{1ee6}'..='\u{1ee6}', '\u{1ee8}'..='\u{1ee8}', + '\u{1eea}'..='\u{1eea}', '\u{1eec}'..='\u{1eec}', '\u{1eee}'..='\u{1eee}', + '\u{1ef0}'..='\u{1ef0}', '\u{1ef2}'..='\u{1ef2}', '\u{1ef4}'..='\u{1ef4}', + '\u{1ef6}'..='\u{1ef6}', '\u{1ef8}'..='\u{1ef8}', '\u{1efa}'..='\u{1efa}', + '\u{1efc}'..='\u{1efc}', '\u{1efe}'..='\u{1efe}', '\u{1f08}'..='\u{1f0f}', + '\u{1f18}'..='\u{1f1d}', '\u{1f28}'..='\u{1f2f}', '\u{1f38}'..='\u{1f3f}', + '\u{1f48}'..='\u{1f4d}', '\u{1f59}'..='\u{1f59}', '\u{1f5b}'..='\u{1f5b}', + '\u{1f5d}'..='\u{1f5d}', '\u{1f5f}'..='\u{1f5f}', '\u{1f68}'..='\u{1f6f}', + '\u{1fb8}'..='\u{1fbb}', '\u{1fc8}'..='\u{1fcb}', '\u{1fd8}'..='\u{1fdb}', + '\u{1fe8}'..='\u{1fec}', '\u{1ff8}'..='\u{1ffb}', '\u{2102}'..='\u{2102}', + '\u{2107}'..='\u{2107}', '\u{210b}'..='\u{210d}', '\u{2110}'..='\u{2112}', + '\u{2115}'..='\u{2115}', '\u{2119}'..='\u{211d}', '\u{2124}'..='\u{2124}', + '\u{2126}'..='\u{2126}', '\u{2128}'..='\u{2128}', '\u{212a}'..='\u{212d}', + '\u{2130}'..='\u{2133}', '\u{213e}'..='\u{213f}', '\u{2145}'..='\u{2145}', + '\u{2160}'..='\u{216f}', '\u{2183}'..='\u{2183}', '\u{24b6}'..='\u{24cf}', + '\u{2c00}'..='\u{2c2f}', '\u{2c60}'..='\u{2c60}', '\u{2c62}'..='\u{2c64}', + '\u{2c67}'..='\u{2c67}', '\u{2c69}'..='\u{2c69}', '\u{2c6b}'..='\u{2c6b}', + '\u{2c6d}'..='\u{2c70}', '\u{2c72}'..='\u{2c72}', '\u{2c75}'..='\u{2c75}', + '\u{2c7e}'..='\u{2c80}', '\u{2c82}'..='\u{2c82}', '\u{2c84}'..='\u{2c84}', + '\u{2c86}'..='\u{2c86}', '\u{2c88}'..='\u{2c88}', '\u{2c8a}'..='\u{2c8a}', + '\u{2c8c}'..='\u{2c8c}', '\u{2c8e}'..='\u{2c8e}', '\u{2c90}'..='\u{2c90}', + '\u{2c92}'..='\u{2c92}', '\u{2c94}'..='\u{2c94}', '\u{2c96}'..='\u{2c96}', + '\u{2c98}'..='\u{2c98}', '\u{2c9a}'..='\u{2c9a}', '\u{2c9c}'..='\u{2c9c}', + '\u{2c9e}'..='\u{2c9e}', '\u{2ca0}'..='\u{2ca0}', '\u{2ca2}'..='\u{2ca2}', + '\u{2ca4}'..='\u{2ca4}', '\u{2ca6}'..='\u{2ca6}', '\u{2ca8}'..='\u{2ca8}', + '\u{2caa}'..='\u{2caa}', '\u{2cac}'..='\u{2cac}', '\u{2cae}'..='\u{2cae}', + '\u{2cb0}'..='\u{2cb0}', '\u{2cb2}'..='\u{2cb2}', '\u{2cb4}'..='\u{2cb4}', + '\u{2cb6}'..='\u{2cb6}', '\u{2cb8}'..='\u{2cb8}', '\u{2cba}'..='\u{2cba}', + '\u{2cbc}'..='\u{2cbc}', '\u{2cbe}'..='\u{2cbe}', '\u{2cc0}'..='\u{2cc0}', + '\u{2cc2}'..='\u{2cc2}', '\u{2cc4}'..='\u{2cc4}', '\u{2cc6}'..='\u{2cc6}', + '\u{2cc8}'..='\u{2cc8}', '\u{2cca}'..='\u{2cca}', '\u{2ccc}'..='\u{2ccc}', + '\u{2cce}'..='\u{2cce}', '\u{2cd0}'..='\u{2cd0}', '\u{2cd2}'..='\u{2cd2}', + '\u{2cd4}'..='\u{2cd4}', '\u{2cd6}'..='\u{2cd6}', '\u{2cd8}'..='\u{2cd8}', + '\u{2cda}'..='\u{2cda}', '\u{2cdc}'..='\u{2cdc}', '\u{2cde}'..='\u{2cde}', + '\u{2ce0}'..='\u{2ce0}', '\u{2ce2}'..='\u{2ce2}', '\u{2ceb}'..='\u{2ceb}', + '\u{2ced}'..='\u{2ced}', '\u{2cf2}'..='\u{2cf2}', '\u{a640}'..='\u{a640}', + '\u{a642}'..='\u{a642}', '\u{a644}'..='\u{a644}', '\u{a646}'..='\u{a646}', + '\u{a648}'..='\u{a648}', '\u{a64a}'..='\u{a64a}', '\u{a64c}'..='\u{a64c}', + '\u{a64e}'..='\u{a64e}', '\u{a650}'..='\u{a650}', '\u{a652}'..='\u{a652}', + '\u{a654}'..='\u{a654}', '\u{a656}'..='\u{a656}', '\u{a658}'..='\u{a658}', + '\u{a65a}'..='\u{a65a}', '\u{a65c}'..='\u{a65c}', '\u{a65e}'..='\u{a65e}', + '\u{a660}'..='\u{a660}', '\u{a662}'..='\u{a662}', '\u{a664}'..='\u{a664}', + '\u{a666}'..='\u{a666}', '\u{a668}'..='\u{a668}', '\u{a66a}'..='\u{a66a}', + '\u{a66c}'..='\u{a66c}', '\u{a680}'..='\u{a680}', '\u{a682}'..='\u{a682}', + '\u{a684}'..='\u{a684}', '\u{a686}'..='\u{a686}', '\u{a688}'..='\u{a688}', + '\u{a68a}'..='\u{a68a}', '\u{a68c}'..='\u{a68c}', '\u{a68e}'..='\u{a68e}', + '\u{a690}'..='\u{a690}', '\u{a692}'..='\u{a692}', '\u{a694}'..='\u{a694}', + '\u{a696}'..='\u{a696}', '\u{a698}'..='\u{a698}', '\u{a69a}'..='\u{a69a}', + '\u{a722}'..='\u{a722}', '\u{a724}'..='\u{a724}', '\u{a726}'..='\u{a726}', + '\u{a728}'..='\u{a728}', '\u{a72a}'..='\u{a72a}', '\u{a72c}'..='\u{a72c}', + '\u{a72e}'..='\u{a72e}', '\u{a732}'..='\u{a732}', '\u{a734}'..='\u{a734}', + '\u{a736}'..='\u{a736}', '\u{a738}'..='\u{a738}', '\u{a73a}'..='\u{a73a}', + '\u{a73c}'..='\u{a73c}', '\u{a73e}'..='\u{a73e}', '\u{a740}'..='\u{a740}', + '\u{a742}'..='\u{a742}', '\u{a744}'..='\u{a744}', '\u{a746}'..='\u{a746}', + '\u{a748}'..='\u{a748}', '\u{a74a}'..='\u{a74a}', '\u{a74c}'..='\u{a74c}', + '\u{a74e}'..='\u{a74e}', '\u{a750}'..='\u{a750}', '\u{a752}'..='\u{a752}', + '\u{a754}'..='\u{a754}', '\u{a756}'..='\u{a756}', '\u{a758}'..='\u{a758}', + '\u{a75a}'..='\u{a75a}', '\u{a75c}'..='\u{a75c}', '\u{a75e}'..='\u{a75e}', + '\u{a760}'..='\u{a760}', '\u{a762}'..='\u{a762}', '\u{a764}'..='\u{a764}', + '\u{a766}'..='\u{a766}', '\u{a768}'..='\u{a768}', '\u{a76a}'..='\u{a76a}', + '\u{a76c}'..='\u{a76c}', '\u{a76e}'..='\u{a76e}', '\u{a779}'..='\u{a779}', + '\u{a77b}'..='\u{a77b}', '\u{a77d}'..='\u{a77e}', '\u{a780}'..='\u{a780}', + '\u{a782}'..='\u{a782}', '\u{a784}'..='\u{a784}', '\u{a786}'..='\u{a786}', + '\u{a78b}'..='\u{a78b}', '\u{a78d}'..='\u{a78d}', '\u{a790}'..='\u{a790}', + '\u{a792}'..='\u{a792}', '\u{a796}'..='\u{a796}', '\u{a798}'..='\u{a798}', + '\u{a79a}'..='\u{a79a}', '\u{a79c}'..='\u{a79c}', '\u{a79e}'..='\u{a79e}', + '\u{a7a0}'..='\u{a7a0}', '\u{a7a2}'..='\u{a7a2}', '\u{a7a4}'..='\u{a7a4}', + '\u{a7a6}'..='\u{a7a6}', '\u{a7a8}'..='\u{a7a8}', '\u{a7aa}'..='\u{a7ae}', + '\u{a7b0}'..='\u{a7b4}', '\u{a7b6}'..='\u{a7b6}', '\u{a7b8}'..='\u{a7b8}', + '\u{a7ba}'..='\u{a7ba}', '\u{a7bc}'..='\u{a7bc}', '\u{a7be}'..='\u{a7be}', + '\u{a7c0}'..='\u{a7c0}', '\u{a7c2}'..='\u{a7c2}', '\u{a7c4}'..='\u{a7c7}', + '\u{a7c9}'..='\u{a7c9}', '\u{a7cb}'..='\u{a7cc}', '\u{a7ce}'..='\u{a7ce}', + '\u{a7d0}'..='\u{a7d0}', '\u{a7d2}'..='\u{a7d2}', '\u{a7d4}'..='\u{a7d4}', + '\u{a7d6}'..='\u{a7d6}', '\u{a7d8}'..='\u{a7d8}', '\u{a7da}'..='\u{a7da}', + '\u{a7dc}'..='\u{a7dc}', '\u{a7f5}'..='\u{a7f5}', '\u{ff21}'..='\u{ff3a}', + '\u{10400}'..='\u{10427}', '\u{104b0}'..='\u{104d3}', '\u{10570}'..='\u{1057a}', + '\u{1057c}'..='\u{1058a}', '\u{1058c}'..='\u{10592}', '\u{10594}'..='\u{10595}', + '\u{10c80}'..='\u{10cb2}', '\u{10d50}'..='\u{10d65}', '\u{118a0}'..='\u{118bf}', + '\u{16e40}'..='\u{16e5f}', '\u{16ea0}'..='\u{16eb8}', '\u{1d400}'..='\u{1d419}', + '\u{1d434}'..='\u{1d44d}', '\u{1d468}'..='\u{1d481}', '\u{1d49c}'..='\u{1d49c}', + '\u{1d49e}'..='\u{1d49f}', '\u{1d4a2}'..='\u{1d4a2}', '\u{1d4a5}'..='\u{1d4a6}', + '\u{1d4a9}'..='\u{1d4ac}', '\u{1d4ae}'..='\u{1d4b5}', '\u{1d4d0}'..='\u{1d4e9}', + '\u{1d504}'..='\u{1d505}', '\u{1d507}'..='\u{1d50a}', '\u{1d50d}'..='\u{1d514}', + '\u{1d516}'..='\u{1d51c}', '\u{1d538}'..='\u{1d539}', '\u{1d53b}'..='\u{1d53e}', + '\u{1d540}'..='\u{1d544}', '\u{1d546}'..='\u{1d546}', '\u{1d54a}'..='\u{1d550}', + '\u{1d56c}'..='\u{1d585}', '\u{1d5a0}'..='\u{1d5b9}', '\u{1d5d4}'..='\u{1d5ed}', + '\u{1d608}'..='\u{1d621}', '\u{1d63c}'..='\u{1d655}', '\u{1d670}'..='\u{1d689}', + '\u{1d6a8}'..='\u{1d6c0}', '\u{1d6e2}'..='\u{1d6fa}', '\u{1d71c}'..='\u{1d734}', + '\u{1d756}'..='\u{1d76e}', '\u{1d790}'..='\u{1d7a8}', '\u{1d7ca}'..='\u{1d7ca}', + '\u{1e900}'..='\u{1e921}', '\u{1f130}'..='\u{1f149}', '\u{1f150}'..='\u{1f169}', + '\u{1f170}'..='\u{1f189}', +]; + +#[rustfmt::skip] +pub(super) static WHITE_SPACE: &[RangeInclusive; 8] = &[ + '\u{85}'..='\u{85}', '\u{a0}'..='\u{a0}', '\u{1680}'..='\u{1680}', '\u{2000}'..='\u{200a}', + '\u{2028}'..='\u{2029}', '\u{202f}'..='\u{202f}', '\u{205f}'..='\u{205f}', + '\u{3000}'..='\u{3000}', +]; + +#[rustfmt::skip] +pub(super) static TO_LOWER: &[(char, [char; 3]); 1462] = &[ + ('\u{c0}', ['\u{e0}', '\u{0}', '\u{0}']), ('\u{c1}', ['\u{e1}', '\u{0}', '\u{0}']), + ('\u{c2}', ['\u{e2}', '\u{0}', '\u{0}']), ('\u{c3}', ['\u{e3}', '\u{0}', '\u{0}']), + ('\u{c4}', ['\u{e4}', '\u{0}', '\u{0}']), ('\u{c5}', ['\u{e5}', '\u{0}', '\u{0}']), + ('\u{c6}', ['\u{e6}', '\u{0}', '\u{0}']), ('\u{c7}', ['\u{e7}', '\u{0}', '\u{0}']), + ('\u{c8}', ['\u{e8}', '\u{0}', '\u{0}']), ('\u{c9}', ['\u{e9}', '\u{0}', '\u{0}']), + ('\u{ca}', ['\u{ea}', '\u{0}', '\u{0}']), ('\u{cb}', ['\u{eb}', '\u{0}', '\u{0}']), + ('\u{cc}', ['\u{ec}', '\u{0}', '\u{0}']), ('\u{cd}', ['\u{ed}', '\u{0}', '\u{0}']), + ('\u{ce}', ['\u{ee}', '\u{0}', '\u{0}']), ('\u{cf}', ['\u{ef}', '\u{0}', '\u{0}']), + ('\u{d0}', ['\u{f0}', '\u{0}', '\u{0}']), ('\u{d1}', ['\u{f1}', '\u{0}', '\u{0}']), + ('\u{d2}', ['\u{f2}', '\u{0}', '\u{0}']), ('\u{d3}', ['\u{f3}', '\u{0}', '\u{0}']), + ('\u{d4}', ['\u{f4}', '\u{0}', '\u{0}']), ('\u{d5}', ['\u{f5}', '\u{0}', '\u{0}']), + ('\u{d6}', ['\u{f6}', '\u{0}', '\u{0}']), ('\u{d8}', ['\u{f8}', '\u{0}', '\u{0}']), + ('\u{d9}', ['\u{f9}', '\u{0}', '\u{0}']), ('\u{da}', ['\u{fa}', '\u{0}', '\u{0}']), + ('\u{db}', ['\u{fb}', '\u{0}', '\u{0}']), ('\u{dc}', ['\u{fc}', '\u{0}', '\u{0}']), + ('\u{dd}', ['\u{fd}', '\u{0}', '\u{0}']), ('\u{de}', ['\u{fe}', '\u{0}', '\u{0}']), + ('\u{100}', ['\u{101}', '\u{0}', '\u{0}']), ('\u{102}', ['\u{103}', '\u{0}', '\u{0}']), + ('\u{104}', ['\u{105}', '\u{0}', '\u{0}']), ('\u{106}', ['\u{107}', '\u{0}', '\u{0}']), + ('\u{108}', ['\u{109}', '\u{0}', '\u{0}']), ('\u{10a}', ['\u{10b}', '\u{0}', '\u{0}']), + ('\u{10c}', ['\u{10d}', '\u{0}', '\u{0}']), ('\u{10e}', ['\u{10f}', '\u{0}', '\u{0}']), + ('\u{110}', ['\u{111}', '\u{0}', '\u{0}']), ('\u{112}', ['\u{113}', '\u{0}', '\u{0}']), + ('\u{114}', ['\u{115}', '\u{0}', '\u{0}']), ('\u{116}', ['\u{117}', '\u{0}', '\u{0}']), + ('\u{118}', ['\u{119}', '\u{0}', '\u{0}']), ('\u{11a}', ['\u{11b}', '\u{0}', '\u{0}']), + ('\u{11c}', ['\u{11d}', '\u{0}', '\u{0}']), ('\u{11e}', ['\u{11f}', '\u{0}', '\u{0}']), + ('\u{120}', ['\u{121}', '\u{0}', '\u{0}']), ('\u{122}', ['\u{123}', '\u{0}', '\u{0}']), + ('\u{124}', ['\u{125}', '\u{0}', '\u{0}']), ('\u{126}', ['\u{127}', '\u{0}', '\u{0}']), + ('\u{128}', ['\u{129}', '\u{0}', '\u{0}']), ('\u{12a}', ['\u{12b}', '\u{0}', '\u{0}']), + ('\u{12c}', ['\u{12d}', '\u{0}', '\u{0}']), ('\u{12e}', ['\u{12f}', '\u{0}', '\u{0}']), + ('\u{130}', ['i', '\u{307}', '\u{0}']), ('\u{132}', ['\u{133}', '\u{0}', '\u{0}']), + ('\u{134}', ['\u{135}', '\u{0}', '\u{0}']), ('\u{136}', ['\u{137}', '\u{0}', '\u{0}']), + ('\u{139}', ['\u{13a}', '\u{0}', '\u{0}']), ('\u{13b}', ['\u{13c}', '\u{0}', '\u{0}']), + ('\u{13d}', ['\u{13e}', '\u{0}', '\u{0}']), ('\u{13f}', ['\u{140}', '\u{0}', '\u{0}']), + ('\u{141}', ['\u{142}', '\u{0}', '\u{0}']), ('\u{143}', ['\u{144}', '\u{0}', '\u{0}']), + ('\u{145}', ['\u{146}', '\u{0}', '\u{0}']), ('\u{147}', ['\u{148}', '\u{0}', '\u{0}']), + ('\u{14a}', ['\u{14b}', '\u{0}', '\u{0}']), ('\u{14c}', ['\u{14d}', '\u{0}', '\u{0}']), + ('\u{14e}', ['\u{14f}', '\u{0}', '\u{0}']), ('\u{150}', ['\u{151}', '\u{0}', '\u{0}']), + ('\u{152}', ['\u{153}', '\u{0}', '\u{0}']), ('\u{154}', ['\u{155}', '\u{0}', '\u{0}']), + ('\u{156}', ['\u{157}', '\u{0}', '\u{0}']), ('\u{158}', ['\u{159}', '\u{0}', '\u{0}']), + ('\u{15a}', ['\u{15b}', '\u{0}', '\u{0}']), ('\u{15c}', ['\u{15d}', '\u{0}', '\u{0}']), + ('\u{15e}', ['\u{15f}', '\u{0}', '\u{0}']), ('\u{160}', ['\u{161}', '\u{0}', '\u{0}']), + ('\u{162}', ['\u{163}', '\u{0}', '\u{0}']), ('\u{164}', ['\u{165}', '\u{0}', '\u{0}']), + ('\u{166}', ['\u{167}', '\u{0}', '\u{0}']), ('\u{168}', ['\u{169}', '\u{0}', '\u{0}']), + ('\u{16a}', ['\u{16b}', '\u{0}', '\u{0}']), ('\u{16c}', ['\u{16d}', '\u{0}', '\u{0}']), + ('\u{16e}', ['\u{16f}', '\u{0}', '\u{0}']), ('\u{170}', ['\u{171}', '\u{0}', '\u{0}']), + ('\u{172}', ['\u{173}', '\u{0}', '\u{0}']), ('\u{174}', ['\u{175}', '\u{0}', '\u{0}']), + ('\u{176}', ['\u{177}', '\u{0}', '\u{0}']), ('\u{178}', ['\u{ff}', '\u{0}', '\u{0}']), + ('\u{179}', ['\u{17a}', '\u{0}', '\u{0}']), ('\u{17b}', ['\u{17c}', '\u{0}', '\u{0}']), + ('\u{17d}', ['\u{17e}', '\u{0}', '\u{0}']), ('\u{181}', ['\u{253}', '\u{0}', '\u{0}']), + ('\u{182}', ['\u{183}', '\u{0}', '\u{0}']), ('\u{184}', ['\u{185}', '\u{0}', '\u{0}']), + ('\u{186}', ['\u{254}', '\u{0}', '\u{0}']), ('\u{187}', ['\u{188}', '\u{0}', '\u{0}']), + ('\u{189}', ['\u{256}', '\u{0}', '\u{0}']), ('\u{18a}', ['\u{257}', '\u{0}', '\u{0}']), + ('\u{18b}', ['\u{18c}', '\u{0}', '\u{0}']), ('\u{18e}', ['\u{1dd}', '\u{0}', '\u{0}']), + ('\u{18f}', ['\u{259}', '\u{0}', '\u{0}']), ('\u{190}', ['\u{25b}', '\u{0}', '\u{0}']), + ('\u{191}', ['\u{192}', '\u{0}', '\u{0}']), ('\u{193}', ['\u{260}', '\u{0}', '\u{0}']), + ('\u{194}', ['\u{263}', '\u{0}', '\u{0}']), ('\u{196}', ['\u{269}', '\u{0}', '\u{0}']), + ('\u{197}', ['\u{268}', '\u{0}', '\u{0}']), ('\u{198}', ['\u{199}', '\u{0}', '\u{0}']), + ('\u{19c}', ['\u{26f}', '\u{0}', '\u{0}']), ('\u{19d}', ['\u{272}', '\u{0}', '\u{0}']), + ('\u{19f}', ['\u{275}', '\u{0}', '\u{0}']), ('\u{1a0}', ['\u{1a1}', '\u{0}', '\u{0}']), + ('\u{1a2}', ['\u{1a3}', '\u{0}', '\u{0}']), ('\u{1a4}', ['\u{1a5}', '\u{0}', '\u{0}']), + ('\u{1a6}', ['\u{280}', '\u{0}', '\u{0}']), ('\u{1a7}', ['\u{1a8}', '\u{0}', '\u{0}']), + ('\u{1a9}', ['\u{283}', '\u{0}', '\u{0}']), ('\u{1ac}', ['\u{1ad}', '\u{0}', '\u{0}']), + ('\u{1ae}', ['\u{288}', '\u{0}', '\u{0}']), ('\u{1af}', ['\u{1b0}', '\u{0}', '\u{0}']), + ('\u{1b1}', ['\u{28a}', '\u{0}', '\u{0}']), ('\u{1b2}', ['\u{28b}', '\u{0}', '\u{0}']), + ('\u{1b3}', ['\u{1b4}', '\u{0}', '\u{0}']), ('\u{1b5}', ['\u{1b6}', '\u{0}', '\u{0}']), + ('\u{1b7}', ['\u{292}', '\u{0}', '\u{0}']), ('\u{1b8}', ['\u{1b9}', '\u{0}', '\u{0}']), + ('\u{1bc}', ['\u{1bd}', '\u{0}', '\u{0}']), ('\u{1c4}', ['\u{1c6}', '\u{0}', '\u{0}']), + ('\u{1c5}', ['\u{1c6}', '\u{0}', '\u{0}']), ('\u{1c7}', ['\u{1c9}', '\u{0}', '\u{0}']), + ('\u{1c8}', ['\u{1c9}', '\u{0}', '\u{0}']), ('\u{1ca}', ['\u{1cc}', '\u{0}', '\u{0}']), + ('\u{1cb}', ['\u{1cc}', '\u{0}', '\u{0}']), ('\u{1cd}', ['\u{1ce}', '\u{0}', '\u{0}']), + ('\u{1cf}', ['\u{1d0}', '\u{0}', '\u{0}']), ('\u{1d1}', ['\u{1d2}', '\u{0}', '\u{0}']), + ('\u{1d3}', ['\u{1d4}', '\u{0}', '\u{0}']), ('\u{1d5}', ['\u{1d6}', '\u{0}', '\u{0}']), + ('\u{1d7}', ['\u{1d8}', '\u{0}', '\u{0}']), ('\u{1d9}', ['\u{1da}', '\u{0}', '\u{0}']), + ('\u{1db}', ['\u{1dc}', '\u{0}', '\u{0}']), ('\u{1de}', ['\u{1df}', '\u{0}', '\u{0}']), + ('\u{1e0}', ['\u{1e1}', '\u{0}', '\u{0}']), ('\u{1e2}', ['\u{1e3}', '\u{0}', '\u{0}']), + ('\u{1e4}', ['\u{1e5}', '\u{0}', '\u{0}']), ('\u{1e6}', ['\u{1e7}', '\u{0}', '\u{0}']), + ('\u{1e8}', ['\u{1e9}', '\u{0}', '\u{0}']), ('\u{1ea}', ['\u{1eb}', '\u{0}', '\u{0}']), + ('\u{1ec}', ['\u{1ed}', '\u{0}', '\u{0}']), ('\u{1ee}', ['\u{1ef}', '\u{0}', '\u{0}']), + ('\u{1f1}', ['\u{1f3}', '\u{0}', '\u{0}']), ('\u{1f2}', ['\u{1f3}', '\u{0}', '\u{0}']), + ('\u{1f4}', ['\u{1f5}', '\u{0}', '\u{0}']), ('\u{1f6}', ['\u{195}', '\u{0}', '\u{0}']), + ('\u{1f7}', ['\u{1bf}', '\u{0}', '\u{0}']), ('\u{1f8}', ['\u{1f9}', '\u{0}', '\u{0}']), + ('\u{1fa}', ['\u{1fb}', '\u{0}', '\u{0}']), ('\u{1fc}', ['\u{1fd}', '\u{0}', '\u{0}']), + ('\u{1fe}', ['\u{1ff}', '\u{0}', '\u{0}']), ('\u{200}', ['\u{201}', '\u{0}', '\u{0}']), + ('\u{202}', ['\u{203}', '\u{0}', '\u{0}']), ('\u{204}', ['\u{205}', '\u{0}', '\u{0}']), + ('\u{206}', ['\u{207}', '\u{0}', '\u{0}']), ('\u{208}', ['\u{209}', '\u{0}', '\u{0}']), + ('\u{20a}', ['\u{20b}', '\u{0}', '\u{0}']), ('\u{20c}', ['\u{20d}', '\u{0}', '\u{0}']), + ('\u{20e}', ['\u{20f}', '\u{0}', '\u{0}']), ('\u{210}', ['\u{211}', '\u{0}', '\u{0}']), + ('\u{212}', ['\u{213}', '\u{0}', '\u{0}']), ('\u{214}', ['\u{215}', '\u{0}', '\u{0}']), + ('\u{216}', ['\u{217}', '\u{0}', '\u{0}']), ('\u{218}', ['\u{219}', '\u{0}', '\u{0}']), + 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('\u{398}', ['\u{3b8}', '\u{0}', '\u{0}']), ('\u{399}', ['\u{3b9}', '\u{0}', '\u{0}']), + ('\u{39a}', ['\u{3ba}', '\u{0}', '\u{0}']), ('\u{39b}', ['\u{3bb}', '\u{0}', '\u{0}']), + ('\u{39c}', ['\u{3bc}', '\u{0}', '\u{0}']), ('\u{39d}', ['\u{3bd}', '\u{0}', '\u{0}']), + ('\u{39e}', ['\u{3be}', '\u{0}', '\u{0}']), ('\u{39f}', ['\u{3bf}', '\u{0}', '\u{0}']), + ('\u{3a0}', ['\u{3c0}', '\u{0}', '\u{0}']), ('\u{3a1}', ['\u{3c1}', '\u{0}', '\u{0}']), + ('\u{3a3}', ['\u{3c3}', '\u{0}', '\u{0}']), ('\u{3a4}', ['\u{3c4}', '\u{0}', '\u{0}']), + ('\u{3a5}', ['\u{3c5}', '\u{0}', '\u{0}']), ('\u{3a6}', ['\u{3c6}', '\u{0}', '\u{0}']), + ('\u{3a7}', ['\u{3c7}', '\u{0}', '\u{0}']), ('\u{3a8}', ['\u{3c8}', '\u{0}', '\u{0}']), + ('\u{3a9}', ['\u{3c9}', '\u{0}', '\u{0}']), ('\u{3aa}', ['\u{3ca}', '\u{0}', '\u{0}']), + ('\u{3ab}', ['\u{3cb}', '\u{0}', '\u{0}']), ('\u{3cf}', ['\u{3d7}', '\u{0}', '\u{0}']), + ('\u{3d8}', ['\u{3d9}', '\u{0}', '\u{0}']), ('\u{3da}', ['\u{3db}', '\u{0}', '\u{0}']), + ('\u{3dc}', ['\u{3dd}', '\u{0}', '\u{0}']), ('\u{3de}', ['\u{3df}', '\u{0}', '\u{0}']), + ('\u{3e0}', ['\u{3e1}', '\u{0}', '\u{0}']), ('\u{3e2}', ['\u{3e3}', '\u{0}', '\u{0}']), + ('\u{3e4}', ['\u{3e5}', '\u{0}', '\u{0}']), ('\u{3e6}', ['\u{3e7}', '\u{0}', '\u{0}']), + ('\u{3e8}', ['\u{3e9}', '\u{0}', '\u{0}']), ('\u{3ea}', ['\u{3eb}', '\u{0}', '\u{0}']), + ('\u{3ec}', ['\u{3ed}', '\u{0}', '\u{0}']), ('\u{3ee}', ['\u{3ef}', '\u{0}', '\u{0}']), + ('\u{3f4}', ['\u{3b8}', '\u{0}', '\u{0}']), ('\u{3f7}', ['\u{3f8}', '\u{0}', '\u{0}']), + ('\u{3f9}', ['\u{3f2}', '\u{0}', '\u{0}']), ('\u{3fa}', ['\u{3fb}', '\u{0}', '\u{0}']), + ('\u{3fd}', ['\u{37b}', '\u{0}', '\u{0}']), ('\u{3fe}', ['\u{37c}', '\u{0}', '\u{0}']), + ('\u{3ff}', ['\u{37d}', '\u{0}', '\u{0}']), ('\u{400}', ['\u{450}', '\u{0}', '\u{0}']), + ('\u{401}', ['\u{451}', '\u{0}', '\u{0}']), ('\u{402}', ['\u{452}', '\u{0}', '\u{0}']), + ('\u{403}', ['\u{453}', '\u{0}', '\u{0}']), ('\u{404}', ['\u{454}', '\u{0}', '\u{0}']), + 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['\u{2d10}', '\u{0}', '\u{0}']), + ('\u{10b1}', ['\u{2d11}', '\u{0}', '\u{0}']), ('\u{10b2}', ['\u{2d12}', '\u{0}', '\u{0}']), + ('\u{10b3}', ['\u{2d13}', '\u{0}', '\u{0}']), ('\u{10b4}', ['\u{2d14}', '\u{0}', '\u{0}']), + ('\u{10b5}', ['\u{2d15}', '\u{0}', '\u{0}']), ('\u{10b6}', ['\u{2d16}', '\u{0}', '\u{0}']), + ('\u{10b7}', ['\u{2d17}', '\u{0}', '\u{0}']), ('\u{10b8}', ['\u{2d18}', '\u{0}', '\u{0}']), + ('\u{10b9}', ['\u{2d19}', '\u{0}', '\u{0}']), ('\u{10ba}', ['\u{2d1a}', '\u{0}', '\u{0}']), + ('\u{10bb}', ['\u{2d1b}', '\u{0}', '\u{0}']), ('\u{10bc}', ['\u{2d1c}', '\u{0}', '\u{0}']), + ('\u{10bd}', ['\u{2d1d}', '\u{0}', '\u{0}']), ('\u{10be}', ['\u{2d1e}', '\u{0}', '\u{0}']), + ('\u{10bf}', ['\u{2d1f}', '\u{0}', '\u{0}']), ('\u{10c0}', ['\u{2d20}', '\u{0}', '\u{0}']), + ('\u{10c1}', ['\u{2d21}', '\u{0}', '\u{0}']), ('\u{10c2}', ['\u{2d22}', '\u{0}', '\u{0}']), + ('\u{10c3}', ['\u{2d23}', '\u{0}', '\u{0}']), ('\u{10c4}', ['\u{2d24}', '\u{0}', '\u{0}']), + ('\u{10c5}', ['\u{2d25}', '\u{0}', '\u{0}']), ('\u{10c7}', ['\u{2d27}', '\u{0}', '\u{0}']), + ('\u{10cd}', ['\u{2d2d}', '\u{0}', '\u{0}']), ('\u{13a0}', ['\u{ab70}', '\u{0}', '\u{0}']), + ('\u{13a1}', ['\u{ab71}', '\u{0}', '\u{0}']), ('\u{13a2}', ['\u{ab72}', '\u{0}', '\u{0}']), + ('\u{13a3}', ['\u{ab73}', '\u{0}', '\u{0}']), ('\u{13a4}', ['\u{ab74}', '\u{0}', '\u{0}']), + ('\u{13a5}', ['\u{ab75}', '\u{0}', '\u{0}']), ('\u{13a6}', ['\u{ab76}', '\u{0}', '\u{0}']), + ('\u{13a7}', ['\u{ab77}', '\u{0}', '\u{0}']), ('\u{13a8}', ['\u{ab78}', '\u{0}', '\u{0}']), + ('\u{13a9}', ['\u{ab79}', '\u{0}', '\u{0}']), ('\u{13aa}', ['\u{ab7a}', '\u{0}', '\u{0}']), + ('\u{13ab}', ['\u{ab7b}', '\u{0}', '\u{0}']), ('\u{13ac}', ['\u{ab7c}', '\u{0}', '\u{0}']), + ('\u{13ad}', ['\u{ab7d}', '\u{0}', '\u{0}']), ('\u{13ae}', ['\u{ab7e}', '\u{0}', '\u{0}']), + ('\u{13af}', ['\u{ab7f}', '\u{0}', '\u{0}']), ('\u{13b0}', ['\u{ab80}', '\u{0}', '\u{0}']), + ('\u{13b1}', ['\u{ab81}', '\u{0}', '\u{0}']), ('\u{13b2}', ['\u{ab82}', '\u{0}', '\u{0}']), + ('\u{13b3}', ['\u{ab83}', '\u{0}', '\u{0}']), ('\u{13b4}', ['\u{ab84}', '\u{0}', '\u{0}']), + ('\u{13b5}', ['\u{ab85}', '\u{0}', '\u{0}']), ('\u{13b6}', ['\u{ab86}', '\u{0}', '\u{0}']), + ('\u{13b7}', ['\u{ab87}', '\u{0}', '\u{0}']), ('\u{13b8}', ['\u{ab88}', '\u{0}', '\u{0}']), + ('\u{13b9}', ['\u{ab89}', '\u{0}', '\u{0}']), ('\u{13ba}', ['\u{ab8a}', '\u{0}', '\u{0}']), + ('\u{13bb}', ['\u{ab8b}', '\u{0}', '\u{0}']), ('\u{13bc}', ['\u{ab8c}', '\u{0}', '\u{0}']), + ('\u{13bd}', ['\u{ab8d}', '\u{0}', '\u{0}']), ('\u{13be}', ['\u{ab8e}', '\u{0}', '\u{0}']), + ('\u{13bf}', ['\u{ab8f}', '\u{0}', '\u{0}']), ('\u{13c0}', ['\u{ab90}', '\u{0}', '\u{0}']), + ('\u{13c1}', ['\u{ab91}', '\u{0}', '\u{0}']), ('\u{13c2}', ['\u{ab92}', '\u{0}', '\u{0}']), + ('\u{13c3}', ['\u{ab93}', '\u{0}', '\u{0}']), ('\u{13c4}', ['\u{ab94}', '\u{0}', '\u{0}']), + ('\u{13c5}', ['\u{ab95}', '\u{0}', '\u{0}']), ('\u{13c6}', ['\u{ab96}', '\u{0}', '\u{0}']), + ('\u{13c7}', ['\u{ab97}', '\u{0}', '\u{0}']), ('\u{13c8}', ['\u{ab98}', '\u{0}', '\u{0}']), + ('\u{13c9}', ['\u{ab99}', '\u{0}', '\u{0}']), ('\u{13ca}', ['\u{ab9a}', '\u{0}', '\u{0}']), + ('\u{13cb}', ['\u{ab9b}', '\u{0}', '\u{0}']), ('\u{13cc}', ['\u{ab9c}', '\u{0}', '\u{0}']), + ('\u{13cd}', ['\u{ab9d}', '\u{0}', '\u{0}']), ('\u{13ce}', ['\u{ab9e}', '\u{0}', '\u{0}']), + ('\u{13cf}', ['\u{ab9f}', '\u{0}', '\u{0}']), ('\u{13d0}', ['\u{aba0}', '\u{0}', '\u{0}']), + ('\u{13d1}', ['\u{aba1}', '\u{0}', '\u{0}']), ('\u{13d2}', ['\u{aba2}', '\u{0}', '\u{0}']), + ('\u{13d3}', ['\u{aba3}', '\u{0}', '\u{0}']), ('\u{13d4}', ['\u{aba4}', '\u{0}', '\u{0}']), + ('\u{13d5}', ['\u{aba5}', '\u{0}', '\u{0}']), ('\u{13d6}', ['\u{aba6}', '\u{0}', '\u{0}']), + ('\u{13d7}', ['\u{aba7}', '\u{0}', '\u{0}']), ('\u{13d8}', ['\u{aba8}', '\u{0}', '\u{0}']), + ('\u{13d9}', ['\u{aba9}', '\u{0}', '\u{0}']), ('\u{13da}', ['\u{abaa}', '\u{0}', '\u{0}']), + ('\u{13db}', ['\u{abab}', '\u{0}', '\u{0}']), ('\u{13dc}', ['\u{abac}', '\u{0}', '\u{0}']), + ('\u{13dd}', ['\u{abad}', '\u{0}', '\u{0}']), ('\u{13de}', ['\u{abae}', '\u{0}', '\u{0}']), + ('\u{13df}', ['\u{abaf}', '\u{0}', '\u{0}']), ('\u{13e0}', ['\u{abb0}', '\u{0}', '\u{0}']), + ('\u{13e1}', ['\u{abb1}', '\u{0}', '\u{0}']), ('\u{13e2}', ['\u{abb2}', '\u{0}', '\u{0}']), + ('\u{13e3}', ['\u{abb3}', '\u{0}', '\u{0}']), ('\u{13e4}', ['\u{abb4}', '\u{0}', '\u{0}']), + ('\u{13e5}', ['\u{abb5}', '\u{0}', '\u{0}']), ('\u{13e6}', ['\u{abb6}', '\u{0}', '\u{0}']), + ('\u{13e7}', ['\u{abb7}', '\u{0}', '\u{0}']), ('\u{13e8}', ['\u{abb8}', '\u{0}', '\u{0}']), + ('\u{13e9}', ['\u{abb9}', '\u{0}', '\u{0}']), ('\u{13ea}', ['\u{abba}', '\u{0}', '\u{0}']), + ('\u{13eb}', ['\u{abbb}', '\u{0}', '\u{0}']), ('\u{13ec}', ['\u{abbc}', '\u{0}', '\u{0}']), + ('\u{13ed}', ['\u{abbd}', '\u{0}', '\u{0}']), ('\u{13ee}', ['\u{abbe}', '\u{0}', '\u{0}']), + ('\u{13ef}', ['\u{abbf}', '\u{0}', '\u{0}']), ('\u{13f0}', ['\u{13f8}', '\u{0}', '\u{0}']), + ('\u{13f1}', ['\u{13f9}', '\u{0}', '\u{0}']), ('\u{13f2}', ['\u{13fa}', '\u{0}', '\u{0}']), + ('\u{13f3}', ['\u{13fb}', '\u{0}', '\u{0}']), ('\u{13f4}', ['\u{13fc}', '\u{0}', '\u{0}']), + ('\u{13f5}', ['\u{13fd}', '\u{0}', '\u{0}']), ('\u{1c89}', ['\u{1c8a}', '\u{0}', '\u{0}']), + ('\u{1c90}', ['\u{10d0}', '\u{0}', '\u{0}']), ('\u{1c91}', ['\u{10d1}', '\u{0}', '\u{0}']), + ('\u{1c92}', ['\u{10d2}', '\u{0}', '\u{0}']), ('\u{1c93}', ['\u{10d3}', '\u{0}', '\u{0}']), + ('\u{1c94}', ['\u{10d4}', '\u{0}', '\u{0}']), ('\u{1c95}', ['\u{10d5}', '\u{0}', '\u{0}']), + ('\u{1c96}', ['\u{10d6}', '\u{0}', '\u{0}']), ('\u{1c97}', ['\u{10d7}', '\u{0}', '\u{0}']), + ('\u{1c98}', ['\u{10d8}', '\u{0}', '\u{0}']), ('\u{1c99}', ['\u{10d9}', '\u{0}', '\u{0}']), + ('\u{1c9a}', ['\u{10da}', '\u{0}', '\u{0}']), ('\u{1c9b}', ['\u{10db}', '\u{0}', '\u{0}']), + ('\u{1c9c}', ['\u{10dc}', '\u{0}', '\u{0}']), ('\u{1c9d}', ['\u{10dd}', '\u{0}', '\u{0}']), + ('\u{1c9e}', ['\u{10de}', '\u{0}', '\u{0}']), ('\u{1c9f}', ['\u{10df}', '\u{0}', '\u{0}']), + ('\u{1ca0}', ['\u{10e0}', '\u{0}', '\u{0}']), ('\u{1ca1}', ['\u{10e1}', '\u{0}', '\u{0}']), + ('\u{1ca2}', ['\u{10e2}', '\u{0}', '\u{0}']), ('\u{1ca3}', ['\u{10e3}', '\u{0}', '\u{0}']), + ('\u{1ca4}', ['\u{10e4}', '\u{0}', '\u{0}']), ('\u{1ca5}', ['\u{10e5}', '\u{0}', '\u{0}']), + ('\u{1ca6}', ['\u{10e6}', '\u{0}', '\u{0}']), ('\u{1ca7}', ['\u{10e7}', '\u{0}', '\u{0}']), + ('\u{1ca8}', ['\u{10e8}', '\u{0}', '\u{0}']), ('\u{1ca9}', ['\u{10e9}', '\u{0}', '\u{0}']), + ('\u{1caa}', ['\u{10ea}', '\u{0}', '\u{0}']), ('\u{1cab}', ['\u{10eb}', '\u{0}', '\u{0}']), + ('\u{1cac}', ['\u{10ec}', '\u{0}', '\u{0}']), ('\u{1cad}', ['\u{10ed}', '\u{0}', '\u{0}']), + ('\u{1cae}', ['\u{10ee}', '\u{0}', '\u{0}']), ('\u{1caf}', ['\u{10ef}', '\u{0}', '\u{0}']), + ('\u{1cb0}', ['\u{10f0}', '\u{0}', '\u{0}']), ('\u{1cb1}', ['\u{10f1}', '\u{0}', '\u{0}']), + ('\u{1cb2}', ['\u{10f2}', '\u{0}', '\u{0}']), ('\u{1cb3}', ['\u{10f3}', '\u{0}', '\u{0}']), + ('\u{1cb4}', ['\u{10f4}', '\u{0}', '\u{0}']), ('\u{1cb5}', ['\u{10f5}', '\u{0}', '\u{0}']), + ('\u{1cb6}', ['\u{10f6}', '\u{0}', '\u{0}']), ('\u{1cb7}', ['\u{10f7}', '\u{0}', '\u{0}']), + ('\u{1cb8}', ['\u{10f8}', '\u{0}', '\u{0}']), ('\u{1cb9}', ['\u{10f9}', '\u{0}', '\u{0}']), + ('\u{1cba}', ['\u{10fa}', '\u{0}', '\u{0}']), ('\u{1cbd}', ['\u{10fd}', '\u{0}', '\u{0}']), + ('\u{1cbe}', ['\u{10fe}', '\u{0}', '\u{0}']), ('\u{1cbf}', ['\u{10ff}', '\u{0}', '\u{0}']), + ('\u{1e00}', ['\u{1e01}', '\u{0}', '\u{0}']), ('\u{1e02}', ['\u{1e03}', '\u{0}', '\u{0}']), + ('\u{1e04}', ['\u{1e05}', '\u{0}', '\u{0}']), ('\u{1e06}', ['\u{1e07}', '\u{0}', '\u{0}']), + ('\u{1e08}', ['\u{1e09}', '\u{0}', '\u{0}']), ('\u{1e0a}', ['\u{1e0b}', '\u{0}', '\u{0}']), + ('\u{1e0c}', ['\u{1e0d}', '\u{0}', '\u{0}']), ('\u{1e0e}', ['\u{1e0f}', '\u{0}', '\u{0}']), + ('\u{1e10}', ['\u{1e11}', '\u{0}', '\u{0}']), ('\u{1e12}', ['\u{1e13}', '\u{0}', '\u{0}']), + ('\u{1e14}', ['\u{1e15}', '\u{0}', '\u{0}']), ('\u{1e16}', ['\u{1e17}', '\u{0}', '\u{0}']), + ('\u{1e18}', ['\u{1e19}', '\u{0}', '\u{0}']), ('\u{1e1a}', ['\u{1e1b}', '\u{0}', '\u{0}']), + ('\u{1e1c}', ['\u{1e1d}', '\u{0}', '\u{0}']), ('\u{1e1e}', ['\u{1e1f}', '\u{0}', '\u{0}']), + ('\u{1e20}', ['\u{1e21}', '\u{0}', '\u{0}']), ('\u{1e22}', ['\u{1e23}', '\u{0}', '\u{0}']), + ('\u{1e24}', ['\u{1e25}', '\u{0}', '\u{0}']), ('\u{1e26}', ['\u{1e27}', '\u{0}', '\u{0}']), + ('\u{1e28}', ['\u{1e29}', '\u{0}', '\u{0}']), ('\u{1e2a}', ['\u{1e2b}', '\u{0}', '\u{0}']), + ('\u{1e2c}', ['\u{1e2d}', '\u{0}', '\u{0}']), ('\u{1e2e}', ['\u{1e2f}', '\u{0}', '\u{0}']), + ('\u{1e30}', ['\u{1e31}', '\u{0}', '\u{0}']), ('\u{1e32}', ['\u{1e33}', '\u{0}', '\u{0}']), + ('\u{1e34}', ['\u{1e35}', '\u{0}', '\u{0}']), ('\u{1e36}', ['\u{1e37}', '\u{0}', '\u{0}']), + ('\u{1e38}', ['\u{1e39}', '\u{0}', '\u{0}']), ('\u{1e3a}', ['\u{1e3b}', '\u{0}', '\u{0}']), + ('\u{1e3c}', ['\u{1e3d}', '\u{0}', '\u{0}']), ('\u{1e3e}', ['\u{1e3f}', '\u{0}', '\u{0}']), + ('\u{1e40}', ['\u{1e41}', '\u{0}', '\u{0}']), ('\u{1e42}', ['\u{1e43}', '\u{0}', '\u{0}']), + ('\u{1e44}', ['\u{1e45}', '\u{0}', '\u{0}']), ('\u{1e46}', ['\u{1e47}', '\u{0}', '\u{0}']), + ('\u{1e48}', ['\u{1e49}', '\u{0}', '\u{0}']), ('\u{1e4a}', ['\u{1e4b}', '\u{0}', '\u{0}']), + ('\u{1e4c}', ['\u{1e4d}', '\u{0}', '\u{0}']), ('\u{1e4e}', ['\u{1e4f}', '\u{0}', '\u{0}']), + ('\u{1e50}', ['\u{1e51}', '\u{0}', '\u{0}']), ('\u{1e52}', ['\u{1e53}', '\u{0}', '\u{0}']), + ('\u{1e54}', ['\u{1e55}', '\u{0}', '\u{0}']), ('\u{1e56}', ['\u{1e57}', '\u{0}', '\u{0}']), + ('\u{1e58}', ['\u{1e59}', '\u{0}', '\u{0}']), ('\u{1e5a}', ['\u{1e5b}', '\u{0}', '\u{0}']), + ('\u{1e5c}', ['\u{1e5d}', '\u{0}', '\u{0}']), ('\u{1e5e}', ['\u{1e5f}', '\u{0}', '\u{0}']), + ('\u{1e60}', ['\u{1e61}', '\u{0}', '\u{0}']), ('\u{1e62}', ['\u{1e63}', '\u{0}', '\u{0}']), + ('\u{1e64}', ['\u{1e65}', '\u{0}', '\u{0}']), ('\u{1e66}', ['\u{1e67}', '\u{0}', '\u{0}']), + ('\u{1e68}', ['\u{1e69}', '\u{0}', '\u{0}']), ('\u{1e6a}', ['\u{1e6b}', '\u{0}', '\u{0}']), + ('\u{1e6c}', ['\u{1e6d}', '\u{0}', '\u{0}']), ('\u{1e6e}', ['\u{1e6f}', '\u{0}', '\u{0}']), + ('\u{1e70}', ['\u{1e71}', '\u{0}', '\u{0}']), ('\u{1e72}', ['\u{1e73}', '\u{0}', '\u{0}']), + ('\u{1e74}', ['\u{1e75}', '\u{0}', '\u{0}']), ('\u{1e76}', ['\u{1e77}', '\u{0}', '\u{0}']), + ('\u{1e78}', ['\u{1e79}', '\u{0}', '\u{0}']), ('\u{1e7a}', ['\u{1e7b}', '\u{0}', '\u{0}']), + ('\u{1e7c}', ['\u{1e7d}', '\u{0}', '\u{0}']), ('\u{1e7e}', ['\u{1e7f}', '\u{0}', '\u{0}']), + ('\u{1e80}', ['\u{1e81}', '\u{0}', '\u{0}']), ('\u{1e82}', ['\u{1e83}', '\u{0}', '\u{0}']), + ('\u{1e84}', ['\u{1e85}', '\u{0}', '\u{0}']), ('\u{1e86}', ['\u{1e87}', '\u{0}', '\u{0}']), + ('\u{1e88}', ['\u{1e89}', '\u{0}', '\u{0}']), ('\u{1e8a}', ['\u{1e8b}', '\u{0}', '\u{0}']), + ('\u{1e8c}', ['\u{1e8d}', '\u{0}', '\u{0}']), ('\u{1e8e}', ['\u{1e8f}', '\u{0}', '\u{0}']), + ('\u{1e90}', ['\u{1e91}', '\u{0}', '\u{0}']), ('\u{1e92}', ['\u{1e93}', '\u{0}', '\u{0}']), + ('\u{1e94}', ['\u{1e95}', '\u{0}', '\u{0}']), ('\u{1e9e}', ['\u{df}', '\u{0}', '\u{0}']), + ('\u{1ea0}', ['\u{1ea1}', '\u{0}', '\u{0}']), ('\u{1ea2}', ['\u{1ea3}', '\u{0}', '\u{0}']), + ('\u{1ea4}', ['\u{1ea5}', '\u{0}', '\u{0}']), ('\u{1ea6}', ['\u{1ea7}', '\u{0}', '\u{0}']), + ('\u{1ea8}', ['\u{1ea9}', '\u{0}', '\u{0}']), ('\u{1eaa}', ['\u{1eab}', '\u{0}', '\u{0}']), + ('\u{1eac}', ['\u{1ead}', '\u{0}', '\u{0}']), ('\u{1eae}', ['\u{1eaf}', '\u{0}', '\u{0}']), + ('\u{1eb0}', ['\u{1eb1}', '\u{0}', '\u{0}']), ('\u{1eb2}', ['\u{1eb3}', '\u{0}', '\u{0}']), + ('\u{1eb4}', ['\u{1eb5}', '\u{0}', '\u{0}']), ('\u{1eb6}', ['\u{1eb7}', '\u{0}', '\u{0}']), + ('\u{1eb8}', ['\u{1eb9}', '\u{0}', '\u{0}']), ('\u{1eba}', ['\u{1ebb}', '\u{0}', '\u{0}']), + ('\u{1ebc}', ['\u{1ebd}', '\u{0}', '\u{0}']), ('\u{1ebe}', ['\u{1ebf}', '\u{0}', '\u{0}']), + ('\u{1ec0}', ['\u{1ec1}', '\u{0}', '\u{0}']), ('\u{1ec2}', ['\u{1ec3}', '\u{0}', '\u{0}']), + ('\u{1ec4}', ['\u{1ec5}', '\u{0}', '\u{0}']), ('\u{1ec6}', ['\u{1ec7}', '\u{0}', '\u{0}']), + ('\u{1ec8}', ['\u{1ec9}', '\u{0}', '\u{0}']), ('\u{1eca}', ['\u{1ecb}', '\u{0}', '\u{0}']), + ('\u{1ecc}', ['\u{1ecd}', '\u{0}', '\u{0}']), ('\u{1ece}', ['\u{1ecf}', '\u{0}', '\u{0}']), + ('\u{1ed0}', ['\u{1ed1}', '\u{0}', '\u{0}']), ('\u{1ed2}', ['\u{1ed3}', '\u{0}', '\u{0}']), + ('\u{1ed4}', ['\u{1ed5}', '\u{0}', '\u{0}']), ('\u{1ed6}', ['\u{1ed7}', '\u{0}', '\u{0}']), + ('\u{1ed8}', ['\u{1ed9}', '\u{0}', '\u{0}']), ('\u{1eda}', ['\u{1edb}', '\u{0}', '\u{0}']), + ('\u{1edc}', ['\u{1edd}', '\u{0}', '\u{0}']), ('\u{1ede}', ['\u{1edf}', '\u{0}', '\u{0}']), + ('\u{1ee0}', ['\u{1ee1}', '\u{0}', '\u{0}']), ('\u{1ee2}', ['\u{1ee3}', '\u{0}', '\u{0}']), + ('\u{1ee4}', ['\u{1ee5}', '\u{0}', '\u{0}']), ('\u{1ee6}', ['\u{1ee7}', '\u{0}', '\u{0}']), + ('\u{1ee8}', ['\u{1ee9}', '\u{0}', '\u{0}']), ('\u{1eea}', ['\u{1eeb}', '\u{0}', '\u{0}']), + ('\u{1eec}', ['\u{1eed}', '\u{0}', '\u{0}']), ('\u{1eee}', ['\u{1eef}', '\u{0}', '\u{0}']), + ('\u{1ef0}', ['\u{1ef1}', '\u{0}', '\u{0}']), ('\u{1ef2}', ['\u{1ef3}', '\u{0}', '\u{0}']), + ('\u{1ef4}', ['\u{1ef5}', '\u{0}', '\u{0}']), ('\u{1ef6}', ['\u{1ef7}', '\u{0}', '\u{0}']), + ('\u{1ef8}', ['\u{1ef9}', '\u{0}', '\u{0}']), ('\u{1efa}', ['\u{1efb}', '\u{0}', '\u{0}']), + ('\u{1efc}', ['\u{1efd}', '\u{0}', '\u{0}']), ('\u{1efe}', ['\u{1eff}', '\u{0}', '\u{0}']), + ('\u{1f08}', ['\u{1f00}', '\u{0}', '\u{0}']), ('\u{1f09}', ['\u{1f01}', '\u{0}', '\u{0}']), + ('\u{1f0a}', ['\u{1f02}', '\u{0}', '\u{0}']), ('\u{1f0b}', ['\u{1f03}', '\u{0}', '\u{0}']), + ('\u{1f0c}', ['\u{1f04}', '\u{0}', '\u{0}']), ('\u{1f0d}', ['\u{1f05}', '\u{0}', '\u{0}']), + ('\u{1f0e}', ['\u{1f06}', '\u{0}', '\u{0}']), ('\u{1f0f}', ['\u{1f07}', '\u{0}', '\u{0}']), + ('\u{1f18}', ['\u{1f10}', '\u{0}', '\u{0}']), ('\u{1f19}', ['\u{1f11}', '\u{0}', '\u{0}']), + ('\u{1f1a}', ['\u{1f12}', '\u{0}', '\u{0}']), ('\u{1f1b}', ['\u{1f13}', '\u{0}', '\u{0}']), + ('\u{1f1c}', ['\u{1f14}', '\u{0}', '\u{0}']), ('\u{1f1d}', ['\u{1f15}', '\u{0}', '\u{0}']), + ('\u{1f28}', ['\u{1f20}', '\u{0}', '\u{0}']), ('\u{1f29}', ['\u{1f21}', '\u{0}', '\u{0}']), + ('\u{1f2a}', ['\u{1f22}', '\u{0}', '\u{0}']), ('\u{1f2b}', ['\u{1f23}', '\u{0}', '\u{0}']), + ('\u{1f2c}', ['\u{1f24}', '\u{0}', '\u{0}']), ('\u{1f2d}', ['\u{1f25}', '\u{0}', '\u{0}']), + ('\u{1f2e}', ['\u{1f26}', '\u{0}', '\u{0}']), ('\u{1f2f}', ['\u{1f27}', '\u{0}', '\u{0}']), + ('\u{1f38}', ['\u{1f30}', '\u{0}', '\u{0}']), ('\u{1f39}', ['\u{1f31}', '\u{0}', '\u{0}']), + ('\u{1f3a}', ['\u{1f32}', '\u{0}', '\u{0}']), ('\u{1f3b}', ['\u{1f33}', '\u{0}', '\u{0}']), + ('\u{1f3c}', ['\u{1f34}', '\u{0}', '\u{0}']), ('\u{1f3d}', ['\u{1f35}', '\u{0}', '\u{0}']), + ('\u{1f3e}', ['\u{1f36}', '\u{0}', '\u{0}']), ('\u{1f3f}', ['\u{1f37}', '\u{0}', '\u{0}']), + ('\u{1f48}', ['\u{1f40}', '\u{0}', '\u{0}']), ('\u{1f49}', ['\u{1f41}', '\u{0}', '\u{0}']), + ('\u{1f4a}', ['\u{1f42}', '\u{0}', '\u{0}']), ('\u{1f4b}', ['\u{1f43}', '\u{0}', '\u{0}']), + ('\u{1f4c}', ['\u{1f44}', '\u{0}', '\u{0}']), ('\u{1f4d}', ['\u{1f45}', '\u{0}', '\u{0}']), + ('\u{1f59}', ['\u{1f51}', '\u{0}', '\u{0}']), ('\u{1f5b}', ['\u{1f53}', '\u{0}', '\u{0}']), + ('\u{1f5d}', ['\u{1f55}', '\u{0}', '\u{0}']), ('\u{1f5f}', ['\u{1f57}', '\u{0}', '\u{0}']), + ('\u{1f68}', ['\u{1f60}', '\u{0}', '\u{0}']), ('\u{1f69}', ['\u{1f61}', '\u{0}', '\u{0}']), + ('\u{1f6a}', ['\u{1f62}', '\u{0}', '\u{0}']), ('\u{1f6b}', ['\u{1f63}', '\u{0}', '\u{0}']), + ('\u{1f6c}', ['\u{1f64}', '\u{0}', '\u{0}']), ('\u{1f6d}', ['\u{1f65}', '\u{0}', '\u{0}']), + ('\u{1f6e}', ['\u{1f66}', '\u{0}', '\u{0}']), ('\u{1f6f}', ['\u{1f67}', '\u{0}', '\u{0}']), + ('\u{1f88}', ['\u{1f80}', '\u{0}', '\u{0}']), ('\u{1f89}', ['\u{1f81}', '\u{0}', '\u{0}']), + ('\u{1f8a}', ['\u{1f82}', '\u{0}', '\u{0}']), ('\u{1f8b}', ['\u{1f83}', '\u{0}', '\u{0}']), + ('\u{1f8c}', ['\u{1f84}', '\u{0}', '\u{0}']), ('\u{1f8d}', ['\u{1f85}', '\u{0}', '\u{0}']), + ('\u{1f8e}', ['\u{1f86}', '\u{0}', '\u{0}']), ('\u{1f8f}', ['\u{1f87}', '\u{0}', '\u{0}']), + ('\u{1f98}', ['\u{1f90}', '\u{0}', '\u{0}']), ('\u{1f99}', ['\u{1f91}', '\u{0}', '\u{0}']), + ('\u{1f9a}', ['\u{1f92}', '\u{0}', '\u{0}']), ('\u{1f9b}', ['\u{1f93}', '\u{0}', '\u{0}']), + ('\u{1f9c}', ['\u{1f94}', '\u{0}', '\u{0}']), ('\u{1f9d}', ['\u{1f95}', '\u{0}', '\u{0}']), + ('\u{1f9e}', ['\u{1f96}', '\u{0}', '\u{0}']), ('\u{1f9f}', ['\u{1f97}', '\u{0}', '\u{0}']), + ('\u{1fa8}', ['\u{1fa0}', '\u{0}', '\u{0}']), ('\u{1fa9}', ['\u{1fa1}', '\u{0}', '\u{0}']), + ('\u{1faa}', ['\u{1fa2}', '\u{0}', '\u{0}']), ('\u{1fab}', ['\u{1fa3}', '\u{0}', '\u{0}']), + ('\u{1fac}', ['\u{1fa4}', '\u{0}', '\u{0}']), ('\u{1fad}', ['\u{1fa5}', '\u{0}', '\u{0}']), + ('\u{1fae}', ['\u{1fa6}', '\u{0}', '\u{0}']), ('\u{1faf}', ['\u{1fa7}', '\u{0}', '\u{0}']), + ('\u{1fb8}', ['\u{1fb0}', '\u{0}', '\u{0}']), ('\u{1fb9}', ['\u{1fb1}', '\u{0}', '\u{0}']), + ('\u{1fba}', ['\u{1f70}', '\u{0}', '\u{0}']), ('\u{1fbb}', ['\u{1f71}', '\u{0}', '\u{0}']), + ('\u{1fbc}', ['\u{1fb3}', '\u{0}', '\u{0}']), ('\u{1fc8}', ['\u{1f72}', '\u{0}', '\u{0}']), + ('\u{1fc9}', ['\u{1f73}', '\u{0}', '\u{0}']), ('\u{1fca}', ['\u{1f74}', '\u{0}', '\u{0}']), + ('\u{1fcb}', ['\u{1f75}', '\u{0}', '\u{0}']), ('\u{1fcc}', ['\u{1fc3}', '\u{0}', '\u{0}']), + ('\u{1fd8}', ['\u{1fd0}', '\u{0}', '\u{0}']), ('\u{1fd9}', ['\u{1fd1}', '\u{0}', '\u{0}']), + ('\u{1fda}', ['\u{1f76}', '\u{0}', '\u{0}']), ('\u{1fdb}', ['\u{1f77}', '\u{0}', '\u{0}']), + ('\u{1fe8}', ['\u{1fe0}', '\u{0}', '\u{0}']), ('\u{1fe9}', ['\u{1fe1}', '\u{0}', '\u{0}']), + ('\u{1fea}', ['\u{1f7a}', '\u{0}', '\u{0}']), ('\u{1feb}', ['\u{1f7b}', '\u{0}', '\u{0}']), + ('\u{1fec}', ['\u{1fe5}', '\u{0}', '\u{0}']), ('\u{1ff8}', ['\u{1f78}', '\u{0}', '\u{0}']), + ('\u{1ff9}', ['\u{1f79}', '\u{0}', '\u{0}']), ('\u{1ffa}', ['\u{1f7c}', '\u{0}', '\u{0}']), + ('\u{1ffb}', ['\u{1f7d}', '\u{0}', '\u{0}']), ('\u{1ffc}', ['\u{1ff3}', '\u{0}', '\u{0}']), + ('\u{2126}', ['\u{3c9}', '\u{0}', '\u{0}']), ('\u{212a}', ['k', '\u{0}', '\u{0}']), + ('\u{212b}', ['\u{e5}', '\u{0}', '\u{0}']), ('\u{2132}', ['\u{214e}', '\u{0}', '\u{0}']), + ('\u{2160}', ['\u{2170}', '\u{0}', '\u{0}']), ('\u{2161}', ['\u{2171}', '\u{0}', '\u{0}']), + ('\u{2162}', ['\u{2172}', '\u{0}', '\u{0}']), ('\u{2163}', ['\u{2173}', '\u{0}', '\u{0}']), + ('\u{2164}', ['\u{2174}', '\u{0}', '\u{0}']), ('\u{2165}', ['\u{2175}', '\u{0}', '\u{0}']), + ('\u{2166}', ['\u{2176}', '\u{0}', '\u{0}']), ('\u{2167}', ['\u{2177}', '\u{0}', '\u{0}']), + ('\u{2168}', ['\u{2178}', '\u{0}', '\u{0}']), ('\u{2169}', ['\u{2179}', '\u{0}', '\u{0}']), + ('\u{216a}', ['\u{217a}', '\u{0}', '\u{0}']), ('\u{216b}', ['\u{217b}', '\u{0}', '\u{0}']), + ('\u{216c}', ['\u{217c}', '\u{0}', '\u{0}']), ('\u{216d}', ['\u{217d}', '\u{0}', '\u{0}']), + ('\u{216e}', ['\u{217e}', '\u{0}', '\u{0}']), ('\u{216f}', ['\u{217f}', '\u{0}', '\u{0}']), + ('\u{2183}', ['\u{2184}', '\u{0}', '\u{0}']), ('\u{24b6}', ['\u{24d0}', '\u{0}', '\u{0}']), + ('\u{24b7}', ['\u{24d1}', '\u{0}', '\u{0}']), ('\u{24b8}', ['\u{24d2}', '\u{0}', '\u{0}']), + ('\u{24b9}', ['\u{24d3}', '\u{0}', '\u{0}']), ('\u{24ba}', ['\u{24d4}', '\u{0}', '\u{0}']), + ('\u{24bb}', ['\u{24d5}', '\u{0}', '\u{0}']), ('\u{24bc}', ['\u{24d6}', '\u{0}', '\u{0}']), + ('\u{24bd}', ['\u{24d7}', '\u{0}', '\u{0}']), ('\u{24be}', ['\u{24d8}', '\u{0}', '\u{0}']), + ('\u{24bf}', ['\u{24d9}', '\u{0}', '\u{0}']), ('\u{24c0}', ['\u{24da}', '\u{0}', '\u{0}']), + ('\u{24c1}', ['\u{24db}', '\u{0}', '\u{0}']), ('\u{24c2}', ['\u{24dc}', '\u{0}', '\u{0}']), + ('\u{24c3}', ['\u{24dd}', '\u{0}', '\u{0}']), ('\u{24c4}', ['\u{24de}', '\u{0}', '\u{0}']), + ('\u{24c5}', ['\u{24df}', '\u{0}', '\u{0}']), ('\u{24c6}', ['\u{24e0}', '\u{0}', '\u{0}']), + ('\u{24c7}', ['\u{24e1}', '\u{0}', '\u{0}']), ('\u{24c8}', ['\u{24e2}', '\u{0}', '\u{0}']), + ('\u{24c9}', ['\u{24e3}', '\u{0}', '\u{0}']), ('\u{24ca}', ['\u{24e4}', '\u{0}', '\u{0}']), + ('\u{24cb}', ['\u{24e5}', '\u{0}', '\u{0}']), ('\u{24cc}', ['\u{24e6}', '\u{0}', '\u{0}']), + ('\u{24cd}', ['\u{24e7}', '\u{0}', '\u{0}']), ('\u{24ce}', ['\u{24e8}', '\u{0}', '\u{0}']), + ('\u{24cf}', ['\u{24e9}', '\u{0}', '\u{0}']), ('\u{2c00}', ['\u{2c30}', '\u{0}', '\u{0}']), + ('\u{2c01}', ['\u{2c31}', '\u{0}', '\u{0}']), ('\u{2c02}', ['\u{2c32}', '\u{0}', '\u{0}']), + ('\u{2c03}', ['\u{2c33}', '\u{0}', '\u{0}']), ('\u{2c04}', ['\u{2c34}', '\u{0}', '\u{0}']), + ('\u{2c05}', ['\u{2c35}', '\u{0}', '\u{0}']), ('\u{2c06}', ['\u{2c36}', '\u{0}', '\u{0}']), + ('\u{2c07}', ['\u{2c37}', '\u{0}', '\u{0}']), ('\u{2c08}', ['\u{2c38}', '\u{0}', '\u{0}']), + ('\u{2c09}', ['\u{2c39}', '\u{0}', '\u{0}']), ('\u{2c0a}', ['\u{2c3a}', '\u{0}', '\u{0}']), + ('\u{2c0b}', ['\u{2c3b}', '\u{0}', '\u{0}']), ('\u{2c0c}', ['\u{2c3c}', '\u{0}', '\u{0}']), + ('\u{2c0d}', ['\u{2c3d}', '\u{0}', '\u{0}']), ('\u{2c0e}', ['\u{2c3e}', '\u{0}', '\u{0}']), + ('\u{2c0f}', ['\u{2c3f}', '\u{0}', '\u{0}']), ('\u{2c10}', ['\u{2c40}', '\u{0}', '\u{0}']), + ('\u{2c11}', ['\u{2c41}', '\u{0}', '\u{0}']), ('\u{2c12}', ['\u{2c42}', '\u{0}', '\u{0}']), + ('\u{2c13}', ['\u{2c43}', '\u{0}', '\u{0}']), ('\u{2c14}', ['\u{2c44}', '\u{0}', '\u{0}']), + ('\u{2c15}', ['\u{2c45}', '\u{0}', '\u{0}']), ('\u{2c16}', ['\u{2c46}', '\u{0}', '\u{0}']), + ('\u{2c17}', ['\u{2c47}', '\u{0}', '\u{0}']), ('\u{2c18}', ['\u{2c48}', '\u{0}', '\u{0}']), + ('\u{2c19}', ['\u{2c49}', '\u{0}', '\u{0}']), ('\u{2c1a}', ['\u{2c4a}', '\u{0}', '\u{0}']), + ('\u{2c1b}', ['\u{2c4b}', '\u{0}', '\u{0}']), ('\u{2c1c}', ['\u{2c4c}', '\u{0}', '\u{0}']), + ('\u{2c1d}', ['\u{2c4d}', '\u{0}', '\u{0}']), ('\u{2c1e}', ['\u{2c4e}', '\u{0}', '\u{0}']), + ('\u{2c1f}', ['\u{2c4f}', '\u{0}', '\u{0}']), ('\u{2c20}', ['\u{2c50}', '\u{0}', '\u{0}']), + ('\u{2c21}', ['\u{2c51}', '\u{0}', '\u{0}']), ('\u{2c22}', ['\u{2c52}', '\u{0}', '\u{0}']), + ('\u{2c23}', ['\u{2c53}', '\u{0}', '\u{0}']), ('\u{2c24}', ['\u{2c54}', '\u{0}', '\u{0}']), + ('\u{2c25}', ['\u{2c55}', '\u{0}', '\u{0}']), ('\u{2c26}', ['\u{2c56}', '\u{0}', '\u{0}']), + ('\u{2c27}', ['\u{2c57}', '\u{0}', '\u{0}']), ('\u{2c28}', ['\u{2c58}', '\u{0}', '\u{0}']), + ('\u{2c29}', ['\u{2c59}', '\u{0}', '\u{0}']), ('\u{2c2a}', ['\u{2c5a}', '\u{0}', '\u{0}']), + ('\u{2c2b}', ['\u{2c5b}', '\u{0}', '\u{0}']), ('\u{2c2c}', ['\u{2c5c}', '\u{0}', '\u{0}']), + ('\u{2c2d}', ['\u{2c5d}', '\u{0}', '\u{0}']), ('\u{2c2e}', ['\u{2c5e}', '\u{0}', '\u{0}']), + ('\u{2c2f}', ['\u{2c5f}', '\u{0}', '\u{0}']), ('\u{2c60}', ['\u{2c61}', '\u{0}', '\u{0}']), + ('\u{2c62}', ['\u{26b}', '\u{0}', '\u{0}']), ('\u{2c63}', ['\u{1d7d}', '\u{0}', '\u{0}']), + ('\u{2c64}', ['\u{27d}', '\u{0}', '\u{0}']), ('\u{2c67}', ['\u{2c68}', '\u{0}', '\u{0}']), + ('\u{2c69}', ['\u{2c6a}', '\u{0}', '\u{0}']), ('\u{2c6b}', ['\u{2c6c}', '\u{0}', '\u{0}']), + ('\u{2c6d}', ['\u{251}', '\u{0}', '\u{0}']), ('\u{2c6e}', ['\u{271}', '\u{0}', '\u{0}']), + ('\u{2c6f}', ['\u{250}', '\u{0}', '\u{0}']), ('\u{2c70}', ['\u{252}', '\u{0}', '\u{0}']), + ('\u{2c72}', ['\u{2c73}', '\u{0}', '\u{0}']), ('\u{2c75}', ['\u{2c76}', '\u{0}', '\u{0}']), + ('\u{2c7e}', ['\u{23f}', '\u{0}', '\u{0}']), ('\u{2c7f}', ['\u{240}', '\u{0}', '\u{0}']), + ('\u{2c80}', ['\u{2c81}', '\u{0}', '\u{0}']), ('\u{2c82}', ['\u{2c83}', '\u{0}', '\u{0}']), + ('\u{2c84}', ['\u{2c85}', '\u{0}', '\u{0}']), ('\u{2c86}', ['\u{2c87}', '\u{0}', '\u{0}']), + ('\u{2c88}', ['\u{2c89}', '\u{0}', '\u{0}']), ('\u{2c8a}', ['\u{2c8b}', '\u{0}', '\u{0}']), + ('\u{2c8c}', ['\u{2c8d}', '\u{0}', '\u{0}']), ('\u{2c8e}', ['\u{2c8f}', '\u{0}', '\u{0}']), + ('\u{2c90}', ['\u{2c91}', '\u{0}', '\u{0}']), ('\u{2c92}', ['\u{2c93}', '\u{0}', '\u{0}']), + ('\u{2c94}', ['\u{2c95}', '\u{0}', '\u{0}']), ('\u{2c96}', ['\u{2c97}', '\u{0}', '\u{0}']), + ('\u{2c98}', ['\u{2c99}', '\u{0}', '\u{0}']), ('\u{2c9a}', ['\u{2c9b}', '\u{0}', '\u{0}']), + ('\u{2c9c}', ['\u{2c9d}', '\u{0}', '\u{0}']), ('\u{2c9e}', ['\u{2c9f}', '\u{0}', '\u{0}']), + ('\u{2ca0}', ['\u{2ca1}', '\u{0}', '\u{0}']), ('\u{2ca2}', ['\u{2ca3}', '\u{0}', '\u{0}']), + ('\u{2ca4}', ['\u{2ca5}', '\u{0}', '\u{0}']), ('\u{2ca6}', ['\u{2ca7}', '\u{0}', '\u{0}']), + ('\u{2ca8}', ['\u{2ca9}', '\u{0}', '\u{0}']), ('\u{2caa}', ['\u{2cab}', '\u{0}', '\u{0}']), + ('\u{2cac}', ['\u{2cad}', '\u{0}', '\u{0}']), ('\u{2cae}', ['\u{2caf}', '\u{0}', '\u{0}']), + ('\u{2cb0}', ['\u{2cb1}', '\u{0}', '\u{0}']), ('\u{2cb2}', ['\u{2cb3}', '\u{0}', '\u{0}']), + ('\u{2cb4}', ['\u{2cb5}', '\u{0}', '\u{0}']), ('\u{2cb6}', ['\u{2cb7}', '\u{0}', '\u{0}']), + ('\u{2cb8}', ['\u{2cb9}', '\u{0}', '\u{0}']), ('\u{2cba}', ['\u{2cbb}', '\u{0}', '\u{0}']), + ('\u{2cbc}', ['\u{2cbd}', '\u{0}', '\u{0}']), ('\u{2cbe}', ['\u{2cbf}', '\u{0}', '\u{0}']), + ('\u{2cc0}', ['\u{2cc1}', '\u{0}', '\u{0}']), ('\u{2cc2}', ['\u{2cc3}', '\u{0}', '\u{0}']), + ('\u{2cc4}', ['\u{2cc5}', '\u{0}', '\u{0}']), ('\u{2cc6}', ['\u{2cc7}', '\u{0}', '\u{0}']), + ('\u{2cc8}', ['\u{2cc9}', '\u{0}', '\u{0}']), ('\u{2cca}', ['\u{2ccb}', '\u{0}', '\u{0}']), + ('\u{2ccc}', ['\u{2ccd}', '\u{0}', '\u{0}']), ('\u{2cce}', ['\u{2ccf}', '\u{0}', '\u{0}']), + ('\u{2cd0}', ['\u{2cd1}', '\u{0}', '\u{0}']), ('\u{2cd2}', ['\u{2cd3}', '\u{0}', '\u{0}']), + ('\u{2cd4}', ['\u{2cd5}', '\u{0}', '\u{0}']), ('\u{2cd6}', ['\u{2cd7}', '\u{0}', '\u{0}']), + ('\u{2cd8}', ['\u{2cd9}', '\u{0}', '\u{0}']), ('\u{2cda}', ['\u{2cdb}', '\u{0}', '\u{0}']), + ('\u{2cdc}', ['\u{2cdd}', '\u{0}', '\u{0}']), ('\u{2cde}', ['\u{2cdf}', '\u{0}', '\u{0}']), + ('\u{2ce0}', ['\u{2ce1}', '\u{0}', '\u{0}']), ('\u{2ce2}', ['\u{2ce3}', '\u{0}', '\u{0}']), + ('\u{2ceb}', ['\u{2cec}', '\u{0}', '\u{0}']), ('\u{2ced}', ['\u{2cee}', '\u{0}', '\u{0}']), + ('\u{2cf2}', ['\u{2cf3}', '\u{0}', '\u{0}']), ('\u{a640}', ['\u{a641}', '\u{0}', '\u{0}']), + ('\u{a642}', ['\u{a643}', '\u{0}', '\u{0}']), ('\u{a644}', ['\u{a645}', '\u{0}', '\u{0}']), + ('\u{a646}', ['\u{a647}', '\u{0}', '\u{0}']), ('\u{a648}', ['\u{a649}', '\u{0}', '\u{0}']), + ('\u{a64a}', ['\u{a64b}', '\u{0}', '\u{0}']), ('\u{a64c}', ['\u{a64d}', '\u{0}', '\u{0}']), + ('\u{a64e}', ['\u{a64f}', '\u{0}', '\u{0}']), ('\u{a650}', ['\u{a651}', '\u{0}', '\u{0}']), + ('\u{a652}', ['\u{a653}', '\u{0}', '\u{0}']), ('\u{a654}', ['\u{a655}', '\u{0}', '\u{0}']), + ('\u{a656}', ['\u{a657}', '\u{0}', '\u{0}']), ('\u{a658}', ['\u{a659}', '\u{0}', '\u{0}']), + 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['\u{a697}', '\u{0}', '\u{0}']), + ('\u{a698}', ['\u{a699}', '\u{0}', '\u{0}']), ('\u{a69a}', ['\u{a69b}', '\u{0}', '\u{0}']), + ('\u{a722}', ['\u{a723}', '\u{0}', '\u{0}']), ('\u{a724}', ['\u{a725}', '\u{0}', '\u{0}']), + ('\u{a726}', ['\u{a727}', '\u{0}', '\u{0}']), ('\u{a728}', ['\u{a729}', '\u{0}', '\u{0}']), + ('\u{a72a}', ['\u{a72b}', '\u{0}', '\u{0}']), ('\u{a72c}', ['\u{a72d}', '\u{0}', '\u{0}']), + ('\u{a72e}', ['\u{a72f}', '\u{0}', '\u{0}']), ('\u{a732}', ['\u{a733}', '\u{0}', '\u{0}']), + ('\u{a734}', ['\u{a735}', '\u{0}', '\u{0}']), ('\u{a736}', ['\u{a737}', '\u{0}', '\u{0}']), + ('\u{a738}', ['\u{a739}', '\u{0}', '\u{0}']), ('\u{a73a}', ['\u{a73b}', '\u{0}', '\u{0}']), + ('\u{a73c}', ['\u{a73d}', '\u{0}', '\u{0}']), ('\u{a73e}', ['\u{a73f}', '\u{0}', '\u{0}']), + ('\u{a740}', ['\u{a741}', '\u{0}', '\u{0}']), ('\u{a742}', ['\u{a743}', '\u{0}', '\u{0}']), + ('\u{a744}', ['\u{a745}', '\u{0}', '\u{0}']), ('\u{a746}', ['\u{a747}', '\u{0}', '\u{0}']), + ('\u{a748}', ['\u{a749}', '\u{0}', '\u{0}']), ('\u{a74a}', ['\u{a74b}', '\u{0}', '\u{0}']), + ('\u{a74c}', ['\u{a74d}', '\u{0}', '\u{0}']), ('\u{a74e}', ['\u{a74f}', '\u{0}', '\u{0}']), + ('\u{a750}', ['\u{a751}', '\u{0}', '\u{0}']), ('\u{a752}', ['\u{a753}', '\u{0}', '\u{0}']), + ('\u{a754}', ['\u{a755}', '\u{0}', '\u{0}']), ('\u{a756}', ['\u{a757}', '\u{0}', '\u{0}']), + ('\u{a758}', ['\u{a759}', '\u{0}', '\u{0}']), ('\u{a75a}', ['\u{a75b}', '\u{0}', '\u{0}']), + ('\u{a75c}', ['\u{a75d}', '\u{0}', '\u{0}']), ('\u{a75e}', ['\u{a75f}', '\u{0}', '\u{0}']), + ('\u{a760}', ['\u{a761}', '\u{0}', '\u{0}']), ('\u{a762}', ['\u{a763}', '\u{0}', '\u{0}']), + ('\u{a764}', ['\u{a765}', '\u{0}', '\u{0}']), ('\u{a766}', ['\u{a767}', '\u{0}', '\u{0}']), + ('\u{a768}', ['\u{a769}', '\u{0}', '\u{0}']), ('\u{a76a}', ['\u{a76b}', '\u{0}', '\u{0}']), + ('\u{a76c}', ['\u{a76d}', '\u{0}', '\u{0}']), ('\u{a76e}', ['\u{a76f}', '\u{0}', '\u{0}']), + ('\u{a779}', ['\u{a77a}', '\u{0}', '\u{0}']), ('\u{a77b}', ['\u{a77c}', '\u{0}', '\u{0}']), + ('\u{a77d}', ['\u{1d79}', '\u{0}', '\u{0}']), ('\u{a77e}', ['\u{a77f}', '\u{0}', '\u{0}']), + ('\u{a780}', ['\u{a781}', '\u{0}', '\u{0}']), ('\u{a782}', ['\u{a783}', '\u{0}', '\u{0}']), + ('\u{a784}', ['\u{a785}', '\u{0}', '\u{0}']), ('\u{a786}', ['\u{a787}', '\u{0}', '\u{0}']), + ('\u{a78b}', ['\u{a78c}', '\u{0}', '\u{0}']), ('\u{a78d}', ['\u{265}', '\u{0}', '\u{0}']), + ('\u{a790}', ['\u{a791}', '\u{0}', '\u{0}']), ('\u{a792}', ['\u{a793}', '\u{0}', '\u{0}']), + ('\u{a796}', ['\u{a797}', '\u{0}', '\u{0}']), ('\u{a798}', ['\u{a799}', '\u{0}', '\u{0}']), + ('\u{a79a}', ['\u{a79b}', '\u{0}', '\u{0}']), ('\u{a79c}', ['\u{a79d}', '\u{0}', '\u{0}']), + ('\u{a79e}', ['\u{a79f}', '\u{0}', '\u{0}']), ('\u{a7a0}', ['\u{a7a1}', '\u{0}', '\u{0}']), + ('\u{a7a2}', ['\u{a7a3}', '\u{0}', '\u{0}']), ('\u{a7a4}', ['\u{a7a5}', '\u{0}', '\u{0}']), + ('\u{a7a6}', ['\u{a7a7}', '\u{0}', '\u{0}']), ('\u{a7a8}', ['\u{a7a9}', '\u{0}', '\u{0}']), + ('\u{a7aa}', ['\u{266}', '\u{0}', '\u{0}']), ('\u{a7ab}', ['\u{25c}', '\u{0}', '\u{0}']), + ('\u{a7ac}', ['\u{261}', '\u{0}', '\u{0}']), ('\u{a7ad}', ['\u{26c}', '\u{0}', '\u{0}']), + ('\u{a7ae}', ['\u{26a}', '\u{0}', '\u{0}']), ('\u{a7b0}', ['\u{29e}', '\u{0}', '\u{0}']), + ('\u{a7b1}', ['\u{287}', '\u{0}', '\u{0}']), ('\u{a7b2}', ['\u{29d}', '\u{0}', '\u{0}']), + ('\u{a7b3}', ['\u{ab53}', '\u{0}', '\u{0}']), ('\u{a7b4}', ['\u{a7b5}', '\u{0}', '\u{0}']), + ('\u{a7b6}', ['\u{a7b7}', '\u{0}', '\u{0}']), ('\u{a7b8}', ['\u{a7b9}', '\u{0}', '\u{0}']), + ('\u{a7ba}', ['\u{a7bb}', '\u{0}', '\u{0}']), ('\u{a7bc}', ['\u{a7bd}', '\u{0}', '\u{0}']), + ('\u{a7be}', ['\u{a7bf}', '\u{0}', '\u{0}']), ('\u{a7c0}', ['\u{a7c1}', '\u{0}', '\u{0}']), + ('\u{a7c2}', ['\u{a7c3}', '\u{0}', '\u{0}']), ('\u{a7c4}', ['\u{a794}', '\u{0}', '\u{0}']), + ('\u{a7c5}', ['\u{282}', '\u{0}', '\u{0}']), ('\u{a7c6}', ['\u{1d8e}', '\u{0}', '\u{0}']), + ('\u{a7c7}', ['\u{a7c8}', '\u{0}', '\u{0}']), ('\u{a7c9}', ['\u{a7ca}', '\u{0}', '\u{0}']), + ('\u{a7cb}', ['\u{264}', '\u{0}', '\u{0}']), ('\u{a7cc}', ['\u{a7cd}', '\u{0}', '\u{0}']), + ('\u{a7ce}', ['\u{a7cf}', '\u{0}', '\u{0}']), ('\u{a7d0}', ['\u{a7d1}', '\u{0}', '\u{0}']), + ('\u{a7d2}', ['\u{a7d3}', '\u{0}', '\u{0}']), ('\u{a7d4}', ['\u{a7d5}', '\u{0}', '\u{0}']), + ('\u{a7d6}', ['\u{a7d7}', '\u{0}', '\u{0}']), ('\u{a7d8}', ['\u{a7d9}', '\u{0}', '\u{0}']), + ('\u{a7da}', ['\u{a7db}', '\u{0}', '\u{0}']), ('\u{a7dc}', ['\u{19b}', '\u{0}', '\u{0}']), + ('\u{a7f5}', ['\u{a7f6}', '\u{0}', '\u{0}']), ('\u{ff21}', ['\u{ff41}', '\u{0}', '\u{0}']), + ('\u{ff22}', ['\u{ff42}', '\u{0}', '\u{0}']), ('\u{ff23}', ['\u{ff43}', '\u{0}', '\u{0}']), + ('\u{ff24}', ['\u{ff44}', '\u{0}', '\u{0}']), ('\u{ff25}', ['\u{ff45}', '\u{0}', '\u{0}']), + ('\u{ff26}', ['\u{ff46}', '\u{0}', '\u{0}']), ('\u{ff27}', ['\u{ff47}', '\u{0}', '\u{0}']), + ('\u{ff28}', ['\u{ff48}', '\u{0}', '\u{0}']), ('\u{ff29}', ['\u{ff49}', '\u{0}', '\u{0}']), + ('\u{ff2a}', ['\u{ff4a}', '\u{0}', '\u{0}']), ('\u{ff2b}', ['\u{ff4b}', '\u{0}', '\u{0}']), + ('\u{ff2c}', ['\u{ff4c}', '\u{0}', '\u{0}']), ('\u{ff2d}', ['\u{ff4d}', '\u{0}', '\u{0}']), + ('\u{ff2e}', ['\u{ff4e}', '\u{0}', '\u{0}']), ('\u{ff2f}', ['\u{ff4f}', '\u{0}', '\u{0}']), + ('\u{ff30}', ['\u{ff50}', '\u{0}', '\u{0}']), ('\u{ff31}', ['\u{ff51}', '\u{0}', '\u{0}']), + ('\u{ff32}', ['\u{ff52}', '\u{0}', '\u{0}']), ('\u{ff33}', ['\u{ff53}', '\u{0}', '\u{0}']), + ('\u{ff34}', ['\u{ff54}', '\u{0}', '\u{0}']), ('\u{ff35}', ['\u{ff55}', '\u{0}', '\u{0}']), + ('\u{ff36}', ['\u{ff56}', '\u{0}', '\u{0}']), ('\u{ff37}', ['\u{ff57}', '\u{0}', '\u{0}']), + ('\u{ff38}', ['\u{ff58}', '\u{0}', '\u{0}']), ('\u{ff39}', ['\u{ff59}', '\u{0}', '\u{0}']), + ('\u{ff3a}', ['\u{ff5a}', '\u{0}', '\u{0}']), + ('\u{10400}', ['\u{10428}', '\u{0}', '\u{0}']), + ('\u{10401}', ['\u{10429}', '\u{0}', '\u{0}']), + ('\u{10402}', ['\u{1042a}', '\u{0}', '\u{0}']), + ('\u{10403}', ['\u{1042b}', '\u{0}', '\u{0}']), + ('\u{10404}', ['\u{1042c}', '\u{0}', '\u{0}']), + ('\u{10405}', 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['\u{10d73}', '\u{0}', '\u{0}']), + ('\u{10d54}', ['\u{10d74}', '\u{0}', '\u{0}']), + ('\u{10d55}', ['\u{10d75}', '\u{0}', '\u{0}']), + ('\u{10d56}', ['\u{10d76}', '\u{0}', '\u{0}']), + ('\u{10d57}', ['\u{10d77}', '\u{0}', '\u{0}']), + ('\u{10d58}', ['\u{10d78}', '\u{0}', '\u{0}']), + ('\u{10d59}', ['\u{10d79}', '\u{0}', '\u{0}']), + ('\u{10d5a}', ['\u{10d7a}', '\u{0}', '\u{0}']), + ('\u{10d5b}', ['\u{10d7b}', '\u{0}', '\u{0}']), + ('\u{10d5c}', ['\u{10d7c}', '\u{0}', '\u{0}']), + ('\u{10d5d}', ['\u{10d7d}', '\u{0}', '\u{0}']), + ('\u{10d5e}', ['\u{10d7e}', '\u{0}', '\u{0}']), + ('\u{10d5f}', ['\u{10d7f}', '\u{0}', '\u{0}']), + ('\u{10d60}', ['\u{10d80}', '\u{0}', '\u{0}']), + ('\u{10d61}', ['\u{10d81}', '\u{0}', '\u{0}']), + ('\u{10d62}', ['\u{10d82}', '\u{0}', '\u{0}']), + ('\u{10d63}', ['\u{10d83}', '\u{0}', '\u{0}']), + ('\u{10d64}', ['\u{10d84}', '\u{0}', '\u{0}']), + ('\u{10d65}', ['\u{10d85}', '\u{0}', '\u{0}']), + ('\u{118a0}', ['\u{118c0}', '\u{0}', '\u{0}']), + ('\u{118a1}', ['\u{118c1}', '\u{0}', '\u{0}']), + ('\u{118a2}', ['\u{118c2}', '\u{0}', '\u{0}']), + ('\u{118a3}', ['\u{118c3}', '\u{0}', '\u{0}']), + ('\u{118a4}', ['\u{118c4}', '\u{0}', '\u{0}']), + ('\u{118a5}', ['\u{118c5}', '\u{0}', '\u{0}']), + ('\u{118a6}', ['\u{118c6}', '\u{0}', '\u{0}']), + ('\u{118a7}', ['\u{118c7}', '\u{0}', '\u{0}']), + ('\u{118a8}', ['\u{118c8}', '\u{0}', '\u{0}']), + ('\u{118a9}', ['\u{118c9}', '\u{0}', '\u{0}']), + ('\u{118aa}', ['\u{118ca}', '\u{0}', '\u{0}']), + ('\u{118ab}', ['\u{118cb}', '\u{0}', '\u{0}']), + ('\u{118ac}', ['\u{118cc}', '\u{0}', '\u{0}']), + ('\u{118ad}', ['\u{118cd}', '\u{0}', '\u{0}']), + ('\u{118ae}', ['\u{118ce}', '\u{0}', '\u{0}']), + ('\u{118af}', ['\u{118cf}', '\u{0}', '\u{0}']), + ('\u{118b0}', ['\u{118d0}', '\u{0}', '\u{0}']), + ('\u{118b1}', ['\u{118d1}', '\u{0}', '\u{0}']), + ('\u{118b2}', ['\u{118d2}', '\u{0}', '\u{0}']), + ('\u{118b3}', ['\u{118d3}', '\u{0}', '\u{0}']), + ('\u{118b4}', ['\u{118d4}', '\u{0}', '\u{0}']), + ('\u{118b5}', ['\u{118d5}', '\u{0}', '\u{0}']), + ('\u{118b6}', ['\u{118d6}', '\u{0}', '\u{0}']), + ('\u{118b7}', ['\u{118d7}', '\u{0}', '\u{0}']), + ('\u{118b8}', ['\u{118d8}', '\u{0}', '\u{0}']), + ('\u{118b9}', ['\u{118d9}', '\u{0}', '\u{0}']), + ('\u{118ba}', ['\u{118da}', '\u{0}', '\u{0}']), + ('\u{118bb}', ['\u{118db}', '\u{0}', '\u{0}']), + ('\u{118bc}', ['\u{118dc}', '\u{0}', '\u{0}']), + ('\u{118bd}', ['\u{118dd}', '\u{0}', '\u{0}']), + ('\u{118be}', ['\u{118de}', '\u{0}', '\u{0}']), + ('\u{118bf}', ['\u{118df}', '\u{0}', '\u{0}']), + ('\u{16e40}', ['\u{16e60}', '\u{0}', '\u{0}']), + ('\u{16e41}', ['\u{16e61}', '\u{0}', '\u{0}']), + ('\u{16e42}', ['\u{16e62}', '\u{0}', '\u{0}']), + ('\u{16e43}', ['\u{16e63}', '\u{0}', '\u{0}']), + ('\u{16e44}', ['\u{16e64}', '\u{0}', '\u{0}']), + ('\u{16e45}', ['\u{16e65}', '\u{0}', '\u{0}']), + ('\u{16e46}', ['\u{16e66}', '\u{0}', '\u{0}']), + ('\u{16e47}', ['\u{16e67}', '\u{0}', '\u{0}']), + ('\u{16e48}', ['\u{16e68}', '\u{0}', '\u{0}']), + ('\u{16e49}', ['\u{16e69}', '\u{0}', '\u{0}']), + ('\u{16e4a}', ['\u{16e6a}', '\u{0}', '\u{0}']), + ('\u{16e4b}', ['\u{16e6b}', '\u{0}', '\u{0}']), + ('\u{16e4c}', ['\u{16e6c}', '\u{0}', '\u{0}']), + ('\u{16e4d}', ['\u{16e6d}', '\u{0}', '\u{0}']), + ('\u{16e4e}', ['\u{16e6e}', '\u{0}', '\u{0}']), + ('\u{16e4f}', ['\u{16e6f}', '\u{0}', '\u{0}']), + ('\u{16e50}', ['\u{16e70}', '\u{0}', '\u{0}']), + ('\u{16e51}', ['\u{16e71}', '\u{0}', '\u{0}']), + ('\u{16e52}', ['\u{16e72}', '\u{0}', '\u{0}']), + ('\u{16e53}', ['\u{16e73}', '\u{0}', '\u{0}']), + ('\u{16e54}', ['\u{16e74}', '\u{0}', '\u{0}']), + ('\u{16e55}', ['\u{16e75}', '\u{0}', '\u{0}']), + ('\u{16e56}', ['\u{16e76}', '\u{0}', '\u{0}']), + ('\u{16e57}', ['\u{16e77}', '\u{0}', '\u{0}']), + ('\u{16e58}', ['\u{16e78}', '\u{0}', '\u{0}']), + ('\u{16e59}', ['\u{16e79}', '\u{0}', '\u{0}']), + ('\u{16e5a}', ['\u{16e7a}', '\u{0}', '\u{0}']), + ('\u{16e5b}', ['\u{16e7b}', '\u{0}', '\u{0}']), + ('\u{16e5c}', ['\u{16e7c}', '\u{0}', '\u{0}']), + ('\u{16e5d}', ['\u{16e7d}', '\u{0}', '\u{0}']), + ('\u{16e5e}', ['\u{16e7e}', '\u{0}', '\u{0}']), + ('\u{16e5f}', ['\u{16e7f}', '\u{0}', '\u{0}']), + ('\u{16ea0}', ['\u{16ebb}', '\u{0}', '\u{0}']), + ('\u{16ea1}', ['\u{16ebc}', '\u{0}', '\u{0}']), + ('\u{16ea2}', ['\u{16ebd}', '\u{0}', '\u{0}']), + ('\u{16ea3}', ['\u{16ebe}', '\u{0}', '\u{0}']), + ('\u{16ea4}', ['\u{16ebf}', '\u{0}', '\u{0}']), + ('\u{16ea5}', ['\u{16ec0}', '\u{0}', '\u{0}']), + ('\u{16ea6}', ['\u{16ec1}', '\u{0}', '\u{0}']), + ('\u{16ea7}', ['\u{16ec2}', '\u{0}', '\u{0}']), + ('\u{16ea8}', ['\u{16ec3}', '\u{0}', '\u{0}']), + ('\u{16ea9}', ['\u{16ec4}', '\u{0}', '\u{0}']), + ('\u{16eaa}', ['\u{16ec5}', '\u{0}', '\u{0}']), + ('\u{16eab}', ['\u{16ec6}', '\u{0}', '\u{0}']), + ('\u{16eac}', ['\u{16ec7}', '\u{0}', '\u{0}']), + ('\u{16ead}', ['\u{16ec8}', '\u{0}', '\u{0}']), + ('\u{16eae}', ['\u{16ec9}', '\u{0}', '\u{0}']), + ('\u{16eaf}', ['\u{16eca}', '\u{0}', '\u{0}']), + ('\u{16eb0}', ['\u{16ecb}', '\u{0}', '\u{0}']), + ('\u{16eb1}', ['\u{16ecc}', '\u{0}', '\u{0}']), + ('\u{16eb2}', ['\u{16ecd}', '\u{0}', '\u{0}']), + ('\u{16eb3}', ['\u{16ece}', '\u{0}', '\u{0}']), + ('\u{16eb4}', ['\u{16ecf}', '\u{0}', '\u{0}']), + ('\u{16eb5}', ['\u{16ed0}', '\u{0}', '\u{0}']), + ('\u{16eb6}', ['\u{16ed1}', '\u{0}', '\u{0}']), + ('\u{16eb7}', ['\u{16ed2}', '\u{0}', '\u{0}']), + ('\u{16eb8}', ['\u{16ed3}', '\u{0}', '\u{0}']), + ('\u{1e900}', ['\u{1e922}', '\u{0}', '\u{0}']), + ('\u{1e901}', ['\u{1e923}', '\u{0}', '\u{0}']), + ('\u{1e902}', ['\u{1e924}', '\u{0}', '\u{0}']), + ('\u{1e903}', ['\u{1e925}', '\u{0}', '\u{0}']), + ('\u{1e904}', ['\u{1e926}', '\u{0}', '\u{0}']), + ('\u{1e905}', ['\u{1e927}', '\u{0}', '\u{0}']), + ('\u{1e906}', ['\u{1e928}', '\u{0}', '\u{0}']), + ('\u{1e907}', ['\u{1e929}', '\u{0}', '\u{0}']), + ('\u{1e908}', ['\u{1e92a}', '\u{0}', '\u{0}']), + ('\u{1e909}', ['\u{1e92b}', '\u{0}', '\u{0}']), + ('\u{1e90a}', ['\u{1e92c}', '\u{0}', '\u{0}']), + ('\u{1e90b}', ['\u{1e92d}', '\u{0}', '\u{0}']), + ('\u{1e90c}', ['\u{1e92e}', '\u{0}', '\u{0}']), + ('\u{1e90d}', ['\u{1e92f}', '\u{0}', '\u{0}']), + ('\u{1e90e}', ['\u{1e930}', '\u{0}', '\u{0}']), + ('\u{1e90f}', ['\u{1e931}', '\u{0}', '\u{0}']), + ('\u{1e910}', ['\u{1e932}', '\u{0}', '\u{0}']), + ('\u{1e911}', ['\u{1e933}', '\u{0}', '\u{0}']), + ('\u{1e912}', ['\u{1e934}', '\u{0}', '\u{0}']), + ('\u{1e913}', ['\u{1e935}', '\u{0}', '\u{0}']), + ('\u{1e914}', ['\u{1e936}', '\u{0}', '\u{0}']), + ('\u{1e915}', ['\u{1e937}', '\u{0}', '\u{0}']), + ('\u{1e916}', ['\u{1e938}', '\u{0}', '\u{0}']), + ('\u{1e917}', ['\u{1e939}', '\u{0}', '\u{0}']), + ('\u{1e918}', ['\u{1e93a}', '\u{0}', '\u{0}']), + ('\u{1e919}', ['\u{1e93b}', '\u{0}', '\u{0}']), + ('\u{1e91a}', ['\u{1e93c}', '\u{0}', '\u{0}']), + ('\u{1e91b}', ['\u{1e93d}', '\u{0}', '\u{0}']), + ('\u{1e91c}', ['\u{1e93e}', '\u{0}', '\u{0}']), + ('\u{1e91d}', ['\u{1e93f}', '\u{0}', '\u{0}']), + ('\u{1e91e}', ['\u{1e940}', '\u{0}', '\u{0}']), + ('\u{1e91f}', ['\u{1e941}', '\u{0}', '\u{0}']), + ('\u{1e920}', ['\u{1e942}', '\u{0}', '\u{0}']), + ('\u{1e921}', ['\u{1e943}', '\u{0}', '\u{0}']), +]; + +#[rustfmt::skip] +pub(super) static TO_UPPER: &[(char, [char; 3]); 1554] = &[ + ('\u{b5}', ['\u{39c}', '\u{0}', '\u{0}']), ('\u{df}', ['S', 'S', '\u{0}']), + ('\u{e0}', ['\u{c0}', '\u{0}', '\u{0}']), ('\u{e1}', ['\u{c1}', '\u{0}', '\u{0}']), + ('\u{e2}', ['\u{c2}', '\u{0}', '\u{0}']), ('\u{e3}', ['\u{c3}', '\u{0}', '\u{0}']), + ('\u{e4}', ['\u{c4}', '\u{0}', '\u{0}']), ('\u{e5}', ['\u{c5}', '\u{0}', '\u{0}']), + ('\u{e6}', ['\u{c6}', '\u{0}', '\u{0}']), ('\u{e7}', ['\u{c7}', '\u{0}', '\u{0}']), + ('\u{e8}', ['\u{c8}', '\u{0}', '\u{0}']), ('\u{e9}', ['\u{c9}', '\u{0}', '\u{0}']), + ('\u{ea}', ['\u{ca}', '\u{0}', '\u{0}']), ('\u{eb}', ['\u{cb}', '\u{0}', '\u{0}']), + ('\u{ec}', ['\u{cc}', '\u{0}', '\u{0}']), ('\u{ed}', ['\u{cd}', '\u{0}', '\u{0}']), + ('\u{ee}', ['\u{ce}', '\u{0}', '\u{0}']), ('\u{ef}', ['\u{cf}', '\u{0}', '\u{0}']), + ('\u{f0}', ['\u{d0}', '\u{0}', '\u{0}']), ('\u{f1}', ['\u{d1}', '\u{0}', '\u{0}']), + ('\u{f2}', ['\u{d2}', '\u{0}', '\u{0}']), ('\u{f3}', ['\u{d3}', '\u{0}', '\u{0}']), + ('\u{f4}', ['\u{d4}', '\u{0}', '\u{0}']), ('\u{f5}', ['\u{d5}', '\u{0}', '\u{0}']), + ('\u{f6}', ['\u{d6}', '\u{0}', '\u{0}']), ('\u{f8}', ['\u{d8}', '\u{0}', '\u{0}']), + ('\u{f9}', ['\u{d9}', '\u{0}', '\u{0}']), ('\u{fa}', ['\u{da}', '\u{0}', '\u{0}']), + ('\u{fb}', ['\u{db}', '\u{0}', '\u{0}']), ('\u{fc}', ['\u{dc}', '\u{0}', '\u{0}']), + ('\u{fd}', ['\u{dd}', '\u{0}', '\u{0}']), ('\u{fe}', ['\u{de}', '\u{0}', '\u{0}']), + ('\u{ff}', ['\u{178}', '\u{0}', '\u{0}']), ('\u{101}', ['\u{100}', '\u{0}', '\u{0}']), + ('\u{103}', ['\u{102}', '\u{0}', '\u{0}']), ('\u{105}', ['\u{104}', '\u{0}', '\u{0}']), + ('\u{107}', ['\u{106}', '\u{0}', '\u{0}']), ('\u{109}', ['\u{108}', '\u{0}', '\u{0}']), + ('\u{10b}', ['\u{10a}', '\u{0}', '\u{0}']), ('\u{10d}', ['\u{10c}', '\u{0}', '\u{0}']), + ('\u{10f}', ['\u{10e}', '\u{0}', '\u{0}']), ('\u{111}', ['\u{110}', '\u{0}', '\u{0}']), + ('\u{113}', ['\u{112}', '\u{0}', '\u{0}']), ('\u{115}', ['\u{114}', '\u{0}', '\u{0}']), + ('\u{117}', ['\u{116}', '\u{0}', '\u{0}']), ('\u{119}', ['\u{118}', '\u{0}', '\u{0}']), + ('\u{11b}', ['\u{11a}', '\u{0}', '\u{0}']), ('\u{11d}', ['\u{11c}', '\u{0}', '\u{0}']), + ('\u{11f}', ['\u{11e}', '\u{0}', '\u{0}']), ('\u{121}', ['\u{120}', '\u{0}', '\u{0}']), + ('\u{123}', ['\u{122}', '\u{0}', '\u{0}']), ('\u{125}', ['\u{124}', '\u{0}', '\u{0}']), + ('\u{127}', ['\u{126}', '\u{0}', '\u{0}']), ('\u{129}', ['\u{128}', '\u{0}', '\u{0}']), + ('\u{12b}', ['\u{12a}', '\u{0}', '\u{0}']), ('\u{12d}', ['\u{12c}', '\u{0}', '\u{0}']), + ('\u{12f}', ['\u{12e}', '\u{0}', '\u{0}']), ('\u{131}', ['I', '\u{0}', '\u{0}']), + ('\u{133}', ['\u{132}', '\u{0}', '\u{0}']), ('\u{135}', ['\u{134}', '\u{0}', '\u{0}']), + ('\u{137}', ['\u{136}', '\u{0}', '\u{0}']), ('\u{13a}', ['\u{139}', '\u{0}', '\u{0}']), + ('\u{13c}', ['\u{13b}', '\u{0}', '\u{0}']), ('\u{13e}', ['\u{13d}', '\u{0}', '\u{0}']), + ('\u{140}', ['\u{13f}', '\u{0}', '\u{0}']), ('\u{142}', ['\u{141}', '\u{0}', '\u{0}']), + ('\u{144}', ['\u{143}', '\u{0}', '\u{0}']), ('\u{146}', ['\u{145}', '\u{0}', '\u{0}']), + ('\u{148}', ['\u{147}', '\u{0}', '\u{0}']), ('\u{149}', ['\u{2bc}', 'N', '\u{0}']), + ('\u{14b}', ['\u{14a}', '\u{0}', '\u{0}']), ('\u{14d}', ['\u{14c}', '\u{0}', '\u{0}']), + ('\u{14f}', ['\u{14e}', '\u{0}', '\u{0}']), ('\u{151}', ['\u{150}', '\u{0}', '\u{0}']), + ('\u{153}', ['\u{152}', '\u{0}', '\u{0}']), ('\u{155}', ['\u{154}', '\u{0}', '\u{0}']), + ('\u{157}', ['\u{156}', '\u{0}', '\u{0}']), ('\u{159}', ['\u{158}', '\u{0}', '\u{0}']), + ('\u{15b}', ['\u{15a}', '\u{0}', '\u{0}']), ('\u{15d}', ['\u{15c}', '\u{0}', '\u{0}']), + ('\u{15f}', ['\u{15e}', '\u{0}', '\u{0}']), ('\u{161}', ['\u{160}', '\u{0}', '\u{0}']), + ('\u{163}', ['\u{162}', '\u{0}', '\u{0}']), ('\u{165}', ['\u{164}', '\u{0}', '\u{0}']), + ('\u{167}', ['\u{166}', '\u{0}', '\u{0}']), ('\u{169}', ['\u{168}', '\u{0}', '\u{0}']), + ('\u{16b}', ['\u{16a}', '\u{0}', '\u{0}']), ('\u{16d}', ['\u{16c}', '\u{0}', '\u{0}']), + ('\u{16f}', ['\u{16e}', '\u{0}', '\u{0}']), ('\u{171}', ['\u{170}', '\u{0}', '\u{0}']), + ('\u{173}', ['\u{172}', '\u{0}', '\u{0}']), ('\u{175}', ['\u{174}', '\u{0}', '\u{0}']), + ('\u{177}', ['\u{176}', '\u{0}', '\u{0}']), ('\u{17a}', ['\u{179}', '\u{0}', '\u{0}']), + ('\u{17c}', ['\u{17b}', '\u{0}', '\u{0}']), ('\u{17e}', ['\u{17d}', '\u{0}', '\u{0}']), + ('\u{17f}', ['S', '\u{0}', '\u{0}']), ('\u{180}', ['\u{243}', '\u{0}', '\u{0}']), + ('\u{183}', ['\u{182}', '\u{0}', '\u{0}']), ('\u{185}', ['\u{184}', '\u{0}', '\u{0}']), + ('\u{188}', ['\u{187}', '\u{0}', '\u{0}']), ('\u{18c}', ['\u{18b}', '\u{0}', '\u{0}']), + ('\u{192}', ['\u{191}', '\u{0}', '\u{0}']), ('\u{195}', ['\u{1f6}', '\u{0}', '\u{0}']), + ('\u{199}', ['\u{198}', '\u{0}', '\u{0}']), ('\u{19a}', ['\u{23d}', '\u{0}', '\u{0}']), + ('\u{19b}', ['\u{a7dc}', '\u{0}', '\u{0}']), ('\u{19e}', ['\u{220}', '\u{0}', '\u{0}']), + ('\u{1a1}', ['\u{1a0}', '\u{0}', '\u{0}']), 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['\u{1cab}', '\u{0}', '\u{0}']), ('\u{10ec}', ['\u{1cac}', '\u{0}', '\u{0}']), + ('\u{10ed}', ['\u{1cad}', '\u{0}', '\u{0}']), ('\u{10ee}', ['\u{1cae}', '\u{0}', '\u{0}']), + ('\u{10ef}', ['\u{1caf}', '\u{0}', '\u{0}']), ('\u{10f0}', ['\u{1cb0}', '\u{0}', '\u{0}']), + ('\u{10f1}', ['\u{1cb1}', '\u{0}', '\u{0}']), ('\u{10f2}', ['\u{1cb2}', '\u{0}', '\u{0}']), + ('\u{10f3}', ['\u{1cb3}', '\u{0}', '\u{0}']), ('\u{10f4}', ['\u{1cb4}', '\u{0}', '\u{0}']), + ('\u{10f5}', ['\u{1cb5}', '\u{0}', '\u{0}']), ('\u{10f6}', ['\u{1cb6}', '\u{0}', '\u{0}']), + ('\u{10f7}', ['\u{1cb7}', '\u{0}', '\u{0}']), ('\u{10f8}', ['\u{1cb8}', '\u{0}', '\u{0}']), + ('\u{10f9}', ['\u{1cb9}', '\u{0}', '\u{0}']), ('\u{10fa}', ['\u{1cba}', '\u{0}', '\u{0}']), + ('\u{10fd}', ['\u{1cbd}', '\u{0}', '\u{0}']), ('\u{10fe}', ['\u{1cbe}', '\u{0}', '\u{0}']), + ('\u{10ff}', ['\u{1cbf}', '\u{0}', '\u{0}']), ('\u{13f8}', ['\u{13f0}', '\u{0}', '\u{0}']), + ('\u{13f9}', ['\u{13f1}', '\u{0}', '\u{0}']), ('\u{13fa}', ['\u{13f2}', '\u{0}', '\u{0}']), + ('\u{13fb}', ['\u{13f3}', '\u{0}', '\u{0}']), ('\u{13fc}', ['\u{13f4}', '\u{0}', '\u{0}']), + ('\u{13fd}', ['\u{13f5}', '\u{0}', '\u{0}']), ('\u{1c80}', ['\u{412}', '\u{0}', '\u{0}']), + ('\u{1c81}', ['\u{414}', '\u{0}', '\u{0}']), ('\u{1c82}', ['\u{41e}', '\u{0}', '\u{0}']), + ('\u{1c83}', ['\u{421}', '\u{0}', '\u{0}']), ('\u{1c84}', ['\u{422}', '\u{0}', '\u{0}']), + ('\u{1c85}', ['\u{422}', '\u{0}', '\u{0}']), ('\u{1c86}', ['\u{42a}', '\u{0}', '\u{0}']), + ('\u{1c87}', ['\u{462}', '\u{0}', '\u{0}']), ('\u{1c88}', ['\u{a64a}', '\u{0}', '\u{0}']), + ('\u{1c8a}', ['\u{1c89}', '\u{0}', '\u{0}']), ('\u{1d79}', ['\u{a77d}', '\u{0}', '\u{0}']), + ('\u{1d7d}', ['\u{2c63}', '\u{0}', '\u{0}']), ('\u{1d8e}', ['\u{a7c6}', '\u{0}', '\u{0}']), + ('\u{1e01}', ['\u{1e00}', '\u{0}', '\u{0}']), ('\u{1e03}', ['\u{1e02}', '\u{0}', '\u{0}']), + ('\u{1e05}', ['\u{1e04}', '\u{0}', '\u{0}']), ('\u{1e07}', ['\u{1e06}', '\u{0}', '\u{0}']), + ('\u{1e09}', ['\u{1e08}', '\u{0}', '\u{0}']), ('\u{1e0b}', ['\u{1e0a}', '\u{0}', '\u{0}']), + ('\u{1e0d}', ['\u{1e0c}', '\u{0}', '\u{0}']), ('\u{1e0f}', ['\u{1e0e}', '\u{0}', '\u{0}']), + ('\u{1e11}', ['\u{1e10}', '\u{0}', '\u{0}']), ('\u{1e13}', ['\u{1e12}', '\u{0}', '\u{0}']), + ('\u{1e15}', ['\u{1e14}', '\u{0}', '\u{0}']), ('\u{1e17}', ['\u{1e16}', '\u{0}', '\u{0}']), + ('\u{1e19}', ['\u{1e18}', '\u{0}', '\u{0}']), ('\u{1e1b}', ['\u{1e1a}', '\u{0}', '\u{0}']), + ('\u{1e1d}', ['\u{1e1c}', '\u{0}', '\u{0}']), ('\u{1e1f}', ['\u{1e1e}', '\u{0}', '\u{0}']), + ('\u{1e21}', ['\u{1e20}', '\u{0}', '\u{0}']), ('\u{1e23}', ['\u{1e22}', '\u{0}', '\u{0}']), + ('\u{1e25}', ['\u{1e24}', '\u{0}', '\u{0}']), ('\u{1e27}', ['\u{1e26}', '\u{0}', '\u{0}']), + ('\u{1e29}', ['\u{1e28}', '\u{0}', '\u{0}']), ('\u{1e2b}', ['\u{1e2a}', '\u{0}', '\u{0}']), + ('\u{1e2d}', ['\u{1e2c}', '\u{0}', '\u{0}']), ('\u{1e2f}', ['\u{1e2e}', '\u{0}', '\u{0}']), + ('\u{1e31}', ['\u{1e30}', '\u{0}', '\u{0}']), ('\u{1e33}', ['\u{1e32}', '\u{0}', '\u{0}']), + ('\u{1e35}', ['\u{1e34}', '\u{0}', '\u{0}']), ('\u{1e37}', ['\u{1e36}', '\u{0}', '\u{0}']), + ('\u{1e39}', ['\u{1e38}', '\u{0}', '\u{0}']), ('\u{1e3b}', ['\u{1e3a}', '\u{0}', '\u{0}']), + ('\u{1e3d}', ['\u{1e3c}', '\u{0}', '\u{0}']), ('\u{1e3f}', ['\u{1e3e}', '\u{0}', '\u{0}']), + ('\u{1e41}', ['\u{1e40}', '\u{0}', '\u{0}']), ('\u{1e43}', ['\u{1e42}', '\u{0}', '\u{0}']), + ('\u{1e45}', ['\u{1e44}', '\u{0}', '\u{0}']), ('\u{1e47}', ['\u{1e46}', '\u{0}', '\u{0}']), + ('\u{1e49}', ['\u{1e48}', '\u{0}', '\u{0}']), ('\u{1e4b}', ['\u{1e4a}', '\u{0}', '\u{0}']), + ('\u{1e4d}', ['\u{1e4c}', '\u{0}', '\u{0}']), ('\u{1e4f}', ['\u{1e4e}', '\u{0}', '\u{0}']), + ('\u{1e51}', ['\u{1e50}', '\u{0}', '\u{0}']), ('\u{1e53}', ['\u{1e52}', '\u{0}', '\u{0}']), + ('\u{1e55}', ['\u{1e54}', '\u{0}', '\u{0}']), ('\u{1e57}', ['\u{1e56}', '\u{0}', '\u{0}']), + ('\u{1e59}', ['\u{1e58}', '\u{0}', '\u{0}']), ('\u{1e5b}', ['\u{1e5a}', '\u{0}', '\u{0}']), + ('\u{1e5d}', ['\u{1e5c}', '\u{0}', '\u{0}']), ('\u{1e5f}', ['\u{1e5e}', '\u{0}', '\u{0}']), + ('\u{1e61}', ['\u{1e60}', '\u{0}', '\u{0}']), ('\u{1e63}', ['\u{1e62}', '\u{0}', '\u{0}']), + ('\u{1e65}', ['\u{1e64}', '\u{0}', '\u{0}']), ('\u{1e67}', ['\u{1e66}', '\u{0}', '\u{0}']), + ('\u{1e69}', ['\u{1e68}', '\u{0}', '\u{0}']), ('\u{1e6b}', ['\u{1e6a}', '\u{0}', '\u{0}']), + ('\u{1e6d}', ['\u{1e6c}', '\u{0}', '\u{0}']), ('\u{1e6f}', ['\u{1e6e}', '\u{0}', '\u{0}']), + ('\u{1e71}', ['\u{1e70}', '\u{0}', '\u{0}']), ('\u{1e73}', ['\u{1e72}', '\u{0}', '\u{0}']), + ('\u{1e75}', ['\u{1e74}', '\u{0}', '\u{0}']), ('\u{1e77}', ['\u{1e76}', '\u{0}', '\u{0}']), + ('\u{1e79}', ['\u{1e78}', '\u{0}', '\u{0}']), ('\u{1e7b}', ['\u{1e7a}', '\u{0}', '\u{0}']), + ('\u{1e7d}', ['\u{1e7c}', '\u{0}', '\u{0}']), ('\u{1e7f}', ['\u{1e7e}', '\u{0}', '\u{0}']), + ('\u{1e81}', ['\u{1e80}', '\u{0}', '\u{0}']), ('\u{1e83}', ['\u{1e82}', '\u{0}', '\u{0}']), + ('\u{1e85}', ['\u{1e84}', '\u{0}', '\u{0}']), ('\u{1e87}', ['\u{1e86}', '\u{0}', '\u{0}']), + ('\u{1e89}', ['\u{1e88}', '\u{0}', '\u{0}']), ('\u{1e8b}', ['\u{1e8a}', '\u{0}', '\u{0}']), + ('\u{1e8d}', ['\u{1e8c}', '\u{0}', '\u{0}']), ('\u{1e8f}', ['\u{1e8e}', '\u{0}', '\u{0}']), + ('\u{1e91}', ['\u{1e90}', '\u{0}', '\u{0}']), ('\u{1e93}', ['\u{1e92}', '\u{0}', '\u{0}']), + ('\u{1e95}', ['\u{1e94}', '\u{0}', '\u{0}']), ('\u{1e96}', ['H', '\u{331}', '\u{0}']), + ('\u{1e97}', ['T', '\u{308}', '\u{0}']), ('\u{1e98}', ['W', '\u{30a}', '\u{0}']), + ('\u{1e99}', ['Y', '\u{30a}', '\u{0}']), ('\u{1e9a}', ['A', '\u{2be}', '\u{0}']), + ('\u{1e9b}', ['\u{1e60}', '\u{0}', '\u{0}']), ('\u{1ea1}', ['\u{1ea0}', '\u{0}', '\u{0}']), + ('\u{1ea3}', ['\u{1ea2}', '\u{0}', '\u{0}']), ('\u{1ea5}', ['\u{1ea4}', '\u{0}', '\u{0}']), + ('\u{1ea7}', ['\u{1ea6}', '\u{0}', '\u{0}']), ('\u{1ea9}', ['\u{1ea8}', '\u{0}', '\u{0}']), + ('\u{1eab}', ['\u{1eaa}', '\u{0}', '\u{0}']), ('\u{1ead}', ['\u{1eac}', '\u{0}', '\u{0}']), + ('\u{1eaf}', ['\u{1eae}', '\u{0}', '\u{0}']), ('\u{1eb1}', ['\u{1eb0}', '\u{0}', '\u{0}']), + ('\u{1eb3}', ['\u{1eb2}', '\u{0}', '\u{0}']), ('\u{1eb5}', ['\u{1eb4}', '\u{0}', '\u{0}']), + ('\u{1eb7}', ['\u{1eb6}', '\u{0}', '\u{0}']), ('\u{1eb9}', ['\u{1eb8}', '\u{0}', '\u{0}']), + ('\u{1ebb}', ['\u{1eba}', '\u{0}', '\u{0}']), ('\u{1ebd}', ['\u{1ebc}', '\u{0}', '\u{0}']), + ('\u{1ebf}', ['\u{1ebe}', '\u{0}', '\u{0}']), ('\u{1ec1}', ['\u{1ec0}', '\u{0}', '\u{0}']), + ('\u{1ec3}', ['\u{1ec2}', '\u{0}', '\u{0}']), ('\u{1ec5}', ['\u{1ec4}', '\u{0}', '\u{0}']), + ('\u{1ec7}', ['\u{1ec6}', '\u{0}', '\u{0}']), ('\u{1ec9}', ['\u{1ec8}', '\u{0}', '\u{0}']), + ('\u{1ecb}', ['\u{1eca}', '\u{0}', '\u{0}']), ('\u{1ecd}', ['\u{1ecc}', '\u{0}', '\u{0}']), + ('\u{1ecf}', ['\u{1ece}', '\u{0}', '\u{0}']), ('\u{1ed1}', ['\u{1ed0}', '\u{0}', '\u{0}']), + ('\u{1ed3}', ['\u{1ed2}', '\u{0}', '\u{0}']), ('\u{1ed5}', ['\u{1ed4}', '\u{0}', '\u{0}']), + ('\u{1ed7}', ['\u{1ed6}', '\u{0}', '\u{0}']), ('\u{1ed9}', ['\u{1ed8}', '\u{0}', '\u{0}']), + ('\u{1edb}', ['\u{1eda}', '\u{0}', '\u{0}']), ('\u{1edd}', ['\u{1edc}', '\u{0}', '\u{0}']), + ('\u{1edf}', ['\u{1ede}', '\u{0}', '\u{0}']), ('\u{1ee1}', ['\u{1ee0}', '\u{0}', '\u{0}']), + ('\u{1ee3}', ['\u{1ee2}', '\u{0}', '\u{0}']), ('\u{1ee5}', ['\u{1ee4}', '\u{0}', '\u{0}']), + ('\u{1ee7}', ['\u{1ee6}', '\u{0}', '\u{0}']), ('\u{1ee9}', ['\u{1ee8}', '\u{0}', '\u{0}']), + ('\u{1eeb}', ['\u{1eea}', '\u{0}', '\u{0}']), ('\u{1eed}', ['\u{1eec}', '\u{0}', '\u{0}']), + ('\u{1eef}', ['\u{1eee}', '\u{0}', '\u{0}']), ('\u{1ef1}', ['\u{1ef0}', '\u{0}', '\u{0}']), + ('\u{1ef3}', ['\u{1ef2}', '\u{0}', '\u{0}']), ('\u{1ef5}', ['\u{1ef4}', '\u{0}', '\u{0}']), + ('\u{1ef7}', ['\u{1ef6}', '\u{0}', '\u{0}']), ('\u{1ef9}', ['\u{1ef8}', '\u{0}', '\u{0}']), + ('\u{1efb}', ['\u{1efa}', '\u{0}', '\u{0}']), ('\u{1efd}', ['\u{1efc}', '\u{0}', '\u{0}']), + ('\u{1eff}', ['\u{1efe}', '\u{0}', '\u{0}']), ('\u{1f00}', ['\u{1f08}', '\u{0}', '\u{0}']), + ('\u{1f01}', ['\u{1f09}', '\u{0}', '\u{0}']), ('\u{1f02}', ['\u{1f0a}', '\u{0}', '\u{0}']), + ('\u{1f03}', ['\u{1f0b}', '\u{0}', '\u{0}']), ('\u{1f04}', ['\u{1f0c}', '\u{0}', '\u{0}']), + ('\u{1f05}', ['\u{1f0d}', '\u{0}', '\u{0}']), ('\u{1f06}', ['\u{1f0e}', '\u{0}', '\u{0}']), + ('\u{1f07}', ['\u{1f0f}', '\u{0}', '\u{0}']), ('\u{1f10}', ['\u{1f18}', '\u{0}', '\u{0}']), + ('\u{1f11}', ['\u{1f19}', '\u{0}', '\u{0}']), ('\u{1f12}', ['\u{1f1a}', '\u{0}', '\u{0}']), + ('\u{1f13}', ['\u{1f1b}', '\u{0}', '\u{0}']), ('\u{1f14}', ['\u{1f1c}', '\u{0}', '\u{0}']), + ('\u{1f15}', ['\u{1f1d}', '\u{0}', '\u{0}']), ('\u{1f20}', ['\u{1f28}', '\u{0}', '\u{0}']), + ('\u{1f21}', ['\u{1f29}', '\u{0}', '\u{0}']), ('\u{1f22}', ['\u{1f2a}', '\u{0}', '\u{0}']), + ('\u{1f23}', ['\u{1f2b}', '\u{0}', '\u{0}']), ('\u{1f24}', ['\u{1f2c}', '\u{0}', '\u{0}']), + ('\u{1f25}', ['\u{1f2d}', '\u{0}', '\u{0}']), ('\u{1f26}', ['\u{1f2e}', '\u{0}', '\u{0}']), + ('\u{1f27}', ['\u{1f2f}', '\u{0}', '\u{0}']), ('\u{1f30}', ['\u{1f38}', '\u{0}', '\u{0}']), + ('\u{1f31}', ['\u{1f39}', '\u{0}', '\u{0}']), ('\u{1f32}', ['\u{1f3a}', '\u{0}', '\u{0}']), + ('\u{1f33}', ['\u{1f3b}', '\u{0}', '\u{0}']), ('\u{1f34}', ['\u{1f3c}', '\u{0}', '\u{0}']), + ('\u{1f35}', ['\u{1f3d}', '\u{0}', '\u{0}']), ('\u{1f36}', ['\u{1f3e}', '\u{0}', '\u{0}']), + ('\u{1f37}', ['\u{1f3f}', '\u{0}', '\u{0}']), ('\u{1f40}', ['\u{1f48}', '\u{0}', '\u{0}']), + ('\u{1f41}', ['\u{1f49}', '\u{0}', '\u{0}']), ('\u{1f42}', ['\u{1f4a}', '\u{0}', '\u{0}']), + ('\u{1f43}', ['\u{1f4b}', '\u{0}', '\u{0}']), ('\u{1f44}', ['\u{1f4c}', '\u{0}', '\u{0}']), + ('\u{1f45}', ['\u{1f4d}', '\u{0}', '\u{0}']), ('\u{1f50}', ['\u{3a5}', '\u{313}', '\u{0}']), + ('\u{1f51}', ['\u{1f59}', '\u{0}', '\u{0}']), + ('\u{1f52}', ['\u{3a5}', '\u{313}', '\u{300}']), + ('\u{1f53}', ['\u{1f5b}', '\u{0}', '\u{0}']), + ('\u{1f54}', ['\u{3a5}', '\u{313}', '\u{301}']), + ('\u{1f55}', ['\u{1f5d}', '\u{0}', '\u{0}']), + ('\u{1f56}', ['\u{3a5}', '\u{313}', '\u{342}']), + ('\u{1f57}', ['\u{1f5f}', '\u{0}', '\u{0}']), ('\u{1f60}', ['\u{1f68}', '\u{0}', '\u{0}']), + ('\u{1f61}', ['\u{1f69}', '\u{0}', '\u{0}']), ('\u{1f62}', ['\u{1f6a}', '\u{0}', '\u{0}']), + ('\u{1f63}', ['\u{1f6b}', '\u{0}', '\u{0}']), ('\u{1f64}', ['\u{1f6c}', '\u{0}', '\u{0}']), + ('\u{1f65}', ['\u{1f6d}', '\u{0}', '\u{0}']), ('\u{1f66}', ['\u{1f6e}', '\u{0}', '\u{0}']), + ('\u{1f67}', ['\u{1f6f}', '\u{0}', '\u{0}']), ('\u{1f70}', ['\u{1fba}', '\u{0}', '\u{0}']), + ('\u{1f71}', ['\u{1fbb}', '\u{0}', '\u{0}']), ('\u{1f72}', ['\u{1fc8}', '\u{0}', '\u{0}']), + ('\u{1f73}', ['\u{1fc9}', '\u{0}', '\u{0}']), ('\u{1f74}', ['\u{1fca}', '\u{0}', '\u{0}']), + ('\u{1f75}', ['\u{1fcb}', '\u{0}', '\u{0}']), ('\u{1f76}', ['\u{1fda}', '\u{0}', '\u{0}']), + ('\u{1f77}', ['\u{1fdb}', '\u{0}', '\u{0}']), ('\u{1f78}', ['\u{1ff8}', '\u{0}', '\u{0}']), + ('\u{1f79}', ['\u{1ff9}', '\u{0}', '\u{0}']), ('\u{1f7a}', ['\u{1fea}', '\u{0}', '\u{0}']), + ('\u{1f7b}', ['\u{1feb}', '\u{0}', '\u{0}']), ('\u{1f7c}', ['\u{1ffa}', '\u{0}', '\u{0}']), + ('\u{1f7d}', ['\u{1ffb}', '\u{0}', '\u{0}']), + ('\u{1f80}', ['\u{1f08}', '\u{399}', '\u{0}']), + ('\u{1f81}', ['\u{1f09}', '\u{399}', '\u{0}']), + ('\u{1f82}', ['\u{1f0a}', '\u{399}', '\u{0}']), + ('\u{1f83}', ['\u{1f0b}', '\u{399}', '\u{0}']), + ('\u{1f84}', ['\u{1f0c}', '\u{399}', '\u{0}']), + ('\u{1f85}', ['\u{1f0d}', '\u{399}', '\u{0}']), + ('\u{1f86}', ['\u{1f0e}', '\u{399}', '\u{0}']), + ('\u{1f87}', ['\u{1f0f}', '\u{399}', '\u{0}']), + ('\u{1f88}', ['\u{1f08}', '\u{399}', '\u{0}']), + ('\u{1f89}', ['\u{1f09}', '\u{399}', '\u{0}']), + ('\u{1f8a}', ['\u{1f0a}', '\u{399}', '\u{0}']), + ('\u{1f8b}', ['\u{1f0b}', '\u{399}', '\u{0}']), + ('\u{1f8c}', ['\u{1f0c}', '\u{399}', '\u{0}']), + ('\u{1f8d}', ['\u{1f0d}', '\u{399}', '\u{0}']), + ('\u{1f8e}', ['\u{1f0e}', '\u{399}', '\u{0}']), + ('\u{1f8f}', ['\u{1f0f}', '\u{399}', '\u{0}']), + ('\u{1f90}', ['\u{1f28}', '\u{399}', '\u{0}']), + ('\u{1f91}', ['\u{1f29}', '\u{399}', '\u{0}']), + ('\u{1f92}', ['\u{1f2a}', '\u{399}', '\u{0}']), + ('\u{1f93}', ['\u{1f2b}', '\u{399}', '\u{0}']), + ('\u{1f94}', ['\u{1f2c}', '\u{399}', '\u{0}']), + ('\u{1f95}', ['\u{1f2d}', '\u{399}', '\u{0}']), + ('\u{1f96}', ['\u{1f2e}', '\u{399}', '\u{0}']), + ('\u{1f97}', ['\u{1f2f}', '\u{399}', '\u{0}']), + ('\u{1f98}', ['\u{1f28}', '\u{399}', '\u{0}']), + ('\u{1f99}', ['\u{1f29}', '\u{399}', '\u{0}']), + ('\u{1f9a}', ['\u{1f2a}', '\u{399}', '\u{0}']), + ('\u{1f9b}', ['\u{1f2b}', '\u{399}', '\u{0}']), + ('\u{1f9c}', ['\u{1f2c}', '\u{399}', '\u{0}']), + ('\u{1f9d}', ['\u{1f2d}', '\u{399}', '\u{0}']), + ('\u{1f9e}', ['\u{1f2e}', '\u{399}', '\u{0}']), + ('\u{1f9f}', ['\u{1f2f}', '\u{399}', '\u{0}']), + ('\u{1fa0}', ['\u{1f68}', '\u{399}', '\u{0}']), + ('\u{1fa1}', ['\u{1f69}', '\u{399}', '\u{0}']), + ('\u{1fa2}', ['\u{1f6a}', '\u{399}', '\u{0}']), + ('\u{1fa3}', ['\u{1f6b}', '\u{399}', '\u{0}']), + ('\u{1fa4}', ['\u{1f6c}', '\u{399}', '\u{0}']), + ('\u{1fa5}', ['\u{1f6d}', '\u{399}', '\u{0}']), + ('\u{1fa6}', ['\u{1f6e}', '\u{399}', '\u{0}']), + ('\u{1fa7}', ['\u{1f6f}', '\u{399}', '\u{0}']), + ('\u{1fa8}', ['\u{1f68}', '\u{399}', '\u{0}']), + ('\u{1fa9}', ['\u{1f69}', '\u{399}', '\u{0}']), + ('\u{1faa}', ['\u{1f6a}', '\u{399}', '\u{0}']), + ('\u{1fab}', ['\u{1f6b}', '\u{399}', '\u{0}']), + ('\u{1fac}', ['\u{1f6c}', '\u{399}', '\u{0}']), + ('\u{1fad}', ['\u{1f6d}', '\u{399}', '\u{0}']), + ('\u{1fae}', ['\u{1f6e}', '\u{399}', '\u{0}']), + ('\u{1faf}', ['\u{1f6f}', '\u{399}', '\u{0}']), + ('\u{1fb0}', ['\u{1fb8}', '\u{0}', '\u{0}']), ('\u{1fb1}', ['\u{1fb9}', '\u{0}', '\u{0}']), + ('\u{1fb2}', ['\u{1fba}', '\u{399}', '\u{0}']), + ('\u{1fb3}', ['\u{391}', '\u{399}', '\u{0}']), + ('\u{1fb4}', ['\u{386}', '\u{399}', '\u{0}']), + ('\u{1fb6}', ['\u{391}', '\u{342}', '\u{0}']), + ('\u{1fb7}', ['\u{391}', '\u{342}', '\u{399}']), + ('\u{1fbc}', ['\u{391}', '\u{399}', '\u{0}']), ('\u{1fbe}', ['\u{399}', '\u{0}', '\u{0}']), + ('\u{1fc2}', ['\u{1fca}', '\u{399}', '\u{0}']), + ('\u{1fc3}', ['\u{397}', '\u{399}', '\u{0}']), + ('\u{1fc4}', ['\u{389}', '\u{399}', '\u{0}']), + ('\u{1fc6}', ['\u{397}', '\u{342}', '\u{0}']), + ('\u{1fc7}', ['\u{397}', '\u{342}', '\u{399}']), + ('\u{1fcc}', ['\u{397}', '\u{399}', '\u{0}']), ('\u{1fd0}', ['\u{1fd8}', '\u{0}', '\u{0}']), + ('\u{1fd1}', ['\u{1fd9}', '\u{0}', '\u{0}']), + ('\u{1fd2}', ['\u{399}', '\u{308}', '\u{300}']), + ('\u{1fd3}', ['\u{399}', '\u{308}', '\u{301}']), + ('\u{1fd6}', ['\u{399}', '\u{342}', '\u{0}']), + ('\u{1fd7}', ['\u{399}', '\u{308}', '\u{342}']), + ('\u{1fe0}', ['\u{1fe8}', '\u{0}', '\u{0}']), ('\u{1fe1}', ['\u{1fe9}', '\u{0}', '\u{0}']), + ('\u{1fe2}', ['\u{3a5}', '\u{308}', '\u{300}']), + ('\u{1fe3}', ['\u{3a5}', '\u{308}', '\u{301}']), + ('\u{1fe4}', ['\u{3a1}', '\u{313}', '\u{0}']), ('\u{1fe5}', ['\u{1fec}', '\u{0}', '\u{0}']), + ('\u{1fe6}', ['\u{3a5}', '\u{342}', '\u{0}']), + ('\u{1fe7}', ['\u{3a5}', '\u{308}', '\u{342}']), + ('\u{1ff2}', ['\u{1ffa}', '\u{399}', '\u{0}']), + ('\u{1ff3}', ['\u{3a9}', '\u{399}', '\u{0}']), + ('\u{1ff4}', ['\u{38f}', '\u{399}', '\u{0}']), + ('\u{1ff6}', ['\u{3a9}', '\u{342}', '\u{0}']), + ('\u{1ff7}', ['\u{3a9}', '\u{342}', '\u{399}']), + ('\u{1ffc}', ['\u{3a9}', '\u{399}', '\u{0}']), ('\u{214e}', ['\u{2132}', '\u{0}', '\u{0}']), + ('\u{2170}', ['\u{2160}', '\u{0}', '\u{0}']), ('\u{2171}', ['\u{2161}', '\u{0}', '\u{0}']), + ('\u{2172}', ['\u{2162}', '\u{0}', '\u{0}']), ('\u{2173}', ['\u{2163}', '\u{0}', '\u{0}']), + ('\u{2174}', ['\u{2164}', '\u{0}', '\u{0}']), ('\u{2175}', ['\u{2165}', '\u{0}', '\u{0}']), + ('\u{2176}', ['\u{2166}', '\u{0}', '\u{0}']), ('\u{2177}', ['\u{2167}', '\u{0}', '\u{0}']), + ('\u{2178}', ['\u{2168}', '\u{0}', '\u{0}']), ('\u{2179}', ['\u{2169}', '\u{0}', '\u{0}']), + ('\u{217a}', ['\u{216a}', '\u{0}', '\u{0}']), ('\u{217b}', ['\u{216b}', '\u{0}', '\u{0}']), + ('\u{217c}', ['\u{216c}', '\u{0}', '\u{0}']), ('\u{217d}', ['\u{216d}', '\u{0}', '\u{0}']), + ('\u{217e}', ['\u{216e}', '\u{0}', '\u{0}']), ('\u{217f}', ['\u{216f}', '\u{0}', '\u{0}']), + ('\u{2184}', ['\u{2183}', '\u{0}', '\u{0}']), ('\u{24d0}', ['\u{24b6}', '\u{0}', '\u{0}']), + ('\u{24d1}', ['\u{24b7}', '\u{0}', '\u{0}']), ('\u{24d2}', ['\u{24b8}', '\u{0}', '\u{0}']), + ('\u{24d3}', ['\u{24b9}', '\u{0}', '\u{0}']), ('\u{24d4}', ['\u{24ba}', '\u{0}', '\u{0}']), + ('\u{24d5}', ['\u{24bb}', '\u{0}', '\u{0}']), ('\u{24d6}', ['\u{24bc}', '\u{0}', '\u{0}']), + ('\u{24d7}', ['\u{24bd}', '\u{0}', '\u{0}']), ('\u{24d8}', ['\u{24be}', '\u{0}', '\u{0}']), + ('\u{24d9}', ['\u{24bf}', '\u{0}', '\u{0}']), ('\u{24da}', ['\u{24c0}', '\u{0}', '\u{0}']), + ('\u{24db}', ['\u{24c1}', '\u{0}', '\u{0}']), ('\u{24dc}', ['\u{24c2}', '\u{0}', '\u{0}']), + ('\u{24dd}', ['\u{24c3}', '\u{0}', '\u{0}']), ('\u{24de}', ['\u{24c4}', '\u{0}', '\u{0}']), + ('\u{24df}', ['\u{24c5}', '\u{0}', '\u{0}']), ('\u{24e0}', ['\u{24c6}', '\u{0}', '\u{0}']), + ('\u{24e1}', ['\u{24c7}', '\u{0}', '\u{0}']), ('\u{24e2}', ['\u{24c8}', '\u{0}', '\u{0}']), + ('\u{24e3}', ['\u{24c9}', '\u{0}', '\u{0}']), ('\u{24e4}', ['\u{24ca}', '\u{0}', '\u{0}']), + ('\u{24e5}', ['\u{24cb}', '\u{0}', '\u{0}']), ('\u{24e6}', ['\u{24cc}', '\u{0}', '\u{0}']), + ('\u{24e7}', ['\u{24cd}', '\u{0}', '\u{0}']), ('\u{24e8}', ['\u{24ce}', '\u{0}', '\u{0}']), + ('\u{24e9}', ['\u{24cf}', '\u{0}', '\u{0}']), ('\u{2c30}', ['\u{2c00}', '\u{0}', '\u{0}']), + ('\u{2c31}', ['\u{2c01}', '\u{0}', '\u{0}']), ('\u{2c32}', ['\u{2c02}', '\u{0}', '\u{0}']), + ('\u{2c33}', ['\u{2c03}', '\u{0}', '\u{0}']), ('\u{2c34}', ['\u{2c04}', '\u{0}', '\u{0}']), + ('\u{2c35}', ['\u{2c05}', '\u{0}', '\u{0}']), ('\u{2c36}', ['\u{2c06}', '\u{0}', '\u{0}']), + ('\u{2c37}', ['\u{2c07}', '\u{0}', '\u{0}']), ('\u{2c38}', ['\u{2c08}', '\u{0}', '\u{0}']), + ('\u{2c39}', ['\u{2c09}', '\u{0}', '\u{0}']), ('\u{2c3a}', ['\u{2c0a}', '\u{0}', '\u{0}']), + ('\u{2c3b}', ['\u{2c0b}', '\u{0}', '\u{0}']), ('\u{2c3c}', ['\u{2c0c}', '\u{0}', '\u{0}']), + ('\u{2c3d}', ['\u{2c0d}', '\u{0}', '\u{0}']), ('\u{2c3e}', ['\u{2c0e}', '\u{0}', '\u{0}']), + ('\u{2c3f}', ['\u{2c0f}', '\u{0}', '\u{0}']), ('\u{2c40}', ['\u{2c10}', '\u{0}', '\u{0}']), + ('\u{2c41}', ['\u{2c11}', '\u{0}', '\u{0}']), ('\u{2c42}', ['\u{2c12}', '\u{0}', '\u{0}']), + ('\u{2c43}', ['\u{2c13}', '\u{0}', '\u{0}']), ('\u{2c44}', ['\u{2c14}', '\u{0}', '\u{0}']), + ('\u{2c45}', ['\u{2c15}', '\u{0}', '\u{0}']), ('\u{2c46}', ['\u{2c16}', '\u{0}', '\u{0}']), + ('\u{2c47}', ['\u{2c17}', '\u{0}', '\u{0}']), ('\u{2c48}', ['\u{2c18}', '\u{0}', '\u{0}']), + ('\u{2c49}', ['\u{2c19}', '\u{0}', '\u{0}']), ('\u{2c4a}', ['\u{2c1a}', '\u{0}', '\u{0}']), + ('\u{2c4b}', ['\u{2c1b}', '\u{0}', '\u{0}']), ('\u{2c4c}', ['\u{2c1c}', '\u{0}', '\u{0}']), + ('\u{2c4d}', ['\u{2c1d}', '\u{0}', '\u{0}']), ('\u{2c4e}', ['\u{2c1e}', '\u{0}', '\u{0}']), + ('\u{2c4f}', ['\u{2c1f}', '\u{0}', '\u{0}']), ('\u{2c50}', ['\u{2c20}', '\u{0}', '\u{0}']), + ('\u{2c51}', ['\u{2c21}', '\u{0}', '\u{0}']), ('\u{2c52}', ['\u{2c22}', '\u{0}', '\u{0}']), + ('\u{2c53}', ['\u{2c23}', '\u{0}', '\u{0}']), ('\u{2c54}', ['\u{2c24}', '\u{0}', '\u{0}']), + ('\u{2c55}', ['\u{2c25}', '\u{0}', '\u{0}']), ('\u{2c56}', ['\u{2c26}', '\u{0}', '\u{0}']), + ('\u{2c57}', ['\u{2c27}', '\u{0}', '\u{0}']), ('\u{2c58}', ['\u{2c28}', '\u{0}', '\u{0}']), + ('\u{2c59}', ['\u{2c29}', '\u{0}', '\u{0}']), ('\u{2c5a}', ['\u{2c2a}', '\u{0}', '\u{0}']), + ('\u{2c5b}', ['\u{2c2b}', '\u{0}', '\u{0}']), ('\u{2c5c}', ['\u{2c2c}', '\u{0}', '\u{0}']), + ('\u{2c5d}', ['\u{2c2d}', '\u{0}', '\u{0}']), ('\u{2c5e}', ['\u{2c2e}', '\u{0}', '\u{0}']), + ('\u{2c5f}', ['\u{2c2f}', '\u{0}', '\u{0}']), ('\u{2c61}', ['\u{2c60}', '\u{0}', '\u{0}']), + ('\u{2c65}', ['\u{23a}', '\u{0}', '\u{0}']), ('\u{2c66}', ['\u{23e}', '\u{0}', '\u{0}']), + ('\u{2c68}', ['\u{2c67}', '\u{0}', '\u{0}']), ('\u{2c6a}', ['\u{2c69}', '\u{0}', '\u{0}']), + ('\u{2c6c}', ['\u{2c6b}', '\u{0}', '\u{0}']), ('\u{2c73}', ['\u{2c72}', '\u{0}', '\u{0}']), + ('\u{2c76}', ['\u{2c75}', '\u{0}', '\u{0}']), ('\u{2c81}', ['\u{2c80}', '\u{0}', '\u{0}']), + ('\u{2c83}', ['\u{2c82}', '\u{0}', '\u{0}']), ('\u{2c85}', ['\u{2c84}', '\u{0}', '\u{0}']), + ('\u{2c87}', ['\u{2c86}', '\u{0}', '\u{0}']), ('\u{2c89}', ['\u{2c88}', '\u{0}', '\u{0}']), + ('\u{2c8b}', ['\u{2c8a}', '\u{0}', '\u{0}']), ('\u{2c8d}', ['\u{2c8c}', '\u{0}', '\u{0}']), + ('\u{2c8f}', ['\u{2c8e}', '\u{0}', '\u{0}']), ('\u{2c91}', ['\u{2c90}', '\u{0}', '\u{0}']), + ('\u{2c93}', ['\u{2c92}', '\u{0}', '\u{0}']), ('\u{2c95}', ['\u{2c94}', '\u{0}', '\u{0}']), + ('\u{2c97}', ['\u{2c96}', '\u{0}', '\u{0}']), ('\u{2c99}', ['\u{2c98}', '\u{0}', '\u{0}']), + ('\u{2c9b}', ['\u{2c9a}', '\u{0}', '\u{0}']), ('\u{2c9d}', ['\u{2c9c}', '\u{0}', '\u{0}']), + ('\u{2c9f}', ['\u{2c9e}', '\u{0}', '\u{0}']), ('\u{2ca1}', ['\u{2ca0}', '\u{0}', '\u{0}']), + ('\u{2ca3}', ['\u{2ca2}', '\u{0}', '\u{0}']), ('\u{2ca5}', ['\u{2ca4}', '\u{0}', '\u{0}']), + ('\u{2ca7}', ['\u{2ca6}', '\u{0}', '\u{0}']), ('\u{2ca9}', ['\u{2ca8}', '\u{0}', '\u{0}']), + ('\u{2cab}', ['\u{2caa}', '\u{0}', '\u{0}']), ('\u{2cad}', ['\u{2cac}', '\u{0}', '\u{0}']), + ('\u{2caf}', ['\u{2cae}', '\u{0}', '\u{0}']), ('\u{2cb1}', ['\u{2cb0}', '\u{0}', '\u{0}']), + ('\u{2cb3}', ['\u{2cb2}', '\u{0}', '\u{0}']), ('\u{2cb5}', ['\u{2cb4}', '\u{0}', '\u{0}']), + ('\u{2cb7}', ['\u{2cb6}', '\u{0}', '\u{0}']), ('\u{2cb9}', ['\u{2cb8}', '\u{0}', '\u{0}']), + ('\u{2cbb}', ['\u{2cba}', '\u{0}', '\u{0}']), ('\u{2cbd}', ['\u{2cbc}', '\u{0}', '\u{0}']), + ('\u{2cbf}', ['\u{2cbe}', '\u{0}', '\u{0}']), ('\u{2cc1}', ['\u{2cc0}', '\u{0}', '\u{0}']), + ('\u{2cc3}', ['\u{2cc2}', '\u{0}', '\u{0}']), ('\u{2cc5}', ['\u{2cc4}', '\u{0}', '\u{0}']), + ('\u{2cc7}', ['\u{2cc6}', '\u{0}', '\u{0}']), ('\u{2cc9}', ['\u{2cc8}', '\u{0}', '\u{0}']), + ('\u{2ccb}', ['\u{2cca}', '\u{0}', '\u{0}']), ('\u{2ccd}', ['\u{2ccc}', '\u{0}', '\u{0}']), + ('\u{2ccf}', ['\u{2cce}', '\u{0}', '\u{0}']), ('\u{2cd1}', ['\u{2cd0}', '\u{0}', '\u{0}']), + ('\u{2cd3}', ['\u{2cd2}', '\u{0}', '\u{0}']), ('\u{2cd5}', ['\u{2cd4}', '\u{0}', '\u{0}']), + ('\u{2cd7}', ['\u{2cd6}', '\u{0}', '\u{0}']), ('\u{2cd9}', ['\u{2cd8}', '\u{0}', '\u{0}']), + ('\u{2cdb}', ['\u{2cda}', '\u{0}', '\u{0}']), ('\u{2cdd}', ['\u{2cdc}', '\u{0}', '\u{0}']), + ('\u{2cdf}', ['\u{2cde}', '\u{0}', '\u{0}']), ('\u{2ce1}', ['\u{2ce0}', '\u{0}', '\u{0}']), + ('\u{2ce3}', ['\u{2ce2}', '\u{0}', '\u{0}']), ('\u{2cec}', ['\u{2ceb}', '\u{0}', '\u{0}']), + ('\u{2cee}', ['\u{2ced}', '\u{0}', '\u{0}']), ('\u{2cf3}', ['\u{2cf2}', '\u{0}', '\u{0}']), + ('\u{2d00}', ['\u{10a0}', '\u{0}', '\u{0}']), ('\u{2d01}', ['\u{10a1}', '\u{0}', '\u{0}']), + ('\u{2d02}', ['\u{10a2}', '\u{0}', '\u{0}']), ('\u{2d03}', ['\u{10a3}', '\u{0}', '\u{0}']), + ('\u{2d04}', ['\u{10a4}', '\u{0}', '\u{0}']), ('\u{2d05}', ['\u{10a5}', '\u{0}', '\u{0}']), + ('\u{2d06}', ['\u{10a6}', '\u{0}', '\u{0}']), ('\u{2d07}', ['\u{10a7}', '\u{0}', '\u{0}']), + ('\u{2d08}', ['\u{10a8}', '\u{0}', '\u{0}']), ('\u{2d09}', ['\u{10a9}', '\u{0}', '\u{0}']), + ('\u{2d0a}', ['\u{10aa}', '\u{0}', '\u{0}']), ('\u{2d0b}', ['\u{10ab}', '\u{0}', '\u{0}']), + ('\u{2d0c}', ['\u{10ac}', '\u{0}', '\u{0}']), ('\u{2d0d}', ['\u{10ad}', '\u{0}', '\u{0}']), + ('\u{2d0e}', ['\u{10ae}', '\u{0}', '\u{0}']), ('\u{2d0f}', ['\u{10af}', '\u{0}', '\u{0}']), + ('\u{2d10}', ['\u{10b0}', '\u{0}', '\u{0}']), ('\u{2d11}', ['\u{10b1}', '\u{0}', '\u{0}']), + ('\u{2d12}', ['\u{10b2}', '\u{0}', '\u{0}']), ('\u{2d13}', ['\u{10b3}', '\u{0}', '\u{0}']), + ('\u{2d14}', ['\u{10b4}', '\u{0}', '\u{0}']), ('\u{2d15}', ['\u{10b5}', '\u{0}', '\u{0}']), + ('\u{2d16}', ['\u{10b6}', '\u{0}', '\u{0}']), ('\u{2d17}', ['\u{10b7}', '\u{0}', '\u{0}']), + ('\u{2d18}', ['\u{10b8}', '\u{0}', '\u{0}']), ('\u{2d19}', ['\u{10b9}', '\u{0}', '\u{0}']), + ('\u{2d1a}', ['\u{10ba}', '\u{0}', '\u{0}']), ('\u{2d1b}', ['\u{10bb}', '\u{0}', '\u{0}']), + ('\u{2d1c}', ['\u{10bc}', '\u{0}', '\u{0}']), ('\u{2d1d}', ['\u{10bd}', '\u{0}', '\u{0}']), + ('\u{2d1e}', ['\u{10be}', '\u{0}', '\u{0}']), ('\u{2d1f}', ['\u{10bf}', '\u{0}', '\u{0}']), + ('\u{2d20}', ['\u{10c0}', '\u{0}', '\u{0}']), ('\u{2d21}', ['\u{10c1}', '\u{0}', '\u{0}']), + ('\u{2d22}', ['\u{10c2}', '\u{0}', '\u{0}']), ('\u{2d23}', ['\u{10c3}', '\u{0}', '\u{0}']), + ('\u{2d24}', ['\u{10c4}', '\u{0}', '\u{0}']), ('\u{2d25}', ['\u{10c5}', '\u{0}', '\u{0}']), + ('\u{2d27}', ['\u{10c7}', '\u{0}', '\u{0}']), ('\u{2d2d}', ['\u{10cd}', '\u{0}', '\u{0}']), + ('\u{a641}', ['\u{a640}', '\u{0}', '\u{0}']), ('\u{a643}', ['\u{a642}', '\u{0}', '\u{0}']), + ('\u{a645}', ['\u{a644}', '\u{0}', '\u{0}']), ('\u{a647}', ['\u{a646}', '\u{0}', '\u{0}']), + ('\u{a649}', ['\u{a648}', '\u{0}', '\u{0}']), ('\u{a64b}', ['\u{a64a}', '\u{0}', '\u{0}']), + ('\u{a64d}', ['\u{a64c}', '\u{0}', '\u{0}']), ('\u{a64f}', ['\u{a64e}', '\u{0}', '\u{0}']), + ('\u{a651}', ['\u{a650}', '\u{0}', '\u{0}']), ('\u{a653}', ['\u{a652}', '\u{0}', '\u{0}']), + ('\u{a655}', ['\u{a654}', '\u{0}', '\u{0}']), ('\u{a657}', ['\u{a656}', '\u{0}', '\u{0}']), + ('\u{a659}', ['\u{a658}', '\u{0}', '\u{0}']), ('\u{a65b}', ['\u{a65a}', '\u{0}', '\u{0}']), + ('\u{a65d}', ['\u{a65c}', '\u{0}', '\u{0}']), ('\u{a65f}', ['\u{a65e}', '\u{0}', '\u{0}']), + ('\u{a661}', ['\u{a660}', '\u{0}', '\u{0}']), ('\u{a663}', ['\u{a662}', '\u{0}', '\u{0}']), + ('\u{a665}', ['\u{a664}', '\u{0}', '\u{0}']), ('\u{a667}', ['\u{a666}', '\u{0}', '\u{0}']), + ('\u{a669}', ['\u{a668}', '\u{0}', '\u{0}']), ('\u{a66b}', ['\u{a66a}', '\u{0}', '\u{0}']), + ('\u{a66d}', ['\u{a66c}', '\u{0}', '\u{0}']), ('\u{a681}', ['\u{a680}', '\u{0}', '\u{0}']), + ('\u{a683}', ['\u{a682}', '\u{0}', '\u{0}']), ('\u{a685}', ['\u{a684}', '\u{0}', '\u{0}']), + ('\u{a687}', ['\u{a686}', '\u{0}', '\u{0}']), ('\u{a689}', ['\u{a688}', '\u{0}', '\u{0}']), + ('\u{a68b}', ['\u{a68a}', '\u{0}', '\u{0}']), ('\u{a68d}', ['\u{a68c}', '\u{0}', '\u{0}']), + ('\u{a68f}', ['\u{a68e}', '\u{0}', '\u{0}']), ('\u{a691}', ['\u{a690}', '\u{0}', '\u{0}']), + ('\u{a693}', ['\u{a692}', '\u{0}', '\u{0}']), ('\u{a695}', ['\u{a694}', '\u{0}', '\u{0}']), + ('\u{a697}', ['\u{a696}', '\u{0}', '\u{0}']), ('\u{a699}', ['\u{a698}', '\u{0}', '\u{0}']), + ('\u{a69b}', ['\u{a69a}', '\u{0}', '\u{0}']), ('\u{a723}', ['\u{a722}', '\u{0}', '\u{0}']), + ('\u{a725}', ['\u{a724}', '\u{0}', '\u{0}']), ('\u{a727}', ['\u{a726}', '\u{0}', '\u{0}']), + ('\u{a729}', ['\u{a728}', '\u{0}', '\u{0}']), ('\u{a72b}', ['\u{a72a}', '\u{0}', '\u{0}']), + ('\u{a72d}', ['\u{a72c}', '\u{0}', '\u{0}']), ('\u{a72f}', ['\u{a72e}', '\u{0}', '\u{0}']), + ('\u{a733}', ['\u{a732}', '\u{0}', '\u{0}']), ('\u{a735}', ['\u{a734}', '\u{0}', '\u{0}']), + ('\u{a737}', ['\u{a736}', '\u{0}', '\u{0}']), ('\u{a739}', ['\u{a738}', '\u{0}', '\u{0}']), + ('\u{a73b}', ['\u{a73a}', '\u{0}', '\u{0}']), ('\u{a73d}', ['\u{a73c}', '\u{0}', '\u{0}']), + ('\u{a73f}', ['\u{a73e}', '\u{0}', '\u{0}']), ('\u{a741}', ['\u{a740}', '\u{0}', '\u{0}']), + ('\u{a743}', ['\u{a742}', '\u{0}', '\u{0}']), ('\u{a745}', ['\u{a744}', '\u{0}', '\u{0}']), + ('\u{a747}', ['\u{a746}', '\u{0}', '\u{0}']), ('\u{a749}', ['\u{a748}', '\u{0}', '\u{0}']), + ('\u{a74b}', ['\u{a74a}', '\u{0}', '\u{0}']), ('\u{a74d}', ['\u{a74c}', '\u{0}', '\u{0}']), + ('\u{a74f}', ['\u{a74e}', '\u{0}', '\u{0}']), ('\u{a751}', ['\u{a750}', '\u{0}', '\u{0}']), + ('\u{a753}', ['\u{a752}', '\u{0}', '\u{0}']), ('\u{a755}', ['\u{a754}', '\u{0}', '\u{0}']), + ('\u{a757}', ['\u{a756}', '\u{0}', '\u{0}']), ('\u{a759}', ['\u{a758}', '\u{0}', '\u{0}']), + ('\u{a75b}', ['\u{a75a}', '\u{0}', '\u{0}']), ('\u{a75d}', ['\u{a75c}', '\u{0}', '\u{0}']), + ('\u{a75f}', ['\u{a75e}', '\u{0}', '\u{0}']), ('\u{a761}', ['\u{a760}', '\u{0}', '\u{0}']), + ('\u{a763}', ['\u{a762}', '\u{0}', '\u{0}']), ('\u{a765}', ['\u{a764}', '\u{0}', '\u{0}']), + ('\u{a767}', ['\u{a766}', '\u{0}', '\u{0}']), ('\u{a769}', ['\u{a768}', '\u{0}', '\u{0}']), + ('\u{a76b}', ['\u{a76a}', '\u{0}', '\u{0}']), ('\u{a76d}', ['\u{a76c}', '\u{0}', '\u{0}']), + ('\u{a76f}', ['\u{a76e}', '\u{0}', '\u{0}']), ('\u{a77a}', ['\u{a779}', '\u{0}', '\u{0}']), + ('\u{a77c}', ['\u{a77b}', '\u{0}', '\u{0}']), ('\u{a77f}', ['\u{a77e}', '\u{0}', '\u{0}']), + ('\u{a781}', ['\u{a780}', '\u{0}', '\u{0}']), ('\u{a783}', ['\u{a782}', '\u{0}', '\u{0}']), + ('\u{a785}', ['\u{a784}', '\u{0}', '\u{0}']), ('\u{a787}', ['\u{a786}', '\u{0}', '\u{0}']), + ('\u{a78c}', ['\u{a78b}', '\u{0}', '\u{0}']), ('\u{a791}', ['\u{a790}', '\u{0}', '\u{0}']), + ('\u{a793}', ['\u{a792}', '\u{0}', '\u{0}']), ('\u{a794}', ['\u{a7c4}', '\u{0}', '\u{0}']), + ('\u{a797}', ['\u{a796}', '\u{0}', '\u{0}']), ('\u{a799}', ['\u{a798}', '\u{0}', '\u{0}']), + ('\u{a79b}', ['\u{a79a}', '\u{0}', '\u{0}']), ('\u{a79d}', ['\u{a79c}', '\u{0}', '\u{0}']), + ('\u{a79f}', ['\u{a79e}', '\u{0}', '\u{0}']), ('\u{a7a1}', ['\u{a7a0}', '\u{0}', '\u{0}']), + ('\u{a7a3}', ['\u{a7a2}', '\u{0}', '\u{0}']), ('\u{a7a5}', ['\u{a7a4}', '\u{0}', '\u{0}']), + ('\u{a7a7}', ['\u{a7a6}', '\u{0}', '\u{0}']), ('\u{a7a9}', ['\u{a7a8}', '\u{0}', '\u{0}']), + ('\u{a7b5}', ['\u{a7b4}', '\u{0}', '\u{0}']), ('\u{a7b7}', ['\u{a7b6}', '\u{0}', '\u{0}']), + ('\u{a7b9}', ['\u{a7b8}', '\u{0}', '\u{0}']), ('\u{a7bb}', ['\u{a7ba}', '\u{0}', '\u{0}']), + ('\u{a7bd}', ['\u{a7bc}', '\u{0}', '\u{0}']), ('\u{a7bf}', ['\u{a7be}', '\u{0}', '\u{0}']), + ('\u{a7c1}', ['\u{a7c0}', '\u{0}', '\u{0}']), ('\u{a7c3}', ['\u{a7c2}', '\u{0}', '\u{0}']), + ('\u{a7c8}', ['\u{a7c7}', '\u{0}', '\u{0}']), ('\u{a7ca}', ['\u{a7c9}', '\u{0}', '\u{0}']), + ('\u{a7cd}', ['\u{a7cc}', '\u{0}', '\u{0}']), ('\u{a7cf}', ['\u{a7ce}', '\u{0}', '\u{0}']), + ('\u{a7d1}', ['\u{a7d0}', '\u{0}', '\u{0}']), ('\u{a7d3}', ['\u{a7d2}', '\u{0}', '\u{0}']), + ('\u{a7d5}', ['\u{a7d4}', '\u{0}', '\u{0}']), ('\u{a7d7}', ['\u{a7d6}', '\u{0}', '\u{0}']), + ('\u{a7d9}', ['\u{a7d8}', '\u{0}', '\u{0}']), ('\u{a7db}', ['\u{a7da}', '\u{0}', '\u{0}']), + ('\u{a7f6}', ['\u{a7f5}', '\u{0}', '\u{0}']), ('\u{ab53}', ['\u{a7b3}', '\u{0}', '\u{0}']), + ('\u{ab70}', ['\u{13a0}', '\u{0}', '\u{0}']), ('\u{ab71}', ['\u{13a1}', '\u{0}', '\u{0}']), + ('\u{ab72}', ['\u{13a2}', '\u{0}', '\u{0}']), ('\u{ab73}', ['\u{13a3}', '\u{0}', '\u{0}']), + ('\u{ab74}', ['\u{13a4}', '\u{0}', '\u{0}']), ('\u{ab75}', ['\u{13a5}', '\u{0}', '\u{0}']), + ('\u{ab76}', ['\u{13a6}', '\u{0}', '\u{0}']), ('\u{ab77}', ['\u{13a7}', '\u{0}', '\u{0}']), + ('\u{ab78}', ['\u{13a8}', '\u{0}', '\u{0}']), ('\u{ab79}', ['\u{13a9}', '\u{0}', '\u{0}']), + ('\u{ab7a}', ['\u{13aa}', '\u{0}', '\u{0}']), ('\u{ab7b}', ['\u{13ab}', '\u{0}', '\u{0}']), + ('\u{ab7c}', ['\u{13ac}', '\u{0}', '\u{0}']), ('\u{ab7d}', ['\u{13ad}', '\u{0}', '\u{0}']), + ('\u{ab7e}', ['\u{13ae}', '\u{0}', '\u{0}']), ('\u{ab7f}', ['\u{13af}', '\u{0}', '\u{0}']), + ('\u{ab80}', ['\u{13b0}', '\u{0}', '\u{0}']), ('\u{ab81}', ['\u{13b1}', '\u{0}', '\u{0}']), + ('\u{ab82}', ['\u{13b2}', '\u{0}', '\u{0}']), ('\u{ab83}', ['\u{13b3}', '\u{0}', '\u{0}']), + ('\u{ab84}', ['\u{13b4}', '\u{0}', '\u{0}']), ('\u{ab85}', ['\u{13b5}', '\u{0}', '\u{0}']), + ('\u{ab86}', ['\u{13b6}', '\u{0}', '\u{0}']), ('\u{ab87}', ['\u{13b7}', '\u{0}', '\u{0}']), + ('\u{ab88}', ['\u{13b8}', '\u{0}', '\u{0}']), ('\u{ab89}', ['\u{13b9}', '\u{0}', '\u{0}']), + ('\u{ab8a}', ['\u{13ba}', '\u{0}', '\u{0}']), ('\u{ab8b}', ['\u{13bb}', '\u{0}', '\u{0}']), + ('\u{ab8c}', ['\u{13bc}', '\u{0}', '\u{0}']), ('\u{ab8d}', ['\u{13bd}', '\u{0}', '\u{0}']), + ('\u{ab8e}', ['\u{13be}', '\u{0}', '\u{0}']), ('\u{ab8f}', ['\u{13bf}', '\u{0}', '\u{0}']), + ('\u{ab90}', ['\u{13c0}', '\u{0}', '\u{0}']), ('\u{ab91}', ['\u{13c1}', '\u{0}', '\u{0}']), + ('\u{ab92}', ['\u{13c2}', '\u{0}', '\u{0}']), ('\u{ab93}', ['\u{13c3}', '\u{0}', '\u{0}']), + ('\u{ab94}', ['\u{13c4}', '\u{0}', '\u{0}']), ('\u{ab95}', ['\u{13c5}', '\u{0}', '\u{0}']), + ('\u{ab96}', ['\u{13c6}', '\u{0}', '\u{0}']), ('\u{ab97}', ['\u{13c7}', '\u{0}', '\u{0}']), + ('\u{ab98}', ['\u{13c8}', '\u{0}', '\u{0}']), ('\u{ab99}', ['\u{13c9}', '\u{0}', '\u{0}']), + ('\u{ab9a}', ['\u{13ca}', '\u{0}', '\u{0}']), ('\u{ab9b}', ['\u{13cb}', '\u{0}', '\u{0}']), + ('\u{ab9c}', ['\u{13cc}', '\u{0}', '\u{0}']), ('\u{ab9d}', ['\u{13cd}', '\u{0}', '\u{0}']), + ('\u{ab9e}', ['\u{13ce}', '\u{0}', '\u{0}']), ('\u{ab9f}', ['\u{13cf}', '\u{0}', '\u{0}']), + ('\u{aba0}', ['\u{13d0}', '\u{0}', '\u{0}']), ('\u{aba1}', ['\u{13d1}', '\u{0}', '\u{0}']), + ('\u{aba2}', ['\u{13d2}', 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'\u{0}']), + ('\u{105ae}', ['\u{10587}', '\u{0}', '\u{0}']), + ('\u{105af}', ['\u{10588}', '\u{0}', '\u{0}']), + ('\u{105b0}', ['\u{10589}', '\u{0}', '\u{0}']), + ('\u{105b1}', ['\u{1058a}', '\u{0}', '\u{0}']), + ('\u{105b3}', ['\u{1058c}', '\u{0}', '\u{0}']), + ('\u{105b4}', ['\u{1058d}', '\u{0}', '\u{0}']), + ('\u{105b5}', ['\u{1058e}', '\u{0}', '\u{0}']), + ('\u{105b6}', ['\u{1058f}', '\u{0}', '\u{0}']), + ('\u{105b7}', ['\u{10590}', '\u{0}', '\u{0}']), + ('\u{105b8}', ['\u{10591}', '\u{0}', '\u{0}']), + ('\u{105b9}', ['\u{10592}', '\u{0}', '\u{0}']), + ('\u{105bb}', ['\u{10594}', '\u{0}', '\u{0}']), + ('\u{105bc}', ['\u{10595}', '\u{0}', '\u{0}']), + ('\u{10cc0}', ['\u{10c80}', '\u{0}', '\u{0}']), + ('\u{10cc1}', ['\u{10c81}', '\u{0}', '\u{0}']), + ('\u{10cc2}', ['\u{10c82}', '\u{0}', '\u{0}']), + ('\u{10cc3}', ['\u{10c83}', '\u{0}', '\u{0}']), + ('\u{10cc4}', ['\u{10c84}', '\u{0}', '\u{0}']), + ('\u{10cc5}', ['\u{10c85}', '\u{0}', '\u{0}']), + ('\u{10cc6}', ['\u{10c86}', '\u{0}', '\u{0}']), + ('\u{10cc7}', ['\u{10c87}', '\u{0}', '\u{0}']), + ('\u{10cc8}', ['\u{10c88}', '\u{0}', '\u{0}']), + ('\u{10cc9}', ['\u{10c89}', '\u{0}', '\u{0}']), + ('\u{10cca}', ['\u{10c8a}', '\u{0}', '\u{0}']), + ('\u{10ccb}', ['\u{10c8b}', '\u{0}', '\u{0}']), + ('\u{10ccc}', ['\u{10c8c}', '\u{0}', '\u{0}']), + ('\u{10ccd}', ['\u{10c8d}', '\u{0}', '\u{0}']), + ('\u{10cce}', ['\u{10c8e}', '\u{0}', '\u{0}']), + ('\u{10ccf}', ['\u{10c8f}', '\u{0}', '\u{0}']), + ('\u{10cd0}', ['\u{10c90}', '\u{0}', '\u{0}']), + ('\u{10cd1}', ['\u{10c91}', '\u{0}', '\u{0}']), + ('\u{10cd2}', ['\u{10c92}', '\u{0}', '\u{0}']), + ('\u{10cd3}', ['\u{10c93}', '\u{0}', '\u{0}']), + ('\u{10cd4}', ['\u{10c94}', '\u{0}', '\u{0}']), + ('\u{10cd5}', ['\u{10c95}', '\u{0}', '\u{0}']), + ('\u{10cd6}', ['\u{10c96}', '\u{0}', '\u{0}']), + ('\u{10cd7}', ['\u{10c97}', '\u{0}', '\u{0}']), + ('\u{10cd8}', ['\u{10c98}', '\u{0}', '\u{0}']), + ('\u{10cd9}', ['\u{10c99}', '\u{0}', '\u{0}']), + ('\u{10cda}', ['\u{10c9a}', '\u{0}', '\u{0}']), + ('\u{10cdb}', ['\u{10c9b}', '\u{0}', '\u{0}']), + ('\u{10cdc}', ['\u{10c9c}', '\u{0}', '\u{0}']), + ('\u{10cdd}', ['\u{10c9d}', '\u{0}', '\u{0}']), + ('\u{10cde}', ['\u{10c9e}', '\u{0}', '\u{0}']), + ('\u{10cdf}', ['\u{10c9f}', '\u{0}', '\u{0}']), + ('\u{10ce0}', ['\u{10ca0}', '\u{0}', '\u{0}']), + ('\u{10ce1}', ['\u{10ca1}', '\u{0}', '\u{0}']), + ('\u{10ce2}', ['\u{10ca2}', '\u{0}', '\u{0}']), + ('\u{10ce3}', ['\u{10ca3}', '\u{0}', '\u{0}']), + ('\u{10ce4}', ['\u{10ca4}', '\u{0}', '\u{0}']), + ('\u{10ce5}', ['\u{10ca5}', '\u{0}', '\u{0}']), + ('\u{10ce6}', ['\u{10ca6}', '\u{0}', '\u{0}']), + ('\u{10ce7}', ['\u{10ca7}', '\u{0}', '\u{0}']), + ('\u{10ce8}', ['\u{10ca8}', '\u{0}', '\u{0}']), + ('\u{10ce9}', ['\u{10ca9}', '\u{0}', '\u{0}']), + ('\u{10cea}', ['\u{10caa}', '\u{0}', '\u{0}']), + ('\u{10ceb}', ['\u{10cab}', '\u{0}', '\u{0}']), + ('\u{10cec}', ['\u{10cac}', '\u{0}', '\u{0}']), + ('\u{10ced}', ['\u{10cad}', '\u{0}', '\u{0}']), + ('\u{10cee}', ['\u{10cae}', '\u{0}', '\u{0}']), + ('\u{10cef}', ['\u{10caf}', '\u{0}', '\u{0}']), + ('\u{10cf0}', ['\u{10cb0}', '\u{0}', '\u{0}']), + ('\u{10cf1}', ['\u{10cb1}', '\u{0}', '\u{0}']), + ('\u{10cf2}', ['\u{10cb2}', '\u{0}', '\u{0}']), + ('\u{10d70}', ['\u{10d50}', '\u{0}', '\u{0}']), + ('\u{10d71}', ['\u{10d51}', '\u{0}', '\u{0}']), + ('\u{10d72}', ['\u{10d52}', '\u{0}', '\u{0}']), + ('\u{10d73}', ['\u{10d53}', '\u{0}', '\u{0}']), + ('\u{10d74}', ['\u{10d54}', '\u{0}', '\u{0}']), + ('\u{10d75}', ['\u{10d55}', '\u{0}', '\u{0}']), + ('\u{10d76}', ['\u{10d56}', '\u{0}', '\u{0}']), + ('\u{10d77}', ['\u{10d57}', '\u{0}', '\u{0}']), + ('\u{10d78}', ['\u{10d58}', '\u{0}', '\u{0}']), + ('\u{10d79}', ['\u{10d59}', '\u{0}', '\u{0}']), + ('\u{10d7a}', ['\u{10d5a}', '\u{0}', '\u{0}']), + ('\u{10d7b}', ['\u{10d5b}', '\u{0}', '\u{0}']), + ('\u{10d7c}', ['\u{10d5c}', '\u{0}', '\u{0}']), + ('\u{10d7d}', ['\u{10d5d}', '\u{0}', '\u{0}']), + ('\u{10d7e}', ['\u{10d5e}', '\u{0}', '\u{0}']), + ('\u{10d7f}', ['\u{10d5f}', '\u{0}', '\u{0}']), + ('\u{10d80}', ['\u{10d60}', '\u{0}', '\u{0}']), + ('\u{10d81}', ['\u{10d61}', '\u{0}', '\u{0}']), + ('\u{10d82}', ['\u{10d62}', '\u{0}', '\u{0}']), + ('\u{10d83}', ['\u{10d63}', '\u{0}', '\u{0}']), + ('\u{10d84}', ['\u{10d64}', '\u{0}', '\u{0}']), + ('\u{10d85}', ['\u{10d65}', '\u{0}', '\u{0}']), + ('\u{118c0}', ['\u{118a0}', '\u{0}', '\u{0}']), + ('\u{118c1}', ['\u{118a1}', '\u{0}', '\u{0}']), + ('\u{118c2}', ['\u{118a2}', '\u{0}', '\u{0}']), + ('\u{118c3}', ['\u{118a3}', '\u{0}', '\u{0}']), + ('\u{118c4}', ['\u{118a4}', '\u{0}', '\u{0}']), + ('\u{118c5}', ['\u{118a5}', '\u{0}', '\u{0}']), + ('\u{118c6}', ['\u{118a6}', '\u{0}', '\u{0}']), + ('\u{118c7}', ['\u{118a7}', '\u{0}', '\u{0}']), + ('\u{118c8}', ['\u{118a8}', '\u{0}', '\u{0}']), + ('\u{118c9}', ['\u{118a9}', '\u{0}', '\u{0}']), + ('\u{118ca}', ['\u{118aa}', '\u{0}', '\u{0}']), + ('\u{118cb}', ['\u{118ab}', '\u{0}', '\u{0}']), + ('\u{118cc}', ['\u{118ac}', '\u{0}', '\u{0}']), + ('\u{118cd}', ['\u{118ad}', '\u{0}', '\u{0}']), + ('\u{118ce}', ['\u{118ae}', '\u{0}', '\u{0}']), + ('\u{118cf}', ['\u{118af}', '\u{0}', '\u{0}']), + ('\u{118d0}', ['\u{118b0}', '\u{0}', '\u{0}']), + ('\u{118d1}', ['\u{118b1}', '\u{0}', '\u{0}']), + ('\u{118d2}', ['\u{118b2}', '\u{0}', '\u{0}']), + ('\u{118d3}', ['\u{118b3}', '\u{0}', '\u{0}']), + ('\u{118d4}', ['\u{118b4}', '\u{0}', '\u{0}']), + ('\u{118d5}', ['\u{118b5}', '\u{0}', '\u{0}']), + ('\u{118d6}', ['\u{118b6}', '\u{0}', '\u{0}']), + ('\u{118d7}', ['\u{118b7}', '\u{0}', '\u{0}']), + ('\u{118d8}', ['\u{118b8}', '\u{0}', '\u{0}']), + ('\u{118d9}', ['\u{118b9}', '\u{0}', '\u{0}']), + ('\u{118da}', ['\u{118ba}', '\u{0}', '\u{0}']), + ('\u{118db}', ['\u{118bb}', '\u{0}', '\u{0}']), + ('\u{118dc}', ['\u{118bc}', '\u{0}', '\u{0}']), + ('\u{118dd}', ['\u{118bd}', '\u{0}', '\u{0}']), + ('\u{118de}', ['\u{118be}', '\u{0}', '\u{0}']), + ('\u{118df}', ['\u{118bf}', '\u{0}', '\u{0}']), + ('\u{16e60}', ['\u{16e40}', '\u{0}', '\u{0}']), + ('\u{16e61}', ['\u{16e41}', '\u{0}', '\u{0}']), + ('\u{16e62}', ['\u{16e42}', '\u{0}', '\u{0}']), + ('\u{16e63}', ['\u{16e43}', '\u{0}', '\u{0}']), + ('\u{16e64}', ['\u{16e44}', '\u{0}', '\u{0}']), + ('\u{16e65}', ['\u{16e45}', '\u{0}', '\u{0}']), + ('\u{16e66}', ['\u{16e46}', '\u{0}', '\u{0}']), + ('\u{16e67}', ['\u{16e47}', '\u{0}', '\u{0}']), + ('\u{16e68}', ['\u{16e48}', '\u{0}', '\u{0}']), + ('\u{16e69}', ['\u{16e49}', '\u{0}', '\u{0}']), + ('\u{16e6a}', ['\u{16e4a}', '\u{0}', '\u{0}']), + ('\u{16e6b}', ['\u{16e4b}', '\u{0}', '\u{0}']), + ('\u{16e6c}', ['\u{16e4c}', '\u{0}', '\u{0}']), + ('\u{16e6d}', ['\u{16e4d}', '\u{0}', '\u{0}']), + ('\u{16e6e}', ['\u{16e4e}', '\u{0}', '\u{0}']), + ('\u{16e6f}', ['\u{16e4f}', '\u{0}', '\u{0}']), + ('\u{16e70}', ['\u{16e50}', '\u{0}', '\u{0}']), + ('\u{16e71}', ['\u{16e51}', '\u{0}', '\u{0}']), + ('\u{16e72}', ['\u{16e52}', '\u{0}', '\u{0}']), + ('\u{16e73}', ['\u{16e53}', '\u{0}', '\u{0}']), + ('\u{16e74}', ['\u{16e54}', '\u{0}', '\u{0}']), + ('\u{16e75}', ['\u{16e55}', '\u{0}', '\u{0}']), + ('\u{16e76}', ['\u{16e56}', '\u{0}', '\u{0}']), + ('\u{16e77}', ['\u{16e57}', '\u{0}', '\u{0}']), + ('\u{16e78}', ['\u{16e58}', '\u{0}', '\u{0}']), + ('\u{16e79}', ['\u{16e59}', '\u{0}', '\u{0}']), + ('\u{16e7a}', ['\u{16e5a}', '\u{0}', '\u{0}']), + ('\u{16e7b}', ['\u{16e5b}', '\u{0}', '\u{0}']), + ('\u{16e7c}', ['\u{16e5c}', '\u{0}', '\u{0}']), + ('\u{16e7d}', ['\u{16e5d}', '\u{0}', '\u{0}']), + ('\u{16e7e}', ['\u{16e5e}', '\u{0}', '\u{0}']), + ('\u{16e7f}', ['\u{16e5f}', '\u{0}', '\u{0}']), + ('\u{16ebb}', ['\u{16ea0}', '\u{0}', '\u{0}']), + ('\u{16ebc}', ['\u{16ea1}', '\u{0}', '\u{0}']), + ('\u{16ebd}', ['\u{16ea2}', '\u{0}', '\u{0}']), + ('\u{16ebe}', ['\u{16ea3}', '\u{0}', '\u{0}']), + ('\u{16ebf}', ['\u{16ea4}', '\u{0}', '\u{0}']), + ('\u{16ec0}', ['\u{16ea5}', '\u{0}', '\u{0}']), + ('\u{16ec1}', ['\u{16ea6}', '\u{0}', '\u{0}']), + ('\u{16ec2}', ['\u{16ea7}', '\u{0}', '\u{0}']), + ('\u{16ec3}', ['\u{16ea8}', '\u{0}', '\u{0}']), + ('\u{16ec4}', ['\u{16ea9}', '\u{0}', '\u{0}']), + ('\u{16ec5}', ['\u{16eaa}', '\u{0}', '\u{0}']), + ('\u{16ec6}', ['\u{16eab}', '\u{0}', '\u{0}']), + ('\u{16ec7}', ['\u{16eac}', '\u{0}', '\u{0}']), + ('\u{16ec8}', ['\u{16ead}', '\u{0}', '\u{0}']), + ('\u{16ec9}', ['\u{16eae}', '\u{0}', '\u{0}']), + ('\u{16eca}', ['\u{16eaf}', '\u{0}', '\u{0}']), + ('\u{16ecb}', ['\u{16eb0}', '\u{0}', '\u{0}']), + ('\u{16ecc}', ['\u{16eb1}', '\u{0}', '\u{0}']), + ('\u{16ecd}', ['\u{16eb2}', '\u{0}', '\u{0}']), + ('\u{16ece}', ['\u{16eb3}', '\u{0}', '\u{0}']), + ('\u{16ecf}', ['\u{16eb4}', '\u{0}', '\u{0}']), + ('\u{16ed0}', ['\u{16eb5}', '\u{0}', '\u{0}']), + ('\u{16ed1}', ['\u{16eb6}', '\u{0}', '\u{0}']), + ('\u{16ed2}', ['\u{16eb7}', '\u{0}', '\u{0}']), + ('\u{16ed3}', ['\u{16eb8}', '\u{0}', '\u{0}']), + ('\u{1e922}', ['\u{1e900}', '\u{0}', '\u{0}']), + ('\u{1e923}', ['\u{1e901}', '\u{0}', '\u{0}']), + ('\u{1e924}', ['\u{1e902}', '\u{0}', '\u{0}']), + ('\u{1e925}', ['\u{1e903}', '\u{0}', '\u{0}']), + ('\u{1e926}', ['\u{1e904}', '\u{0}', '\u{0}']), + ('\u{1e927}', ['\u{1e905}', '\u{0}', '\u{0}']), + ('\u{1e928}', ['\u{1e906}', '\u{0}', '\u{0}']), + ('\u{1e929}', ['\u{1e907}', '\u{0}', '\u{0}']), + ('\u{1e92a}', ['\u{1e908}', '\u{0}', '\u{0}']), + ('\u{1e92b}', ['\u{1e909}', '\u{0}', '\u{0}']), + ('\u{1e92c}', ['\u{1e90a}', '\u{0}', '\u{0}']), + ('\u{1e92d}', ['\u{1e90b}', '\u{0}', '\u{0}']), + ('\u{1e92e}', ['\u{1e90c}', '\u{0}', '\u{0}']), + ('\u{1e92f}', ['\u{1e90d}', '\u{0}', '\u{0}']), + ('\u{1e930}', ['\u{1e90e}', '\u{0}', '\u{0}']), + ('\u{1e931}', ['\u{1e90f}', '\u{0}', '\u{0}']), + ('\u{1e932}', ['\u{1e910}', '\u{0}', '\u{0}']), + ('\u{1e933}', ['\u{1e911}', '\u{0}', '\u{0}']), + ('\u{1e934}', ['\u{1e912}', '\u{0}', '\u{0}']), + ('\u{1e935}', ['\u{1e913}', '\u{0}', '\u{0}']), + ('\u{1e936}', ['\u{1e914}', '\u{0}', '\u{0}']), + ('\u{1e937}', ['\u{1e915}', '\u{0}', '\u{0}']), + ('\u{1e938}', ['\u{1e916}', '\u{0}', '\u{0}']), + ('\u{1e939}', ['\u{1e917}', '\u{0}', '\u{0}']), + ('\u{1e93a}', ['\u{1e918}', '\u{0}', '\u{0}']), + ('\u{1e93b}', ['\u{1e919}', '\u{0}', '\u{0}']), + ('\u{1e93c}', ['\u{1e91a}', '\u{0}', '\u{0}']), + ('\u{1e93d}', ['\u{1e91b}', '\u{0}', '\u{0}']), + ('\u{1e93e}', ['\u{1e91c}', '\u{0}', '\u{0}']), + ('\u{1e93f}', ['\u{1e91d}', '\u{0}', '\u{0}']), + ('\u{1e940}', ['\u{1e91e}', '\u{0}', '\u{0}']), + ('\u{1e941}', ['\u{1e91f}', '\u{0}', '\u{0}']), + ('\u{1e942}', ['\u{1e920}', '\u{0}', '\u{0}']), + ('\u{1e943}', ['\u{1e921}', '\u{0}', '\u{0}']), +]; + +#[rustfmt::skip] +pub(super) static TO_TITLE: &[(char, [char; 3]); 135] = &[ + ('\u{df}', ['S', 's', '\u{0}']), ('\u{1c4}', ['\u{1c5}', '\u{0}', '\u{0}']), + ('\u{1c5}', ['\u{1c5}', '\u{0}', '\u{0}']), ('\u{1c6}', ['\u{1c5}', '\u{0}', '\u{0}']), + ('\u{1c7}', ['\u{1c8}', '\u{0}', '\u{0}']), ('\u{1c8}', ['\u{1c8}', '\u{0}', '\u{0}']), + ('\u{1c9}', ['\u{1c8}', '\u{0}', '\u{0}']), ('\u{1ca}', ['\u{1cb}', '\u{0}', '\u{0}']), + ('\u{1cb}', ['\u{1cb}', '\u{0}', '\u{0}']), ('\u{1cc}', ['\u{1cb}', '\u{0}', '\u{0}']), + ('\u{1f1}', ['\u{1f2}', '\u{0}', '\u{0}']), ('\u{1f2}', ['\u{1f2}', '\u{0}', '\u{0}']), + ('\u{1f3}', ['\u{1f2}', '\u{0}', '\u{0}']), ('\u{587}', ['\u{535}', '\u{582}', '\u{0}']), + ('\u{10d0}', ['\u{10d0}', '\u{0}', '\u{0}']), ('\u{10d1}', ['\u{10d1}', '\u{0}', '\u{0}']), + ('\u{10d2}', ['\u{10d2}', '\u{0}', '\u{0}']), ('\u{10d3}', ['\u{10d3}', '\u{0}', '\u{0}']), + ('\u{10d4}', ['\u{10d4}', '\u{0}', '\u{0}']), ('\u{10d5}', ['\u{10d5}', '\u{0}', '\u{0}']), + ('\u{10d6}', ['\u{10d6}', '\u{0}', '\u{0}']), ('\u{10d7}', ['\u{10d7}', '\u{0}', '\u{0}']), + ('\u{10d8}', ['\u{10d8}', '\u{0}', '\u{0}']), ('\u{10d9}', ['\u{10d9}', '\u{0}', '\u{0}']), + ('\u{10da}', ['\u{10da}', '\u{0}', '\u{0}']), ('\u{10db}', ['\u{10db}', '\u{0}', '\u{0}']), + ('\u{10dc}', ['\u{10dc}', '\u{0}', '\u{0}']), ('\u{10dd}', ['\u{10dd}', '\u{0}', '\u{0}']), + ('\u{10de}', ['\u{10de}', '\u{0}', '\u{0}']), ('\u{10df}', ['\u{10df}', '\u{0}', '\u{0}']), + ('\u{10e0}', ['\u{10e0}', '\u{0}', '\u{0}']), ('\u{10e1}', ['\u{10e1}', '\u{0}', '\u{0}']), + ('\u{10e2}', ['\u{10e2}', '\u{0}', '\u{0}']), ('\u{10e3}', ['\u{10e3}', '\u{0}', '\u{0}']), + ('\u{10e4}', ['\u{10e4}', '\u{0}', '\u{0}']), ('\u{10e5}', ['\u{10e5}', '\u{0}', '\u{0}']), + ('\u{10e6}', ['\u{10e6}', '\u{0}', '\u{0}']), ('\u{10e7}', ['\u{10e7}', '\u{0}', '\u{0}']), + ('\u{10e8}', ['\u{10e8}', '\u{0}', '\u{0}']), ('\u{10e9}', ['\u{10e9}', '\u{0}', '\u{0}']), + ('\u{10ea}', ['\u{10ea}', '\u{0}', '\u{0}']), ('\u{10eb}', ['\u{10eb}', '\u{0}', '\u{0}']), + ('\u{10ec}', ['\u{10ec}', '\u{0}', '\u{0}']), ('\u{10ed}', ['\u{10ed}', '\u{0}', '\u{0}']), + ('\u{10ee}', ['\u{10ee}', '\u{0}', '\u{0}']), ('\u{10ef}', ['\u{10ef}', '\u{0}', '\u{0}']), + ('\u{10f0}', ['\u{10f0}', '\u{0}', '\u{0}']), ('\u{10f1}', ['\u{10f1}', '\u{0}', '\u{0}']), + ('\u{10f2}', ['\u{10f2}', '\u{0}', '\u{0}']), ('\u{10f3}', ['\u{10f3}', '\u{0}', '\u{0}']), + ('\u{10f4}', ['\u{10f4}', '\u{0}', '\u{0}']), ('\u{10f5}', ['\u{10f5}', '\u{0}', '\u{0}']), + ('\u{10f6}', ['\u{10f6}', '\u{0}', '\u{0}']), ('\u{10f7}', ['\u{10f7}', '\u{0}', '\u{0}']), + ('\u{10f8}', ['\u{10f8}', '\u{0}', '\u{0}']), ('\u{10f9}', ['\u{10f9}', '\u{0}', '\u{0}']), + ('\u{10fa}', ['\u{10fa}', '\u{0}', '\u{0}']), ('\u{10fd}', ['\u{10fd}', '\u{0}', '\u{0}']), + ('\u{10fe}', ['\u{10fe}', '\u{0}', '\u{0}']), ('\u{10ff}', ['\u{10ff}', '\u{0}', '\u{0}']), + ('\u{1f80}', ['\u{1f88}', '\u{0}', '\u{0}']), ('\u{1f81}', ['\u{1f89}', '\u{0}', '\u{0}']), + ('\u{1f82}', ['\u{1f8a}', '\u{0}', '\u{0}']), ('\u{1f83}', ['\u{1f8b}', '\u{0}', '\u{0}']), + ('\u{1f84}', ['\u{1f8c}', '\u{0}', '\u{0}']), ('\u{1f85}', ['\u{1f8d}', '\u{0}', '\u{0}']), + ('\u{1f86}', ['\u{1f8e}', '\u{0}', '\u{0}']), ('\u{1f87}', ['\u{1f8f}', '\u{0}', '\u{0}']), + ('\u{1f88}', ['\u{1f88}', '\u{0}', '\u{0}']), ('\u{1f89}', ['\u{1f89}', '\u{0}', '\u{0}']), + ('\u{1f8a}', ['\u{1f8a}', '\u{0}', '\u{0}']), ('\u{1f8b}', ['\u{1f8b}', '\u{0}', '\u{0}']), + ('\u{1f8c}', ['\u{1f8c}', '\u{0}', '\u{0}']), ('\u{1f8d}', ['\u{1f8d}', '\u{0}', '\u{0}']), + ('\u{1f8e}', ['\u{1f8e}', '\u{0}', '\u{0}']), ('\u{1f8f}', ['\u{1f8f}', '\u{0}', '\u{0}']), + ('\u{1f90}', ['\u{1f98}', '\u{0}', '\u{0}']), ('\u{1f91}', ['\u{1f99}', '\u{0}', '\u{0}']), + ('\u{1f92}', ['\u{1f9a}', '\u{0}', '\u{0}']), ('\u{1f93}', ['\u{1f9b}', '\u{0}', '\u{0}']), + ('\u{1f94}', ['\u{1f9c}', '\u{0}', '\u{0}']), ('\u{1f95}', ['\u{1f9d}', '\u{0}', '\u{0}']), + ('\u{1f96}', ['\u{1f9e}', '\u{0}', '\u{0}']), ('\u{1f97}', ['\u{1f9f}', '\u{0}', '\u{0}']), + ('\u{1f98}', ['\u{1f98}', '\u{0}', '\u{0}']), ('\u{1f99}', ['\u{1f99}', '\u{0}', '\u{0}']), + ('\u{1f9a}', ['\u{1f9a}', '\u{0}', '\u{0}']), ('\u{1f9b}', ['\u{1f9b}', '\u{0}', '\u{0}']), + ('\u{1f9c}', ['\u{1f9c}', '\u{0}', '\u{0}']), ('\u{1f9d}', ['\u{1f9d}', '\u{0}', '\u{0}']), + ('\u{1f9e}', ['\u{1f9e}', '\u{0}', '\u{0}']), ('\u{1f9f}', ['\u{1f9f}', '\u{0}', '\u{0}']), + ('\u{1fa0}', ['\u{1fa8}', '\u{0}', '\u{0}']), ('\u{1fa1}', ['\u{1fa9}', '\u{0}', '\u{0}']), + ('\u{1fa2}', ['\u{1faa}', '\u{0}', '\u{0}']), ('\u{1fa3}', ['\u{1fab}', '\u{0}', '\u{0}']), + ('\u{1fa4}', ['\u{1fac}', '\u{0}', '\u{0}']), ('\u{1fa5}', ['\u{1fad}', '\u{0}', '\u{0}']), + ('\u{1fa6}', ['\u{1fae}', '\u{0}', '\u{0}']), ('\u{1fa7}', ['\u{1faf}', '\u{0}', '\u{0}']), + ('\u{1fa8}', ['\u{1fa8}', '\u{0}', '\u{0}']), ('\u{1fa9}', ['\u{1fa9}', '\u{0}', '\u{0}']), + ('\u{1faa}', ['\u{1faa}', '\u{0}', '\u{0}']), ('\u{1fab}', ['\u{1fab}', '\u{0}', '\u{0}']), + ('\u{1fac}', ['\u{1fac}', '\u{0}', '\u{0}']), ('\u{1fad}', ['\u{1fad}', '\u{0}', '\u{0}']), + ('\u{1fae}', ['\u{1fae}', '\u{0}', '\u{0}']), ('\u{1faf}', ['\u{1faf}', '\u{0}', '\u{0}']), + ('\u{1fb2}', ['\u{1fba}', '\u{345}', '\u{0}']), + ('\u{1fb3}', ['\u{1fbc}', '\u{0}', '\u{0}']), ('\u{1fb4}', ['\u{386}', '\u{345}', '\u{0}']), + ('\u{1fb7}', ['\u{391}', '\u{342}', '\u{345}']), + ('\u{1fbc}', ['\u{1fbc}', '\u{0}', '\u{0}']), + ('\u{1fc2}', ['\u{1fca}', '\u{345}', '\u{0}']), + ('\u{1fc3}', ['\u{1fcc}', '\u{0}', '\u{0}']), ('\u{1fc4}', ['\u{389}', '\u{345}', '\u{0}']), + ('\u{1fc7}', ['\u{397}', '\u{342}', '\u{345}']), + ('\u{1fcc}', ['\u{1fcc}', '\u{0}', '\u{0}']), + ('\u{1ff2}', ['\u{1ffa}', '\u{345}', '\u{0}']), + ('\u{1ff3}', ['\u{1ffc}', '\u{0}', '\u{0}']), ('\u{1ff4}', ['\u{38f}', '\u{345}', '\u{0}']), + ('\u{1ff7}', ['\u{3a9}', '\u{342}', '\u{345}']), + ('\u{1ffc}', ['\u{1ffc}', '\u{0}', '\u{0}']), ('\u{fb00}', ['F', 'f', '\u{0}']), + ('\u{fb01}', ['F', 'i', '\u{0}']), ('\u{fb02}', ['F', 'l', '\u{0}']), + ('\u{fb03}', ['F', 'f', 'i']), ('\u{fb04}', ['F', 'f', 'l']), + ('\u{fb05}', ['S', 't', '\u{0}']), ('\u{fb06}', ['S', 't', '\u{0}']), + ('\u{fb13}', ['\u{544}', '\u{576}', '\u{0}']), + ('\u{fb14}', ['\u{544}', '\u{565}', '\u{0}']), + ('\u{fb15}', ['\u{544}', '\u{56b}', '\u{0}']), + ('\u{fb16}', ['\u{54e}', '\u{576}', '\u{0}']), + ('\u{fb17}', ['\u{544}', '\u{56d}', '\u{0}']), +]; diff --git a/panic_unwind/src/lib.rs b/panic_unwind/src/lib.rs index 1be19913f260f..fc0a627d293f3 100644 --- a/panic_unwind/src/lib.rs +++ b/panic_unwind/src/lib.rs @@ -14,10 +14,9 @@ #![no_std] #![unstable(feature = "panic_unwind", issue = "32837")] #![doc(issue_tracker_base_url = "https://github.com/rust-lang/rust/issues/")] +#![cfg_attr(all(target_os = "emscripten", not(emscripten_wasm_eh)), feature(lang_items))] #![feature(cfg_emscripten_wasm_eh)] -#![feature(cfg_select)] #![feature(core_intrinsics)] -#![feature(lang_items)] #![feature(panic_unwind)] #![feature(staged_api)] #![feature(std_internals)] @@ -25,6 +24,7 @@ #![panic_runtime] #![feature(panic_runtime)] #![allow(internal_features)] +#![allow(unused_features)] #![warn(unreachable_pub)] #![deny(unsafe_op_in_unsafe_fn)] diff --git a/portable-simd/crates/core_simd/src/simd/num/float.rs b/portable-simd/crates/core_simd/src/simd/num/float.rs index efd7c2469512b..175cbce4f58be 100644 --- a/portable-simd/crates/core_simd/src/simd/num/float.rs +++ b/portable-simd/crates/core_simd/src/simd/num/float.rs @@ -385,13 +385,13 @@ macro_rules! impl_trait { #[inline] fn simd_min(self, other: Self) -> Self { // Safety: `self` and `other` are float vectors - unsafe { core::intrinsics::simd::simd_fmin(self, other) } + unsafe { core::intrinsics::simd::simd_minimum_number_nsz(self, other) } } #[inline] fn simd_max(self, other: Self) -> Self { // Safety: `self` and `other` are floating point vectors - unsafe { core::intrinsics::simd::simd_fmax(self, other) } + unsafe { core::intrinsics::simd::simd_maximum_number_nsz(self, other) } } #[inline] diff --git a/proc_macro/src/bridge/client.rs b/proc_macro/src/bridge/client.rs index 8f4a79b389f62..696cd4ee3d887 100644 --- a/proc_macro/src/bridge/client.rs +++ b/proc_macro/src/bridge/client.rs @@ -98,7 +98,7 @@ pub(crate) use super::symbol::Symbol; macro_rules! define_client_side { ( - $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)* + $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)?;)* ) => { impl Methods { $(pub(crate) fn $method($($arg: $arg_ty),*) $(-> $ret_ty)? { @@ -121,7 +121,7 @@ macro_rules! define_client_side { } } } -with_api!(self, define_client_side); +with_api!(define_client_side, TokenStream, Span, Symbol); struct Bridge<'a> { /// Reusable buffer (only `clear`-ed, never shrunk), primarily @@ -129,7 +129,7 @@ struct Bridge<'a> { cached_buffer: Buffer, /// Server-side function that the client uses to make requests. - dispatch: closure::Closure<'a, Buffer, Buffer>, + dispatch: closure::Closure<'a>, /// Provided globals for this macro expansion. globals: ExpnGlobals, diff --git a/proc_macro/src/bridge/closure.rs b/proc_macro/src/bridge/closure.rs index e5133907854b2..88c4dd6630b15 100644 --- a/proc_macro/src/bridge/closure.rs +++ b/proc_macro/src/bridge/closure.rs @@ -1,10 +1,12 @@ -//! Closure type (equivalent to `&mut dyn FnMut(A) -> R`) that's `repr(C)`. +//! Closure type (equivalent to `&mut dyn FnMut(Buffer) -> Buffer`) that's `repr(C)`. use std::marker::PhantomData; +use super::Buffer; + #[repr(C)] -pub(super) struct Closure<'a, A, R> { - call: unsafe extern "C" fn(*mut Env, A) -> R, +pub(super) struct Closure<'a> { + call: extern "C" fn(*mut Env, Buffer) -> Buffer, env: *mut Env, // Prevent Send and Sync impls. // @@ -14,17 +16,17 @@ pub(super) struct Closure<'a, A, R> { struct Env; -impl<'a, A, R, F: FnMut(A) -> R> From<&'a mut F> for Closure<'a, A, R> { +impl<'a, F: FnMut(Buffer) -> Buffer> From<&'a mut F> for Closure<'a> { fn from(f: &'a mut F) -> Self { - unsafe extern "C" fn call R>(env: *mut Env, arg: A) -> R { + extern "C" fn call Buffer>(env: *mut Env, arg: Buffer) -> Buffer { unsafe { (*(env as *mut _ as *mut F))(arg) } } - Closure { call: call::, env: f as *mut _ as *mut Env, _marker: PhantomData } + Closure { call: call::, env: f as *mut _ as *mut Env, _marker: PhantomData } } } -impl<'a, A, R> Closure<'a, A, R> { - pub(super) fn call(&mut self, arg: A) -> R { - unsafe { (self.call)(self.env, arg) } +impl<'a> Closure<'a> { + pub(super) fn call(&mut self, arg: Buffer) -> Buffer { + (self.call)(self.env, arg) } } diff --git a/proc_macro/src/bridge/mod.rs b/proc_macro/src/bridge/mod.rs index 244ab7d81b022..72f4e2dcdd7c2 100644 --- a/proc_macro/src/bridge/mod.rs +++ b/proc_macro/src/bridge/mod.rs @@ -18,71 +18,67 @@ use crate::{Delimiter, Level}; /// Higher-order macro describing the server RPC API, allowing automatic /// generation of type-safe Rust APIs, both client-side and server-side. /// -/// `with_api!(MySelf, my_macro)` expands to: +/// `with_api!(my_macro, MyTokenStream, MySpan, MySymbol)` expands to: /// ```rust,ignore (pseudo-code) /// my_macro! { -/// fn lit_character(ch: char) -> MySelf::Literal; -/// fn lit_span(lit: &MySelf::Literal) -> MySelf::Span; -/// fn lit_set_span(lit: &mut MySelf::Literal, span: MySelf::Span); +/// fn ts_clone(stream: &MyTokenStream) -> MyTokenStream; +/// fn span_debug(span: &MySpan) -> String; /// // ... /// } /// ``` /// -/// The first argument serves to customize the argument/return types, -/// to enable several different usecases: -/// -/// If `MySelf` is just `Self`, then the types are only valid inside -/// a trait or a trait impl, where the trait has associated types -/// for each of the API types. If non-associated types are desired, -/// a module name (`self` in practice) can be used instead of `Self`. +/// The second (`TokenStream`), third (`Span`) and fourth (`Symbol`) +/// argument serve to customize the argument/return types that need +/// special handling, to enable several different representations of +/// these types. macro_rules! with_api { - ($S:ident, $m:ident) => { + ($m:ident, $TokenStream: path, $Span: path, $Symbol: path) => { $m! { fn injected_env_var(var: &str) -> Option; fn track_env_var(var: &str, value: Option<&str>); fn track_path(path: &str); - fn literal_from_str(s: &str) -> Result, ()>; - fn emit_diagnostic(diagnostic: Diagnostic<$S::Span>); - - fn ts_drop(stream: $S::TokenStream); - fn ts_clone(stream: &$S::TokenStream) -> $S::TokenStream; - fn ts_is_empty(stream: &$S::TokenStream) -> bool; - fn ts_expand_expr(stream: &$S::TokenStream) -> Result<$S::TokenStream, ()>; - fn ts_from_str(src: &str) -> $S::TokenStream; - fn ts_to_string(stream: &$S::TokenStream) -> String; + fn literal_from_str(s: &str) -> Result, String>; + fn emit_diagnostic(diagnostic: Diagnostic<$Span>); + + fn ts_drop(stream: $TokenStream); + fn ts_clone(stream: &$TokenStream) -> $TokenStream; + fn ts_is_empty(stream: &$TokenStream) -> bool; + fn ts_expand_expr(stream: &$TokenStream) -> Result<$TokenStream, ()>; + fn ts_from_str(src: &str) -> Result<$TokenStream, String>; + fn ts_to_string(stream: &$TokenStream) -> String; fn ts_from_token_tree( - tree: TokenTree<$S::TokenStream, $S::Span, $S::Symbol>, - ) -> $S::TokenStream; + tree: TokenTree<$TokenStream, $Span, $Symbol>, + ) -> $TokenStream; fn ts_concat_trees( - base: Option<$S::TokenStream>, - trees: Vec>, - ) -> $S::TokenStream; + base: Option<$TokenStream>, + trees: Vec>, + ) -> $TokenStream; fn ts_concat_streams( - base: Option<$S::TokenStream>, - streams: Vec<$S::TokenStream>, - ) -> $S::TokenStream; + base: Option<$TokenStream>, + streams: Vec<$TokenStream>, + ) -> $TokenStream; fn ts_into_trees( - stream: $S::TokenStream - ) -> Vec>; - - fn span_debug(span: $S::Span) -> String; - fn span_parent(span: $S::Span) -> Option<$S::Span>; - fn span_source(span: $S::Span) -> $S::Span; - fn span_byte_range(span: $S::Span) -> Range; - fn span_start(span: $S::Span) -> $S::Span; - fn span_end(span: $S::Span) -> $S::Span; - fn span_line(span: $S::Span) -> usize; - fn span_column(span: $S::Span) -> usize; - fn span_file(span: $S::Span) -> String; - fn span_local_file(span: $S::Span) -> Option; - fn span_join(span: $S::Span, other: $S::Span) -> Option<$S::Span>; - fn span_subspan(span: $S::Span, start: Bound, end: Bound) -> Option<$S::Span>; - fn span_resolved_at(span: $S::Span, at: $S::Span) -> $S::Span; - fn span_source_text(span: $S::Span) -> Option; - fn span_save_span(span: $S::Span) -> usize; - fn span_recover_proc_macro_span(id: usize) -> $S::Span; - - fn symbol_normalize_and_validate_ident(string: &str) -> Result<$S::Symbol, ()>; + stream: $TokenStream + ) -> Vec>; + + fn span_debug(span: $Span) -> String; + fn span_parent(span: $Span) -> Option<$Span>; + fn span_source(span: $Span) -> $Span; + fn span_byte_range(span: $Span) -> Range; + fn span_start(span: $Span) -> $Span; + fn span_end(span: $Span) -> $Span; + fn span_line(span: $Span) -> usize; + fn span_column(span: $Span) -> usize; + fn span_file(span: $Span) -> String; + fn span_local_file(span: $Span) -> Option; + fn span_join(span: $Span, other: $Span) -> Option<$Span>; + fn span_subspan(span: $Span, start: Bound, end: Bound) -> Option<$Span>; + fn span_resolved_at(span: $Span, at: $Span) -> $Span; + fn span_source_text(span: $Span) -> Option; + fn span_save_span(span: $Span) -> usize; + fn span_recover_proc_macro_span(id: usize) -> $Span; + + fn symbol_normalize_and_validate_ident(string: &str) -> Result<$Symbol, ()>; } }; } @@ -126,7 +122,7 @@ pub struct BridgeConfig<'a> { input: Buffer, /// Server-side function that the client uses to make requests. - dispatch: closure::Closure<'a, Buffer, Buffer>, + dispatch: closure::Closure<'a>, /// If 'true', always invoke the default panic hook force_show_panics: bool, @@ -137,7 +133,7 @@ impl !Sync for BridgeConfig<'_> {} macro_rules! declare_tags { ( - $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)* + $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)?;)* ) => { #[allow(non_camel_case_types)] pub(super) enum ApiTags { @@ -146,7 +142,7 @@ macro_rules! declare_tags { rpc_encode_decode!(enum ApiTags { $($method),* }); } } -with_api!(self, declare_tags); +with_api!(declare_tags, __, __, __); /// Helper to wrap associated types to allow trait impl dispatch. /// That is, normally a pair of impls for `T::Foo` and `T::Bar` @@ -173,7 +169,7 @@ impl Mark for Marked { self.value } } -impl<'a, T, M> Mark for &'a Marked { +impl<'a, T> Mark for &'a Marked { type Unmarked = &'a T; fn mark(_: Self::Unmarked) -> Self { unreachable!() @@ -220,6 +216,8 @@ mark_noop! { Delimiter, LitKind, Level, + Bound, + Range, } rpc_encode_decode!( @@ -318,7 +316,7 @@ macro_rules! compound_traits { }; } -compound_traits!( +rpc_encode_decode!( enum Bound { Included(x), Excluded(x), @@ -390,7 +388,7 @@ pub struct Literal { pub span: Span, } -compound_traits!(struct Literal { kind, symbol, suffix, span }); +compound_traits!(struct Literal { kind, symbol, suffix, span }); #[derive(Clone)] pub enum TokenTree { @@ -434,6 +432,6 @@ compound_traits!( struct ExpnGlobals { def_site, call_site, mixed_site } ); -compound_traits!( +rpc_encode_decode!( struct Range { start, end } ); diff --git a/proc_macro/src/bridge/rpc.rs b/proc_macro/src/bridge/rpc.rs index 63329c8c02601..7fee8654bc788 100644 --- a/proc_macro/src/bridge/rpc.rs +++ b/proc_macro/src/bridge/rpc.rs @@ -52,45 +52,37 @@ macro_rules! rpc_encode_decode { } }; (enum $name:ident $(<$($T:ident),+>)? { $($variant:ident $(($field:ident))*),* $(,)? }) => { - impl),+)?> Encode for $name $(<$($T),+>)? { - fn encode(self, w: &mut Buffer, s: &mut S) { - // HACK(eddyb): `Tag` enum duplicated between the - // two impls as there's no other place to stash it. - #[allow(non_camel_case_types)] - #[repr(u8)] - enum Tag { $($variant),* } - - match self { - $($name::$variant $(($field))* => { - (Tag::$variant as u8).encode(w, s); - $($field.encode(w, s);)* - })* + #[allow(non_upper_case_globals, non_camel_case_types)] + const _: () = { + #[repr(u8)] enum Tag { $($variant),* } + + $(const $variant: u8 = Tag::$variant as u8;)* + + impl),+)?> Encode for $name $(<$($T),+>)? { + fn encode(self, w: &mut Buffer, s: &mut S) { + match self { + $($name::$variant $(($field))* => { + $variant.encode(w, s); + $($field.encode(w, s);)* + })* + } } } - } - impl<'a, S, $($($T: for<'s> Decode<'a, 's, S>),+)?> Decode<'a, '_, S> - for $name $(<$($T),+>)? - { - fn decode(r: &mut &'a [u8], s: &mut S) -> Self { - // HACK(eddyb): `Tag` enum duplicated between the - // two impls as there's no other place to stash it. - #[allow(non_upper_case_globals, non_camel_case_types)] - mod tag { - #[repr(u8)] enum Tag { $($variant),* } - - $(pub(crate) const $variant: u8 = Tag::$variant as u8;)* - } - - match u8::decode(r, s) { - $(tag::$variant => { - $(let $field = Decode::decode(r, s);)* - $name::$variant $(($field))* - })* - _ => unreachable!(), + impl<'a, S, $($($T: for<'s> Decode<'a, 's, S>),+)?> Decode<'a, '_, S> + for $name $(<$($T),+>)? + { + fn decode(r: &mut &'a [u8], s: &mut S) -> Self { + match u8::decode(r, s) { + $($variant => { + $(let $field = Decode::decode(r, s);)* + $name::$variant $(($field))* + })* + _ => unreachable!(), + } } } - } + }; } } diff --git a/proc_macro/src/bridge/selfless_reify.rs b/proc_macro/src/bridge/selfless_reify.rs index a53550e0b9e0c..1a9951af8c9f1 100644 --- a/proc_macro/src/bridge/selfless_reify.rs +++ b/proc_macro/src/bridge/selfless_reify.rs @@ -38,47 +38,27 @@ use std::mem; -// FIXME(eddyb) this could be `trait` impls except for the `const fn` requirement. -macro_rules! define_reify_functions { - ($( - fn $name:ident $(<$($param:ident),*>)? - for $(extern $abi:tt)? fn($($arg:ident: $arg_ty:ty),*) -> $ret_ty:ty; - )+) => { - $(pub(super) const fn $name< - $($($param,)*)? - F: Fn($($arg_ty),*) -> $ret_ty + Copy - >(f: F) -> $(extern $abi)? fn($($arg_ty),*) -> $ret_ty { - // FIXME(eddyb) describe the `F` type (e.g. via `type_name::`) once panic - // formatting becomes possible in `const fn`. - const { assert!(size_of::() == 0, "selfless_reify: closure must be zero-sized"); } - - $(extern $abi)? fn wrapper< - $($($param,)*)? - F: Fn($($arg_ty),*) -> $ret_ty + Copy - >($($arg: $arg_ty),*) -> $ret_ty { - let f = unsafe { - // SAFETY: `F` satisfies all criteria for "out of thin air" - // reconstructability (see module-level doc comment). - mem::MaybeUninit::::uninit().assume_init() - }; - f($($arg),*) - } - let _f_proof = f; - wrapper::< - $($($param,)*)? - F - > - })+ +pub(super) const fn reify_to_extern_c_fn_hrt_bridge< + R, + F: Fn(super::BridgeConfig<'_>) -> R + Copy, +>( + f: F, +) -> extern "C" fn(super::BridgeConfig<'_>) -> R { + // FIXME(eddyb) describe the `F` type (e.g. via `type_name::`) once panic + // formatting becomes possible in `const fn`. + const { + assert!(size_of::() == 0, "selfless_reify: closure must be zero-sized"); } -} - -define_reify_functions! { - fn _reify_to_extern_c_fn_unary for extern "C" fn(arg: A) -> R; - - // HACK(eddyb) this abstraction is used with `for<'a> fn(BridgeConfig<'a>) - // -> T` but that doesn't work with just `reify_to_extern_c_fn_unary` - // because of the `fn` pointer type being "higher-ranked" (i.e. the - // `for<'a>` binder). - // FIXME(eddyb) try to remove the lifetime from `BridgeConfig`, that'd help. - fn reify_to_extern_c_fn_hrt_bridge for extern "C" fn(bridge: super::BridgeConfig<'_>) -> R; + extern "C" fn wrapper) -> R + Copy>( + bridge: super::BridgeConfig<'_>, + ) -> R { + let f = unsafe { + // SAFETY: `F` satisfies all criteria for "out of thin air" + // reconstructability (see module-level doc comment). + mem::conjure_zst::() + }; + f(bridge) + } + let _f_proof = f; + wrapper:: } diff --git a/proc_macro/src/bridge/server.rs b/proc_macro/src/bridge/server.rs index 073ddb554994c..1151798fccf40 100644 --- a/proc_macro/src/bridge/server.rs +++ b/proc_macro/src/bridge/server.rs @@ -1,7 +1,7 @@ //! Server-side traits. use std::cell::Cell; -use std::marker::PhantomData; +use std::sync::mpsc; use super::*; @@ -53,17 +53,12 @@ impl Decode<'_, '_, HandleStore> for MarkedSpan { } } -struct Dispatcher { - handle_store: HandleStore, - server: S, -} - -macro_rules! define_server_dispatcher_impl { +macro_rules! define_server { ( - $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)* + $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)?;)* ) => { pub trait Server { - type TokenStream: 'static + Clone; + type TokenStream: 'static + Clone + Default; type Span: 'static + Copy + Eq + Hash; type Symbol: 'static; @@ -77,22 +72,21 @@ macro_rules! define_server_dispatcher_impl { $(fn $method(&mut self, $($arg: $arg_ty),*) $(-> $ret_ty)?;)* } + } +} +with_api!(define_server, Self::TokenStream, Self::Span, Self::Symbol); - // FIXME(eddyb) `pub` only for `ExecutionStrategy` below. - pub trait DispatcherTrait { - // HACK(eddyb) these are here to allow `Self::$name` to work below. - type TokenStream; - type Span; - type Symbol; - - fn dispatch(&mut self, buf: Buffer) -> Buffer; - } - - impl DispatcherTrait for Dispatcher { - type TokenStream = MarkedTokenStream; - type Span = MarkedSpan; - type Symbol = MarkedSymbol; +// FIXME(eddyb) `pub` only for `ExecutionStrategy` below. +pub struct Dispatcher { + handle_store: HandleStore, + server: S, +} +macro_rules! define_dispatcher { + ( + $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)?;)* + ) => { + impl Dispatcher { fn dispatch(&mut self, mut buf: Buffer) -> Buffer { let Dispatcher { handle_store, server } = self; @@ -102,9 +96,7 @@ macro_rules! define_server_dispatcher_impl { let mut call_method = || { $(let $arg = <$arg_ty>::decode(&mut reader, handle_store).unmark();)* let r = server.$method($($arg),*); - $( - let r: $ret_ty = Mark::mark(r); - )* + $(let r: $ret_ty = Mark::mark(r);)? r }; // HACK(eddyb) don't use `panic::catch_unwind` in a panic. @@ -127,12 +119,15 @@ macro_rules! define_server_dispatcher_impl { } } } -with_api!(Self, define_server_dispatcher_impl); +with_api!(define_dispatcher, MarkedTokenStream, MarkedSpan, MarkedSymbol); +// This trait is currently only implemented and used once, inside of this crate. +// We keep it public to allow implementing more complex execution strategies in +// the future, such as wasm proc-macros. pub trait ExecutionStrategy { fn run_bridge_and_client( &self, - dispatcher: &mut impl DispatcherTrait, + dispatcher: &mut Dispatcher, input: Buffer, run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, force_show_panics: bool, @@ -171,110 +166,78 @@ impl Drop for RunningSameThreadGuard { } } -pub struct MaybeCrossThread