From d11e1511400e4e1907f146ed5afbdc0d8c917c51 Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Fri, 26 Jun 2026 21:22:42 +0000 Subject: [PATCH] Removed portions of specify block from Verilog Signed-off-by: Jeff Ng --- test/au/spsram_256x256.au | 3 --- test/au/spsram_256x32.au | 3 --- test/au/spsram_256x32_h.au | 3 --- utils/single_port_ram_verilog_exporter.py | 3 --- 4 files changed, 12 deletions(-) diff --git a/test/au/spsram_256x256.au b/test/au/spsram_256x256.au index 1616379..78e290a 100644 --- a/test/au/spsram_256x256.au +++ b/test/au/spsram_256x256.au @@ -4500,9 +4500,6 @@ module spsram_256x256 // Timing check placeholders (will be replaced during SDF back-annotation) reg notifier; specify - // Delay from clk to rd_out - (posedge clk *> rd_out) = (0, 0); - // Timing checks $width (posedge clk, 0, 0, notifier); $width (negedge clk, 0, 0, notifier); diff --git a/test/au/spsram_256x32.au b/test/au/spsram_256x32.au index 4d45a5c..9a3fc1e 100644 --- a/test/au/spsram_256x32.au +++ b/test/au/spsram_256x32.au @@ -807,9 +807,6 @@ module spsram_256x32 // Timing check placeholders (will be replaced during SDF back-annotation) reg notifier; specify - // Delay from clk to rd_out - (posedge clk *> rd_out) = (0, 0); - // Timing checks $width (posedge clk, 0, 0, notifier); $width (negedge clk, 0, 0, notifier); diff --git a/test/au/spsram_256x32_h.au b/test/au/spsram_256x32_h.au index 130f580..3391650 100644 --- a/test/au/spsram_256x32_h.au +++ b/test/au/spsram_256x32_h.au @@ -814,9 +814,6 @@ module spsram_256x32_h // Timing check placeholders (will be replaced during SDF back-annotation) reg notifier; specify - // Delay from clk to rd_out - (posedge clk *> rd_out) = (0, 0); - // Timing checks $width (posedge clk, 0, 0, notifier); $width (negedge clk, 0, 0, notifier); diff --git a/utils/single_port_ram_verilog_exporter.py b/utils/single_port_ram_verilog_exporter.py index 0e07c2c..fa8e1dd 100644 --- a/utils/single_port_ram_verilog_exporter.py +++ b/utils/single_port_ram_verilog_exporter.py @@ -111,9 +111,6 @@ def write_timing_check(self, out_fh): ) out_fh.write(" reg notifier;\n") out_fh.write(" specify\n") - out_fh.write(f" // Delay from {clk_pin} to {dout_bus}\n") - out_fh.write(f" (posedge {clk_pin} *> {dout_bus}) = (0, 0);\n") - out_fh.write("\n") out_fh.write(" // Timing checks\n") out_fh.write( f" $width (posedge {clk_pin}, 0, 0, notifier);\n"