Describe the bug
- Sail / spec: rd = original memory value (sign-extended) 0xffffffff899fbaae
- DUT: rd = XOR result 0xffffffffa461e4eb
Expected behavior
RISC-V Unprivileged Spec, A extension: an AMO atomically loads from the address in rs1, places that original value into rd, applies the binary operator, and stores the result back to memory.
- Expected: sp = 0xffffffff899fbaae
- Actual: sp = 0xffffffffa461e4eb
The AMO FSM in UnpipelinedLSU.scala (s_amo_l / s_amo_a / s_amo_s) is unchanged on current master.
Environment
NutShell: 041f694
Describe the bug
Expected behavior
RISC-V Unprivileged Spec, A extension: an AMO atomically loads from the address in rs1, places that original value into rd, applies the binary operator, and stores the result back to memory.
The AMO FSM in UnpipelinedLSU.scala (s_amo_l / s_amo_a / s_amo_s) is unchanged on current master.
Environment
NutShell: 041f694