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Dyad · ModelingToolkit · acausal simulation
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CMOS Building Blocks, End to End

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A long-channel EKV MOSFET pair drives a two-stage Miller op-amp, which in turn becomes a + self-running relaxation oscillator. Every curve below is real simulation output from the + compiled Dyad models — no idealized equations, no fitted overlays.

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Op-amp open-loop gain
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Output swing (5 V rail)
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Oscillator frequency
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EKV
Single-expression FET model
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01

The MOSFET models

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+ NMOS and PMOS use the charge-based EKV formulation: one smooth + expression spans weak, moderate and strong inversion — no operating-region branches. The + output family shows clean saturation; the transfer curves show the continuous + sub-threshold-to-strong transition, with the p-channel scaled by its lower transconductance. +

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NMOS output characteristics

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Drain current vs VDS, stepped gate bias — the classic saturation family
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Transfer characteristic +

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ID vs gate drive at VDS = 1 V — NMOS vs PMOS
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+ NMOS KP = 200 µA/V² + PMOS KP = 70 µA/V² + VT0 = 0.4 V + L = 1 µm + Wright-ω inversion of the EKV charge equation keeps the model finite across the whole + floating-point range. +
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02

Two-stage CMOS op-amp

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+ An NMOS differential pair with a PMOS mirror load feeds a common-source second stage, Miller + compensated. Sized for near-zero systematic offset, it reaches ~90 dB of open-loop gain + and swings nearly rail to rail. Closed as a unity-gain follower it tracks its input to a + fraction of a millivolt. +

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Circuit schematic

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The exact topology of the simulated CMOSOpAmp Dyad component — eight EKV FETs, one resistor, two capacitors, self-biased from the rails
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+ NMOS + PMOS + node A (stage-1 output) +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + VDD + VSS + in − + in + + out + M3 + M4 + M6 + 2 W + M1 + M2 + M5 + M7 + M8 + Rb 220 kΩ + Cc 2 pF + Cl 1 pF + A + + INPUT STAGE + SECOND STAGE + BIAS + +
+ M1/M2 form the differential pair on M5's tail current, loaded by the M3/M4 mirror; stage-1 + output is node A. M6 (sized 2 W for zero systematic offset) drives the output against + the M7 sink, Miller-compensated by Cc. Rb through diode-connected M8 + sets the reference that M5 and M7 mirror — the amplifier biases itself from the rails. + Bulk connections (NMOS→VSS, PMOS→VDD) are omitted for clarity. +
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Open-loop transfer (VTC)

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Output vs differential input — the steep crossover is the DC gain
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Unity-gain follower tracking

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Output follows a 50 kHz input about mid-rail
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03

Relaxation oscillator

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+ With positive feedback the op-amp becomes a Schmitt-trigger comparator; an RC on the + inverting input charges and discharges between the trip points, so the loop has no stable + DC state and free-runs. The square-wave output and the exponential capacitor ramp are shown + together — the ramp turns around exactly at the Schmitt thresholds. +

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Output square wave & timing-capacitor ramp

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±2.5 V split supply — free-running, self-starting
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+ Output (square wave) + Timing cap VC + Schmitt thresholds +
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+ f ≈ 9.4 kHz + T ≈ 106 µs + β = R₂/(R₁+R₂) ≈ 0.25 + Measured period sits within ~5% of the ideal 2·R·C·ln((1+β)/(1−β)), the gap being the + finite comparator switching speed. +
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