From 892f0d752fa87cef0e2ca966975a842e1120ff12 Mon Sep 17 00:00:00 2001 From: Santhosh C Date: Mon, 8 Jun 2026 13:37:51 +0530 Subject: [PATCH 01/10] Add subckt and simulation files for IC_74LS31 --- .../SubcircuitLibrary/IC_74LS31/IC_74LS31.cir | 9 + .../IC_74LS31/IC_74LS31.cir.out | 36 ++ .../IC_74LS31/IC_74LS31.kicad_sch | 490 ++++++++++++++++++ .../SubcircuitLibrary/IC_74LS31/IC_74LS31.sub | 30 ++ .../IC_74LS31/IC_74LS31_Previous_Values.xml | 1 + library/SubcircuitLibrary/IC_74LS31/analysis | 1 + 6 files changed, 567 insertions(+) create mode 100644 library/SubcircuitLibrary/IC_74LS31/IC_74LS31.cir create mode 100644 library/SubcircuitLibrary/IC_74LS31/IC_74LS31.cir.out create mode 100644 library/SubcircuitLibrary/IC_74LS31/IC_74LS31.kicad_sch create mode 100644 library/SubcircuitLibrary/IC_74LS31/IC_74LS31.sub create mode 100644 library/SubcircuitLibrary/IC_74LS31/IC_74LS31_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/IC_74LS31/analysis diff --git a/library/SubcircuitLibrary/IC_74LS31/IC_74LS31.cir b/library/SubcircuitLibrary/IC_74LS31/IC_74LS31.cir new file mode 100644 index 000000000..b5eb27372 --- /dev/null +++ b/library/SubcircuitLibrary/IC_74LS31/IC_74LS31.cir @@ -0,0 +1,9 @@ +.title KiCad schematic +U4 Net-_U3-Pad2_ Net-_U4-Pad2_ d_inverter +U3 Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ PORT +U7 Net-_U6-Pad2_ Net-_U1-Pad2_ d_inverter +U5 Net-_U4-Pad2_ Net-_U5-Pad2_ d_inverter +U6 Net-_U5-Pad2_ Net-_U6-Pad2_ d_inverter +.end diff --git a/library/SubcircuitLibrary/IC_74LS31/IC_74LS31.cir.out b/library/SubcircuitLibrary/IC_74LS31/IC_74LS31.cir.out new file mode 100644 index 000000000..f0288ec9b --- /dev/null +++ b/library/SubcircuitLibrary/IC_74LS31/IC_74LS31.cir.out @@ -0,0 +1,36 @@ +.title kicad schematic + +* u4 net-_u3-pad2_ net-_u4-pad2_ d_inverter +* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ port +* u7 net-_u6-pad2_ net-_u1-pad2_ d_inverter +* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter +* u6 net-_u5-pad2_ net-_u6-pad2_ d_inverter +a1 net-_u3-pad2_ net-_u4-pad2_ u4 +a2 net-_u2-pad2_ net-_u3-pad2_ u3 +a3 net-_u1-pad1_ net-_u2-pad2_ u2 +a4 net-_u6-pad2_ net-_u1-pad2_ u7 +a5 net-_u4-pad2_ net-_u5-pad2_ u5 +a6 net-_u5-pad2_ net-_u6-pad2_ u6 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/IC_74LS31/IC_74LS31.kicad_sch b/library/SubcircuitLibrary/IC_74LS31/IC_74LS31.kicad_sch new file mode 100644 index 000000000..de91e7bce --- /dev/null +++ b/library/SubcircuitLibrary/IC_74LS31/IC_74LS31.kicad_sch @@ -0,0 +1,490 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid d1f09450-d5f3-4486-926c-dfcf6fec91f1) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Digital:d_inverter" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 -2.54 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_inverter" (id 1) (at 0 3.81 0) + (effects (font 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(path "/4d5fb1c4-7765-4d42-8b07-6ff63bd68cc6" + (reference "U1") (unit 2) (value "PORT") (footprint "") + ) + (path "/47bc52ef-9112-4959-a89f-3e35e023543f" + (reference "U2") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/d28121e3-1ebb-4192-99ef-781f3f6c9e37" + (reference "U3") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/caea2a68-2f7d-43f2-a0d9-2c0c4d7b3f43" + (reference "U4") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/39d526d4-2f90-4180-8d34-c0bd728e58d0" + (reference "U5") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/ac91ffb2-ec59-47bb-a612-2046f480c1e6" + (reference "U6") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/5202cb02-a3ae-46db-b2c8-2c1dbc524ef7" + (reference "U7") (unit 1) (value "d_inverter") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/IC_74LS31/IC_74LS31.sub b/library/SubcircuitLibrary/IC_74LS31/IC_74LS31.sub new file mode 100644 index 000000000..69eb9341b --- /dev/null +++ b/library/SubcircuitLibrary/IC_74LS31/IC_74LS31.sub @@ -0,0 +1,30 @@ +* Subcircuit IC_74LS31 +.subckt IC_74LS31 net-_u1-pad1_ net-_u1-pad2_ +.title kicad schematic +* u4 net-_u3-pad2_ net-_u4-pad2_ d_inverter +* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u7 net-_u6-pad2_ net-_u1-pad2_ d_inverter +* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter +* u6 net-_u5-pad2_ net-_u6-pad2_ d_inverter +a1 net-_u3-pad2_ net-_u4-pad2_ u4 +a2 net-_u2-pad2_ net-_u3-pad2_ u3 +a3 net-_u1-pad1_ net-_u2-pad2_ u2 +a4 net-_u6-pad2_ net-_u1-pad2_ u7 +a5 net-_u4-pad2_ net-_u5-pad2_ u5 +a6 net-_u5-pad2_ net-_u6-pad2_ u6 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends IC_74LS31 \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_74LS31/IC_74LS31_Previous_Values.xml b/library/SubcircuitLibrary/IC_74LS31/IC_74LS31_Previous_Values.xml new file mode 100644 index 000000000..86b70963f --- /dev/null +++ b/library/SubcircuitLibrary/IC_74LS31/IC_74LS31_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterd_inverterd_inverterd_inverterd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_74LS31/analysis b/library/SubcircuitLibrary/IC_74LS31/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/IC_74LS31/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From 67dc82d4e4cf0b2ab3357eb536fb7c25d2015c09 Mon Sep 17 00:00:00 2001 From: Santhosh C Date: Mon, 8 Jun 2026 13:40:29 +0530 Subject: [PATCH 02/10] Add subckt and simulation files for IC_CD74AC174 --- .../IC_CD74AC174/IC_CD74AC174.cir | 17 + .../IC_CD74AC174/IC_CD74AC174.cir.out | 68 + .../IC_CD74AC174/IC_CD74AC174.kicad_sch | 1556 +++++++++++++++++ .../IC_CD74AC174/IC_CD74AC174.sub | 62 + .../IC_CD74AC174_Previous_Values.xml | 1 + .../SubcircuitLibrary/IC_CD74AC174/analysis | 1 + 6 files changed, 1705 insertions(+) create mode 100644 library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.cir create mode 100644 library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.cir.out create mode 100644 library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.kicad_sch create mode 100644 library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.sub create mode 100644 library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/IC_CD74AC174/analysis diff --git a/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.cir b/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.cir new file mode 100644 index 000000000..634706b33 --- /dev/null +++ b/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.cir @@ -0,0 +1,17 @@ +.title KiCad schematic +U13 Net-_U13-Pad1_ /Q4 d_buffer +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ /Q6 /Q5 /Q4 /Q3 /Q2 /Q1 PORT +U6 Net-_U1-Pad3_ /CLK unconnected-_U6-Pad3_ /CLR Net-_U12-Pad1_ unconnected-_U6-Pad6_ d_dff +U15 Net-_U15-Pad1_ /Q6 d_buffer +U12 Net-_U12-Pad1_ /Q3 d_buffer +U14 Net-_U14-Pad1_ /Q5 d_buffer +U9 Net-_U1-Pad6_ /CLK unconnected-_U9-Pad3_ /CLR Net-_U15-Pad1_ unconnected-_U9-Pad6_ d_dff +U8 Net-_U1-Pad5_ /CLK unconnected-_U8-Pad3_ /CLR Net-_U14-Pad1_ unconnected-_U8-Pad6_ d_dff +U7 Net-_U1-Pad4_ /CLK unconnected-_U7-Pad3_ /CLR Net-_U13-Pad1_ unconnected-_U7-Pad6_ d_dff +U3 Net-_U1-Pad7_ /CLK d_buffer +U10 Net-_U10-Pad1_ /Q1 d_buffer +U11 Net-_U11-Pad1_ /Q2 d_buffer +U4 Net-_U1-Pad1_ /CLK unconnected-_U4-Pad3_ /CLR Net-_U10-Pad1_ unconnected-_U4-Pad6_ d_dff +U5 Net-_U1-Pad2_ /CLK unconnected-_U5-Pad3_ /CLR Net-_U11-Pad1_ unconnected-_U5-Pad6_ d_dff +U2 Net-_U1-Pad8_ /CLR d_inverter +.end diff --git a/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.cir.out b/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.cir.out new file mode 100644 index 000000000..1faa73d5b --- /dev/null +++ b/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.cir.out @@ -0,0 +1,68 @@ +.title kicad schematic + +* u13 net-_u13-pad1_ /q4 d_buffer +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ /q6 /q5 /q4 /q3 /q2 /q1 port +* u6 net-_u1-pad3_ /clk unconnected-_u6-pad3_ /clr net-_u12-pad1_ unconnected-_u6-pad6_ d_dff +* u15 net-_u15-pad1_ /q6 d_buffer +* u12 net-_u12-pad1_ /q3 d_buffer +* u14 net-_u14-pad1_ /q5 d_buffer +* u9 net-_u1-pad6_ /clk unconnected-_u9-pad3_ /clr net-_u15-pad1_ unconnected-_u9-pad6_ d_dff +* u8 net-_u1-pad5_ /clk unconnected-_u8-pad3_ /clr net-_u14-pad1_ unconnected-_u8-pad6_ d_dff +* u7 net-_u1-pad4_ /clk unconnected-_u7-pad3_ /clr net-_u13-pad1_ unconnected-_u7-pad6_ d_dff +* u3 net-_u1-pad7_ /clk d_buffer +* u10 net-_u10-pad1_ /q1 d_buffer +* u11 net-_u11-pad1_ /q2 d_buffer +* u4 net-_u1-pad1_ /clk unconnected-_u4-pad3_ /clr net-_u10-pad1_ unconnected-_u4-pad6_ d_dff +* u5 net-_u1-pad2_ /clk unconnected-_u5-pad3_ /clr net-_u11-pad1_ unconnected-_u5-pad6_ d_dff +* u2 net-_u1-pad8_ /clr d_inverter +a1 net-_u13-pad1_ /q4 u13 +a2 net-_u1-pad3_ /clk unconnected-_u6-pad3_ /clr net-_u12-pad1_ unconnected-_u6-pad6_ u6 +a3 net-_u15-pad1_ /q6 u15 +a4 net-_u12-pad1_ /q3 u12 +a5 net-_u14-pad1_ /q5 u14 +a6 net-_u1-pad6_ /clk unconnected-_u9-pad3_ /clr net-_u15-pad1_ unconnected-_u9-pad6_ u9 +a7 net-_u1-pad5_ /clk unconnected-_u8-pad3_ /clr net-_u14-pad1_ unconnected-_u8-pad6_ u8 +a8 net-_u1-pad4_ /clk unconnected-_u7-pad3_ /clr net-_u13-pad1_ unconnected-_u7-pad6_ u7 +a9 net-_u1-pad7_ /clk u3 +a10 net-_u10-pad1_ /q1 u10 +a11 net-_u11-pad1_ /q2 u11 +a12 net-_u1-pad1_ /clk unconnected-_u4-pad3_ /clr net-_u10-pad1_ unconnected-_u4-pad6_ u4 +a13 net-_u1-pad2_ /clk unconnected-_u5-pad3_ /clr net-_u11-pad1_ unconnected-_u5-pad6_ u5 +a14 net-_u1-pad8_ /clr u2 +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u13 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u15 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.kicad_sch b/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.kicad_sch new file mode 100644 index 000000000..4e73f93f3 --- /dev/null +++ b/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.kicad_sch @@ -0,0 +1,1556 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 442a5a5a-8e79-4187-b466-277f4dfa4761) + + (paper "A2") + + (lib_symbols + (symbol "eSim_Digital:d_buffer" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 -1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_buffer" (id 1) (at 0 1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) 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(effects (font (size 1.524 1.524))) + ) + (pin "1" (uuid e7b96660-8123-4304-bf3b-cff4d9d0475a)) + (pin "2" (uuid fa07bbfc-1427-402d-bab1-524cbee62cb3)) + (pin "3" (uuid 76ac648d-9683-454d-95bb-bdc09f42c159)) + (pin "4" (uuid 18935d1e-3ea3-4fbb-a805-023a48ef1b5d)) + (pin "5" (uuid 2786789c-db2a-4b94-a37a-ac38790f80f8)) + (pin "6" (uuid 2c4fd6f9-fbe4-4374-b890-40baffea5ca0)) + (pin "7" (uuid dcfc8f94-397c-4065-9bdc-81cfb2d23667)) + (pin "8" (uuid 8e409859-3a21-4c4c-91b5-50c7e4095372)) + (pin "9" (uuid 6cd7d96b-2514-4cd8-87fd-829e3e1f375a)) + (pin "10" (uuid 8afcbf32-30c9-4d5b-9d46-3f9dc00b5831)) + (pin "11" (uuid 19d58f22-1d04-4ae1-849f-dd65c42760eb)) + (pin "12" (uuid 9d83b677-5562-4147-8bd2-7b7bf82f5fee)) + (pin "13" (uuid 8f48e088-32fd-47d1-be27-fabf12d1b104)) + (pin "14" (uuid caa2fe83-6e92-41d4-a680-85db2f8bf745)) + (pin "15" (uuid a266ea10-c2ff-4432-a63f-bd49c9e79571)) + (pin "16" (uuid 6e039ba7-760b-4626-b21a-e5c59f4d5651)) + (pin "17" (uuid 82262ab8-067a-4500-abe3-0d2d6f1a47c0)) + (pin "18" (uuid 95dcb744-c057-4fab-9597-fb882c39b56c)) + (pin "19" (uuid be03368b-5b54-4bf7-809c-e379fa61d9f3)) + (pin "20" (uuid fb096233-97e2-4d3b-a510-f09058def763)) + (pin "21" (uuid f192af8d-fabf-42fa-8f66-7ef65c2d2b53)) + (pin "22" (uuid 92003786-b473-4e30-a641-156dd89c5524)) + (pin "23" (uuid 4b33d894-5b20-46d1-9a09-a8da0f4d35b7)) + (pin "24" (uuid 7b0f07e3-fd4f-4d3b-83ed-c5216e399ceb)) + (pin "25" (uuid f422bc81-63ff-4368-bee8-ff6d3d1ba557)) + (pin "26" (uuid 69e842c8-4038-4aa2-92e7-ebe69b090ebb)) + ) + + (sheet_instances + (path "/" (page "1")) + ) + + (symbol_instances + (path "/ae74a5e2-a282-48bb-80fb-56ad11c8fca6" + (reference "U1") (unit 1) (value "PORT") (footprint "") + ) + (path "/239f347b-e487-422f-9647-38881def0415" + (reference "U1") (unit 2) (value "PORT") (footprint "") + ) + (path "/48ad4024-21b6-41d3-b673-62306d1319d9" + (reference "U1") (unit 3) (value "PORT") (footprint "") + ) + (path "/0d089315-ad07-4b73-a91d-0a51083fb72c" + (reference "U1") (unit 4) (value "PORT") (footprint "") + ) + (path "/eb10cbc8-e60e-41f0-9194-a71dab539a2b" + (reference "U1") (unit 5) (value "PORT") (footprint "") + ) + (path "/aff65b41-96d0-461e-b5c7-626d4bd641cd" + (reference "U1") (unit 6) (value "PORT") (footprint "") + ) + (path "/594c9a11-e64b-4db1-ba54-10d2ff51b064" + (reference "U1") (unit 7) (value "PORT") (footprint "") + ) + (path "/09adf8ab-ed63-4690-91fe-9073e1d7a862" + (reference "U1") (unit 8) (value "PORT") (footprint "") + ) + (path "/8110a1f8-538a-4cbb-b734-a36379cf27a7" + (reference "U1") (unit 9) (value "PORT") (footprint "") + ) + (path "/47bf1cd8-2a23-472c-b9c4-c6db530a6fba" + (reference "U1") (unit 10) (value "PORT") (footprint "") + ) + (path "/a0862aa0-2d17-491f-87c1-f8271df648b7" + (reference "U1") (unit 11) (value "PORT") (footprint "") + ) + (path "/191591ee-5bed-472e-8ed3-31e6b27755c9" + (reference "U1") (unit 12) (value "PORT") (footprint "") + ) + (path "/bb2932e1-21c1-4a7c-8b26-d82f7a937b37" + (reference "U1") (unit 13) (value "PORT") (footprint "") + ) + (path "/53974ecf-c4c2-49f6-8a02-0daf152e42fc" + (reference "U1") (unit 14) (value "PORT") (footprint "") + ) + (path "/8f9514ff-09ea-4699-8440-2304cfb41a71" + (reference "U2") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/5aeb50ed-05e4-4712-92a9-21927e9756d0" + (reference "U3") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/8e544e1b-f572-4865-a5d1-1bced1380eda" + (reference "U4") (unit 1) (value "d_dff") (footprint "") + ) + (path "/b902c0c2-7e0e-4379-9b9f-2f6a78767790" + (reference "U5") (unit 1) (value "d_dff") (footprint "") + ) + (path "/04afe41d-3abe-40c4-87ed-e41548b56a4f" + (reference "U6") (unit 1) (value "d_dff") (footprint "") + ) + (path "/2def0cc9-0fe9-4fd9-ba9d-2014ec5c8cf9" + (reference "U7") (unit 1) (value "d_dff") (footprint "") + ) + (path "/5ffbb8f5-6b25-49b2-9948-b9742d7029a1" + (reference "U8") (unit 1) (value "d_dff") (footprint "") + ) + (path "/8512eac5-628d-48cb-9091-c950c8ab0dc5" + (reference "U9") (unit 1) (value "d_dff") (footprint "") + ) + (path "/069a0ecf-c88b-493a-b0ce-3522c5036f13" + (reference "U10") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/e4c9c8db-76a3-4102-84a9-976a465c2bd4" + (reference "U11") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/6bef8c38-843f-4997-871a-1fa840628150" + (reference "U12") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/c30a3759-ad88-4901-98e2-c335327b7d85" + (reference "U13") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/a2ad52f2-8794-47c2-9a44-803d75affd8b" + (reference "U14") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/04f5ec72-7f78-4a8a-b87e-b4400dc21552" + (reference "U15") (unit 1) (value "d_buffer") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.sub b/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.sub new file mode 100644 index 000000000..a420effbb --- /dev/null +++ b/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174.sub @@ -0,0 +1,62 @@ +* Subcircuit IC_CD74AC174 +.subckt IC_CD74AC174 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ /q6 /q5 /q4 /q3 /q2 /q1 +.title kicad schematic +* u13 net-_u13-pad1_ /q4 d_buffer +* u6 net-_u1-pad3_ /clk unconnected-_u6-pad3_ /clr net-_u12-pad1_ unconnected-_u6-pad6_ d_dff +* u15 net-_u15-pad1_ /q6 d_buffer +* u12 net-_u12-pad1_ /q3 d_buffer +* u14 net-_u14-pad1_ /q5 d_buffer +* u9 net-_u1-pad6_ /clk unconnected-_u9-pad3_ /clr net-_u15-pad1_ unconnected-_u9-pad6_ d_dff +* u8 net-_u1-pad5_ /clk unconnected-_u8-pad3_ /clr net-_u14-pad1_ unconnected-_u8-pad6_ d_dff +* u7 net-_u1-pad4_ /clk unconnected-_u7-pad3_ /clr net-_u13-pad1_ unconnected-_u7-pad6_ d_dff +* u3 net-_u1-pad7_ /clk d_buffer +* u10 net-_u10-pad1_ /q1 d_buffer +* u11 net-_u11-pad1_ /q2 d_buffer +* u4 net-_u1-pad1_ /clk unconnected-_u4-pad3_ /clr net-_u10-pad1_ unconnected-_u4-pad6_ d_dff +* u5 net-_u1-pad2_ /clk unconnected-_u5-pad3_ /clr net-_u11-pad1_ unconnected-_u5-pad6_ d_dff +* u2 net-_u1-pad8_ /clr d_inverter +a1 net-_u13-pad1_ /q4 u13 +a2 net-_u1-pad3_ /clk unconnected-_u6-pad3_ /clr net-_u12-pad1_ unconnected-_u6-pad6_ u6 +a3 net-_u15-pad1_ /q6 u15 +a4 net-_u12-pad1_ /q3 u12 +a5 net-_u14-pad1_ /q5 u14 +a6 net-_u1-pad6_ /clk unconnected-_u9-pad3_ /clr net-_u15-pad1_ unconnected-_u9-pad6_ u9 +a7 net-_u1-pad5_ /clk unconnected-_u8-pad3_ /clr net-_u14-pad1_ unconnected-_u8-pad6_ u8 +a8 net-_u1-pad4_ /clk unconnected-_u7-pad3_ /clr net-_u13-pad1_ unconnected-_u7-pad6_ u7 +a9 net-_u1-pad7_ /clk u3 +a10 net-_u10-pad1_ /q1 u10 +a11 net-_u11-pad1_ /q2 u11 +a12 net-_u1-pad1_ /clk unconnected-_u4-pad3_ /clr net-_u10-pad1_ unconnected-_u4-pad6_ u4 +a13 net-_u1-pad2_ /clk unconnected-_u5-pad3_ /clr net-_u11-pad1_ unconnected-_u5-pad6_ u5 +a14 net-_u1-pad8_ /clr u2 +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u13 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u15 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends IC_CD74AC174 \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174_Previous_Values.xml b/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174_Previous_Values.xml new file mode 100644 index 000000000..e7de15a27 --- /dev/null +++ b/library/SubcircuitLibrary/IC_CD74AC174/IC_CD74AC174_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_bufferd_dffd_bufferd_bufferd_bufferd_dffd_dffd_dffd_bufferd_bufferd_bufferd_dffd_dffd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_CD74AC174/analysis b/library/SubcircuitLibrary/IC_CD74AC174/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/IC_CD74AC174/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From 771bb22bb7589e83d8d7ca37b12f080f267d7484 Mon Sep 17 00:00:00 2001 From: Santhosh C Date: Mon, 8 Jun 2026 13:41:14 +0530 Subject: [PATCH 03/10] Add subckt and simulation files for IC_CD74HC533 --- .../IC_CD74HC533/IC_CD74HC533.cir | 30 + .../IC_CD74HC533/IC_CD74HC533.cir.out | 120 + .../IC_CD74HC533/IC_CD74HC533.kicad_sch | 2269 +++++++++++++++++ .../IC_CD74HC533/IC_CD74HC533.sub | 114 + .../IC_CD74HC533_Previous_Values.xml | 1 + .../SubcircuitLibrary/IC_CD74HC533/analysis | 1 + 6 files changed, 2535 insertions(+) create mode 100644 library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.cir create mode 100644 library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.cir.out create mode 100644 library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.kicad_sch create mode 100644 library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.sub create mode 100644 library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/IC_CD74HC533/analysis diff --git a/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.cir b/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.cir new file mode 100644 index 000000000..1cb35880d --- /dev/null +++ b/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.cir @@ -0,0 +1,30 @@ +.title KiCad schematic +U18 Net-_U17-Pad5_ Net-_U12-Pad2_ Net-_U18-Pad3_ d_tristate +U21 Net-_U20-Pad5_ Net-_U12-Pad2_ Net-_U21-Pad3_ d_tristate +U19 Net-_U18-Pad3_ Net-_U1-Pad14_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ PORT +U22 Net-_U21-Pad3_ Net-_U1-Pad13_ d_inverter +U17 Net-_U1-Pad5_ Net-_U11-Pad2_ unconnected-_U17-Pad3_ unconnected-_U17-Pad4_ Net-_U17-Pad5_ unconnected-_U17-Pad6_ d_dlatch +U20 Net-_U1-Pad6_ Net-_U11-Pad2_ unconnected-_U20-Pad3_ unconnected-_U20-Pad4_ Net-_U20-Pad5_ unconnected-_U20-Pad6_ d_dlatch +U26 Net-_U1-Pad8_ Net-_U11-Pad2_ unconnected-_U26-Pad3_ unconnected-_U26-Pad4_ Net-_U26-Pad5_ unconnected-_U26-Pad6_ d_dlatch +U25 Net-_U24-Pad3_ Net-_U1-Pad12_ d_inverter +U24 Net-_U23-Pad5_ Net-_U12-Pad2_ Net-_U24-Pad3_ d_tristate +U23 Net-_U1-Pad7_ Net-_U11-Pad2_ unconnected-_U23-Pad3_ unconnected-_U23-Pad4_ Net-_U23-Pad5_ unconnected-_U23-Pad6_ d_dlatch +U28 Net-_U27-Pad3_ Net-_U1-Pad11_ d_inverter +U27 Net-_U26-Pad5_ Net-_U12-Pad2_ Net-_U27-Pad3_ d_tristate +U6 Net-_U5-Pad5_ Net-_U12-Pad2_ Net-_U6-Pad3_ d_tristate +U5 Net-_U1-Pad1_ Net-_U11-Pad2_ unconnected-_U5-Pad3_ unconnected-_U5-Pad4_ Net-_U5-Pad5_ unconnected-_U5-Pad6_ d_dlatch +U4 Net-_U3-Pad2_ Net-_U12-Pad2_ d_buffer +U2 Net-_U1-Pad9_ Net-_U11-Pad2_ d_inverter +U3 Net-_U1-Pad10_ Net-_U3-Pad2_ d_inverter +U15 Net-_U14-Pad5_ Net-_U12-Pad2_ Net-_U15-Pad3_ d_tristate +U11 Net-_U1-Pad3_ Net-_U11-Pad2_ unconnected-_U11-Pad3_ unconnected-_U11-Pad4_ Net-_U11-Pad5_ unconnected-_U11-Pad6_ d_dlatch +U14 Net-_U1-Pad4_ Net-_U11-Pad2_ unconnected-_U14-Pad3_ unconnected-_U14-Pad4_ Net-_U14-Pad5_ unconnected-_U14-Pad6_ d_dlatch +U16 Net-_U15-Pad3_ Net-_U1-Pad15_ d_inverter +U8 Net-_U1-Pad2_ Net-_U11-Pad2_ unconnected-_U8-Pad3_ unconnected-_U8-Pad4_ Net-_U8-Pad5_ unconnected-_U8-Pad6_ d_dlatch +U12 Net-_U11-Pad5_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_tristate +U13 Net-_U12-Pad3_ Net-_U1-Pad16_ d_inverter +U7 Net-_U6-Pad3_ Net-_U1-Pad18_ d_inverter +U9 Net-_U8-Pad5_ Net-_U12-Pad2_ Net-_U10-Pad1_ d_tristate +U10 Net-_U10-Pad1_ Net-_U1-Pad17_ d_inverter +.end diff --git a/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.cir.out b/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.cir.out new file mode 100644 index 000000000..63f052fa8 --- /dev/null +++ b/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.cir.out @@ -0,0 +1,120 @@ +.title kicad schematic + +* u18 net-_u17-pad5_ net-_u12-pad2_ net-_u18-pad3_ d_tristate +* u21 net-_u20-pad5_ net-_u12-pad2_ net-_u21-pad3_ d_tristate +* u19 net-_u18-pad3_ net-_u1-pad14_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ port +* u22 net-_u21-pad3_ net-_u1-pad13_ d_inverter +* u17 net-_u1-pad5_ net-_u11-pad2_ unconnected-_u17-pad3_ unconnected-_u17-pad4_ net-_u17-pad5_ unconnected-_u17-pad6_ d_dlatch +* u20 net-_u1-pad6_ net-_u11-pad2_ unconnected-_u20-pad3_ unconnected-_u20-pad4_ net-_u20-pad5_ unconnected-_u20-pad6_ d_dlatch +* u26 net-_u1-pad8_ net-_u11-pad2_ unconnected-_u26-pad3_ unconnected-_u26-pad4_ net-_u26-pad5_ unconnected-_u26-pad6_ d_dlatch +* u25 net-_u24-pad3_ net-_u1-pad12_ d_inverter +* u24 net-_u23-pad5_ net-_u12-pad2_ net-_u24-pad3_ d_tristate +* u23 net-_u1-pad7_ net-_u11-pad2_ unconnected-_u23-pad3_ unconnected-_u23-pad4_ net-_u23-pad5_ unconnected-_u23-pad6_ d_dlatch +* u28 net-_u27-pad3_ net-_u1-pad11_ d_inverter +* u27 net-_u26-pad5_ net-_u12-pad2_ net-_u27-pad3_ d_tristate +* u6 net-_u5-pad5_ net-_u12-pad2_ net-_u6-pad3_ d_tristate +* u5 net-_u1-pad1_ net-_u11-pad2_ unconnected-_u5-pad3_ unconnected-_u5-pad4_ net-_u5-pad5_ unconnected-_u5-pad6_ d_dlatch +* u4 net-_u3-pad2_ net-_u12-pad2_ d_buffer +* u2 net-_u1-pad9_ net-_u11-pad2_ d_inverter +* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter +* u15 net-_u14-pad5_ net-_u12-pad2_ net-_u15-pad3_ d_tristate +* u11 net-_u1-pad3_ net-_u11-pad2_ unconnected-_u11-pad3_ unconnected-_u11-pad4_ net-_u11-pad5_ unconnected-_u11-pad6_ d_dlatch +* u14 net-_u1-pad4_ net-_u11-pad2_ unconnected-_u14-pad3_ unconnected-_u14-pad4_ net-_u14-pad5_ unconnected-_u14-pad6_ d_dlatch +* u16 net-_u15-pad3_ net-_u1-pad15_ d_inverter +* u8 net-_u1-pad2_ net-_u11-pad2_ unconnected-_u8-pad3_ unconnected-_u8-pad4_ net-_u8-pad5_ unconnected-_u8-pad6_ d_dlatch +* u12 net-_u11-pad5_ net-_u12-pad2_ net-_u12-pad3_ d_tristate +* u13 net-_u12-pad3_ net-_u1-pad16_ d_inverter +* u7 net-_u6-pad3_ net-_u1-pad18_ d_inverter +* u9 net-_u8-pad5_ net-_u12-pad2_ net-_u10-pad1_ d_tristate +* u10 net-_u10-pad1_ net-_u1-pad17_ d_inverter +a1 net-_u17-pad5_ net-_u12-pad2_ net-_u18-pad3_ u18 +a2 net-_u20-pad5_ net-_u12-pad2_ net-_u21-pad3_ u21 +a3 net-_u18-pad3_ net-_u1-pad14_ u19 +a4 net-_u21-pad3_ net-_u1-pad13_ u22 +a5 net-_u1-pad5_ net-_u11-pad2_ unconnected-_u17-pad3_ unconnected-_u17-pad4_ net-_u17-pad5_ unconnected-_u17-pad6_ u17 +a6 net-_u1-pad6_ net-_u11-pad2_ unconnected-_u20-pad3_ unconnected-_u20-pad4_ net-_u20-pad5_ unconnected-_u20-pad6_ u20 +a7 net-_u1-pad8_ net-_u11-pad2_ unconnected-_u26-pad3_ unconnected-_u26-pad4_ net-_u26-pad5_ unconnected-_u26-pad6_ u26 +a8 net-_u24-pad3_ net-_u1-pad12_ u25 +a9 net-_u23-pad5_ net-_u12-pad2_ net-_u24-pad3_ u24 +a10 net-_u1-pad7_ net-_u11-pad2_ unconnected-_u23-pad3_ unconnected-_u23-pad4_ net-_u23-pad5_ unconnected-_u23-pad6_ u23 +a11 net-_u27-pad3_ net-_u1-pad11_ u28 +a12 net-_u26-pad5_ net-_u12-pad2_ net-_u27-pad3_ u27 +a13 net-_u5-pad5_ net-_u12-pad2_ net-_u6-pad3_ u6 +a14 net-_u1-pad1_ net-_u11-pad2_ unconnected-_u5-pad3_ unconnected-_u5-pad4_ net-_u5-pad5_ unconnected-_u5-pad6_ u5 +a15 net-_u3-pad2_ net-_u12-pad2_ u4 +a16 net-_u1-pad9_ net-_u11-pad2_ u2 +a17 net-_u1-pad10_ net-_u3-pad2_ u3 +a18 net-_u14-pad5_ net-_u12-pad2_ net-_u15-pad3_ u15 +a19 net-_u1-pad3_ net-_u11-pad2_ unconnected-_u11-pad3_ unconnected-_u11-pad4_ net-_u11-pad5_ unconnected-_u11-pad6_ u11 +a20 net-_u1-pad4_ net-_u11-pad2_ unconnected-_u14-pad3_ unconnected-_u14-pad4_ net-_u14-pad5_ unconnected-_u14-pad6_ u14 +a21 net-_u15-pad3_ net-_u1-pad15_ u16 +a22 net-_u1-pad2_ net-_u11-pad2_ unconnected-_u8-pad3_ unconnected-_u8-pad4_ net-_u8-pad5_ unconnected-_u8-pad6_ u8 +a23 net-_u11-pad5_ net-_u12-pad2_ net-_u12-pad3_ u12 +a24 net-_u12-pad3_ net-_u1-pad16_ u13 +a25 net-_u6-pad3_ net-_u1-pad18_ u7 +a26 net-_u8-pad5_ net-_u12-pad2_ net-_u10-pad1_ u9 +a27 net-_u10-pad1_ net-_u1-pad17_ u10 +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u21 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u17 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u20 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u26 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u24 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u23 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u27 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u5 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u15 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u11 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u14 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u8 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.kicad_sch b/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.kicad_sch new file mode 100644 index 000000000..70e0184dd --- /dev/null +++ b/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.kicad_sch @@ -0,0 +1,2269 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid d161802c-cc1c-4a97-b77c-0a2feb58bb22) + + (paper "A1") + + (lib_symbols + (symbol "eSim_Digital:d_buffer" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 -1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_buffer" (id 1) (at 0 1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "d_buffer_0_1" + (polyline + (pts + (xy -7.62 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"/370907f2-dd80-485e-8c30-a242de9be6f5" + (reference "U5") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/849fc6ae-3be9-4ca8-ad34-3cb786c2a720" + (reference "U6") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/f53a8c45-9d53-4508-96ce-c972fff7da65" + (reference "U7") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/7d0750aa-dea5-4c85-a2b1-8e8be4ecdc6b" + (reference "U8") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/ed7a3fa4-a8a9-4289-9953-4511504ae01b" + (reference "U9") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/cfe0bfb5-a260-4a8f-8f1b-d1b8adb7fd90" + (reference "U10") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/71777415-3f20-414a-ae3f-3c4fd42fb21b" + (reference "U11") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/1568d3c4-86dd-4b77-bb60-60c942686580" + (reference "U12") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/8598e3a8-0e66-4cd5-9eb1-a18d6de7f2d0" + (reference "U13") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/23841a41-932a-433b-8174-ea2807c16274" + (reference "U14") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/b72065c9-40f5-4c50-8d80-203f9536aa11" + (reference "U15") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/3f1cd832-8e9c-4ff9-92f1-c6631861f536" + (reference "U16") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/386facbf-3e0d-4048-a622-6c0c69f64c0b" + (reference "U17") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/74b7448b-c37e-47b4-a657-af41d172500e" + (reference "U18") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/0a0cfd53-3071-4eef-98fc-685400b295b5" + (reference "U19") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/5ed8310a-25d1-42a7-9ba3-f236fac34571" + (reference "U20") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/ada1db0b-510e-4c63-b3e8-ab860654d307" + (reference "U21") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/110fbde8-5a7a-4080-aca8-07adb2fb76dc" + (reference "U22") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/7c428c5b-a48b-4a57-8a3b-27c782eee805" + (reference "U23") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/994607de-8067-422c-8c08-28722a7a73c0" + (reference "U24") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/af81e449-58f3-4824-8557-1cb6451f6f4c" + (reference "U25") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/5048d7cb-d8b3-4568-bc9a-242ac4ccc9f5" + (reference "U26") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/fca35eb6-e646-41da-a3c8-9de3d2718a83" + (reference "U27") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/b02955d4-e066-4d90-8ec8-79b5031d54d4" + (reference "U28") (unit 1) (value "d_inverter") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.sub b/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.sub new file mode 100644 index 000000000..e0702553b --- /dev/null +++ b/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533.sub @@ -0,0 +1,114 @@ +* Subcircuit IC_CD74HC533 +.subckt IC_CD74HC533 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ +.title kicad schematic +* u18 net-_u17-pad5_ net-_u12-pad2_ net-_u18-pad3_ d_tristate +* u21 net-_u20-pad5_ net-_u12-pad2_ net-_u21-pad3_ d_tristate +* u19 net-_u18-pad3_ net-_u1-pad14_ d_inverter +* u22 net-_u21-pad3_ net-_u1-pad13_ d_inverter +* u17 net-_u1-pad5_ net-_u11-pad2_ unconnected-_u17-pad3_ unconnected-_u17-pad4_ net-_u17-pad5_ unconnected-_u17-pad6_ d_dlatch +* u20 net-_u1-pad6_ net-_u11-pad2_ unconnected-_u20-pad3_ unconnected-_u20-pad4_ net-_u20-pad5_ unconnected-_u20-pad6_ d_dlatch +* u26 net-_u1-pad8_ net-_u11-pad2_ unconnected-_u26-pad3_ unconnected-_u26-pad4_ net-_u26-pad5_ unconnected-_u26-pad6_ d_dlatch +* u25 net-_u24-pad3_ net-_u1-pad12_ d_inverter +* u24 net-_u23-pad5_ net-_u12-pad2_ net-_u24-pad3_ d_tristate +* u23 net-_u1-pad7_ net-_u11-pad2_ unconnected-_u23-pad3_ unconnected-_u23-pad4_ net-_u23-pad5_ unconnected-_u23-pad6_ d_dlatch +* u28 net-_u27-pad3_ net-_u1-pad11_ d_inverter +* u27 net-_u26-pad5_ net-_u12-pad2_ net-_u27-pad3_ d_tristate +* u6 net-_u5-pad5_ net-_u12-pad2_ net-_u6-pad3_ d_tristate +* u5 net-_u1-pad1_ net-_u11-pad2_ unconnected-_u5-pad3_ unconnected-_u5-pad4_ net-_u5-pad5_ unconnected-_u5-pad6_ d_dlatch +* u4 net-_u3-pad2_ net-_u12-pad2_ d_buffer +* u2 net-_u1-pad9_ net-_u11-pad2_ d_inverter +* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter +* u15 net-_u14-pad5_ net-_u12-pad2_ net-_u15-pad3_ d_tristate +* u11 net-_u1-pad3_ net-_u11-pad2_ unconnected-_u11-pad3_ unconnected-_u11-pad4_ net-_u11-pad5_ unconnected-_u11-pad6_ d_dlatch +* u14 net-_u1-pad4_ net-_u11-pad2_ unconnected-_u14-pad3_ unconnected-_u14-pad4_ net-_u14-pad5_ unconnected-_u14-pad6_ d_dlatch +* u16 net-_u15-pad3_ net-_u1-pad15_ d_inverter +* u8 net-_u1-pad2_ net-_u11-pad2_ unconnected-_u8-pad3_ unconnected-_u8-pad4_ net-_u8-pad5_ unconnected-_u8-pad6_ d_dlatch +* u12 net-_u11-pad5_ net-_u12-pad2_ net-_u12-pad3_ d_tristate +* u13 net-_u12-pad3_ net-_u1-pad16_ d_inverter +* u7 net-_u6-pad3_ net-_u1-pad18_ d_inverter +* u9 net-_u8-pad5_ net-_u12-pad2_ net-_u10-pad1_ d_tristate +* u10 net-_u10-pad1_ net-_u1-pad17_ d_inverter +a1 net-_u17-pad5_ net-_u12-pad2_ net-_u18-pad3_ u18 +a2 net-_u20-pad5_ net-_u12-pad2_ net-_u21-pad3_ u21 +a3 net-_u18-pad3_ net-_u1-pad14_ u19 +a4 net-_u21-pad3_ net-_u1-pad13_ u22 +a5 net-_u1-pad5_ net-_u11-pad2_ unconnected-_u17-pad3_ unconnected-_u17-pad4_ net-_u17-pad5_ unconnected-_u17-pad6_ u17 +a6 net-_u1-pad6_ net-_u11-pad2_ unconnected-_u20-pad3_ unconnected-_u20-pad4_ net-_u20-pad5_ unconnected-_u20-pad6_ u20 +a7 net-_u1-pad8_ net-_u11-pad2_ unconnected-_u26-pad3_ unconnected-_u26-pad4_ net-_u26-pad5_ unconnected-_u26-pad6_ u26 +a8 net-_u24-pad3_ net-_u1-pad12_ u25 +a9 net-_u23-pad5_ net-_u12-pad2_ net-_u24-pad3_ u24 +a10 net-_u1-pad7_ net-_u11-pad2_ unconnected-_u23-pad3_ unconnected-_u23-pad4_ net-_u23-pad5_ unconnected-_u23-pad6_ u23 +a11 net-_u27-pad3_ net-_u1-pad11_ u28 +a12 net-_u26-pad5_ net-_u12-pad2_ net-_u27-pad3_ u27 +a13 net-_u5-pad5_ net-_u12-pad2_ net-_u6-pad3_ u6 +a14 net-_u1-pad1_ net-_u11-pad2_ unconnected-_u5-pad3_ unconnected-_u5-pad4_ net-_u5-pad5_ unconnected-_u5-pad6_ u5 +a15 net-_u3-pad2_ net-_u12-pad2_ u4 +a16 net-_u1-pad9_ net-_u11-pad2_ u2 +a17 net-_u1-pad10_ net-_u3-pad2_ u3 +a18 net-_u14-pad5_ net-_u12-pad2_ net-_u15-pad3_ u15 +a19 net-_u1-pad3_ net-_u11-pad2_ unconnected-_u11-pad3_ unconnected-_u11-pad4_ net-_u11-pad5_ unconnected-_u11-pad6_ u11 +a20 net-_u1-pad4_ net-_u11-pad2_ unconnected-_u14-pad3_ unconnected-_u14-pad4_ net-_u14-pad5_ unconnected-_u14-pad6_ u14 +a21 net-_u15-pad3_ net-_u1-pad15_ u16 +a22 net-_u1-pad2_ net-_u11-pad2_ unconnected-_u8-pad3_ unconnected-_u8-pad4_ net-_u8-pad5_ unconnected-_u8-pad6_ u8 +a23 net-_u11-pad5_ net-_u12-pad2_ net-_u12-pad3_ u12 +a24 net-_u12-pad3_ net-_u1-pad16_ u13 +a25 net-_u6-pad3_ net-_u1-pad18_ u7 +a26 net-_u8-pad5_ net-_u12-pad2_ net-_u10-pad1_ u9 +a27 net-_u10-pad1_ net-_u1-pad17_ u10 +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u21 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u17 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u20 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u26 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u24 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u23 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u27 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u5 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u15 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u11 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u14 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u8 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends IC_CD74HC533 \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533_Previous_Values.xml b/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533_Previous_Values.xml new file mode 100644 index 000000000..637759b65 --- /dev/null +++ b/library/SubcircuitLibrary/IC_CD74HC533/IC_CD74HC533_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_tristated_tristated_inverterd_inverterd_dlatchd_dlatchd_dlatchd_inverterd_tristated_dlatchd_inverterd_tristated_tristated_dlatchd_bufferd_inverterd_inverterd_tristated_dlatchd_dlatchd_inverterd_dlatchd_tristated_inverterd_inverterd_tristated_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_CD74HC533/analysis b/library/SubcircuitLibrary/IC_CD74HC533/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/IC_CD74HC533/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From 370512d7157ff30694815e8d5ac801315ff61d64 Mon Sep 17 00:00:00 2001 From: Santhosh C Date: Mon, 8 Jun 2026 13:41:34 +0530 Subject: [PATCH 04/10] Add subckt and simulation files for IC_DM8098 --- .../SubcircuitLibrary/IC_DM8098/IC_DM8098.cir | 19 + .../IC_DM8098/IC_DM8098.cir.out | 76 + .../IC_DM8098/IC_DM8098.kicad_sch | 1468 +++++++++++++++++ .../SubcircuitLibrary/IC_DM8098/IC_DM8098.sub | 70 + .../IC_DM8098/IC_DM8098_Previous_Values.xml | 1 + library/SubcircuitLibrary/IC_DM8098/analysis | 1 + 6 files changed, 1635 insertions(+) create mode 100644 library/SubcircuitLibrary/IC_DM8098/IC_DM8098.cir create mode 100644 library/SubcircuitLibrary/IC_DM8098/IC_DM8098.cir.out create mode 100644 library/SubcircuitLibrary/IC_DM8098/IC_DM8098.kicad_sch create mode 100644 library/SubcircuitLibrary/IC_DM8098/IC_DM8098.sub create mode 100644 library/SubcircuitLibrary/IC_DM8098/IC_DM8098_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/IC_DM8098/analysis diff --git a/library/SubcircuitLibrary/IC_DM8098/IC_DM8098.cir b/library/SubcircuitLibrary/IC_DM8098/IC_DM8098.cir new file mode 100644 index 000000000..6a437e9db --- /dev/null +++ b/library/SubcircuitLibrary/IC_DM8098/IC_DM8098.cir @@ -0,0 +1,19 @@ +.title KiCad schematic +U9 Net-_U1-Pad4_ Net-_U4-Pad2_ Net-_U15-Pad1_ d_tristate +U10 Net-_U1-Pad5_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_tristate +U11 Net-_U1-Pad6_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_tristate +U3 Net-_U1-Pad8_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U17-Pad2_ Net-_U16-Pad2_ Net-_U15-Pad2_ Net-_U14-Pad2_ Net-_U13-Pad2_ Net-_U12-Pad2_ PORT +U2 Net-_U1-Pad7_ Net-_U2-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U17 Net-_U11-Pad3_ Net-_U17-Pad2_ d_inverter +U16 Net-_U10-Pad3_ Net-_U16-Pad2_ d_inverter +U4 Net-_U2-Pad2_ Net-_U4-Pad2_ d_buffer +U5 Net-_U3-Pad2_ Net-_U10-Pad2_ d_buffer +U8 Net-_U1-Pad3_ Net-_U4-Pad2_ Net-_U14-Pad1_ d_tristate +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U6 Net-_U1-Pad1_ Net-_U4-Pad2_ Net-_U12-Pad1_ d_tristate +U7 Net-_U1-Pad2_ Net-_U4-Pad2_ Net-_U13-Pad1_ d_tristate +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +.end diff --git a/library/SubcircuitLibrary/IC_DM8098/IC_DM8098.cir.out b/library/SubcircuitLibrary/IC_DM8098/IC_DM8098.cir.out new file mode 100644 index 000000000..deea8a184 --- /dev/null +++ b/library/SubcircuitLibrary/IC_DM8098/IC_DM8098.cir.out @@ -0,0 +1,76 @@ +.title kicad schematic + +* u9 net-_u1-pad4_ net-_u4-pad2_ net-_u15-pad1_ d_tristate +* u10 net-_u1-pad5_ net-_u10-pad2_ net-_u10-pad3_ d_tristate +* u11 net-_u1-pad6_ net-_u10-pad2_ net-_u11-pad3_ d_tristate +* u3 net-_u1-pad8_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u17-pad2_ net-_u16-pad2_ net-_u15-pad2_ net-_u14-pad2_ net-_u13-pad2_ net-_u12-pad2_ port +* u2 net-_u1-pad7_ net-_u2-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u17 net-_u11-pad3_ net-_u17-pad2_ d_inverter +* u16 net-_u10-pad3_ net-_u16-pad2_ d_inverter +* u4 net-_u2-pad2_ net-_u4-pad2_ d_buffer +* u5 net-_u3-pad2_ net-_u10-pad2_ d_buffer +* u8 net-_u1-pad3_ net-_u4-pad2_ net-_u14-pad1_ d_tristate +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u6 net-_u1-pad1_ net-_u4-pad2_ net-_u12-pad1_ d_tristate +* u7 net-_u1-pad2_ net-_u4-pad2_ net-_u13-pad1_ d_tristate +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +a1 net-_u1-pad4_ net-_u4-pad2_ net-_u15-pad1_ u9 +a2 net-_u1-pad5_ net-_u10-pad2_ net-_u10-pad3_ u10 +a3 net-_u1-pad6_ net-_u10-pad2_ net-_u11-pad3_ u11 +a4 net-_u1-pad8_ net-_u3-pad2_ u3 +a5 net-_u1-pad7_ net-_u2-pad2_ u2 +a6 net-_u15-pad1_ net-_u15-pad2_ u15 +a7 net-_u11-pad3_ net-_u17-pad2_ u17 +a8 net-_u10-pad3_ net-_u16-pad2_ u16 +a9 net-_u2-pad2_ net-_u4-pad2_ u4 +a10 net-_u3-pad2_ net-_u10-pad2_ u5 +a11 net-_u1-pad3_ net-_u4-pad2_ net-_u14-pad1_ u8 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u12-pad1_ net-_u12-pad2_ u12 +a14 net-_u1-pad1_ net-_u4-pad2_ net-_u12-pad1_ u6 +a15 net-_u1-pad2_ net-_u4-pad2_ net-_u13-pad1_ u7 +a16 net-_u14-pad1_ net-_u14-pad2_ u14 +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u7 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/IC_DM8098/IC_DM8098.kicad_sch b/library/SubcircuitLibrary/IC_DM8098/IC_DM8098.kicad_sch new file mode 100644 index 000000000..5aee50533 --- /dev/null +++ b/library/SubcircuitLibrary/IC_DM8098/IC_DM8098.kicad_sch @@ -0,0 +1,1468 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 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(reference "U1") (unit 6) (value "PORT") (footprint "") + ) + (path "/6744acd4-f5d2-4d47-8654-1b2e8cd642b7" + (reference "U1") (unit 7) (value "PORT") (footprint "") + ) + (path "/1def826d-8b6f-44a0-853d-92d07529ed38" + (reference "U1") (unit 8) (value "PORT") (footprint "") + ) + (path "/5172c06a-e330-4085-b9c6-e47cf8eca348" + (reference "U1") (unit 9) (value "PORT") (footprint "") + ) + (path "/6e517092-b7e7-40dc-a418-f5bb163e5650" + (reference "U1") (unit 10) (value "PORT") (footprint "") + ) + (path "/fb8affbb-4e52-474b-9e8e-c15fd569aca9" + (reference "U1") (unit 11) (value "PORT") (footprint "") + ) + (path "/163e7587-c7a8-433e-9d43-5c9cb26ac0d4" + (reference "U1") (unit 12) (value "PORT") (footprint "") + ) + (path "/23756e76-3140-41dd-8773-166ece38daa8" + (reference "U1") (unit 13) (value "PORT") (footprint "") + ) + (path "/ba3b54b8-72c3-42e5-85d8-adc118ac2fe0" + (reference "U1") (unit 14) (value "PORT") (footprint "") + ) + (path "/5c418a1c-a626-4065-98a6-7f66813e10b3" + (reference "U2") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/e4d8ed5a-b8ab-4943-ab06-729be7787da9" + (reference "U3") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/e22c47f2-c019-4319-a2e5-2f809e5d8ea5" + (reference "U4") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/612f4d8c-9964-4535-917b-bc79e77a8d36" + (reference "U5") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/500ebb22-2f4e-4bb8-8019-022862fe33b3" + (reference "U6") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/8c83ddc9-17f2-406f-a554-121ee37c2610" + (reference "U7") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/20ee6bde-6aa7-43b8-970c-2c839f6758c8" + (reference "U8") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/265b7926-ab07-4343-a386-9881898f9c09" + (reference "U9") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/27d64c43-2cd5-45c7-b1fa-7c1328fabed4" + (reference "U10") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/237a6073-fe1c-45c0-a11b-58ddb02b9169" + (reference "U11") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/618d93fc-e358-42ca-94e1-6ea6255d8022" + (reference "U12") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/ee9d0187-f5b7-4f33-b888-a83f3b2092e3" + (reference "U13") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/48816861-d9d1-470d-ad30-be339ccd0778" + (reference "U14") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/ddc9efa8-ac21-4f9a-8c3d-1552705c3eda" + (reference "U15") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/a1b46a3b-1e07-4a0d-814a-a9961edb2e20" + (reference "U16") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/a5805c2a-66f0-40fa-a133-7cd5be9efd68" + (reference "U17") (unit 1) (value "d_inverter") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/IC_DM8098/IC_DM8098.sub b/library/SubcircuitLibrary/IC_DM8098/IC_DM8098.sub new file mode 100644 index 000000000..44a3e35f3 --- /dev/null +++ b/library/SubcircuitLibrary/IC_DM8098/IC_DM8098.sub @@ -0,0 +1,70 @@ +* Subcircuit IC_DM8098 +.subckt IC_DM8098 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u17-pad2_ net-_u16-pad2_ net-_u15-pad2_ net-_u14-pad2_ net-_u13-pad2_ net-_u12-pad2_ +.title kicad schematic +* u9 net-_u1-pad4_ net-_u4-pad2_ net-_u15-pad1_ d_tristate +* u10 net-_u1-pad5_ net-_u10-pad2_ net-_u10-pad3_ d_tristate +* u11 net-_u1-pad6_ net-_u10-pad2_ net-_u11-pad3_ d_tristate +* u3 net-_u1-pad8_ net-_u3-pad2_ d_inverter +* u2 net-_u1-pad7_ net-_u2-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u17 net-_u11-pad3_ net-_u17-pad2_ d_inverter +* u16 net-_u10-pad3_ net-_u16-pad2_ d_inverter +* u4 net-_u2-pad2_ net-_u4-pad2_ d_buffer +* u5 net-_u3-pad2_ net-_u10-pad2_ d_buffer +* u8 net-_u1-pad3_ net-_u4-pad2_ net-_u14-pad1_ d_tristate +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u6 net-_u1-pad1_ net-_u4-pad2_ net-_u12-pad1_ d_tristate +* u7 net-_u1-pad2_ net-_u4-pad2_ net-_u13-pad1_ d_tristate +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +a1 net-_u1-pad4_ net-_u4-pad2_ net-_u15-pad1_ u9 +a2 net-_u1-pad5_ net-_u10-pad2_ net-_u10-pad3_ u10 +a3 net-_u1-pad6_ net-_u10-pad2_ net-_u11-pad3_ u11 +a4 net-_u1-pad8_ net-_u3-pad2_ u3 +a5 net-_u1-pad7_ net-_u2-pad2_ u2 +a6 net-_u15-pad1_ net-_u15-pad2_ u15 +a7 net-_u11-pad3_ net-_u17-pad2_ u17 +a8 net-_u10-pad3_ net-_u16-pad2_ u16 +a9 net-_u2-pad2_ net-_u4-pad2_ u4 +a10 net-_u3-pad2_ net-_u10-pad2_ u5 +a11 net-_u1-pad3_ net-_u4-pad2_ net-_u14-pad1_ u8 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u12-pad1_ net-_u12-pad2_ u12 +a14 net-_u1-pad1_ net-_u4-pad2_ net-_u12-pad1_ u6 +a15 net-_u1-pad2_ net-_u4-pad2_ net-_u13-pad1_ u7 +a16 net-_u14-pad1_ net-_u14-pad2_ u14 +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u7 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends IC_DM8098 \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_DM8098/IC_DM8098_Previous_Values.xml b/library/SubcircuitLibrary/IC_DM8098/IC_DM8098_Previous_Values.xml new file mode 100644 index 000000000..ccac1fe53 --- /dev/null +++ b/library/SubcircuitLibrary/IC_DM8098/IC_DM8098_Previous_Values.xml @@ -0,0 +1 @@ +d_tristated_tristated_inverterd_tristated_inverterd_inverterd_inverterd_inverterd_bufferd_bufferd_tristated_inverterd_inverterd_tristated_tristated_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_DM8098/analysis b/library/SubcircuitLibrary/IC_DM8098/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/IC_DM8098/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From f45ac27634f737b51a62967bc8e8c5167c0a627f Mon Sep 17 00:00:00 2001 From: Santhosh C Date: Mon, 8 Jun 2026 13:42:06 +0530 Subject: [PATCH 05/10] Add subckt and simulation files for IC_GD74HCT58 --- .../IC_GD74HCT58/IC_GD74HCT58.cir | 17 + .../IC_GD74HCT58/IC_GD74HCT58.cir.out | 68 + .../IC_GD74HCT58/IC_GD74HCT58.kicad_sch | 1306 +++++++++++++++++ .../IC_GD74HCT58/IC_GD74HCT58.sub | 62 + .../IC_GD74HCT58_Previous_Values.xml | 1 + .../SubcircuitLibrary/IC_GD74HCT58/analysis | 1 + 6 files changed, 1455 insertions(+) create mode 100644 library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.cir create mode 100644 library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.cir.out create mode 100644 library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.kicad_sch create mode 100644 library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.sub create mode 100644 library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/IC_GD74HCT58/analysis diff --git a/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.cir b/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.cir new file mode 100644 index 000000000..784deb4cb --- /dev/null +++ b/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.cir @@ -0,0 +1,17 @@ +.title KiCad schematic +U8 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U11-Pad1_ d_nand +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U12 Net-_U11-Pad2_ Net-_U1-Pad12_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT +U10 Net-_U10-Pad1_ Net-_U1-Pad10_ Net-_U10-Pad3_ d_nand +U9 Net-_U6-Pad3_ Net-_U1-Pad7_ Net-_U13-Pad1_ d_nand +U13 Net-_U13-Pad1_ Net-_U10-Pad3_ Net-_U13-Pad3_ d_nand +U15 Net-_U14-Pad2_ Net-_U1-Pad11_ d_inverter +U14 Net-_U13-Pad3_ Net-_U14-Pad2_ d_inverter +U4 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U4-Pad3_ d_nand +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_nand +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_nand +U5 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U5-Pad3_ d_nand +U7 Net-_U5-Pad3_ Net-_U5-Pad3_ Net-_U10-Pad1_ d_nand +U6 Net-_U4-Pad3_ Net-_U4-Pad3_ Net-_U6-Pad3_ d_nand +.end diff --git a/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.cir.out b/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.cir.out new file mode 100644 index 000000000..d8ed6626f --- /dev/null +++ b/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.cir.out @@ -0,0 +1,68 @@ +.title kicad schematic + +* u8 net-_u2-pad3_ net-_u3-pad3_ net-_u11-pad1_ d_nand +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u11-pad2_ net-_u1-pad12_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port +* u10 net-_u10-pad1_ net-_u1-pad10_ net-_u10-pad3_ d_nand +* u9 net-_u6-pad3_ net-_u1-pad7_ net-_u13-pad1_ d_nand +* u13 net-_u13-pad1_ net-_u10-pad3_ net-_u13-pad3_ d_nand +* u15 net-_u14-pad2_ net-_u1-pad11_ d_inverter +* u14 net-_u13-pad3_ net-_u14-pad2_ d_inverter +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_nand +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u5 net-_u1-pad8_ net-_u1-pad9_ net-_u5-pad3_ d_nand +* u7 net-_u5-pad3_ net-_u5-pad3_ net-_u10-pad1_ d_nand +* u6 net-_u4-pad3_ net-_u4-pad3_ net-_u6-pad3_ d_nand +a1 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u11-pad1_ u8 +a2 net-_u11-pad1_ net-_u11-pad2_ u11 +a3 net-_u11-pad2_ net-_u1-pad12_ u12 +a4 [net-_u10-pad1_ net-_u1-pad10_ ] net-_u10-pad3_ u10 +a5 [net-_u6-pad3_ net-_u1-pad7_ ] net-_u13-pad1_ u9 +a6 [net-_u13-pad1_ net-_u10-pad3_ ] net-_u13-pad3_ u13 +a7 net-_u14-pad2_ net-_u1-pad11_ u15 +a8 net-_u13-pad3_ net-_u14-pad2_ u14 +a9 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a10 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a11 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a12 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u5-pad3_ u5 +a13 [net-_u5-pad3_ net-_u5-pad3_ ] net-_u10-pad1_ u7 +a14 [net-_u4-pad3_ net-_u4-pad3_ ] net-_u6-pad3_ u6 +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.kicad_sch b/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.kicad_sch new file mode 100644 index 000000000..da57e1739 --- /dev/null +++ b/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.kicad_sch @@ -0,0 +1,1306 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 8044377d-c70c-461a-9baa-ee2bc77147aa) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Digital:d_inverter" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 -2.54 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_inverter" (id 1) (at 0 3.81 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 1.27 -1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 1.27 -1.27 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "d_inverter_0_1" + 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(footprint "") + ) + (path "/497583ba-2f42-445b-a4f7-655e81e1f743" + (reference "U14") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/cdfc4a5a-8c72-4e4d-906d-6b343a7cdb93" + (reference "U15") (unit 1) (value "d_inverter") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.sub b/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.sub new file mode 100644 index 000000000..45655333c --- /dev/null +++ b/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58.sub @@ -0,0 +1,62 @@ +* Subcircuit IC_GD74HCT58 +.subckt IC_GD74HCT58 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ +.title kicad schematic +* u8 net-_u2-pad3_ net-_u3-pad3_ net-_u11-pad1_ d_nand +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u11-pad2_ net-_u1-pad12_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad10_ net-_u10-pad3_ d_nand +* u9 net-_u6-pad3_ net-_u1-pad7_ net-_u13-pad1_ d_nand +* u13 net-_u13-pad1_ net-_u10-pad3_ net-_u13-pad3_ d_nand +* u15 net-_u14-pad2_ net-_u1-pad11_ d_inverter +* u14 net-_u13-pad3_ net-_u14-pad2_ d_inverter +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_nand +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u5 net-_u1-pad8_ net-_u1-pad9_ net-_u5-pad3_ d_nand +* u7 net-_u5-pad3_ net-_u5-pad3_ net-_u10-pad1_ d_nand +* u6 net-_u4-pad3_ net-_u4-pad3_ net-_u6-pad3_ d_nand +a1 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u11-pad1_ u8 +a2 net-_u11-pad1_ net-_u11-pad2_ u11 +a3 net-_u11-pad2_ net-_u1-pad12_ u12 +a4 [net-_u10-pad1_ net-_u1-pad10_ ] net-_u10-pad3_ u10 +a5 [net-_u6-pad3_ net-_u1-pad7_ ] net-_u13-pad1_ u9 +a6 [net-_u13-pad1_ net-_u10-pad3_ ] net-_u13-pad3_ u13 +a7 net-_u14-pad2_ net-_u1-pad11_ u15 +a8 net-_u13-pad3_ net-_u14-pad2_ u14 +a9 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a10 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a11 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a12 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u5-pad3_ u5 +a13 [net-_u5-pad3_ net-_u5-pad3_ ] net-_u10-pad1_ u7 +a14 [net-_u4-pad3_ net-_u4-pad3_ ] net-_u6-pad3_ u6 +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends IC_GD74HCT58 \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58_Previous_Values.xml b/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58_Previous_Values.xml new file mode 100644 index 000000000..f492aa5ca --- /dev/null +++ b/library/SubcircuitLibrary/IC_GD74HCT58/IC_GD74HCT58_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_inverterd_inverterd_nandd_nandd_nandd_inverterd_inverterd_nandd_nandd_nandd_nandd_nandd_nand \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_GD74HCT58/analysis b/library/SubcircuitLibrary/IC_GD74HCT58/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/IC_GD74HCT58/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From 3cb63ac468caef8e4f3457dd5477b1a290aaeca7 Mon Sep 17 00:00:00 2001 From: Santhosh C Date: Mon, 8 Jun 2026 13:42:37 +0530 Subject: [PATCH 06/10] Add subckt and simulation files for IC_M74HC4024 --- .../IC_M74HC4024/IC_M74HC4024.cir | 35 + .../IC_M74HC4024/IC_M74HC4024.cir.out | 140 ++ .../IC_M74HC4024/IC_M74HC4024.kicad_sch | 1878 +++++++++++++++++ .../IC_M74HC4024/IC_M74HC4024.sub | 134 ++ .../IC_M74HC4024_Previous_Values.xml | 1 + .../SubcircuitLibrary/IC_M74HC4024/analysis | 1 + 6 files changed, 2189 insertions(+) create mode 100644 library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.cir create mode 100644 library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.cir.out create mode 100644 library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.kicad_sch create mode 100644 library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.sub create mode 100644 library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/IC_M74HC4024/analysis diff --git a/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.cir b/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.cir new file mode 100644 index 000000000..0bfea073b --- /dev/null +++ b/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.cir @@ -0,0 +1,35 @@ +.title KiCad schematic +U27 Net-_U27-Pad1_ Net-_U1-Pad4_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT +U28 Net-_U28-Pad1_ Net-_U27-Pad1_ d_inverter +U29 Net-_U26-Pad1_ Net-_U28-Pad1_ d_inverter +U33 Net-_U30-Pad1_ Net-_U32-Pad1_ d_inverter +U32 Net-_U32-Pad1_ Net-_U31-Pad1_ d_inverter +U30 Net-_U30-Pad1_ Net-_U26-Pad1_ unconnected-_U30-Pad3_ Net-_U10-Pad4_ unconnected-_U30-Pad5_ Net-_U30-Pad1_ d_dff +U31 Net-_U31-Pad1_ Net-_U1-Pad3_ d_inverter +U16 Net-_U16-Pad1_ Net-_U15-Pad1_ d_inverter +U15 Net-_U15-Pad1_ Net-_U1-Pad7_ d_inverter +U11 Net-_U11-Pad1_ Net-_U1-Pad8_ d_inverter +U12 Net-_U12-Pad1_ Net-_U11-Pad1_ d_inverter +U18 Net-_U18-Pad1_ Net-_U14-Pad1_ unconnected-_U18-Pad3_ Net-_U10-Pad4_ unconnected-_U18-Pad5_ Net-_U18-Pad1_ d_dff +U17 Net-_U14-Pad1_ Net-_U16-Pad1_ d_inverter +U13 Net-_U10-Pad1_ Net-_U12-Pad1_ d_inverter +U6 Net-_U10-Pad2_ Net-_U4-Pad2_ unconnected-_U6-Pad3_ Net-_U10-Pad4_ unconnected-_U6-Pad5_ Net-_U10-Pad2_ d_dff +U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter +U3 Net-_U2-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad1_ Net-_U4-Pad2_ d_inverter +U5 Net-_U3-Pad2_ Net-_U10-Pad4_ d_buffer +U21 Net-_U18-Pad1_ Net-_U20-Pad1_ d_inverter +U26 Net-_U26-Pad1_ Net-_U22-Pad1_ unconnected-_U26-Pad3_ Net-_U10-Pad4_ unconnected-_U26-Pad5_ Net-_U26-Pad1_ d_dff +U19 Net-_U19-Pad1_ Net-_U1-Pad6_ d_inverter +U20 Net-_U20-Pad1_ Net-_U19-Pad1_ d_inverter +U22 Net-_U22-Pad1_ Net-_U18-Pad1_ unconnected-_U22-Pad3_ Net-_U10-Pad4_ unconnected-_U22-Pad5_ Net-_U22-Pad1_ d_dff +U23 Net-_U23-Pad1_ Net-_U1-Pad5_ d_inverter +U25 Net-_U22-Pad1_ Net-_U24-Pad1_ d_inverter +U24 Net-_U24-Pad1_ Net-_U23-Pad1_ d_inverter +U14 Net-_U14-Pad1_ Net-_U10-Pad1_ unconnected-_U14-Pad3_ Net-_U10-Pad4_ unconnected-_U14-Pad5_ Net-_U14-Pad1_ d_dff +U7 Net-_U7-Pad1_ Net-_U1-Pad9_ d_inverter +U8 Net-_U8-Pad1_ Net-_U7-Pad1_ d_inverter +U9 Net-_U10-Pad2_ Net-_U8-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ unconnected-_U10-Pad3_ Net-_U10-Pad4_ unconnected-_U10-Pad5_ Net-_U10-Pad1_ d_dff +.end diff --git a/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.cir.out b/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.cir.out new file mode 100644 index 000000000..586c499ca --- /dev/null +++ b/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.cir.out @@ -0,0 +1,140 @@ +.title kicad schematic + +* u27 net-_u27-pad1_ net-_u1-pad4_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port +* u28 net-_u28-pad1_ net-_u27-pad1_ d_inverter +* u29 net-_u26-pad1_ net-_u28-pad1_ d_inverter +* u33 net-_u30-pad1_ net-_u32-pad1_ d_inverter +* u32 net-_u32-pad1_ net-_u31-pad1_ d_inverter +* u30 net-_u30-pad1_ net-_u26-pad1_ unconnected-_u30-pad3_ net-_u10-pad4_ unconnected-_u30-pad5_ net-_u30-pad1_ d_dff +* u31 net-_u31-pad1_ net-_u1-pad3_ d_inverter +* u16 net-_u16-pad1_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u1-pad7_ d_inverter +* u11 net-_u11-pad1_ net-_u1-pad8_ d_inverter +* u12 net-_u12-pad1_ net-_u11-pad1_ d_inverter +* u18 net-_u18-pad1_ net-_u14-pad1_ unconnected-_u18-pad3_ net-_u10-pad4_ unconnected-_u18-pad5_ net-_u18-pad1_ d_dff +* u17 net-_u14-pad1_ net-_u16-pad1_ d_inverter +* u13 net-_u10-pad1_ net-_u12-pad1_ d_inverter +* u6 net-_u10-pad2_ net-_u4-pad2_ unconnected-_u6-pad3_ net-_u10-pad4_ unconnected-_u6-pad5_ net-_u10-pad2_ d_dff +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad1_ net-_u4-pad2_ d_inverter +* u5 net-_u3-pad2_ net-_u10-pad4_ d_buffer +* u21 net-_u18-pad1_ net-_u20-pad1_ d_inverter +* u26 net-_u26-pad1_ net-_u22-pad1_ unconnected-_u26-pad3_ net-_u10-pad4_ unconnected-_u26-pad5_ net-_u26-pad1_ d_dff +* u19 net-_u19-pad1_ net-_u1-pad6_ d_inverter +* u20 net-_u20-pad1_ net-_u19-pad1_ d_inverter +* u22 net-_u22-pad1_ net-_u18-pad1_ unconnected-_u22-pad3_ net-_u10-pad4_ unconnected-_u22-pad5_ net-_u22-pad1_ d_dff +* u23 net-_u23-pad1_ net-_u1-pad5_ d_inverter +* u25 net-_u22-pad1_ net-_u24-pad1_ d_inverter +* u24 net-_u24-pad1_ net-_u23-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u10-pad1_ unconnected-_u14-pad3_ net-_u10-pad4_ unconnected-_u14-pad5_ net-_u14-pad1_ d_dff +* u7 net-_u7-pad1_ net-_u1-pad9_ d_inverter +* u8 net-_u8-pad1_ net-_u7-pad1_ d_inverter +* u9 net-_u10-pad2_ net-_u8-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ unconnected-_u10-pad3_ net-_u10-pad4_ unconnected-_u10-pad5_ net-_u10-pad1_ d_dff +a1 net-_u27-pad1_ net-_u1-pad4_ u27 +a2 net-_u28-pad1_ net-_u27-pad1_ u28 +a3 net-_u26-pad1_ net-_u28-pad1_ u29 +a4 net-_u30-pad1_ net-_u32-pad1_ u33 +a5 net-_u32-pad1_ net-_u31-pad1_ u32 +a6 net-_u30-pad1_ net-_u26-pad1_ unconnected-_u30-pad3_ net-_u10-pad4_ unconnected-_u30-pad5_ net-_u30-pad1_ u30 +a7 net-_u31-pad1_ net-_u1-pad3_ u31 +a8 net-_u16-pad1_ net-_u15-pad1_ u16 +a9 net-_u15-pad1_ net-_u1-pad7_ u15 +a10 net-_u11-pad1_ net-_u1-pad8_ u11 +a11 net-_u12-pad1_ net-_u11-pad1_ u12 +a12 net-_u18-pad1_ net-_u14-pad1_ unconnected-_u18-pad3_ net-_u10-pad4_ unconnected-_u18-pad5_ net-_u18-pad1_ u18 +a13 net-_u14-pad1_ net-_u16-pad1_ u17 +a14 net-_u10-pad1_ net-_u12-pad1_ u13 +a15 net-_u10-pad2_ net-_u4-pad2_ unconnected-_u6-pad3_ net-_u10-pad4_ unconnected-_u6-pad5_ net-_u10-pad2_ u6 +a16 net-_u1-pad2_ net-_u2-pad2_ u2 +a17 net-_u2-pad2_ net-_u3-pad2_ u3 +a18 net-_u1-pad1_ net-_u4-pad2_ u4 +a19 net-_u3-pad2_ net-_u10-pad4_ u5 +a20 net-_u18-pad1_ net-_u20-pad1_ u21 +a21 net-_u26-pad1_ net-_u22-pad1_ unconnected-_u26-pad3_ net-_u10-pad4_ unconnected-_u26-pad5_ net-_u26-pad1_ u26 +a22 net-_u19-pad1_ net-_u1-pad6_ u19 +a23 net-_u20-pad1_ net-_u19-pad1_ u20 +a24 net-_u22-pad1_ net-_u18-pad1_ unconnected-_u22-pad3_ net-_u10-pad4_ unconnected-_u22-pad5_ net-_u22-pad1_ u22 +a25 net-_u23-pad1_ net-_u1-pad5_ u23 +a26 net-_u22-pad1_ net-_u24-pad1_ u25 +a27 net-_u24-pad1_ net-_u23-pad1_ u24 +a28 net-_u14-pad1_ net-_u10-pad1_ unconnected-_u14-pad3_ net-_u10-pad4_ unconnected-_u14-pad5_ net-_u14-pad1_ u14 +a29 net-_u7-pad1_ net-_u1-pad9_ u7 +a30 net-_u8-pad1_ net-_u7-pad1_ u8 +a31 net-_u10-pad2_ net-_u8-pad1_ u9 +a32 net-_u10-pad1_ net-_u10-pad2_ unconnected-_u10-pad3_ net-_u10-pad4_ unconnected-_u10-pad5_ net-_u10-pad1_ u10 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u18 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u26 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u14 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u10 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.kicad_sch b/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.kicad_sch new file mode 100644 index 000000000..0c09909ce --- /dev/null +++ b/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.kicad_sch @@ -0,0 +1,1878 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(reference "U10") (unit 1) (value "d_dff") (footprint "") + ) + (path "/e6eb5793-3cd7-4f64-b18c-7e21ed577271" + (reference "U11") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/008713dd-244c-4402-8fa2-d4181a229458" + (reference "U12") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/d2b8d928-a047-4a63-8036-384ceb700e96" + (reference "U13") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/de985354-52d3-411d-94f1-09651ae60984" + (reference "U14") (unit 1) (value "d_dff") (footprint "") + ) + (path "/84997399-8f9c-4f01-b4e2-af7a8753dcaa" + (reference "U15") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/d1d62ab1-d8df-402a-a344-28c28958c221" + (reference "U16") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/bc9254be-acc5-4baa-8bf6-e3091ef0badd" + (reference "U17") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/335ac0ae-12d0-48de-b9dc-d909bd7a8647" + (reference "U18") (unit 1) (value "d_dff") (footprint "") + ) + (path "/a3ebb5ea-2325-4e9e-8684-4a711dcce742" + (reference "U19") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/50d3418f-1c52-4e8a-9bd2-f3d3c1fb7107" + (reference "U20") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/7e105f36-a34a-442b-b062-b0563f54327b" + (reference "U21") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/de186ecd-0811-40ea-9111-20920474e80d" + (reference "U22") (unit 1) (value "d_dff") (footprint "") + ) + (path "/15c220c1-2cb3-40a0-9da2-67092ce70efc" + (reference "U23") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/f10d6dfd-8f38-4889-9598-a4b906d01cf2" + (reference "U24") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/299eb4a2-c2ae-4224-a16e-7606d0a9e6d6" + (reference "U25") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/93874c57-2342-4792-b022-92b63a6ffaac" + (reference "U26") (unit 1) (value "d_dff") (footprint "") + ) + (path "/4b841f68-dbcb-442f-9231-c74b5cc34a75" + (reference "U27") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/f18d366a-822f-4b1e-ab69-9651a07f6742" + (reference "U28") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/96eb17d0-eaa1-4039-9e61-2bf26cc48faa" + (reference "U29") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/666f092b-54ad-4503-a38d-88f84433e168" + (reference "U30") (unit 1) (value "d_dff") (footprint "") + ) + (path "/5c9a359e-e8dc-4226-83ae-343527f7b670" + (reference "U31") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/2107e224-1f9a-4dce-a73d-b929e67da692" + (reference "U32") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/8f983226-8415-459b-a4f0-883c2c0bf47d" + (reference "U33") (unit 1) (value "d_inverter") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.sub b/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.sub new file mode 100644 index 000000000..31d876639 --- /dev/null +++ b/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024.sub @@ -0,0 +1,134 @@ +* Subcircuit IC_M74HC4024 +.subckt IC_M74HC4024 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ +.title kicad schematic +* u27 net-_u27-pad1_ net-_u1-pad4_ d_inverter +* u28 net-_u28-pad1_ net-_u27-pad1_ d_inverter +* u29 net-_u26-pad1_ net-_u28-pad1_ d_inverter +* u33 net-_u30-pad1_ net-_u32-pad1_ d_inverter +* u32 net-_u32-pad1_ net-_u31-pad1_ d_inverter +* u30 net-_u30-pad1_ net-_u26-pad1_ unconnected-_u30-pad3_ net-_u10-pad4_ unconnected-_u30-pad5_ net-_u30-pad1_ d_dff +* u31 net-_u31-pad1_ net-_u1-pad3_ d_inverter +* u16 net-_u16-pad1_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u1-pad7_ d_inverter +* u11 net-_u11-pad1_ net-_u1-pad8_ d_inverter +* u12 net-_u12-pad1_ net-_u11-pad1_ d_inverter +* u18 net-_u18-pad1_ net-_u14-pad1_ unconnected-_u18-pad3_ net-_u10-pad4_ unconnected-_u18-pad5_ net-_u18-pad1_ d_dff +* u17 net-_u14-pad1_ net-_u16-pad1_ d_inverter +* u13 net-_u10-pad1_ net-_u12-pad1_ d_inverter +* u6 net-_u10-pad2_ net-_u4-pad2_ unconnected-_u6-pad3_ net-_u10-pad4_ unconnected-_u6-pad5_ net-_u10-pad2_ d_dff +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad1_ net-_u4-pad2_ d_inverter +* u5 net-_u3-pad2_ net-_u10-pad4_ d_buffer +* u21 net-_u18-pad1_ net-_u20-pad1_ d_inverter +* u26 net-_u26-pad1_ net-_u22-pad1_ unconnected-_u26-pad3_ net-_u10-pad4_ unconnected-_u26-pad5_ net-_u26-pad1_ d_dff +* u19 net-_u19-pad1_ net-_u1-pad6_ d_inverter +* u20 net-_u20-pad1_ net-_u19-pad1_ d_inverter +* u22 net-_u22-pad1_ net-_u18-pad1_ unconnected-_u22-pad3_ net-_u10-pad4_ unconnected-_u22-pad5_ net-_u22-pad1_ d_dff +* u23 net-_u23-pad1_ net-_u1-pad5_ d_inverter +* u25 net-_u22-pad1_ net-_u24-pad1_ d_inverter +* u24 net-_u24-pad1_ net-_u23-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u10-pad1_ unconnected-_u14-pad3_ net-_u10-pad4_ unconnected-_u14-pad5_ net-_u14-pad1_ d_dff +* u7 net-_u7-pad1_ net-_u1-pad9_ d_inverter +* u8 net-_u8-pad1_ net-_u7-pad1_ d_inverter +* u9 net-_u10-pad2_ net-_u8-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ unconnected-_u10-pad3_ net-_u10-pad4_ unconnected-_u10-pad5_ net-_u10-pad1_ d_dff +a1 net-_u27-pad1_ net-_u1-pad4_ u27 +a2 net-_u28-pad1_ net-_u27-pad1_ u28 +a3 net-_u26-pad1_ net-_u28-pad1_ u29 +a4 net-_u30-pad1_ net-_u32-pad1_ u33 +a5 net-_u32-pad1_ net-_u31-pad1_ u32 +a6 net-_u30-pad1_ net-_u26-pad1_ unconnected-_u30-pad3_ net-_u10-pad4_ unconnected-_u30-pad5_ net-_u30-pad1_ u30 +a7 net-_u31-pad1_ net-_u1-pad3_ u31 +a8 net-_u16-pad1_ net-_u15-pad1_ u16 +a9 net-_u15-pad1_ net-_u1-pad7_ u15 +a10 net-_u11-pad1_ net-_u1-pad8_ u11 +a11 net-_u12-pad1_ net-_u11-pad1_ u12 +a12 net-_u18-pad1_ net-_u14-pad1_ unconnected-_u18-pad3_ net-_u10-pad4_ unconnected-_u18-pad5_ net-_u18-pad1_ u18 +a13 net-_u14-pad1_ net-_u16-pad1_ u17 +a14 net-_u10-pad1_ net-_u12-pad1_ u13 +a15 net-_u10-pad2_ net-_u4-pad2_ unconnected-_u6-pad3_ net-_u10-pad4_ unconnected-_u6-pad5_ net-_u10-pad2_ u6 +a16 net-_u1-pad2_ net-_u2-pad2_ u2 +a17 net-_u2-pad2_ net-_u3-pad2_ u3 +a18 net-_u1-pad1_ net-_u4-pad2_ u4 +a19 net-_u3-pad2_ net-_u10-pad4_ u5 +a20 net-_u18-pad1_ net-_u20-pad1_ u21 +a21 net-_u26-pad1_ net-_u22-pad1_ unconnected-_u26-pad3_ net-_u10-pad4_ unconnected-_u26-pad5_ net-_u26-pad1_ u26 +a22 net-_u19-pad1_ net-_u1-pad6_ u19 +a23 net-_u20-pad1_ net-_u19-pad1_ u20 +a24 net-_u22-pad1_ net-_u18-pad1_ unconnected-_u22-pad3_ net-_u10-pad4_ unconnected-_u22-pad5_ net-_u22-pad1_ u22 +a25 net-_u23-pad1_ net-_u1-pad5_ u23 +a26 net-_u22-pad1_ net-_u24-pad1_ u25 +a27 net-_u24-pad1_ net-_u23-pad1_ u24 +a28 net-_u14-pad1_ net-_u10-pad1_ unconnected-_u14-pad3_ net-_u10-pad4_ unconnected-_u14-pad5_ net-_u14-pad1_ u14 +a29 net-_u7-pad1_ net-_u1-pad9_ u7 +a30 net-_u8-pad1_ net-_u7-pad1_ u8 +a31 net-_u10-pad2_ net-_u8-pad1_ u9 +a32 net-_u10-pad1_ net-_u10-pad2_ unconnected-_u10-pad3_ net-_u10-pad4_ unconnected-_u10-pad5_ net-_u10-pad1_ u10 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u18 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u26 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u14 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u10 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends IC_M74HC4024 \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024_Previous_Values.xml b/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024_Previous_Values.xml new file mode 100644 index 000000000..5607735d6 --- /dev/null +++ b/library/SubcircuitLibrary/IC_M74HC4024/IC_M74HC4024_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterd_inverterd_inverterd_inverterd_dffd_inverterd_inverterd_inverterd_inverterd_inverterd_dffd_inverterd_inverterd_dffd_inverterd_inverterd_inverterd_bufferd_inverterd_dffd_inverterd_inverterd_dffd_inverterd_inverterd_inverterd_dffd_inverterd_inverterd_inverterd_dff \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_M74HC4024/analysis b/library/SubcircuitLibrary/IC_M74HC4024/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/IC_M74HC4024/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From 40c6f2c0c3cc0c86a3c90acfb6d64aa690b45d9f Mon Sep 17 00:00:00 2001 From: Santhosh C Date: Mon, 8 Jun 2026 13:42:57 +0530 Subject: [PATCH 07/10] Add subckt and simulation files for IC_MC10E155 --- .../IC_MC10E155/IC_MC10E155.cir | 36 + .../IC_MC10E155/IC_MC10E155.cir.out | 144 + .../IC_MC10E155/IC_MC10E155.kicad_sch | 2839 +++++++++++++++++ .../IC_MC10E155/IC_MC10E155.sub | 138 + .../IC_MC10E155_Previous_Values.xml | 1 + .../SubcircuitLibrary/IC_MC10E155/analysis | 1 + 6 files changed, 3159 insertions(+) create mode 100644 library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.cir create mode 100644 library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.cir.out create mode 100644 library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.kicad_sch create mode 100644 library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.sub create mode 100644 library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/IC_MC10E155/analysis diff --git a/library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.cir b/library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.cir new file mode 100644 index 000000000..564968afc --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.cir @@ -0,0 +1,36 @@ +.title KiCad schematic +U27 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U27-Pad3_ d_or +U33 Net-_U27-Pad3_ Net-_U29-Pad2_ unconnected-_U33-Pad3_ Net-_U29-Pad4_ Net-_U1-Pad18_ unconnected-_U33-Pad6_ d_dlatch +U32 Net-_U26-Pad3_ Net-_U29-Pad2_ unconnected-_U32-Pad3_ Net-_U29-Pad4_ Net-_U1-Pad19_ unconnected-_U32-Pad6_ d_dlatch +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ PORT +U26 Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U26-Pad3_ d_or +U18 Net-_U1-Pad8_ Net-_U10-Pad1_ Net-_U18-Pad3_ d_and +U20 Net-_U1-Pad10_ Net-_U10-Pad1_ Net-_U20-Pad3_ d_and +U19 Net-_U1-Pad9_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_and +U8 Net-_U10-Pad1_ Net-_U17-Pad2_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U4 Net-_U1-Pad14_ Net-_U29-Pad4_ d_buffer +U3 Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U29-Pad2_ d_or +U2 Net-_U1-Pad13_ Net-_U10-Pad1_ d_buffer +U21 Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U21-Pad3_ d_and +U22 Net-_U1-Pad12_ Net-_U10-Pad1_ Net-_U22-Pad3_ d_and +U9 Net-_U10-Pad1_ Net-_U19-Pad2_ d_inverter +U28 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U28-Pad3_ d_or +U34 Net-_U28-Pad3_ Net-_U29-Pad2_ unconnected-_U34-Pad3_ Net-_U29-Pad4_ Net-_U1-Pad17_ unconnected-_U34-Pad6_ d_dlatch +U16 Net-_U1-Pad6_ Net-_U10-Pad1_ Net-_U16-Pad3_ d_and +U15 Net-_U1-Pad5_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and +U17 Net-_U1-Pad7_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and +U7 Net-_U10-Pad1_ Net-_U15-Pad2_ d_inverter +U29 Net-_U23-Pad3_ Net-_U29-Pad2_ unconnected-_U29-Pad3_ Net-_U29-Pad4_ Net-_U1-Pad22_ unconnected-_U29-Pad6_ d_dlatch +U30 Net-_U24-Pad3_ Net-_U29-Pad2_ unconnected-_U30-Pad3_ Net-_U29-Pad4_ Net-_U1-Pad21_ unconnected-_U30-Pad6_ d_dlatch +U31 Net-_U25-Pad3_ Net-_U29-Pad2_ unconnected-_U31-Pad3_ Net-_U29-Pad4_ Net-_U1-Pad20_ unconnected-_U31-Pad6_ d_dlatch +U25 Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U25-Pad3_ d_or +U24 Net-_U13-Pad3_ Net-_U14-Pad3_ Net-_U24-Pad3_ d_or +U23 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U23-Pad3_ d_or +U6 Net-_U10-Pad1_ Net-_U13-Pad2_ d_inverter +U5 Net-_U10-Pad1_ Net-_U11-Pad2_ d_inverter +U12 Net-_U1-Pad2_ Net-_U10-Pad1_ Net-_U12-Pad3_ d_and +U11 Net-_U1-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U13 Net-_U1-Pad3_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U14 Net-_U1-Pad4_ Net-_U10-Pad1_ Net-_U14-Pad3_ d_and +.end diff --git a/library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.cir.out b/library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.cir.out new file mode 100644 index 000000000..ae373a369 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.cir.out @@ -0,0 +1,144 @@ +.title kicad schematic + +* u27 net-_u19-pad3_ net-_u20-pad3_ net-_u27-pad3_ d_or +* u33 net-_u27-pad3_ net-_u29-pad2_ unconnected-_u33-pad3_ net-_u29-pad4_ net-_u1-pad18_ unconnected-_u33-pad6_ d_dlatch +* u32 net-_u26-pad3_ net-_u29-pad2_ unconnected-_u32-pad3_ net-_u29-pad4_ net-_u1-pad19_ unconnected-_u32-pad6_ d_dlatch +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ port +* u26 net-_u17-pad3_ net-_u18-pad3_ net-_u26-pad3_ d_or +* u18 net-_u1-pad8_ net-_u10-pad1_ net-_u18-pad3_ d_and +* u20 net-_u1-pad10_ net-_u10-pad1_ net-_u20-pad3_ d_and +* u19 net-_u1-pad9_ net-_u19-pad2_ net-_u19-pad3_ d_and +* u8 net-_u10-pad1_ net-_u17-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u4 net-_u1-pad14_ net-_u29-pad4_ d_buffer +* u3 net-_u1-pad15_ net-_u1-pad16_ net-_u29-pad2_ d_or +* u2 net-_u1-pad13_ net-_u10-pad1_ d_buffer +* u21 net-_u1-pad11_ net-_u10-pad2_ net-_u21-pad3_ d_and +* u22 net-_u1-pad12_ net-_u10-pad1_ net-_u22-pad3_ d_and +* u9 net-_u10-pad1_ net-_u19-pad2_ d_inverter +* u28 net-_u21-pad3_ net-_u22-pad3_ net-_u28-pad3_ d_or +* u34 net-_u28-pad3_ net-_u29-pad2_ unconnected-_u34-pad3_ net-_u29-pad4_ net-_u1-pad17_ unconnected-_u34-pad6_ d_dlatch +* u16 net-_u1-pad6_ net-_u10-pad1_ net-_u16-pad3_ d_and +* u15 net-_u1-pad5_ net-_u15-pad2_ net-_u15-pad3_ d_and +* u17 net-_u1-pad7_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u7 net-_u10-pad1_ net-_u15-pad2_ d_inverter +* u29 net-_u23-pad3_ net-_u29-pad2_ unconnected-_u29-pad3_ net-_u29-pad4_ net-_u1-pad22_ unconnected-_u29-pad6_ d_dlatch +* u30 net-_u24-pad3_ net-_u29-pad2_ unconnected-_u30-pad3_ net-_u29-pad4_ net-_u1-pad21_ unconnected-_u30-pad6_ d_dlatch +* u31 net-_u25-pad3_ net-_u29-pad2_ unconnected-_u31-pad3_ net-_u29-pad4_ net-_u1-pad20_ unconnected-_u31-pad6_ d_dlatch +* u25 net-_u15-pad3_ net-_u16-pad3_ net-_u25-pad3_ d_or +* u24 net-_u13-pad3_ net-_u14-pad3_ net-_u24-pad3_ d_or +* u23 net-_u11-pad3_ net-_u12-pad3_ net-_u23-pad3_ d_or +* u6 net-_u10-pad1_ net-_u13-pad2_ d_inverter +* u5 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad2_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u11 net-_u1-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u13 net-_u1-pad3_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u14 net-_u1-pad4_ net-_u10-pad1_ net-_u14-pad3_ d_and +a1 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u27-pad3_ u27 +a2 net-_u27-pad3_ net-_u29-pad2_ unconnected-_u33-pad3_ net-_u29-pad4_ net-_u1-pad18_ unconnected-_u33-pad6_ u33 +a3 net-_u26-pad3_ net-_u29-pad2_ unconnected-_u32-pad3_ net-_u29-pad4_ net-_u1-pad19_ unconnected-_u32-pad6_ u32 +a4 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u26-pad3_ u26 +a5 [net-_u1-pad8_ net-_u10-pad1_ ] net-_u18-pad3_ u18 +a6 [net-_u1-pad10_ net-_u10-pad1_ ] net-_u20-pad3_ u20 +a7 [net-_u1-pad9_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a8 net-_u10-pad1_ net-_u17-pad2_ u8 +a9 net-_u10-pad1_ net-_u10-pad2_ u10 +a10 net-_u1-pad14_ net-_u29-pad4_ u4 +a11 [net-_u1-pad15_ net-_u1-pad16_ ] net-_u29-pad2_ u3 +a12 net-_u1-pad13_ net-_u10-pad1_ u2 +a13 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a14 [net-_u1-pad12_ net-_u10-pad1_ ] net-_u22-pad3_ u22 +a15 net-_u10-pad1_ net-_u19-pad2_ u9 +a16 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u28-pad3_ u28 +a17 net-_u28-pad3_ net-_u29-pad2_ unconnected-_u34-pad3_ net-_u29-pad4_ net-_u1-pad17_ unconnected-_u34-pad6_ u34 +a18 [net-_u1-pad6_ net-_u10-pad1_ ] net-_u16-pad3_ u16 +a19 [net-_u1-pad5_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a20 [net-_u1-pad7_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a21 net-_u10-pad1_ net-_u15-pad2_ u7 +a22 net-_u23-pad3_ net-_u29-pad2_ unconnected-_u29-pad3_ net-_u29-pad4_ net-_u1-pad22_ unconnected-_u29-pad6_ u29 +a23 net-_u24-pad3_ net-_u29-pad2_ unconnected-_u30-pad3_ net-_u29-pad4_ net-_u1-pad21_ unconnected-_u30-pad6_ u30 +a24 net-_u25-pad3_ net-_u29-pad2_ unconnected-_u31-pad3_ net-_u29-pad4_ net-_u1-pad20_ unconnected-_u31-pad6_ u31 +a25 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u25-pad3_ u25 +a26 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u24-pad3_ u24 +a27 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u23-pad3_ u23 +a28 net-_u10-pad1_ net-_u13-pad2_ u6 +a29 net-_u10-pad1_ net-_u11-pad2_ u5 +a30 [net-_u1-pad2_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a31 [net-_u1-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a32 [net-_u1-pad3_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a33 [net-_u1-pad4_ net-_u10-pad1_ ] net-_u14-pad3_ u14 +* Schematic Name: d_or, Ngspice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u33 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u32 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u26 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u3 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u34 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u29 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u30 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u31 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u25 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u24 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u23 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git 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(footprint "") + ) + (path "/d986a773-5a74-45d8-98f4-863e8295c349" + (reference "U1") (unit 19) (value "PORT") (footprint "") + ) + (path "/ec84a115-f6a0-46cf-be67-19ff59e8a135" + (reference "U1") (unit 20) (value "PORT") (footprint "") + ) + (path "/72e154b3-efdd-4d5c-9a05-a65ba12f81d5" + (reference "U1") (unit 21) (value "PORT") (footprint "") + ) + (path "/bb75b71c-830d-4bca-9066-548f265d8f88" + (reference "U1") (unit 22) (value "PORT") (footprint "") + ) + (path "/fd642dc9-604d-4f92-94d4-ac4ab7b2ec5c" + (reference "U2") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/a71de703-7e10-4cb6-8e4f-18b3a294ba06" + (reference "U3") (unit 1) (value "d_or") (footprint "") + ) + (path "/a73831d8-f095-4183-9711-d758fe2b91b2" + (reference "U4") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/7ce606a2-1e26-40ab-a60b-bc618bbb0779" + (reference "U5") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/974731a9-bbb8-416f-9a25-0c30d8ab07d4" + (reference "U6") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/d2862414-dfe9-449d-a13c-16243898aca3" + (reference "U7") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/4655c67a-6b0a-4d9e-89f9-5d3bbc4efb7f" + (reference "U8") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/18c3c7b0-aca9-484a-8ea3-1107099aef13" + (reference "U9") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/bce3e1b3-5d6d-4f93-8697-8466a3707777" + (reference "U10") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/fa95283e-4f52-401f-8543-e7cb2aef2983" + (reference "U11") (unit 1) (value "d_and") (footprint "") + ) + (path "/c97ae990-9ea4-401a-8b7c-0ebe206b82dc" + (reference "U12") (unit 1) (value "d_and") (footprint "") + ) + (path "/c7fb65f6-70fa-4411-8573-953a9e10d84f" + (reference "U13") (unit 1) (value "d_and") (footprint "") + ) + (path "/7b76c1c6-e4a6-46f4-9361-5a9ef5b9b839" + (reference "U14") (unit 1) (value "d_and") (footprint "") + ) + (path "/250f1a53-5792-4309-91f2-19a844628ca2" + (reference "U15") (unit 1) (value "d_and") (footprint "") + ) + (path "/94e384f4-1c79-4347-8fc6-7d01a4cc9c33" + (reference "U16") (unit 1) (value "d_and") (footprint "") + ) + (path "/01b1b38e-2b94-4f30-b22a-5c33d73731c2" + (reference "U17") (unit 1) (value "d_and") (footprint "") + ) + (path "/db6dcb92-cdbf-4391-b1cc-0c7ea7c1fea7" + (reference "U18") (unit 1) (value "d_and") (footprint "") + ) + (path "/bf2454ea-2dd2-4c76-901c-e9a9269e2e07" + (reference "U19") (unit 1) (value "d_and") (footprint "") + ) + (path "/132603d6-8c06-4da5-b026-94b19c129708" + (reference "U20") (unit 1) (value "d_and") (footprint "") + ) + (path "/cc043456-31fe-443d-bf1a-9fea786a6fd8" + (reference "U21") (unit 1) (value "d_and") (footprint "") + ) + (path "/a48e1556-b6f7-4004-8a02-7b026b5571ca" + (reference "U22") (unit 1) (value "d_and") (footprint "") + ) + (path "/10a270d1-4c34-456e-97c9-7016d4472ff8" + (reference "U23") (unit 1) (value "d_or") (footprint "") + ) + (path "/81d62144-9385-4554-80c5-0f1ae7b547ad" + (reference "U24") (unit 1) (value "d_or") (footprint "") + ) + (path "/d92c3006-9faf-4b67-9c98-039abeada619" + (reference "U25") (unit 1) (value "d_or") (footprint "") + ) + (path "/4c755c46-be92-4048-af27-78dad16b5033" + (reference "U26") (unit 1) (value "d_or") (footprint "") + ) + (path "/8ab377e3-59d7-4827-b84f-004cfaa01ca0" + (reference "U27") (unit 1) (value "d_or") (footprint "") + ) + (path "/1aea6b04-3458-4d2d-a851-07fb2b177031" + (reference "U28") (unit 1) (value "d_or") (footprint "") + ) + (path "/fadac7d1-0376-4c01-bee4-983f0fc5b72e" + (reference "U29") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/d42f2209-b4ed-44c7-ac34-9564c1b62c7f" + (reference "U30") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/d2483d8f-3942-4287-b32a-e92b684cb4d2" + (reference "U31") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/c8c9cfe4-dfe5-4f34-b7a2-771b2850f5ae" + (reference "U32") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/e3216757-efcd-4495-bbd7-6e21707ecac7" + (reference "U33") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/a7cd4e60-4eee-4555-9280-125af15c4f9f" + (reference "U34") (unit 1) (value "d_dlatch") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.sub b/library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.sub new file mode 100644 index 000000000..d2c342bcc --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155.sub @@ -0,0 +1,138 @@ +* Subcircuit IC_MC10E155 +.subckt IC_MC10E155 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ +.title kicad schematic +* u27 net-_u19-pad3_ net-_u20-pad3_ net-_u27-pad3_ d_or +* u33 net-_u27-pad3_ net-_u29-pad2_ unconnected-_u33-pad3_ net-_u29-pad4_ net-_u1-pad18_ unconnected-_u33-pad6_ d_dlatch +* u32 net-_u26-pad3_ net-_u29-pad2_ unconnected-_u32-pad3_ net-_u29-pad4_ net-_u1-pad19_ unconnected-_u32-pad6_ d_dlatch +* u26 net-_u17-pad3_ net-_u18-pad3_ net-_u26-pad3_ d_or +* u18 net-_u1-pad8_ net-_u10-pad1_ net-_u18-pad3_ d_and +* u20 net-_u1-pad10_ net-_u10-pad1_ net-_u20-pad3_ d_and +* u19 net-_u1-pad9_ net-_u19-pad2_ net-_u19-pad3_ d_and +* u8 net-_u10-pad1_ net-_u17-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u4 net-_u1-pad14_ net-_u29-pad4_ d_buffer +* u3 net-_u1-pad15_ net-_u1-pad16_ net-_u29-pad2_ d_or +* u2 net-_u1-pad13_ net-_u10-pad1_ d_buffer +* u21 net-_u1-pad11_ net-_u10-pad2_ net-_u21-pad3_ d_and +* u22 net-_u1-pad12_ net-_u10-pad1_ net-_u22-pad3_ d_and +* u9 net-_u10-pad1_ net-_u19-pad2_ d_inverter +* u28 net-_u21-pad3_ net-_u22-pad3_ net-_u28-pad3_ d_or +* u34 net-_u28-pad3_ net-_u29-pad2_ unconnected-_u34-pad3_ net-_u29-pad4_ net-_u1-pad17_ unconnected-_u34-pad6_ d_dlatch +* u16 net-_u1-pad6_ net-_u10-pad1_ net-_u16-pad3_ d_and +* u15 net-_u1-pad5_ net-_u15-pad2_ net-_u15-pad3_ d_and +* u17 net-_u1-pad7_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u7 net-_u10-pad1_ net-_u15-pad2_ d_inverter +* u29 net-_u23-pad3_ net-_u29-pad2_ unconnected-_u29-pad3_ net-_u29-pad4_ net-_u1-pad22_ unconnected-_u29-pad6_ d_dlatch +* u30 net-_u24-pad3_ net-_u29-pad2_ unconnected-_u30-pad3_ net-_u29-pad4_ net-_u1-pad21_ unconnected-_u30-pad6_ d_dlatch +* u31 net-_u25-pad3_ net-_u29-pad2_ unconnected-_u31-pad3_ net-_u29-pad4_ net-_u1-pad20_ unconnected-_u31-pad6_ d_dlatch +* u25 net-_u15-pad3_ net-_u16-pad3_ net-_u25-pad3_ d_or +* u24 net-_u13-pad3_ net-_u14-pad3_ net-_u24-pad3_ d_or +* u23 net-_u11-pad3_ net-_u12-pad3_ net-_u23-pad3_ d_or +* u6 net-_u10-pad1_ net-_u13-pad2_ d_inverter +* u5 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad2_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u11 net-_u1-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u13 net-_u1-pad3_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u14 net-_u1-pad4_ net-_u10-pad1_ net-_u14-pad3_ d_and +a1 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u27-pad3_ u27 +a2 net-_u27-pad3_ net-_u29-pad2_ unconnected-_u33-pad3_ net-_u29-pad4_ net-_u1-pad18_ unconnected-_u33-pad6_ u33 +a3 net-_u26-pad3_ net-_u29-pad2_ unconnected-_u32-pad3_ net-_u29-pad4_ net-_u1-pad19_ unconnected-_u32-pad6_ u32 +a4 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u26-pad3_ u26 +a5 [net-_u1-pad8_ net-_u10-pad1_ ] net-_u18-pad3_ u18 +a6 [net-_u1-pad10_ net-_u10-pad1_ ] net-_u20-pad3_ u20 +a7 [net-_u1-pad9_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a8 net-_u10-pad1_ net-_u17-pad2_ u8 +a9 net-_u10-pad1_ net-_u10-pad2_ u10 +a10 net-_u1-pad14_ net-_u29-pad4_ u4 +a11 [net-_u1-pad15_ net-_u1-pad16_ ] net-_u29-pad2_ u3 +a12 net-_u1-pad13_ net-_u10-pad1_ u2 +a13 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a14 [net-_u1-pad12_ net-_u10-pad1_ ] net-_u22-pad3_ u22 +a15 net-_u10-pad1_ net-_u19-pad2_ u9 +a16 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u28-pad3_ u28 +a17 net-_u28-pad3_ net-_u29-pad2_ unconnected-_u34-pad3_ net-_u29-pad4_ net-_u1-pad17_ unconnected-_u34-pad6_ u34 +a18 [net-_u1-pad6_ net-_u10-pad1_ ] net-_u16-pad3_ u16 +a19 [net-_u1-pad5_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a20 [net-_u1-pad7_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a21 net-_u10-pad1_ net-_u15-pad2_ u7 +a22 net-_u23-pad3_ net-_u29-pad2_ unconnected-_u29-pad3_ net-_u29-pad4_ net-_u1-pad22_ unconnected-_u29-pad6_ u29 +a23 net-_u24-pad3_ net-_u29-pad2_ unconnected-_u30-pad3_ net-_u29-pad4_ net-_u1-pad21_ unconnected-_u30-pad6_ u30 +a24 net-_u25-pad3_ net-_u29-pad2_ unconnected-_u31-pad3_ net-_u29-pad4_ net-_u1-pad20_ unconnected-_u31-pad6_ u31 +a25 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u25-pad3_ u25 +a26 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u24-pad3_ u24 +a27 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u23-pad3_ u23 +a28 net-_u10-pad1_ net-_u13-pad2_ u6 +a29 net-_u10-pad1_ net-_u11-pad2_ u5 +a30 [net-_u1-pad2_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a31 [net-_u1-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a32 [net-_u1-pad3_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a33 [net-_u1-pad4_ net-_u10-pad1_ ] net-_u14-pad3_ u14 +* Schematic Name: d_or, Ngspice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u33 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u32 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u26 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u3 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u34 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u29 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u30 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u31 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u25 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u24 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u23 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends IC_MC10E155 \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155_Previous_Values.xml b/library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155_Previous_Values.xml new file mode 100644 index 000000000..90816d243 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E155/IC_MC10E155_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_dlatchd_dlatchd_ord_andd_andd_andd_inverterd_inverterd_ord_bufferd_bufferd_andd_andd_inverterd_ord_dlatchd_andd_andd_inverterd_andd_dlatchd_dlatchd_dlatchd_ord_ord_ord_inverterd_inverterd_andd_andd_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_MC10E155/analysis b/library/SubcircuitLibrary/IC_MC10E155/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E155/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From 9bbf67e2b690bcad3b396a05b2c85a70eb737916 Mon Sep 17 00:00:00 2001 From: Santhosh C Date: Mon, 8 Jun 2026 13:43:36 +0530 Subject: [PATCH 08/10] Add subckt and simulation files for IC_MC10E156 --- .../IC_MC10E156/3_and-cache.lib | 61 + .../SubcircuitLibrary/IC_MC10E156/3_and.cir | 13 + .../IC_MC10E156/3_and.cir.out | 20 + .../SubcircuitLibrary/IC_MC10E156/3_and.pro | 43 + .../SubcircuitLibrary/IC_MC10E156/3_and.sch | 130 + .../SubcircuitLibrary/IC_MC10E156/3_and.sub | 14 + .../IC_MC10E156/3_and_Previous_Values.xml | 1 + .../IC_MC10E156/4_OR-cache.lib | 63 + .../SubcircuitLibrary/IC_MC10E156/4_OR.cir | 14 + .../IC_MC10E156/4_OR.cir.out | 24 + .../SubcircuitLibrary/IC_MC10E156/4_OR.pro | 44 + .../SubcircuitLibrary/IC_MC10E156/4_OR.sch | 150 + .../SubcircuitLibrary/IC_MC10E156/4_OR.sub | 18 + .../IC_MC10E156/4_OR_Previous_Values.xml | 1 + .../IC_MC10E156/IC_MC10E156.cir | 31 + .../IC_MC10E156/IC_MC10E156.cir.out | 81 + .../IC_MC10E156/IC_MC10E156.kicad_sch | 2901 +++++++++++++++++ .../IC_MC10E156/IC_MC10E156.sub | 75 + .../IC_MC10E156_Previous_Values.xml | 1 + .../IC_MC10E156/_autosave-IC_MC10E156.sch | 713 ++++ .../SubcircuitLibrary/IC_MC10E156/analysis | 1 + 21 files changed, 4399 insertions(+) create mode 100644 library/SubcircuitLibrary/IC_MC10E156/3_and-cache.lib create mode 100644 library/SubcircuitLibrary/IC_MC10E156/3_and.cir create mode 100644 library/SubcircuitLibrary/IC_MC10E156/3_and.cir.out create mode 100644 library/SubcircuitLibrary/IC_MC10E156/3_and.pro create mode 100644 library/SubcircuitLibrary/IC_MC10E156/3_and.sch create mode 100644 library/SubcircuitLibrary/IC_MC10E156/3_and.sub create mode 100644 library/SubcircuitLibrary/IC_MC10E156/3_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/IC_MC10E156/4_OR-cache.lib create mode 100644 library/SubcircuitLibrary/IC_MC10E156/4_OR.cir create mode 100644 library/SubcircuitLibrary/IC_MC10E156/4_OR.cir.out create mode 100644 library/SubcircuitLibrary/IC_MC10E156/4_OR.pro create mode 100644 library/SubcircuitLibrary/IC_MC10E156/4_OR.sch create mode 100644 library/SubcircuitLibrary/IC_MC10E156/4_OR.sub create mode 100644 library/SubcircuitLibrary/IC_MC10E156/4_OR_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.cir create mode 100644 library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.cir.out create mode 100644 library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.kicad_sch create mode 100644 library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.sub create mode 100644 library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/IC_MC10E156/_autosave-IC_MC10E156.sch create mode 100644 library/SubcircuitLibrary/IC_MC10E156/analysis diff --git a/library/SubcircuitLibrary/IC_MC10E156/3_and-cache.lib b/library/SubcircuitLibrary/IC_MC10E156/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/IC_MC10E156/3_and.cir b/library/SubcircuitLibrary/IC_MC10E156/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/IC_MC10E156/3_and.cir.out b/library/SubcircuitLibrary/IC_MC10E156/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/IC_MC10E156/3_and.pro b/library/SubcircuitLibrary/IC_MC10E156/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/IC_MC10E156/3_and.sch b/library/SubcircuitLibrary/IC_MC10E156/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/IC_MC10E156/3_and.sub b/library/SubcircuitLibrary/IC_MC10E156/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_MC10E156/3_and_Previous_Values.xml b/library/SubcircuitLibrary/IC_MC10E156/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_MC10E156/4_OR-cache.lib b/library/SubcircuitLibrary/IC_MC10E156/4_OR-cache.lib new file mode 100644 index 000000000..155f5e601 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/IC_MC10E156/4_OR.cir b/library/SubcircuitLibrary/IC_MC10E156/4_OR.cir new file mode 100644 index 000000000..b338b7b5f --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/IC_MC10E156/4_OR.cir.out b/library/SubcircuitLibrary/IC_MC10E156/4_OR.cir.out new file mode 100644 index 000000000..adb6b01be --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/IC_MC10E156/4_OR.pro b/library/SubcircuitLibrary/IC_MC10E156/4_OR.pro new file mode 100644 index 000000000..881563ebd --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/IC_MC10E156/4_OR.sch b/library/SubcircuitLibrary/IC_MC10E156/4_OR.sch new file mode 100644 index 000000000..118968656 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/IC_MC10E156/4_OR.sub b/library/SubcircuitLibrary/IC_MC10E156/4_OR.sub new file mode 100644 index 000000000..d1fd3a241 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_MC10E156/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/IC_MC10E156/4_OR_Previous_Values.xml new file mode 100644 index 000000000..0683d9eb6 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.cir b/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.cir new file mode 100644 index 000000000..357c3f795 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.cir @@ -0,0 +1,31 @@ +.title KiCad schematic +U14 Net-_U14-Pad1_ Net-_U12-Pad2_ unconnected-_U14-Pad3_ Net-_U12-Pad4_ Net-_U1-Pad19_ Net-_U1-Pad18_ d_dlatch +X15 Net-_X15-Pad1_ Net-_X10-Pad4_ Net-_X11-Pad4_ Net-_X12-Pad4_ Net-_U14-Pad1_ 4_OR +U13 Net-_U13-Pad1_ Net-_U12-Pad2_ unconnected-_U13-Pad3_ Net-_U12-Pad4_ Net-_U1-Pad21_ Net-_U1-Pad20_ d_dlatch +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ PORT +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +X8 Net-_U1-Pad8_ Net-_U2-Pad2_ Net-_U10-Pad1_ Net-_X14-Pad4_ 3_and +U9 Net-_U10-Pad1_ Net-_U9-Pad2_ d_inverter +U6 Net-_U2-Pad2_ Net-_U6-Pad2_ d_inverter +X5 Net-_U1-Pad5_ Net-_U7-Pad2_ Net-_U10-Pad2_ Net-_X14-Pad1_ 3_and +X6 Net-_U1-Pad6_ Net-_U2-Pad2_ Net-_U10-Pad2_ Net-_X14-Pad2_ 3_and +X14 Net-_X14-Pad1_ Net-_X14-Pad2_ Net-_X14-Pad3_ Net-_X14-Pad4_ Net-_U13-Pad1_ 4_OR +X7 Net-_U1-Pad7_ Net-_U7-Pad2_ Net-_U10-Pad1_ Net-_X14-Pad3_ 3_and +U3 Net-_U1-Pad15_ Net-_U10-Pad1_ d_buffer +U2 Net-_U1-Pad14_ Net-_U2-Pad2_ d_buffer +U5 Net-_U1-Pad13_ Net-_U12-Pad4_ d_buffer +U4 Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U12-Pad2_ d_or +X12 Net-_U1-Pad12_ Net-_U2-Pad2_ Net-_U10-Pad1_ Net-_X12-Pad4_ 3_and +X11 Net-_U1-Pad11_ Net-_U8-Pad2_ Net-_U10-Pad1_ Net-_X11-Pad4_ 3_and +X9 Net-_U1-Pad9_ Net-_U8-Pad2_ Net-_U11-Pad2_ Net-_X15-Pad1_ 3_and +X10 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U11-Pad2_ Net-_X10-Pad4_ 3_and +U11 Net-_U10-Pad1_ Net-_U11-Pad2_ d_inverter +U8 Net-_U2-Pad2_ Net-_U8-Pad2_ d_inverter +U7 Net-_U2-Pad2_ Net-_U7-Pad2_ d_inverter +X4 Net-_U1-Pad4_ Net-_U2-Pad2_ Net-_U10-Pad1_ Net-_X13-Pad4_ 3_and +X3 Net-_U1-Pad3_ Net-_U6-Pad2_ Net-_U10-Pad1_ Net-_X13-Pad3_ 3_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ unconnected-_U12-Pad3_ Net-_U12-Pad4_ Net-_U1-Pad23_ Net-_U1-Pad22_ d_dlatch +X13 Net-_X1-Pad4_ Net-_X13-Pad2_ Net-_X13-Pad3_ Net-_X13-Pad4_ Net-_U12-Pad1_ 4_OR +X1 Net-_U1-Pad1_ Net-_U6-Pad2_ Net-_U9-Pad2_ Net-_X1-Pad4_ 3_and +X2 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U9-Pad2_ Net-_X13-Pad2_ 3_and +.end diff --git a/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.cir.out b/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.cir.out new file mode 100644 index 000000000..be3205fcb --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.cir.out @@ -0,0 +1,81 @@ +.title kicad schematic + +.include 3_and.sub +.include 4_OR.sub +* u14 net-_u14-pad1_ net-_u12-pad2_ unconnected-_u14-pad3_ net-_u12-pad4_ net-_u1-pad19_ net-_u1-pad18_ d_dlatch +x15 net-_x15-pad1_ net-_x10-pad4_ net-_x11-pad4_ net-_x12-pad4_ net-_u14-pad1_ 4_OR +* u13 net-_u13-pad1_ net-_u12-pad2_ unconnected-_u13-pad3_ net-_u12-pad4_ net-_u1-pad21_ net-_u1-pad20_ d_dlatch +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ port +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +x8 net-_u1-pad8_ net-_u2-pad2_ net-_u10-pad1_ net-_x14-pad4_ 3_and +* u9 net-_u10-pad1_ net-_u9-pad2_ d_inverter +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +x5 net-_u1-pad5_ net-_u7-pad2_ net-_u10-pad2_ net-_x14-pad1_ 3_and +x6 net-_u1-pad6_ net-_u2-pad2_ net-_u10-pad2_ net-_x14-pad2_ 3_and +x14 net-_x14-pad1_ net-_x14-pad2_ net-_x14-pad3_ net-_x14-pad4_ net-_u13-pad1_ 4_OR +x7 net-_u1-pad7_ net-_u7-pad2_ net-_u10-pad1_ net-_x14-pad3_ 3_and +* u3 net-_u1-pad15_ net-_u10-pad1_ d_buffer +* u2 net-_u1-pad14_ net-_u2-pad2_ d_buffer +* u5 net-_u1-pad13_ net-_u12-pad4_ d_buffer +* u4 net-_u1-pad16_ net-_u1-pad17_ net-_u12-pad2_ d_or +x12 net-_u1-pad12_ net-_u2-pad2_ net-_u10-pad1_ net-_x12-pad4_ 3_and +x11 net-_u1-pad11_ net-_u8-pad2_ net-_u10-pad1_ net-_x11-pad4_ 3_and +x9 net-_u1-pad9_ net-_u8-pad2_ net-_u11-pad2_ net-_x15-pad1_ 3_and +x10 net-_u1-pad10_ net-_u2-pad2_ net-_u11-pad2_ net-_x10-pad4_ 3_and +* u11 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u8 net-_u2-pad2_ net-_u8-pad2_ d_inverter +* u7 net-_u2-pad2_ net-_u7-pad2_ d_inverter +x4 net-_u1-pad4_ net-_u2-pad2_ net-_u10-pad1_ net-_x13-pad4_ 3_and +x3 net-_u1-pad3_ net-_u6-pad2_ net-_u10-pad1_ net-_x13-pad3_ 3_and +* u12 net-_u12-pad1_ net-_u12-pad2_ unconnected-_u12-pad3_ net-_u12-pad4_ net-_u1-pad23_ net-_u1-pad22_ d_dlatch +x13 net-_x1-pad4_ net-_x13-pad2_ net-_x13-pad3_ net-_x13-pad4_ net-_u12-pad1_ 4_OR +x1 net-_u1-pad1_ net-_u6-pad2_ net-_u9-pad2_ net-_x1-pad4_ 3_and +x2 net-_u1-pad2_ net-_u2-pad2_ net-_u9-pad2_ net-_x13-pad2_ 3_and +a1 net-_u14-pad1_ net-_u12-pad2_ unconnected-_u14-pad3_ net-_u12-pad4_ net-_u1-pad19_ net-_u1-pad18_ u14 +a2 net-_u13-pad1_ net-_u12-pad2_ unconnected-_u13-pad3_ net-_u12-pad4_ net-_u1-pad21_ net-_u1-pad20_ u13 +a3 net-_u10-pad1_ net-_u10-pad2_ u10 +a4 net-_u10-pad1_ net-_u9-pad2_ u9 +a5 net-_u2-pad2_ net-_u6-pad2_ u6 +a6 net-_u1-pad15_ net-_u10-pad1_ u3 +a7 net-_u1-pad14_ net-_u2-pad2_ u2 +a8 net-_u1-pad13_ net-_u12-pad4_ u5 +a9 [net-_u1-pad16_ net-_u1-pad17_ ] net-_u12-pad2_ u4 +a10 net-_u10-pad1_ net-_u11-pad2_ u11 +a11 net-_u2-pad2_ net-_u8-pad2_ u8 +a12 net-_u2-pad2_ net-_u7-pad2_ u7 +a13 net-_u12-pad1_ net-_u12-pad2_ unconnected-_u12-pad3_ net-_u12-pad4_ net-_u1-pad23_ net-_u1-pad22_ u12 +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u14 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u13 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u12 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.kicad_sch b/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.kicad_sch new file mode 100644 index 000000000..b94612216 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.kicad_sch @@ -0,0 +1,2901 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid c6e7df5b-6560-4678-bb6c-28f90672d8f4) + + (paper "A0") + + (lib_symbols + (symbol "eSim_Digital:d_buffer" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 -1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_buffer" (id 1) (at 0 1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "d_buffer_0_1" + (polyline + (pts + (xy -7.62 5.08) + (xy -7.62 -5.08) + (xy 11.43 0) + (xy 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"d_inverter") (footprint "") + ) + (path "/894729a7-f269-4f3c-b605-56017bc5bda5" + (reference "U7") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/907f9914-1229-4852-a97c-c530d18113d2" + (reference "U8") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/5ed32f37-e2c4-4539-a1eb-4f507ef1d9c6" + (reference "U9") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/d455122d-47b7-4515-89c4-6bfa595c3c70" + (reference "U10") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/51b0108e-9636-4d37-92db-87f3b504e655" + (reference "U11") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/842db722-5a40-4f63-8074-d2f92cd4f075" + (reference "U12") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/4757032d-999f-4b2e-b11a-a1d065b5199d" + (reference "U13") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/ba46f988-f95d-479d-982f-121c7596a8e9" + (reference "U14") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/67718972-6350-471a-ac41-4a4d406ac9b3" + (reference "X1") (unit 1) (value "3_and") (footprint "") + ) + (path "/6182a6ac-185e-49f4-a105-01a70908480a" + (reference "X2") (unit 1) (value "3_and") (footprint "") + ) + (path "/03ad5d9a-57c3-4d4d-afb6-aa6cf85b76b4" + (reference "X3") (unit 1) (value "3_and") (footprint "") + ) + (path "/4e392341-5eff-4a3d-8b18-edfa3761148a" + (reference "X4") (unit 1) (value "3_and") (footprint "") + ) + (path "/949576a2-066a-4b75-bc74-190cad45aedc" + (reference "X5") (unit 1) (value "3_and") (footprint "") + ) + (path "/5d5f8292-7911-4f3f-82c8-20b1b37cc797" + (reference "X6") (unit 1) (value "3_and") (footprint "") + ) + (path "/96e81c67-80db-4386-b4d4-c891c93c56bf" + (reference "X7") (unit 1) (value "3_and") (footprint "") + ) + (path "/1693e1f7-7b75-4ac9-9ded-bbc0968aab0c" + (reference "X8") (unit 1) (value "3_and") (footprint "") + ) + (path "/4ccf5102-7662-4e99-9a9f-b9f007c4bd1b" + (reference "X9") (unit 1) (value "3_and") (footprint "") + ) + (path "/eed62509-86e8-4d5c-9042-2cf851de8cf4" + (reference "X10") (unit 1) (value "3_and") (footprint "") + ) + (path "/2962d051-7c87-4f5b-b77a-f2c194737547" + (reference "X11") (unit 1) (value "3_and") (footprint "") + ) + (path "/45fe1f4a-be66-4e76-86f9-cd95d8c2bedf" + (reference "X12") (unit 1) (value "3_and") (footprint "") + ) + (path "/ab0de437-7918-4ad8-9250-24c4eda1e7c5" + (reference "X13") (unit 1) (value "4_OR") (footprint "") + ) + (path "/15188799-85a0-4abe-b47b-2a2ac7c8f31c" + (reference "X14") (unit 1) (value "4_OR") (footprint "") + ) + (path "/fae3d84c-8753-4968-89a8-34ee9883648f" + (reference "X15") (unit 1) (value "4_OR") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.sub b/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.sub new file mode 100644 index 000000000..f296a192a --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156.sub @@ -0,0 +1,75 @@ +* Subcircuit IC_MC10E156 +.subckt IC_MC10E156 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ +.title kicad schematic +.include 3_and.sub +.include 4_OR.sub +* u14 net-_u14-pad1_ net-_u12-pad2_ unconnected-_u14-pad3_ net-_u12-pad4_ net-_u1-pad19_ net-_u1-pad18_ d_dlatch +x15 net-_x15-pad1_ net-_x10-pad4_ net-_x11-pad4_ net-_x12-pad4_ net-_u14-pad1_ 4_OR +* u13 net-_u13-pad1_ net-_u12-pad2_ unconnected-_u13-pad3_ net-_u12-pad4_ net-_u1-pad21_ net-_u1-pad20_ d_dlatch +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +x8 net-_u1-pad8_ net-_u2-pad2_ net-_u10-pad1_ net-_x14-pad4_ 3_and +* u9 net-_u10-pad1_ net-_u9-pad2_ d_inverter +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +x5 net-_u1-pad5_ net-_u7-pad2_ net-_u10-pad2_ net-_x14-pad1_ 3_and +x6 net-_u1-pad6_ net-_u2-pad2_ net-_u10-pad2_ net-_x14-pad2_ 3_and +x14 net-_x14-pad1_ net-_x14-pad2_ net-_x14-pad3_ net-_x14-pad4_ net-_u13-pad1_ 4_OR +x7 net-_u1-pad7_ net-_u7-pad2_ net-_u10-pad1_ net-_x14-pad3_ 3_and +* u3 net-_u1-pad15_ net-_u10-pad1_ d_buffer +* u2 net-_u1-pad14_ net-_u2-pad2_ d_buffer +* u5 net-_u1-pad13_ net-_u12-pad4_ d_buffer +* u4 net-_u1-pad16_ net-_u1-pad17_ net-_u12-pad2_ d_or +x12 net-_u1-pad12_ net-_u2-pad2_ net-_u10-pad1_ net-_x12-pad4_ 3_and +x11 net-_u1-pad11_ net-_u8-pad2_ net-_u10-pad1_ net-_x11-pad4_ 3_and +x9 net-_u1-pad9_ net-_u8-pad2_ net-_u11-pad2_ net-_x15-pad1_ 3_and +x10 net-_u1-pad10_ net-_u2-pad2_ net-_u11-pad2_ net-_x10-pad4_ 3_and +* u11 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u8 net-_u2-pad2_ net-_u8-pad2_ d_inverter +* u7 net-_u2-pad2_ net-_u7-pad2_ d_inverter +x4 net-_u1-pad4_ net-_u2-pad2_ net-_u10-pad1_ net-_x13-pad4_ 3_and +x3 net-_u1-pad3_ net-_u6-pad2_ net-_u10-pad1_ net-_x13-pad3_ 3_and +* u12 net-_u12-pad1_ net-_u12-pad2_ unconnected-_u12-pad3_ net-_u12-pad4_ net-_u1-pad23_ net-_u1-pad22_ d_dlatch +x13 net-_x1-pad4_ net-_x13-pad2_ net-_x13-pad3_ net-_x13-pad4_ net-_u12-pad1_ 4_OR +x1 net-_u1-pad1_ net-_u6-pad2_ net-_u9-pad2_ net-_x1-pad4_ 3_and +x2 net-_u1-pad2_ net-_u2-pad2_ net-_u9-pad2_ net-_x13-pad2_ 3_and +a1 net-_u14-pad1_ net-_u12-pad2_ unconnected-_u14-pad3_ net-_u12-pad4_ net-_u1-pad19_ net-_u1-pad18_ u14 +a2 net-_u13-pad1_ net-_u12-pad2_ unconnected-_u13-pad3_ net-_u12-pad4_ net-_u1-pad21_ net-_u1-pad20_ u13 +a3 net-_u10-pad1_ net-_u10-pad2_ u10 +a4 net-_u10-pad1_ net-_u9-pad2_ u9 +a5 net-_u2-pad2_ net-_u6-pad2_ u6 +a6 net-_u1-pad15_ net-_u10-pad1_ u3 +a7 net-_u1-pad14_ net-_u2-pad2_ u2 +a8 net-_u1-pad13_ net-_u12-pad4_ u5 +a9 [net-_u1-pad16_ net-_u1-pad17_ ] net-_u12-pad2_ u4 +a10 net-_u10-pad1_ net-_u11-pad2_ u11 +a11 net-_u2-pad2_ net-_u8-pad2_ u8 +a12 net-_u2-pad2_ net-_u7-pad2_ u7 +a13 net-_u12-pad1_ net-_u12-pad2_ unconnected-_u12-pad3_ net-_u12-pad4_ net-_u1-pad23_ net-_u1-pad22_ u12 +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u14 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u13 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u12 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends IC_MC10E156 \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156_Previous_Values.xml b/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156_Previous_Values.xml new file mode 100644 index 000000000..6438ee224 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/IC_MC10E156_Previous_Values.xml @@ -0,0 +1 @@ +d_dlatchd_dlatchd_inverterd_inverterd_inverterd_bufferd_bufferd_bufferd_ord_inverterd_inverterd_inverterd_dlatchC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git 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H 23125 10000 60 0000 C CNN +F 1 "4_OR" H 23125 9850 60 0000 C CNN +F 2 "" H 23050 9550 60 0000 C CNN +F 3 "" H 23050 9550 60 0000 C CNN + 1 23050 9550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Subckt:4_OR X? +U 1 1 00000000 +P 23050 13200 +F 0 "X?" H 23125 13650 60 0000 C CNN +F 1 "4_OR" H 23125 13500 60 0000 C CNN +F 2 "" H 23050 13200 60 0000 C CNN +F 3 "" H 23050 13200 60 0000 C CNN + 1 23050 13200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Subckt:4_OR X? +U 1 1 00000000 +P 23100 16800 +F 0 "X?" H 23175 17250 60 0000 C CNN +F 1 "4_OR" H 23175 17100 60 0000 C CNN +F 2 "" H 23100 16800 60 0000 C CNN +F 3 "" H 23100 16800 60 0000 C CNN + 1 23100 16800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_buffer U? +U 1 1 00000000 +P 19250 19600 +F 0 "U?" H 19325 20000 60 0000 C CNN +F 1 "d_buffer" H 19325 19850 60 0000 C CNN +F 2 "" H 19250 19600 60 0000 C CNN +F 3 "" H 19250 19600 60 0000 C CNN + 1 19250 19600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_buffer U? +U 1 1 00000000 +P 19250 20200 +F 0 "U?" H 19325 20600 60 0000 C CNN +F 1 "d_buffer" H 19325 20450 60 0000 C CNN +F 2 "" H 19250 20200 60 0000 C CNN +F 3 "" H 19250 20200 60 0000 C CNN + 1 19250 20200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_buffer U? +U 1 1 00000000 +P 19250 21350 +F 0 "U?" H 19325 21750 60 0000 C CNN +F 1 "d_buffer" H 19325 21600 60 0000 C CNN +F 2 "" H 19250 21350 60 0000 C CNN +F 3 "" H 19250 21350 60 0000 C CNN + 1 19250 21350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dlatch U? +U 1 1 00000000 +P 24500 9900 +F 0 "U?" H 24580 10550 60 0000 L CNN +F 1 "d_dlatch" H 24580 10400 60 0000 L CNN +F 2 "" H 24500 9900 60 0000 C CNN +F 3 "" H 24500 9900 60 0000 C CNN + 1 24500 9900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dlatch U? +U 1 1 00000000 +P 24500 13550 +F 0 "U?" H 24580 14200 60 0000 L CNN +F 1 "d_dlatch" H 24580 14050 60 0000 L CNN +F 2 "" H 24500 13550 60 0000 C CNN +F 3 "" H 24500 13550 60 0000 C CNN + 1 24500 13550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dlatch U? +U 1 1 00000000 +P 24550 17150 +F 0 "U?" H 24630 17800 60 0000 L CNN +F 1 "d_dlatch" H 24630 17650 60 0000 L CNN +F 2 "" H 24550 17150 60 0000 C CNN +F 3 "" H 24550 17150 60 0000 C CNN + 1 24550 17150 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/IC_MC10E156/analysis b/library/SubcircuitLibrary/IC_MC10E156/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/IC_MC10E156/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From 363e5a69eab3e44f9c5095048bd0efed146a3af8 Mon Sep 17 00:00:00 2001 From: Santhosh C Date: Mon, 8 Jun 2026 13:44:58 +0530 Subject: [PATCH 09/10] Add subckt and simulation files for IC_OR73 --- library/SubcircuitLibrary/IC_OR73/IC_OR73.cir | 9 + .../SubcircuitLibrary/IC_OR73/IC_OR73.cir.out | 36 + .../IC_OR73/IC_OR73.kicad_sch | 842 ++++++++++++++++++ library/SubcircuitLibrary/IC_OR73/IC_OR73.sub | 30 + .../IC_OR73/IC_OR73_Previous_Values.xml | 1 + library/SubcircuitLibrary/IC_OR73/analysis | 1 + 6 files changed, 919 insertions(+) create mode 100644 library/SubcircuitLibrary/IC_OR73/IC_OR73.cir create mode 100644 library/SubcircuitLibrary/IC_OR73/IC_OR73.cir.out create mode 100644 library/SubcircuitLibrary/IC_OR73/IC_OR73.kicad_sch create mode 100644 library/SubcircuitLibrary/IC_OR73/IC_OR73.sub create mode 100644 library/SubcircuitLibrary/IC_OR73/IC_OR73_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/IC_OR73/analysis diff --git a/library/SubcircuitLibrary/IC_OR73/IC_OR73.cir b/library/SubcircuitLibrary/IC_OR73/IC_OR73.cir new file mode 100644 index 000000000..2b96d61d1 --- /dev/null +++ b/library/SubcircuitLibrary/IC_OR73/IC_OR73.cir @@ -0,0 +1,9 @@ +.title KiCad schematic +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT +U6 Net-_U4-Pad3_ Net-_U1-Pad7_ Net-_U6-Pad3_ d_or +U5 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U5-Pad3_ d_or +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U4-Pad3_ d_or +U7 Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U1-Pad8_ d_or +.end diff --git a/library/SubcircuitLibrary/IC_OR73/IC_OR73.cir.out b/library/SubcircuitLibrary/IC_OR73/IC_OR73.cir.out new file mode 100644 index 000000000..b8d8461fd --- /dev/null +++ b/library/SubcircuitLibrary/IC_OR73/IC_OR73.cir.out @@ -0,0 +1,36 @@ +.title kicad schematic + +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port +* u6 net-_u4-pad3_ net-_u1-pad7_ net-_u6-pad3_ d_or +* u5 net-_u2-pad3_ net-_u3-pad3_ net-_u5-pad3_ d_or +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_or +* u7 net-_u5-pad3_ net-_u6-pad3_ net-_u1-pad8_ d_or +a1 [net-_u4-pad3_ net-_u1-pad7_ ] net-_u6-pad3_ u6 +a2 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a3 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a4 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a5 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a6 [net-_u5-pad3_ net-_u6-pad3_ ] net-_u1-pad8_ u7 +* Schematic Name: d_or, Ngspice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u3 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/IC_OR73/IC_OR73.kicad_sch b/library/SubcircuitLibrary/IC_OR73/IC_OR73.kicad_sch new file mode 100644 index 000000000..17b990a21 --- /dev/null +++ b/library/SubcircuitLibrary/IC_OR73/IC_OR73.kicad_sch @@ -0,0 +1,842 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 3a46cef2-bb41-4cab-859b-43b25d1035bb) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Digital:d_or" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_or" (id 1) (at 0 2.54 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "d_or_0_1" + (arc (start -6.35 -1.27) (mid -5.7504 1.27) (end -6.35 3.81) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + 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"/85676890-b110-445d-a3e6-4c501968b65f" + (reference "U1") (unit 5) (value "PORT") (footprint "") + ) + (path "/4dc430fc-262b-48f0-bfa6-d7c4629907a6" + (reference "U1") (unit 6) (value "PORT") (footprint "") + ) + (path "/6a43843b-ec91-4c28-96ba-66aecfc47e0a" + (reference "U1") (unit 7) (value "PORT") (footprint "") + ) + (path "/d50e9aa4-a2e2-4417-90d6-54ab5e2a1332" + (reference "U1") (unit 8) (value "PORT") (footprint "") + ) + (path "/008c681d-032f-4b62-938a-c9abf0f7527f" + (reference "U2") (unit 1) (value "d_or") (footprint "") + ) + (path "/073b13dd-d43d-4147-9d65-d35298d8c605" + (reference "U3") (unit 1) (value "d_or") (footprint "") + ) + (path "/1edc186b-80e9-4b8d-bfcc-71527eda4867" + (reference "U4") (unit 1) (value "d_or") (footprint "") + ) + (path "/f2108f83-e8ef-49a0-9fba-0a4e8a2d9ca5" + (reference "U5") (unit 1) (value "d_or") (footprint "") + ) + (path "/13f253c8-88f6-4342-8c7d-9058e658fbad" + (reference "U6") (unit 1) (value "d_or") (footprint "") + ) + (path "/14773780-85e8-4dca-9bed-3bbe3006b338" + (reference "U7") (unit 1) (value "d_or") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/IC_OR73/IC_OR73.sub b/library/SubcircuitLibrary/IC_OR73/IC_OR73.sub new file mode 100644 index 000000000..34bfad633 --- /dev/null +++ b/library/SubcircuitLibrary/IC_OR73/IC_OR73.sub @@ -0,0 +1,30 @@ +* Subcircuit IC_OR73 +.subckt IC_OR73 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ +.title kicad schematic +* u6 net-_u4-pad3_ net-_u1-pad7_ net-_u6-pad3_ d_or +* u5 net-_u2-pad3_ net-_u3-pad3_ net-_u5-pad3_ d_or +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_or +* u7 net-_u5-pad3_ net-_u6-pad3_ net-_u1-pad8_ d_or +a1 [net-_u4-pad3_ net-_u1-pad7_ ] net-_u6-pad3_ u6 +a2 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u5-pad3_ u5 +a3 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a4 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a5 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4 +a6 [net-_u5-pad3_ net-_u6-pad3_ ] net-_u1-pad8_ u7 +* Schematic Name: d_or, Ngspice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u3 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends IC_OR73 \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_OR73/IC_OR73_Previous_Values.xml b/library/SubcircuitLibrary/IC_OR73/IC_OR73_Previous_Values.xml new file mode 100644 index 000000000..01ee83234 --- /dev/null +++ b/library/SubcircuitLibrary/IC_OR73/IC_OR73_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_ord_ord_ord_ord_ord_or \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_OR73/analysis b/library/SubcircuitLibrary/IC_OR73/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/IC_OR73/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From a47892b22566394cad4028c76593d3455d07731a Mon Sep 17 00:00:00 2001 From: Santhosh C Date: Mon, 8 Jun 2026 13:45:37 +0530 Subject: [PATCH 10/10] Add subckt and simulation files for IC_NA53 --- library/SubcircuitLibrary/IC_NA53/IC_NA53.cir | 8 + .../SubcircuitLibrary/IC_NA53/IC_NA53.cir.out | 32 + .../IC_NA53/IC_NA53.kicad_sch | 728 ++++++++++++++++++ library/SubcircuitLibrary/IC_NA53/IC_NA53.sub | 26 + .../IC_NA53/IC_NA53_Previous_Values.xml | 1 + library/SubcircuitLibrary/IC_NA53/analysis | 1 + 6 files changed, 796 insertions(+) create mode 100644 library/SubcircuitLibrary/IC_NA53/IC_NA53.cir create mode 100644 library/SubcircuitLibrary/IC_NA53/IC_NA53.cir.out create mode 100644 library/SubcircuitLibrary/IC_NA53/IC_NA53.kicad_sch create mode 100644 library/SubcircuitLibrary/IC_NA53/IC_NA53.sub create mode 100644 library/SubcircuitLibrary/IC_NA53/IC_NA53_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/IC_NA53/analysis diff --git a/library/SubcircuitLibrary/IC_NA53/IC_NA53.cir b/library/SubcircuitLibrary/IC_NA53/IC_NA53.cir new file mode 100644 index 000000000..db13d850c --- /dev/null +++ b/library/SubcircuitLibrary/IC_NA53/IC_NA53.cir @@ -0,0 +1,8 @@ +.title KiCad schematic +U6 Net-_U5-Pad3_ Net-_U1-Pad6_ d_inverter +U5 Net-_U4-Pad3_ Net-_U1-Pad5_ Net-_U5-Pad3_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_and +U4 Net-_U3-Pad3_ Net-_U1-Pad4_ Net-_U4-Pad3_ d_and +.end diff --git a/library/SubcircuitLibrary/IC_NA53/IC_NA53.cir.out b/library/SubcircuitLibrary/IC_NA53/IC_NA53.cir.out new file mode 100644 index 000000000..5560a1b80 --- /dev/null +++ b/library/SubcircuitLibrary/IC_NA53/IC_NA53.cir.out @@ -0,0 +1,32 @@ +.title kicad schematic + +* u6 net-_u5-pad3_ net-_u1-pad6_ d_inverter +* u5 net-_u4-pad3_ net-_u1-pad5_ net-_u5-pad3_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u3-pad3_ d_and +* u4 net-_u3-pad3_ net-_u1-pad4_ net-_u4-pad3_ d_and +a1 net-_u5-pad3_ net-_u1-pad6_ u6 +a2 [net-_u4-pad3_ net-_u1-pad5_ ] net-_u5-pad3_ u5 +a3 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a4 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +a5 [net-_u3-pad3_ net-_u1-pad4_ ] net-_u4-pad3_ u4 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/IC_NA53/IC_NA53.kicad_sch b/library/SubcircuitLibrary/IC_NA53/IC_NA53.kicad_sch new file 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net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +.title kicad schematic +* u6 net-_u5-pad3_ net-_u1-pad6_ d_inverter +* u5 net-_u4-pad3_ net-_u1-pad5_ net-_u5-pad3_ d_and +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u3-pad3_ d_and +* u4 net-_u3-pad3_ net-_u1-pad4_ net-_u4-pad3_ d_and +a1 net-_u5-pad3_ net-_u1-pad6_ u6 +a2 [net-_u4-pad3_ net-_u1-pad5_ ] net-_u5-pad3_ u5 +a3 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a4 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +a5 [net-_u3-pad3_ net-_u1-pad4_ ] net-_u4-pad3_ u4 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends IC_NA53 \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_NA53/IC_NA53_Previous_Values.xml b/library/SubcircuitLibrary/IC_NA53/IC_NA53_Previous_Values.xml new file mode 100644 index 000000000..ce07a4293 --- /dev/null +++ b/library/SubcircuitLibrary/IC_NA53/IC_NA53_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_andd_andd_andd_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/IC_NA53/analysis b/library/SubcircuitLibrary/IC_NA53/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/IC_NA53/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file