From 3685487971bcb7e2903418a5f62f349f3b62937c Mon Sep 17 00:00:00 2001 From: Hugo Meiland Date: Thu, 21 May 2026 14:23:23 +0200 Subject: [PATCH 1/6] adding StarFive VisionFive cpu detection string --- init/arch_specs/eessi_arch_riscv.spec | 1 + 1 file changed, 1 insertion(+) diff --git a/init/arch_specs/eessi_arch_riscv.spec b/init/arch_specs/eessi_arch_riscv.spec index aa56fcaa..e437254c 100644 --- a/init/arch_specs/eessi_arch_riscv.spec +++ b/init/arch_specs/eessi_arch_riscv.spec @@ -3,5 +3,6 @@ # Software path in EESSI | Vendor ID | List of defining CPU features "riscv64/sifive/p550" "0x489" "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf" # HiFive Premier P550 +"riscv64/sifive/jh7110" "0x489" "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb" # StarFive VisionFive 2 "riscv64/spacemit/x60" "0x710" "rv64imafdcv_sscofpmf_sstc_svpbmt_zicbom_zicboz_zicbop_zihintpause" # Banana Pi F3 "riscv64/spacemit/x60-k6.6" "0x710" "rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt" # Banana Pi F3 k6.6 From f890645d975925e4a5ac8a1b911b3226c82289ac Mon Sep 17 00:00:00 2001 From: Hugo Meiland Date: Tue, 2 Jun 2026 21:07:57 +0200 Subject: [PATCH 2/6] have riscv match on flags from isa iso only full isa line --- init/arch_specs/eessi_arch_riscv.spec | 8 ++++---- init/eessi_archdetect.sh | 9 +++++++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/init/arch_specs/eessi_arch_riscv.spec b/init/arch_specs/eessi_arch_riscv.spec index e437254c..489ec4fb 100644 --- a/init/arch_specs/eessi_arch_riscv.spec +++ b/init/arch_specs/eessi_arch_riscv.spec @@ -2,7 +2,7 @@ # CPU vendors: SiFive (0x489), Spacemit (0x710) # Software path in EESSI | Vendor ID | List of defining CPU features -"riscv64/sifive/p550" "0x489" "rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf" # HiFive Premier P550 -"riscv64/sifive/jh7110" "0x489" "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb" # StarFive VisionFive 2 -"riscv64/spacemit/x60" "0x710" "rv64imafdcv_sscofpmf_sstc_svpbmt_zicbom_zicboz_zicbop_zihintpause" # Banana Pi F3 -"riscv64/spacemit/x60-k6.6" "0x710" "rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt" # Banana Pi F3 k6.6 +"riscv64/sifive/p550" "0x489" "rv64imafdch zicsr zifencei zba zbb sscofpmf" # HiFive Premier P550 +"riscv64/sifive/jh7110" "0x489" "rv64imafdc zicntr zicsr zifencei zihpm zca zcd zba zbb" # StarFive VisionFive 2 +"riscv64/spacemit/x60" "0x710" "rv64imafdcv sscofpmf sstc svpbmt zicbom zicboz zicbop zihintpause" # Banana Pi F3 +"riscv64/spacemit/x60-k6.6" "0x710" "rv64imafdcv zicbom zicboz zicntr zicond zicsr zifencei zihintpause zihpm zfh zfhmin zca zcd zba zbb zbc zbs zkt zve32f zve32x zve64d zve64f zve64x zvfh zvfhmin zvkt sscofpmf sstc svinval svnapot svpbmt" # Banana Pi F3 k6.6 diff --git a/init/eessi_archdetect.sh b/init/eessi_archdetect.sh index 64d4131f..9ce5c41b 100755 --- a/init/eessi_archdetect.sh +++ b/init/eessi_archdetect.sh @@ -17,7 +17,7 @@ else exit 1 fi -VERSION="1.2.0" +VERSION="1.3.0" # default log level: only emit warnings or errors LOG_LEVEL="WARN" @@ -148,12 +148,17 @@ cpupath(){ cpu_flag_tag='cpu' # on 64-bit RISC-V, we need to look at 'isa' field elif [ "${machine_type}" == "riscv64" ]; then - cpu_flag_tag='isa' + # replace _ with spaces to align with flags notion and partial matching + cpu_flag_tag='isa' else cpu_flag_tag='flags' fi local cpu_flags=$(get_cpuinfo "$cpu_flag_tag") + if [ "${machine_type}" == "riscv64" ]; then + # replace _ with spaces to align with flags notion and partial matching + cpu_flags=${cpu_flags//_/ } + fi log "DEBUG" "cpupath: CPU flags of host system: '$cpu_flags'" # Default to generic CPU From 474710c4fd8896400470fc6ae03ab1fcf6c26cc8 Mon Sep 17 00:00:00 2001 From: Hugo Meiland Date: Tue, 2 Jun 2026 21:13:00 +0200 Subject: [PATCH 3/6] have riscv match on flags from isa iso only full isa line --- init/eessi_archdetect.sh | 1 - 1 file changed, 1 deletion(-) diff --git a/init/eessi_archdetect.sh b/init/eessi_archdetect.sh index 9ce5c41b..f41f7595 100755 --- a/init/eessi_archdetect.sh +++ b/init/eessi_archdetect.sh @@ -148,7 +148,6 @@ cpupath(){ cpu_flag_tag='cpu' # on 64-bit RISC-V, we need to look at 'isa' field elif [ "${machine_type}" == "riscv64" ]; then - # replace _ with spaces to align with flags notion and partial matching cpu_flag_tag='isa' else cpu_flag_tag='flags' From f980bcb40dd6c0df6ad58c7e63a6f90d272a9884 Mon Sep 17 00:00:00 2001 From: Hugo Meiland Date: Tue, 2 Jun 2026 21:13:46 +0200 Subject: [PATCH 4/6] have riscv match on flags from isa iso only full isa line --- init/eessi_archdetect.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/init/eessi_archdetect.sh b/init/eessi_archdetect.sh index f41f7595..0045b39a 100755 --- a/init/eessi_archdetect.sh +++ b/init/eessi_archdetect.sh @@ -148,7 +148,7 @@ cpupath(){ cpu_flag_tag='cpu' # on 64-bit RISC-V, we need to look at 'isa' field elif [ "${machine_type}" == "riscv64" ]; then - cpu_flag_tag='isa' + cpu_flag_tag='isa' else cpu_flag_tag='flags' fi From f4176ae133056635e8843ccf88a7454c70efd5d3 Mon Sep 17 00:00:00 2001 From: Hugo Meiland Date: Wed, 3 Jun 2026 17:20:05 +0200 Subject: [PATCH 5/6] clarifying comment on isa seperation --- init/eessi_archdetect.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/init/eessi_archdetect.sh b/init/eessi_archdetect.sh index 0045b39a..d1584d9d 100755 --- a/init/eessi_archdetect.sh +++ b/init/eessi_archdetect.sh @@ -155,7 +155,9 @@ cpupath(){ local cpu_flags=$(get_cpuinfo "$cpu_flag_tag") if [ "${machine_type}" == "riscv64" ]; then - # replace _ with spaces to align with flags notion and partial matching + # RISC-V ISA strings use '_' as extension separators. + # Convert them to space-separated feature tokens so they + # can be matched like x86 CPU flags. cpu_flags=${cpu_flags//_/ } fi log "DEBUG" "cpupath: CPU flags of host system: '$cpu_flags'" From d01ef98ba82a8f1be2bc41f1d14533e93afc3a1e Mon Sep 17 00:00:00 2001 From: Hugo Meiland Date: Wed, 3 Jun 2026 17:58:48 +0200 Subject: [PATCH 6/6] example specs for rva profiles --- init/arch_specs/eessi_arch_riscv.spec | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/init/arch_specs/eessi_arch_riscv.spec b/init/arch_specs/eessi_arch_riscv.spec index 489ec4fb..cb799bd3 100644 --- a/init/arch_specs/eessi_arch_riscv.spec +++ b/init/arch_specs/eessi_arch_riscv.spec @@ -2,7 +2,10 @@ # CPU vendors: SiFive (0x489), Spacemit (0x710) # Software path in EESSI | Vendor ID | List of defining CPU features -"riscv64/sifive/p550" "0x489" "rv64imafdch zicsr zifencei zba zbb sscofpmf" # HiFive Premier P550 -"riscv64/sifive/jh7110" "0x489" "rv64imafdc zicntr zicsr zifencei zihpm zca zcd zba zbb" # StarFive VisionFive 2 -"riscv64/spacemit/x60" "0x710" "rv64imafdcv sscofpmf sstc svpbmt zicbom zicboz zicbop zihintpause" # Banana Pi F3 -"riscv64/spacemit/x60-k6.6" "0x710" "rv64imafdcv zicbom zicboz zicntr zicond zicsr zifencei zihintpause zihpm zfh zfhmin zca zcd zba zbb zbc zbs zkt zve32f zve32x zve64d zve64f zve64x zvfh zvfhmin zvkt sscofpmf sstc svinval svnapot svpbmt" # Banana Pi F3 k6.6 +"riscv64/generic/rva20u64" "" "rv64imafdc" +"riscv64/generic/rva22u64" "" "rv64imafdc zfhmin" +"riscv64/generic/rva23u64" "" "rv64imafdciv zfhmin" +"riscv64/sifive/p550" "0x489" "rv64imafdch zicsr zifencei zba zbb sscofpmf" # HiFive Premier P550 (rva20 + hypervisor) +"riscv64/sifive/jh7110" "0x489" "rv64imafdc zicntr zicsr zifencei zihpm zca zcd zba zbb" # StarFive VisionFive 2 (rva20) +"riscv64/spacemit/x60" "0x710" "rv64imafdcv sscofpmf sstc svpbmt zicbom zicboz zicbop zihintpause" # Banana Pi F3 (rva22 + vector 1.0 (VLEN=256)) +"riscv64/spacemit/x60-k6.6" "0x710" "rv64imafdcv zicbom zicboz zicntr zicond zicsr zifencei zihintpause zihpm zfh zfhmin zca zcd zba zbb zbc zbs zkt zve32f zve32x zve64d zve64f zve64x zvfh zvfhmin zvkt sscofpmf sstc svinval svnapot svpbmt" # Banana Pi F3 k6.6 (rva22 + vector 1.0 (VLEN=256))