From 70c47c1d3e0060114e1f47c65184e24534cc6e99 Mon Sep 17 00:00:00 2001 From: Claude Date: Thu, 2 Jul 2026 04:26:22 +0000 Subject: [PATCH 1/3] board: post-merge hygiene for PR #626 (LATEST_STATE row + PR_ARC entry) PR #626 merged 2026-07-02 (merge 5aaee33). PR_ARC_INVENTORY prepend with Added/Locked/Deferred/Docs/Confidence; LATEST_STATE Recently-Shipped row. Branch restarted from origin/main per the merged-PR rule. Co-Authored-By: Claude --- .claude/board/LATEST_STATE.md | 1 + .claude/board/PR_ARC_INVENTORY.md | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/.claude/board/LATEST_STATE.md b/.claude/board/LATEST_STATE.md index 85648ed2..cf1acd44 100644 --- a/.claude/board/LATEST_STATE.md +++ b/.claude/board/LATEST_STATE.md @@ -100,6 +100,7 @@ Membrane consumers can now pull BOTH halves of a render `classid` BBB-safely fro | PR | Merged | Title | What it added | |---|---|---|---| +| **#626** | 2026-07-02 | V3 convergence wiring: tenant-carve certification, RungElevator, P6 wave probe, seam-list plan | "Wire, don't invent": `RungLevel::{from_u8,elevate,de_elevate,pearl_level,causal_mask_bits}` + `RungElevator` (sustained-BLOCK policy over P2/P3-certified masks; converged with `escalation::rung_delta` via `apply_delta` — one ladder, two signal sources) wired through the driver (persistent elevator, `ctx.rung=1` proxy retired, grpc rung saturates-never-wraps per codex P2); BOTH V3 tenant carves matrix-certified (Cognitive + Compressed); P6 probe (wave dist == certified palette read, markov_soa verified); `[patch.crates-io] ndarray` → local sibling path (fetch deadlock gone; first in-sandbox core build, 925/925). Plan `v3-convergence-wiring-v1.md`; worker Rule 7. Branch `claude/v3-substrate-migration-review-o0yoxv`, merge `5aaee33`. | | **#542** | 2026-06-18 | E-OGAR-IS-FOUNDRY capstone + 5+3 council + the key→row baton | Foundry/Gotham = "write the OGAR class schema + inheritance"; everything else is generic machinery over it (ontology=`classid→ClassView`+inheritance, AR=DO/THINK, pipelines=`compute_dag`, apps=Jinja-over-classes, query=Cypher⇄SurrealQL one IR). Added `MailboxSoaView::row_for_local_key -> Option` (default `None`, deferred-binding — the key→row baton for a future `Backend::MailboxSoa` router). Epiphanies `E-OGAR-IS-FOUNDRY`/`E-CYPHER-IS-THE-KANBAN-AST`/`E-GUID-IS-THE-GRAPH`; plan `cypher-kanban-ast-unification-v1`. Council corrections: `from_guid_prefix` is on `NiblePath` not `NodeGuid`; "odoo proof" = CONJECTURE; `ogar-adapter-surrealql` not a crate. Branch `claude/q2-substrate-grounding`, merge `faca377f`. | | **#540** | 2026-06-18 | `lite-unified` additive default-OFF coexistence feature gate | **+35/-5, 2 files.** `lite-unified = []` in `crates/lance-graph/Cargo.toml` (empty until SurrealQL-on-lance lowering lands). **datafusion stays DEFAULT — NOT deprecated, NOT made optional.** Process, not switch; promoted per query-shape once OQ-LU-2a is green. Zero behavior change at default features. Branch `claude/lite-unified-gate`, merge `ef7e97ef`. | | **#539** | 2026-06-18 | particle/wave click → `ClassView::compute_dag` (the one Core gap) + electricity-cascade join | **+570, 6 files, additive to `lance-graph-contract` only.** `class_view::{ComputeEdge, compute_dag_is_acyclic, compute_dag_topo_order}` + `ClassView::compute_dag` default (zero-fallback). `compute_dag_topo_order -> Option>` = the recompute ORDER (Kahn; `None` on cycle; leaves excluded). 4+1 epiphanies (`E-OGAR-ROUTER-ENCODER` = router+encoder, physics-duality stripped; `E-EXCEL`, `E-CHESS` = NNUE-proven shape, `E-PERTURBATION` = the cascade IS compute_dag, Weyl bound certifies incrementality; folded `E-AR-DO-WIRING`). Doc-join `crates/perturbation-sim/COMPUTE_DAG_MAPPING.md` (perturbation-sim stays zero-dep). **⚠ tracked: `ClassView::value_schema` default = `ValueSchema::Full` is a TEMPORARY POC — revert to `Bootstrap` + its test when the consumer-transcode phase ends (type-level default stays `Bootstrap`).** 13/13 class_view, clippy/fmt clean. Branch `claude/particle-wave-click-epiphany`, merge `b0255499`. | diff --git a/.claude/board/PR_ARC_INVENTORY.md b/.claude/board/PR_ARC_INVENTORY.md index 184195d1..fe2f4a73 100644 --- a/.claude/board/PR_ARC_INVENTORY.md +++ b/.claude/board/PR_ARC_INVENTORY.md @@ -35,6 +35,24 @@ --- +## #626 lance-graph: V3 convergence wiring — tenant-carve certification, RungElevator, P6 wave probe, seam-list plan + +**Status:** MERGED 2026-07-02 (merge commit `5aaee33`), branch `claude/v3-substrate-migration-review-o0yoxv`. The "wire, don't invent" arc: every deliverable a probe or a wiring of EXISTING types (`E-V3-TENANTS-ALREADY-EXIST-WIRE-DONT-INVENT`); operator all-in, Sonnet-grindwork/Fable-decisions model split. + +**Added:** contract — `RungLevel::{from_u8, elevate, de_elevate, pearl_level, causal_mask_bits}` + `RungElevator{new, on_gate, apply_delta, causal_mask_bits}` (zero-dep sustained-BLOCK policy, converged with `escalation::rung_delta` — one ladder, two signal sources) + the two V3 tenant-carve field-isolation matrices (`osint_v3_cognitive…` / `fma_cpic_v3_compressed…`, shared `assert_value_lane_isolation`); driver — persistent `RwLock` on `ShaderDriver` (base-change reset, gate fed post-decision), `materialize_provenance(…, rung)` retires the `ctx.rung = 1` proxy, `rung_from_wire_u32` grpc saturation (codex P2) + wire/grpc `from_u8` dedup + lab-feature compile repair (Pillar-7 initializer fields, `ContextChain::new()`); core — P6 `p6_palette_join` tests (wave dist == certified palette read), `markov_soa` STATUS verified; build — `[patch.crates-io] ndarray` git-URL → local sibling path (burn submodule out of repo scope; patch was `[[patch.unused]]` either way). Plan `.claude/plans/v3-convergence-wiring-v1.md` + knowledge worker Rule 7 (negative-existence claims need exhaustive-search declaration). + +**Locked:** rung→Pearl mapping (0–2 observe L1, 3–5 intervene L2 → `PO=0b011` P3-certified, 6–9 counterfactual L3 → `SPO=0b111` P3-certified; L1→`O=0b001` labeled convention pending probe; `Counterfactual = 6` IS the boundary); elevator homeostasis (sustained BLOCK up, sustained FLOW down to dispatched base, HOLD resets streaks; threshold 2 hand-tuned, disclosed); two-SoA-worlds doctrine (Lance columnar I/O is the reconciler; consumers write against per-row accessors; `&[T]` borrows are the owner's privilege); grpc wire rung saturates-never-wraps; board files are append-only ledgers (CodeRabbit learning recorded org-side). + +**Deferred:** D-VCW-3 P7 render probe + D-VCW-5 cascade3 nibble falsifier (q2 push-gated, specs ready); D-VCW-4 one-row registry Phase B (OGAR, operator-gated); D-VCW-7 rig/rs-graph-llm FailureTicket loop; osint `0x0700` reconciliation (Options A/B + two-id-spaces addendum strengthening B — operator's); classid human-readable reorder (DEFERRED-by-design). + +**Docs/board:** EPIPHANIES `E-V3-TENANTS-ALREADY-EXIST-WIRE-DONT-INVENT` + `E-RUNG-LADDER-IS-DISPATCH-POLICY-OVER-CERTIFIED-MASKS`; ISSUES `ISS-Q2-CPIC-MIRROR-DIVERGES-FROM-CPIC-V3-REGISTRY` (+ dated truncated-grep correction) + `ISS-Q2-CASCADE3-NIBBLE-ANCESTRY`; TECH_DEBT `TD-DEPRECATED-ACCESSORS-BLOCK-DEP-CLIPPY`; STATUS_BOARD D-VCW rows; INTEGRATION_PLANS prepend; AGENT_LOG ×3. + +**Confidence (2026-07-02):** HIGH — contract 763 (v2+v3 features)/755 default, core 925 (arigraph 124, markov_soa 6), driver 100 default/186 lab-feature, planner 204; fmt clean; codex P2 fixed+tested; CodeRabbit 5/5 pre-merge, 1 finding fixed + 1 withdrawn (append-only-ledger learning recorded). First session where lance-graph CORE builds+tests in-sandbox (crates.io noProxy + local ndarray path patch + protoc). + +**Cross-ref:** plan `v3-convergence-wiring-v1.md`; #624 (P1–P5 probe arc this extends); #496/#500 (tenant-lane layout + no-new-variant guardrail); #618 (V3 identity classes); OGAR #128 (envelope parser, the ReadMode third axis). + +--- + ## #592 lance-graph: `contract::ogar_codebook` APP-prefix (hi-u16) mirror — closes ISS-CONTRACT-APP-PREFIX-MIRROR **Status:** MERGED 2026-06-22 (merge commit `48794eaf`), branch `claude/contract-app-prefix-mirror`. Closes the Core gap the #591 consumer spellbook surfaced: `contract::ogar_codebook` mirrored the lo-u16 concept pull but not OGAR#97's hi-u16 render composition, so membrane consumers had to hand-stamp `0x000N`. From 1230fd8302b12815324da0342b0ac3f8dd182787 Mon Sep 17 00:00:00 2001 From: Claude Date: Thu, 2 Jul 2026 04:43:18 +0000 Subject: [PATCH 2/3] =?UTF-8?q?plans/board:=20classid=20canon:custom=20fli?= =?UTF-8?q?p=20TRIGGERED=20(0x07:01::1000)=20=E2=80=94=20plan=20v1=20+=20r?= =?UTF-8?q?uling=20recorded;=20q2=20gate=20waived;=20osint=20issues=20RESO?= =?UTF-8?q?LVED?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Operator ruling 2026-07-02, four parts, all recorded: 1. OSINT low byte = APPID space domain-wise (00 = domain, 01 = q2 the consumer); zero vocabulary rows — executed OGAR PR #146 (67 -> 65, COUNT_FUSE balances with zero mirror changes). ISSUES ISS-OSINT-SYSTEM-ROOT-SLOT-VIOLATION + ISS-OGAR-OSINT-MIRROR-PENDING -> RESOLVED (statuses flipped, history preserved). 2. 0x1000 was a temporary V3 marker ('hard reminder'), not a format bit. 3. THE FLIP IS TRIGGERED: canon (domain:appid) -> HIGH u16, custom -> LOW; stored 0x0701_1000, human-readable 0x07:01::1000. New plan .claude/plans/classid-canon-custom-flip-v1.md: one flippable compose/split definition (E-CLASSID-SPLIT-ORDER-IS-A-FLIP), flip(flip(x))==x probed, mint-forward with an I-LEGACY version boundary (legacy classids never blanket-reinterpreted), phases P0 route-through -> P1 flip+coexist -> P2 OGAR#95 app-prefix reconciliation (operator checkpoint) -> P3 q2 re-mints (dissolves ISS-Q2-CPIC-MIRROR, resolution RULED as contract-pull) -> P4 marker retirement (operator checkpoint). Executes soa-value-tenant-migration-v2 §2.3; supersedes-by-trigger E-CLASSID-HUMANREADABLE-REORDER-DEFERRED. 4. q2 push gate WAIVED — D-VCW-3/D-VCW-5 unblocked (STATUS_BOARD). Board (same commit): EPIPHANIES E-CLASSID-CANON-HIGH-TRIGGERED, INTEGRATION_PLANS prepend, STATUS_BOARD D-CCF rows + D-VCW updates, ISSUES status flips. Co-Authored-By: Claude --- .claude/board/EPIPHANIES.md | 32 +++++ .claude/board/INTEGRATION_PLANS.md | 4 + .claude/board/ISSUES.md | 9 +- .claude/board/STATUS_BOARD.md | 16 ++- .claude/plans/classid-canon-custom-flip-v1.md | 130 ++++++++++++++++++ 5 files changed, 184 insertions(+), 7 deletions(-) create mode 100644 .claude/plans/classid-canon-custom-flip-v1.md diff --git a/.claude/board/EPIPHANIES.md b/.claude/board/EPIPHANIES.md index 56630f35..207af434 100644 --- a/.claude/board/EPIPHANIES.md +++ b/.claude/board/EPIPHANIES.md @@ -1,3 +1,35 @@ +## 2026-07-02 — E-CLASSID-CANON-HIGH-TRIGGERED — the operator pulled the flip trigger: canon (domain:appid) moves to the HIGH half, `0x1000` was a temporary reminder, OSINT low byte = appid space, q2 gate waived + +**Status:** DOCTRINE (operator ruling, verbatim anchors in the plan §0). + +**Four rulings in one message arc (2026-07-02):** +1. **OSINT semantics:** "OSINT Person was a hallucination." `0x07` = OSINT + domain; low byte applied **domain-wise as APPID** (`00` = the domain + itself; `01` = **q2, our consumer**). OSINT contributes ZERO vocabulary + rows — OGAR PR #146 removed both #145 mints (count 67→65; the COUNT_FUSE + balances with zero mirror changes; `ISS-OSINT-SYSTEM-ROOT-SLOT-VIOLATION` + dissolves — sharper than either of its recorded Options A/B). FMA anatomy + = own domain (`0x0A`, separate from Health `0x09`) under q2; CPIC = own + Genetics domain (`0x0E`) under q2 (⇒ its q2 class normalizes `:00`→`:01`). +2. **The marker was temporary:** `0x1000` was "just a temporary V3 substrate + marker as a hard reminder for V3 substrate migration" — a sticky note, + not a format bit. Retirement is a planned operator checkpoint (plan §4 P4). +3. **The flip is TRIGGERED:** "now is the right time for the migration." + Target stored form `0x0701_1000` — canon (`domain:appid`) HIGH, custom + (marker/render) LOW; human-readable `0x07:01::1000`. This IS the + `soa-value-tenant-migration-v2` §2.3 atomic Canon:Custom flip, now ACTIVE + as `.claude/plans/classid-canon-custom-flip-v1.md` (one flippable + compose/split definition, `flip(flip(x))==x` probed, mint-forward with an + I-LEGACY version boundary — never a blanket reinterpretation of legacy + classids). `E-CLASSID-HUMANREADABLE-REORDER-DEFERRED` is hereby + superseded-by-trigger (entry preserved, per append-only). +4. **q2 push gate WAIVED:** "it was a temporary precaution to not break the + cockpit while working on so many different domains — you can unarm that." + D-VCW-3 (P7 render probe), D-VCW-5 (cascade3 nibble falsifier), and the + q2 phases of the flip (P3) are unblocked. + +--- + ## 2026-07-01 — E-RUNG-LADDER-IS-DISPATCH-POLICY-OVER-CERTIFIED-MASKS — rung elevation needs zero new math; and there is ONE ladder with TWO signal sources (gate streaks + felt-parse delta) **Status:** FINDING (shipped: `RungLevel::{from_u8, elevate, de_elevate, diff --git a/.claude/board/INTEGRATION_PLANS.md b/.claude/board/INTEGRATION_PLANS.md index ce304598..3c32b290 100644 --- a/.claude/board/INTEGRATION_PLANS.md +++ b/.claude/board/INTEGRATION_PLANS.md @@ -1,3 +1,7 @@ +## 2026-07-02 — classid-canon-custom-flip (TRIGGERED — the §2.3 atomic flip is live) + +Plan: `.claude/plans/classid-canon-custom-flip-v1.md`. **Operator pulled the trigger** ("now is the right time for the migration — document it accordingly"): canon (`domain:appid`) moves to the classid's HIGH u16, custom (the temporary `0x1000` V3 marker, later the render/dynamic-classview space) to the LOW — stored `0x0701_1000`, human-readable `0x07:01::1000`. Grounded in the same ruling: OSINT low byte = APPID space domain-wise (q2=`0x01`; zero vocabulary rows — OGAR PR #146), FMA/CPIC own domains under q2 (CPIC normalizes `:00`→`:01`), q2 push gate WAIVED. Mechanism: ONE flippable `compose_classid/split_classid/CLASSID_CANON_HIGH` in the contract (per `E-CLASSID-SPLIT-ORDER-IS-A-FLIP`), `flip(flip(x))==x` probed, **mint-forward with an I-LEGACY version boundary** (legacy `0x0000_XXXX` classids never blanket-reinterpreted). Phases: P0 route-through (zero behavior) → P1 flip+coexist → P2 OGAR#95 hi-u16 app-prefix reconciliation (operator checkpoint) → P3 q2 re-mints (dissolves `ISS-Q2-CPIC-MIRROR…`) → P4 `0x1000` retirement (operator checkpoint). Supersedes-by-trigger `E-CLASSID-HUMANREADABLE-REORDER-DEFERRED`; executes `soa-value-tenant-migration-v2` §2.3. ACTIVE. + ## 2026-07-01 — v3-convergence-wiring (wire, don't invent — every layer already contains its own solution) Plan: `.claude/plans/v3-convergence-wiring-v1.md`. **Operator all-in ("I'm all in for your ideas — document and PR so other sessions converge"); model split Sonnet-grindwork/Fable-decisions.** The organizing finding (`E-V3-TENANTS-ALREADY-EXIST-WIRE-DONT-INVENT`): the V3 substrate's gaps are unwired seams, not missing machinery — every deliverable is a probe or a wiring of EXISTING types, §0 anti-invention throughout. **Seam list:** D1a `RungLevel::{from_u8,elevate,de_elevate,pearl_level,causal_mask_bits}` + `RungElevator` (zero-dep "elevates on sustained BLOCK" as a pure policy over `GateDecision` + the P2/P3-certified mask algebra; converged with `escalation::rung_delta` via `apply_delta` — one ladder, two signal sources: gate streaks = System-2, felt-parse = System-1) — SHIPPED; D1b driver wiring (replace `ctx.rung = 1` proxy, dedup wire/grpc u8→rung matches) — Sonnet in flight; D2 P6 wave-convergence probe (markov_soa's injected distance = the SAME certified 256×256 palette read as P1–P3; the table is the join object) — SHIPPED (2 tests, 6/6 module green); D3 P7 render probe spec (ClassView bitmask → askama; rendered fields == masked tenants; q2-side, push-gated, spec ready §3); D4 one-row registry (codebook row seeds `{tail, value_schema, edge_codec, bitmask, template}`; read-mode parity fuse sibling of COUNT_FUSE; Phase B gated on operator + osint decision); D5 nibble-hierarchy falsifier (FNV `cascade3` bytes have no nibble ancestry → HHTL on bake mints is tier-granular; `ISS-Q2-CASCADE3-NIBBLE-ANCESTRY`); D6 negative-existence-claims worker rule (knowledge doc Rule 7) — SHIPPED; D7 rig/rs-graph-llm FailureTicket loop — deferred frontier (first place determinism ends). **Doctrine (no code):** the two SoA worlds stay two — Lance columnar I/O is the reconciler; consumers write against per-row accessors; column borrows are the owner's privilege. ACTIVE. diff --git a/.claude/board/ISSUES.md b/.claude/board/ISSUES.md index 94ed4953..a6df757d 100644 --- a/.claude/board/ISSUES.md +++ b/.claude/board/ISSUES.md @@ -2,7 +2,7 @@ ## 2026-07-01 — ISS-Q2-CASCADE3-NIBBLE-ANCESTRY — q2 `cascade3` FNV bytes are byte-hierarchical but NOT nibble-hierarchical; HHTL routing over bake mints is sound only at whole-tier granularity -**Status:** OPEN (falsifier specified, not yet run — q2 is push-gated). Owner: +**Status:** OPEN (falsifier specified, not yet run — q2 push gate WAIVED 2026-07-02, "temporary precaution … you can unarm that"; runnable now, D-VCW-5). Owner: q2 `cpic/src/lib.rs::cascade3` (+ any bake reusing it) vs the OGAR canon's 256=4⁴ hierarchical-codebook condition. Plan: `v3-convergence-wiring-v1.md` §5. @@ -26,8 +26,7 @@ assume sub-byte ancestry on these mints until this runs. ## 2026-07-01 — ISS-Q2-CPIC-MIRROR-DIVERGES-FROM-CPIC-V3-REGISTRY — q2's local `cpic::NodeGuid` mirror is V1-layout-parity-true but diverges from the registered CPIC-V3 read-mode on BOTH domain and tail shape -**Status:** OPEN (record-only; resolve WITH the operator — q2 is push-gated and -cross-repo blockers are never silently fixed). Owner: q2 `cpic/src/lib.rs` + +**Status:** RESOLUTION RULED 2026-07-02 (execution queued as flip P3 / D-CCF-3) — the operator ruling ("Same for cpic also under q2, which has a different domain for separation") + the triggered canon:custom flip settle this as shape (a) below, with the target classid updated by the flip: q2's CPIC class = Genetics:q2 = `0x0E:01::…` (post-flip stored `0x0E01_1000`; the pre-flip root `0x1000_0E00` normalizes `:00`→`:01`). q2 push gate WAIVED. cpic re-mints by PULLING the contract (`mint_for(classid_read_mode(…).tail_variant, …)`), retiring the local mirror + the `0x0C` domain. See `classid-canon-custom-flip-v1.md` §2/§4. Owner: q2 `cpic/src/lib.rs` + `lance-graph-contract::canonical_node` (CPIC-V3 registry). Surfaced 2026-07-01 by a verify-the-mirror read after the V3 tenant-carve certification. @@ -80,7 +79,7 @@ declared registry-exempt (bake-only) and its parity comment is scoped to ## 2026-07-01 — ISS-OSINT-SYSTEM-ROOT-SLOT-VIOLATION — OGAR shipped `osint_system` at the reserved `0x0700` root slot; the lance-graph mirror canon forbids it (`CC==0x00` = domain root, reserved) — the parallel-mirror is BLOCKED on a remap decision -**Status:** OPEN · **BLOCKS `ISS-OGAR-OSINT-MIRROR-PENDING`.** Owner: OGAR `ogar-vocab` (merged, needs follow-up) + `lance-graph-contract::ogar_codebook` mirror + q2 `osint_classview`. Surfaced 2026-07-01 when the merged OGAR #145 + lance-graph #624 met and I ran `cargo test -p lance-graph-contract`. +**Status:** RESOLVED 2026-07-02 (operator ruling, executed in OGAR PR #146) — and the resolution is SHARPER than either recorded option: "OSINT Person was a hallucination"; within the OSINT domain the low byte is APPID space applied domain-wise (`00` = the domain itself, `01` = q2 the consumer), so OSINT contributes **zero vocabulary rows**. OGAR #146 removed BOTH #145 mints (`osint_system@0x0700` AND `osint_person@0x0701`); count 67 → 65 == the mirror's 65 — the COUNT_FUSE balances with ZERO mirror-side changes, and the zero-slot invariant is untouched. Options A and B below are preserved as history; neither was taken (B came closest — its addendum's two-id-spaces reading is confirmed, but even the `0x0701` "concept" was a mislabel on q2's appid slot). See `E-CLASSID-CANON-HIGH-TRIGGERED` + `.claude/plans/classid-canon-custom-flip-v1.md` §0 for the full ruling (which also triggers the canon:custom flip). **The violation.** The shared codebook canon (documented in `ogar_codebook.rs` module header: *"`CC == 0x00` = the domain root, reserved"*) requires every concept id `0xDDCC` to have `CC ≥ 0x01`; `0x__00` is the domain-root/default, NOT a concrete concept. OGAR main ships **`("osint_system", 0x0700)`** — `CC == 0x00`, the reserved root. `("osint_person", 0x0701)` is valid (`CC==01`, operator-frozen). The lance-graph mirror enforces the canon via the workspace-member test `codebook_has_no_duplicate_ids_or_zero_concept_slot` (`assert_ne!(id & 0x00FF, 0x00)`), so **mirroring `0x0700` fails lance-graph's own default CI** (748 pass, 1 fail). The `COUNT_FUSE` (in the *excluded* `lance-graph-ogar`) is a separate, downstream break; this one is in-tree. @@ -109,7 +108,7 @@ Option B resolves it without deleting the idea or moving any id. ## 2026-07-01 — ISS-OGAR-OSINT-MIRROR-PENDING — OGAR #145's OSINT mint (+2 to `class_ids::ALL`) breaks the contract-mirror `COUNT_FUSE` on merge; the paired lance-graph mirror rows must land in the same arc -**Status:** OPEN (tracked) · **Resolution path RULED by operator 2026-07-01: keep the fuse (it IS the dependency contract enforcing OGAR↔lance-graph parallel movement); do NOT pin to a rev — "option 1" is REJECTED. Land the 2 mirror rows + `domains_agree` arm in parallel with OGAR #145 (option 2 / coordinated merge; brief transient red is acceptable — "the fuse is okay for now"). See `E-OGAR-LANCEGRAPH-MOVE-IN-PARALLEL`.** · Owner: OGAR `ogar-vocab` (PR #145) + `lance-graph-contract::ogar_codebook` mirror + `lance-graph-ogar::parity::domains_agree`. Surfaced 2026-07-01 while self-reviewing PR #624 / #145. Same cross-repo-arc shape as `ISS-OGAR-AUTH-MIRROR-DRIFT` (which took medcare CI red) and `ISS-OGAR-GENETICS-MIRROR-PENDING`; cited by `E-CODEBOOK-MINT-IS-A-CROSS-REPO-ARC`. +**Status:** RESOLVED 2026-07-02 — dissolved by the same operator ruling as `ISS-OSINT-SYSTEM-ROOT-SLOT-VIOLATION`: OGAR PR #146 removes both #145 OSINT mints (67 → 65), so the fuse balances with NO mirror rows to land; the "2 mirror rows in parallel" path below is moot (preserved as history). The fuse itself stays, per the earlier ruling ("keep the fuse — it IS the dependency contract"). · Original: **Resolution path RULED by operator 2026-07-01: keep the fuse (it IS the dependency contract enforcing OGAR↔lance-graph parallel movement); do NOT pin to a rev — "option 1" is REJECTED. Land the 2 mirror rows + `domains_agree` arm in parallel with OGAR #145 (option 2 / coordinated merge; brief transient red is acceptable — "the fuse is okay for now"). See `E-OGAR-LANCEGRAPH-MOVE-IN-PARALLEL`.** · Owner: OGAR `ogar-vocab` (PR #145) + `lance-graph-contract::ogar_codebook` mirror + `lance-graph-ogar::parity::domains_agree`. Surfaced 2026-07-01 while self-reviewing PR #624 / #145. Same cross-repo-arc shape as `ISS-OGAR-AUTH-MIRROR-DRIFT` (which took medcare CI red) and `ISS-OGAR-GENETICS-MIRROR-PENDING`; cited by `E-CODEBOOK-MINT-IS-A-CROSS-REPO-ARC`. **READY PATCH (apply to lance-graph the moment OGAR #145 is on OGAR main; NOT to #624 while OGAR main is still 65 — that breaks #624's own fuse):** in `crates/lance-graph-contract/src/ogar_codebook.rs` add the two rows `("osint_system", 0x0700), ("osint_person", 0x0701)` to `mirror::CODEBOOK` (65 → 67); add the `(O::Osint, C::Osint)` arm to `lance-graph-ogar::parity::domains_agree` (the `ConceptDomain::Osint` enum + `0x07 => Osint` route already exist). Then `mirror::CODEBOOK.len() == ogar_vocab::class_ids::ALL.len()` (67 == 67) restored. diff --git a/.claude/board/STATUS_BOARD.md b/.claude/board/STATUS_BOARD.md index 0e54e50b..b3602194 100644 --- a/.claude/board/STATUS_BOARD.md +++ b/.claude/board/STATUS_BOARD.md @@ -1,3 +1,15 @@ +## classid-canon-custom-flip-v1 — the TRIGGERED §2.3 atomic flip + +Plan: `.claude/plans/classid-canon-custom-flip-v1.md`. Operator trigger 2026-07-02. + +| D-id | Title | Crate(s) | Status | Evidence | +|---|---|---|---|---| +| D-CCF-0 | compose_classid/split_classid/CLASSID_CANON_HIGH + route all sites (zero behavior) | lance-graph-contract | Queued | plan §3/§4 P0 | +| D-CCF-1 | Flip + mint new-form classids (0x0701_1000 / 0x0A01_1000 / 0x0E01_1000) coexisting | lance-graph-contract | Queued | gated on P0 probes | +| D-CCF-2 | OGAR#95 hi-u16 app-prefix reconciliation | contract + OGAR | Blocked (operator checkpoint) | plan §2 row / §4 P2 | +| D-CCF-3 | q2 re-mints (osint-bake + cpic via contract pull; dissolves ISS-Q2-CPIC-MIRROR) | q2 (gate WAIVED) | Queued | plan §4 P3 | +| D-CCF-4 | 0x1000 marker retirement | all | Blocked (operator checkpoint) | plan §4 P4 | + ## v3-convergence-wiring-v1 — wire, don't invent (the seam list) Plan: `.claude/plans/v3-convergence-wiring-v1.md`. Sonnet-grindwork/Fable-decisions split. @@ -7,9 +19,9 @@ Plan: `.claude/plans/v3-convergence-wiring-v1.md`. Sonnet-grindwork/Fable-decisi | D-VCW-1a | RungLevel arithmetic + RungElevator (sustained-BLOCK policy over certified mask algebra; converged with escalation::rung_delta) | lance-graph-contract | **Shipped** | 755 lib tests green incl. 6 new; clippy clean | | D-VCW-1b | Driver wiring: elevator through cycle loop, ctx.rung proxy retired, wire/grpc from_u8 dedup | cognitive-shader-driver | **Shipped** | driver 100/100 green (2 new tests: sustained-BLOCK elevation across dispatches + rung load-bearing in tactic selection); driver-persistent RwLock elevator, base-change reset | | D-VCW-2 | P6 wave-convergence probe (wave dist == certified palette read) | lance-graph core (arigraph) | **Shipped** | markov_soa 6/6 green (2 new P6 tests) | -| D-VCW-3 | P7 render probe (bitmask → askama; fields == masked tenants) | q2 (push-gated) | Queued | spec ready (plan §3) | +| D-VCW-3 | P7 render probe (bitmask → askama; fields == masked tenants) | q2 (**gate WAIVED 2026-07-02**) | Queued (unblocked) | spec ready (plan §3) | | D-VCW-4 | One-row registry + read-mode parity fuse | contract (+OGAR Phase B) | Queued | plan §4; Phase B operator-gated | -| D-VCW-5 | cascade3 nibble-ancestry falsifier | q2 (push-gated) | Recorded | ISS-Q2-CASCADE3-NIBBLE-ANCESTRY | +| D-VCW-5 | cascade3 nibble-ancestry falsifier | q2 (**gate WAIVED 2026-07-02**) | Queued (unblocked) | ISS-Q2-CASCADE3-NIBBLE-ANCESTRY | | D-VCW-6 | Rule 7: negative-existence claims need exhaustive-search declaration | knowledge doc | **Shipped** | autoattended-multiagent-pattern.md §5 Rule 7 | | D-VCW-7 | rig/rs-graph-llm FailureTicket loop | rs-graph-llm (sibling) | Deferred | plan §6; probe-first when opened | diff --git a/.claude/plans/classid-canon-custom-flip-v1.md b/.claude/plans/classid-canon-custom-flip-v1.md new file mode 100644 index 00000000..93794319 --- /dev/null +++ b/.claude/plans/classid-canon-custom-flip-v1.md @@ -0,0 +1,130 @@ +# Classid Canon:Custom Half-Order Flip — Plan v1 (the migration is TRIGGERED) + +> **Status:** ACTIVE (2026-07-02, operator trigger — verbatim: *"so yes now is +> the right time for the migration — document it accordingly using +> .claude/board and /plans"*). This is the migration `soa-value-tenant- +> migration-v2.md` §2.3 sequenced as "the atomic Canon:Custom half-order flip +> follows once the V3 set is complete" — the V3 set completed (three classes +> wired, both carves matrix-certified, PR #626), and the operator pulled the +> trigger. +> +> Implemented per the standing directive `E-CLASSID-SPLIT-ORDER-IS-A-FLIP`: +> ONE flippable split-order definition, `flip(flip(x)) == x` probed — never +> scattered per-site byte surgery. + +--- + +## §0 The ruling (operator, 2026-07-02 — the semantic ground truth) + +Three verbatim anchors, decoded: + +1. *"0700 is OSINT domain, 00 as in applied domainweise"* — `0xDD` names the + domain; low byte `00` = the domain applied **domain-wise** (the domain + itself as the class). +2. *"0701 is q2 as the OSINT appid, our consumer"* — within a domain the low + byte is **APPID space**, not concept vocabulary (q2 = `0x01`). Concept + vocabularies exist only in domains that have them (project mgmt, ERP, + Health, …); OSINT has none (OGAR PR #146 removed the two hallucinated + rows; count 67 → 65, COUNT_FUSE balances with zero mirror changes). +3. *"(0x0701_1000 — or for mentally understanding, the domain appid; and 1000 + was just a temporary V3 substrate marker as a hard reminder for V3 + substrate migration — (0x07:01::1000"* — the **target stored form** puts + the canon half HIGH and the custom half LOW: + +``` +human-readable 0x07 : 01 :: 1000 + domain appid custom (today: the temporary V3 marker) + +stored (target) 0x0701_1000 hi u16 = CANON (domain:appid) + lo u16 = CUSTOM (marker/render, later the + 64k dynamic classviews × bitmask) + +stored (legacy) 0x1000_0701 hi u16 = marker, lo u16 = canon + (the pre-flip PR #618/#626 form) +``` + +The `0x1000` marker is **temporary by declaration** — a "hard reminder" of the +V3 migration, not a permanent format bit. Its retirement is §4 Phase 4 (an +operator checkpoint, NOT part of the flip itself). + +Also in the ruling: q2's push gate is **waived** ("temporary precaution to not +break the cockpit while working on so many different domains") — the q2-side +phases below are unblocked. + +## §1 What the flip IS (and is not) + +- **IS:** a swap of which u16 half of the stored `classid: u32` carries the + canon (`domain:appid`) and which carries the custom (marker/render) half — + routed through ONE compose/split definition so the swap is a one-place flag. +- **IS NOT:** a re-carve of the 16-byte key (bytes 0..4 stay the classid; no + `ENVELOPE_LAYOUT_VERSION` change), a change to HEEL/HIP/TWIG/tails, or a + change to any concept id value. Only the classid's internal half-order moves. +- **The central risk (name it before it bites):** legacy classids + (`0x0000_0700`-form, hi = 0) read WRONG under a naive global flip + (`0x0000_0700` would decode as canon `0x0000`). So the flip is + **mint-forward with a version boundary**, never a blanket reinterpretation — + full `I-LEGACY-API-FEATURE-GATED` discipline: the same accessor must never + silently mean two things; readers route through the split definition, which + knows the boundary; a field-isolation/round-trip matrix ships with Phase 1. + +## §2 Site inventory (what routes through the flip) + +| Site | Today | Post-flip | +|---|---|---| +| `contract::canonical_node` `CLASSID_OSINT_V3` | `0x1000_0700` | **`0x0701_1000`** (OSINT:q2 — note the appid normalization: the q2 class is `:01`, not the domain root) | +| `CLASSID_FMA_V3` | `0x1000_0A01` | `0x0A01_1000` (Anatomy:q2 — already `:01`, confirmed by the ruling) | +| `CLASSID_CPIC_V3` | `0x1000_0E00` | `0x0E01_1000` (Genetics:q2 — normalized `:00`→`:01` per "same for cpic also under q2") | +| `BUILTIN_READ_MODES` keys | old-form u32s | both forms during transition (the registry maps concrete u32s, so coexistence is free); old-form keys retire at Phase 3 | +| `ogar_codebook::classid_concept_domain` | routes `classid as u16` (lo) | routes the CANON half via `split_classid` | +| `hhtl::NiblePath::from_guid_prefix{,_v3}` | v1 fold refuses `classid >> 16 != 0`; v3 fold ignores classid | both route the marker/canon test through `split_classid` | +| `ogar_codebook::{render_classid, classid_app_prefix, classid_concept}` (OGAR#95 hi-u16 app-prefix mirror) | `(prefix<<16)\|concept` | RECONCILE: the #95 app-prefix scheme put apps in the HI half; the ruling puts canon (domain:appid) HI and custom LO. These must converge on ONE composition — flagged as the Phase-2 operator checkpoint (the #95 table may become the CUSTOM-half render catalogue, or the appid byte subsumes it) | +| q2 `osint-bake` | mints `CLASSID_OSINT` (`0x0000_0700`) rows via `new_v2` | re-mint as `0x0701_1000` via `mint_for(classid_read_mode(c).tail_variant, …)` | +| q2 `cpic` local mirror | domain `0x000C`, V1 tail (ISS-Q2-CPIC-MIRROR…) | re-mint into `0x0E01_1000` + V3 tail by PULLING the contract (dissolves the divergence issue in the same pass) | +| OGAR vocab emission (Phase B of the one-row registry, D-VCW-4) | n/a | emits new-form classids only | + +## §3 The mechanism — one flippable definition + +Add to `lance-graph-contract` (the zero-dep single source): + +```rust +/// The ONE classid composition. canon = domain:appid (e.g. 0x0701), +/// custom = marker/render half (today the temporary V3 reminder 0x1000). +/// CLASSID_CANON_HIGH selects the half-order; flipping it IS the migration. +pub const CLASSID_CANON_HIGH: bool = /* false = legacy, true = target */; +pub const fn compose_classid(canon: u16, custom: u16) -> u32; +pub const fn split_classid(classid: u32) -> (u16 /*canon*/, u16 /*custom*/); +``` + +Probes (mandatory, ship WITH the definition): `split(compose(c,x)) == (c,x)` +both orders; `flip(flip(id)) == id`; domain routing invariant under the flag +for all registered classids; the legacy-boundary matrix (every pre-flip wired +classid decodes identically through the split as before the refactor). + +## §4 Phases + +| Phase | Content | Gate | +|---|---|---| +| **P0** | Land `compose/split/CLASSID_CANON_HIGH=false` + route every §2 lance-graph site through it. ZERO behavior change (probed: all 763+ tests identical). | contract suite green, probes green | +| **P1** | Flip `CLASSID_CANON_HIGH=true` + mint the three new-form classids (`0x0701_1000`/`0x0A01_1000`/`0x0E01_1000`) into the registry ALONGSIDE the old forms (coexistence). | round-trip + boundary matrix + `flip(flip)` green | +| **P2** | Reconcile the OGAR#95 hi-u16 app-prefix mirror with the new order (operator checkpoint — see §2 row); OGAR emits new-form vocab. | operator nod on the #95 reconciliation | +| **P3** | q2 re-mints (osint-bake → `0x0701_1000`; cpic → `0x0E01_1000` via contract pull, dissolving `ISS-Q2-CPIC-MIRROR…`); old-form registry keys retire. | q2 bakes green; fuse green | +| **P4** | `0x1000` marker retirement decision — the custom half opens for the real render catalogue ("later it's 64k dynamic classes and classviews × bitmask"). | **operator checkpoint** | + +## §5 What this plan deliberately does NOT do + +- No key-layout change (16/16/480 locked; classid bytes 0..4 fixed offsets). +- No blanket reinterpretation of legacy classids (mint-forward only). +- No unilateral retirement of the `0x1000` marker (P4 is yours). +- No touching of concept ids in domains that HAVE vocabularies. + +## Cross-references + +- Ruling + OGAR execution: OGAR PR #146 + `DISCOVERY-MAP.md` + `D-OSINT-APPID-NOT-CONCEPT`; lance-graph `ISS-OSINT-SYSTEM-ROOT-SLOT- + VIOLATION` (RESOLVED by the ruling — sharper than its Options A/B). +- Sequencing parent: `soa-value-tenant-migration-v2.md` §2.3 (this IS that + flip); `v3-convergence-wiring-v1.md` (D-VCW-4 registry work feeds P2). +- Directives honored: `E-CLASSID-SPLIT-ORDER-IS-A-FLIP` (one definition), + `E-CLASSID-HUMANREADABLE-REORDER-DEFERRED` (now superseded BY TRIGGER — + status flip recorded on the board, entry preserved), + `I-LEGACY-API-FEATURE-GATED` (the boundary discipline). From 7a796d5f7fbf0e45ea14f9c4314c9ea5145884ce Mon Sep 17 00:00:00 2001 From: Claude Date: Thu, 2 Jul 2026 04:47:56 +0000 Subject: [PATCH 3/3] =?UTF-8?q?plan:=20two=20codex=20P2=20amendments=20?= =?UTF-8?q?=E2=80=94=20class=5Fid=20discriminator=20routes=20through=20spl?= =?UTF-8?q?it=5Fclassid;=20legacy=20registry=20aliases=20demote,=20never?= =?UTF-8?q?=20retire=20blind?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Both #627 codex findings are load-bearing plan corrections: 1. Class-collapse guard (line-76 finding): post-flip, 'classid as u16' yields the CUSTOM half (0x1000) for ALL classes — the SoA class_id / EntityType discriminator would collapse to one value. The stamp MUST route through split_classid(id).canon; 'as u16' on a classid becomes a forbidden pattern with a P0 grep gate + a no-class-collapse probe (three post-flip classids => three distinct canon discriminators). 2. Legacy-alias demotion (line-110 finding): P3 no longer retires old-form registry keys — mint-forward means persisted pre-flip rows (0x1000_0700 etc.) resolve through the concrete registry forever until re-baked; removing the alias would drop them to ReadMode::DEFAULT (wrong tail/schema). Old keys DEMOTE to documented read-only legacy aliases; retirement is a separate step gated on a corpus proof of zero stored old-form rows (RESERVE-DON'T-RECLAIM applied to registry keys). Co-Authored-By: Claude --- .claude/plans/classid-canon-custom-flip-v1.md | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/.claude/plans/classid-canon-custom-flip-v1.md b/.claude/plans/classid-canon-custom-flip-v1.md index 93794319..98391b12 100644 --- a/.claude/plans/classid-canon-custom-flip-v1.md +++ b/.claude/plans/classid-canon-custom-flip-v1.md @@ -78,6 +78,7 @@ phases below are unblocked. | `ogar_codebook::classid_concept_domain` | routes `classid as u16` (lo) | routes the CANON half via `split_classid` | | `hhtl::NiblePath::from_guid_prefix{,_v3}` | v1 fold refuses `classid >> 16 != 0`; v3 fold ignores classid | both route the marker/canon test through `split_classid` | | `ogar_codebook::{render_classid, classid_app_prefix, classid_concept}` (OGAR#95 hi-u16 app-prefix mirror) | `(prefix<<16)\|concept` | RECONCILE: the #95 app-prefix scheme put apps in the HI half; the ruling puts canon (domain:appid) HI and custom LO. These must converge on ONE composition — flagged as the Phase-2 operator checkpoint (the #95 table may become the CUSTOM-half render catalogue, or the appid byte subsumes it) | +| **`EntityType` tenant stamp / `MailboxSoaView::class_id` (the u16 SoA discriminator)** | stamped `classid as u16` (pre-flip that IS the canon lo-half — OSINT `0x0700` / FMA `0x0A01` / CPIC `0x0E00`, distinct) | **MUST route through `split_classid(id).canon`** — a naive `as u16` post-flip yields the CUSTOM half (`0x1000`) for ALL classes: total class collapse, class-based scans/render indistinguishable (codex P2 on #627, line-76 finding). `as u16` on a classid becomes a forbidden pattern (grep gate in P0) | | q2 `osint-bake` | mints `CLASSID_OSINT` (`0x0000_0700`) rows via `new_v2` | re-mint as `0x0701_1000` via `mint_for(classid_read_mode(c).tail_variant, …)` | | q2 `cpic` local mirror | domain `0x000C`, V1 tail (ISS-Q2-CPIC-MIRROR…) | re-mint into `0x0E01_1000` + V3 tail by PULLING the contract (dissolves the divergence issue in the same pass) | | OGAR vocab emission (Phase B of the one-row registry, D-VCW-4) | n/a | emits new-form classids only | @@ -98,7 +99,11 @@ pub const fn split_classid(classid: u32) -> (u16 /*canon*/, u16 /*custom*/); Probes (mandatory, ship WITH the definition): `split(compose(c,x)) == (c,x)` both orders; `flip(flip(id)) == id`; domain routing invariant under the flag for all registered classids; the legacy-boundary matrix (every pre-flip wired -classid decodes identically through the split as before the refactor). +classid decodes identically through the split as before the refactor); +**no-class-collapse probe** (codex P2 #627): the three post-flip classids +yield three DISTINCT `split_classid(id).canon` u16 discriminators — and a +grep gate that no site derives a class discriminator via `as u16` on a +classid (the pattern that collapses every post-flip class to `0x1000`). ## §4 Phases @@ -107,7 +112,7 @@ classid decodes identically through the split as before the refactor). | **P0** | Land `compose/split/CLASSID_CANON_HIGH=false` + route every §2 lance-graph site through it. ZERO behavior change (probed: all 763+ tests identical). | contract suite green, probes green | | **P1** | Flip `CLASSID_CANON_HIGH=true` + mint the three new-form classids (`0x0701_1000`/`0x0A01_1000`/`0x0E01_1000`) into the registry ALONGSIDE the old forms (coexistence). | round-trip + boundary matrix + `flip(flip)` green | | **P2** | Reconcile the OGAR#95 hi-u16 app-prefix mirror with the new order (operator checkpoint — see §2 row); OGAR emits new-form vocab. | operator nod on the #95 reconciliation | -| **P3** | q2 re-mints (osint-bake → `0x0701_1000`; cpic → `0x0E01_1000` via contract pull, dissolving `ISS-Q2-CPIC-MIRROR…`); old-form registry keys retire. | q2 bakes green; fuse green | +| **P3** | q2 re-mints (osint-bake → `0x0701_1000`; cpic → `0x0E01_1000` via contract pull, dissolving `ISS-Q2-CPIC-MIRROR…`); old-form registry keys **DEMOTE to documented read-only legacy aliases — they do NOT retire here** (codex P2 #627, line-110 finding: mint-forward means persisted pre-flip rows like `0x1000_0700` keep resolving through the concrete registry forever until re-baked; removing the alias would drop them to `ReadMode::DEFAULT` and read the wrong tail/schema). Retirement is a separate later step gated on a **corpus proof** (a scan showing zero stored old-form rows remain) — RESERVE-DON'T-RECLAIM applied to registry keys. | q2 bakes green; fuse green; legacy aliases still resolving | | **P4** | `0x1000` marker retirement decision — the custom half opens for the real render catalogue ("later it's 64k dynamic classes and classviews × bitmask"). | **operator checkpoint** | ## §5 What this plan deliberately does NOT do